1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * Copyright 2007-2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * Modified by Cort Dougan (cort@cs.nmt.edu) 11 * and Paul Mackerras (paulus@samba.org) 12 */ 13 14 /* 15 * This file handles the architecture-dependent parts of hardware exceptions 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/sched/debug.h> 21 #include <linux/kernel.h> 22 #include <linux/mm.h> 23 #include <linux/stddef.h> 24 #include <linux/unistd.h> 25 #include <linux/ptrace.h> 26 #include <linux/user.h> 27 #include <linux/interrupt.h> 28 #include <linux/init.h> 29 #include <linux/extable.h> 30 #include <linux/module.h> /* print_modules */ 31 #include <linux/prctl.h> 32 #include <linux/delay.h> 33 #include <linux/kprobes.h> 34 #include <linux/kexec.h> 35 #include <linux/backlight.h> 36 #include <linux/bug.h> 37 #include <linux/kdebug.h> 38 #include <linux/ratelimit.h> 39 #include <linux/context_tracking.h> 40 #include <linux/smp.h> 41 42 #include <asm/emulated_ops.h> 43 #include <asm/pgtable.h> 44 #include <linux/uaccess.h> 45 #include <asm/debugfs.h> 46 #include <asm/io.h> 47 #include <asm/machdep.h> 48 #include <asm/rtas.h> 49 #include <asm/pmc.h> 50 #include <asm/reg.h> 51 #ifdef CONFIG_PMAC_BACKLIGHT 52 #include <asm/backlight.h> 53 #endif 54 #ifdef CONFIG_PPC64 55 #include <asm/firmware.h> 56 #include <asm/processor.h> 57 #include <asm/tm.h> 58 #endif 59 #include <asm/kexec.h> 60 #include <asm/ppc-opcode.h> 61 #include <asm/rio.h> 62 #include <asm/fadump.h> 63 #include <asm/switch_to.h> 64 #include <asm/tm.h> 65 #include <asm/debug.h> 66 #include <asm/asm-prototypes.h> 67 #include <asm/hmi.h> 68 #include <sysdev/fsl_pci.h> 69 #include <asm/kprobes.h> 70 71 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 72 int (*__debugger)(struct pt_regs *regs) __read_mostly; 73 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 74 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 79 80 EXPORT_SYMBOL(__debugger); 81 EXPORT_SYMBOL(__debugger_ipi); 82 EXPORT_SYMBOL(__debugger_bpt); 83 EXPORT_SYMBOL(__debugger_sstep); 84 EXPORT_SYMBOL(__debugger_iabr_match); 85 EXPORT_SYMBOL(__debugger_break_match); 86 EXPORT_SYMBOL(__debugger_fault_handler); 87 #endif 88 89 /* Transactional Memory trap debug */ 90 #ifdef TM_DEBUG_SW 91 #define TM_DEBUG(x...) printk(KERN_INFO x) 92 #else 93 #define TM_DEBUG(x...) do { } while(0) 94 #endif 95 96 /* 97 * Trap & Exception support 98 */ 99 100 #ifdef CONFIG_PMAC_BACKLIGHT 101 static void pmac_backlight_unblank(void) 102 { 103 mutex_lock(&pmac_backlight_mutex); 104 if (pmac_backlight) { 105 struct backlight_properties *props; 106 107 props = &pmac_backlight->props; 108 props->brightness = props->max_brightness; 109 props->power = FB_BLANK_UNBLANK; 110 backlight_update_status(pmac_backlight); 111 } 112 mutex_unlock(&pmac_backlight_mutex); 113 } 114 #else 115 static inline void pmac_backlight_unblank(void) { } 116 #endif 117 118 /* 119 * If oops/die is expected to crash the machine, return true here. 120 * 121 * This should not be expected to be 100% accurate, there may be 122 * notifiers registered or other unexpected conditions that may bring 123 * down the kernel. Or if the current process in the kernel is holding 124 * locks or has other critical state, the kernel may become effectively 125 * unusable anyway. 126 */ 127 bool die_will_crash(void) 128 { 129 if (should_fadump_crash()) 130 return true; 131 if (kexec_should_crash(current)) 132 return true; 133 if (in_interrupt() || panic_on_oops || 134 !current->pid || is_global_init(current)) 135 return true; 136 137 return false; 138 } 139 140 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 141 static int die_owner = -1; 142 static unsigned int die_nest_count; 143 static int die_counter; 144 145 static unsigned long oops_begin(struct pt_regs *regs) 146 { 147 int cpu; 148 unsigned long flags; 149 150 oops_enter(); 151 152 /* racy, but better than risking deadlock. */ 153 raw_local_irq_save(flags); 154 cpu = smp_processor_id(); 155 if (!arch_spin_trylock(&die_lock)) { 156 if (cpu == die_owner) 157 /* nested oops. should stop eventually */; 158 else 159 arch_spin_lock(&die_lock); 160 } 161 die_nest_count++; 162 die_owner = cpu; 163 console_verbose(); 164 bust_spinlocks(1); 165 if (machine_is(powermac)) 166 pmac_backlight_unblank(); 167 return flags; 168 } 169 NOKPROBE_SYMBOL(oops_begin); 170 171 static void oops_end(unsigned long flags, struct pt_regs *regs, 172 int signr) 173 { 174 bust_spinlocks(0); 175 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 176 die_nest_count--; 177 oops_exit(); 178 printk("\n"); 179 if (!die_nest_count) { 180 /* Nest count reaches zero, release the lock. */ 181 die_owner = -1; 182 arch_spin_unlock(&die_lock); 183 } 184 raw_local_irq_restore(flags); 185 186 crash_fadump(regs, "die oops"); 187 188 if (kexec_should_crash(current)) 189 crash_kexec(regs); 190 191 if (!signr) 192 return; 193 194 /* 195 * While our oops output is serialised by a spinlock, output 196 * from panic() called below can race and corrupt it. If we 197 * know we are going to panic, delay for 1 second so we have a 198 * chance to get clean backtraces from all CPUs that are oopsing. 199 */ 200 if (in_interrupt() || panic_on_oops || !current->pid || 201 is_global_init(current)) { 202 mdelay(MSEC_PER_SEC); 203 } 204 205 if (in_interrupt()) 206 panic("Fatal exception in interrupt"); 207 if (panic_on_oops) 208 panic("Fatal exception"); 209 do_exit(signr); 210 } 211 NOKPROBE_SYMBOL(oops_end); 212 213 static int __die(const char *str, struct pt_regs *regs, long err) 214 { 215 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 216 217 if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 218 printk("LE "); 219 else 220 printk("BE "); 221 222 if (IS_ENABLED(CONFIG_PREEMPT)) 223 pr_cont("PREEMPT "); 224 225 if (IS_ENABLED(CONFIG_SMP)) 226 pr_cont("SMP NR_CPUS=%d ", NR_CPUS); 227 228 if (debug_pagealloc_enabled()) 229 pr_cont("DEBUG_PAGEALLOC "); 230 231 if (IS_ENABLED(CONFIG_NUMA)) 232 pr_cont("NUMA "); 233 234 pr_cont("%s\n", ppc_md.name ? ppc_md.name : ""); 235 236 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 237 return 1; 238 239 print_modules(); 240 show_regs(regs); 241 242 return 0; 243 } 244 NOKPROBE_SYMBOL(__die); 245 246 void die(const char *str, struct pt_regs *regs, long err) 247 { 248 unsigned long flags; 249 250 if (debugger(regs)) 251 return; 252 253 flags = oops_begin(regs); 254 if (__die(str, regs, err)) 255 err = 0; 256 oops_end(flags, regs, err); 257 } 258 NOKPROBE_SYMBOL(die); 259 260 void user_single_step_siginfo(struct task_struct *tsk, 261 struct pt_regs *regs, siginfo_t *info) 262 { 263 memset(info, 0, sizeof(*info)); 264 info->si_signo = SIGTRAP; 265 info->si_code = TRAP_TRACE; 266 info->si_addr = (void __user *)regs->nip; 267 } 268 269 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 270 { 271 siginfo_t info; 272 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 273 "at %08lx nip %08lx lr %08lx code %x\n"; 274 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 275 "at %016lx nip %016lx lr %016lx code %x\n"; 276 277 if (!user_mode(regs)) { 278 die("Exception in kernel mode", regs, signr); 279 return; 280 } 281 282 if (show_unhandled_signals && unhandled_signal(current, signr)) { 283 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, 284 current->comm, current->pid, signr, 285 addr, regs->nip, regs->link, code); 286 } 287 288 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 289 local_irq_enable(); 290 291 current->thread.trap_nr = code; 292 memset(&info, 0, sizeof(info)); 293 info.si_signo = signr; 294 info.si_code = code; 295 info.si_addr = (void __user *) addr; 296 force_sig_info(signr, &info, current); 297 } 298 299 void system_reset_exception(struct pt_regs *regs) 300 { 301 /* 302 * Avoid crashes in case of nested NMI exceptions. Recoverability 303 * is determined by RI and in_nmi 304 */ 305 bool nested = in_nmi(); 306 if (!nested) 307 nmi_enter(); 308 309 __this_cpu_inc(irq_stat.sreset_irqs); 310 311 /* See if any machine dependent calls */ 312 if (ppc_md.system_reset_exception) { 313 if (ppc_md.system_reset_exception(regs)) 314 goto out; 315 } 316 317 if (debugger(regs)) 318 goto out; 319 320 /* 321 * A system reset is a request to dump, so we always send 322 * it through the crashdump code (if fadump or kdump are 323 * registered). 324 */ 325 crash_fadump(regs, "System Reset"); 326 327 crash_kexec(regs); 328 329 /* 330 * We aren't the primary crash CPU. We need to send it 331 * to a holding pattern to avoid it ending up in the panic 332 * code. 333 */ 334 crash_kexec_secondary(regs); 335 336 /* 337 * No debugger or crash dump registered, print logs then 338 * panic. 339 */ 340 __die("System Reset", regs, SIGABRT); 341 342 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 343 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 344 nmi_panic(regs, "System Reset"); 345 346 out: 347 #ifdef CONFIG_PPC_BOOK3S_64 348 BUG_ON(get_paca()->in_nmi == 0); 349 if (get_paca()->in_nmi > 1) 350 nmi_panic(regs, "Unrecoverable nested System Reset"); 351 #endif 352 /* Must die if the interrupt is not recoverable */ 353 if (!(regs->msr & MSR_RI)) 354 nmi_panic(regs, "Unrecoverable System Reset"); 355 356 if (!nested) 357 nmi_exit(); 358 359 /* What should we do here? We could issue a shutdown or hard reset. */ 360 } 361 362 /* 363 * I/O accesses can cause machine checks on powermacs. 364 * Check if the NIP corresponds to the address of a sync 365 * instruction for which there is an entry in the exception 366 * table. 367 * Note that the 601 only takes a machine check on TEA 368 * (transfer error ack) signal assertion, and does not 369 * set any of the top 16 bits of SRR1. 370 * -- paulus. 371 */ 372 static inline int check_io_access(struct pt_regs *regs) 373 { 374 #ifdef CONFIG_PPC32 375 unsigned long msr = regs->msr; 376 const struct exception_table_entry *entry; 377 unsigned int *nip = (unsigned int *)regs->nip; 378 379 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 380 && (entry = search_exception_tables(regs->nip)) != NULL) { 381 /* 382 * Check that it's a sync instruction, or somewhere 383 * in the twi; isync; nop sequence that inb/inw/inl uses. 384 * As the address is in the exception table 385 * we should be able to read the instr there. 386 * For the debug message, we look at the preceding 387 * load or store. 388 */ 389 if (*nip == PPC_INST_NOP) 390 nip -= 2; 391 else if (*nip == PPC_INST_ISYNC) 392 --nip; 393 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { 394 unsigned int rb; 395 396 --nip; 397 rb = (*nip >> 11) & 0x1f; 398 printk(KERN_DEBUG "%s bad port %lx at %p\n", 399 (*nip & 0x100)? "OUT to": "IN from", 400 regs->gpr[rb] - _IO_BASE, nip); 401 regs->msr |= MSR_RI; 402 regs->nip = extable_fixup(entry); 403 return 1; 404 } 405 } 406 #endif /* CONFIG_PPC32 */ 407 return 0; 408 } 409 410 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 411 /* On 4xx, the reason for the machine check or program exception 412 is in the ESR. */ 413 #define get_reason(regs) ((regs)->dsisr) 414 #define REASON_FP ESR_FP 415 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 416 #define REASON_PRIVILEGED ESR_PPR 417 #define REASON_TRAP ESR_PTR 418 419 /* single-step stuff */ 420 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 421 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 422 423 #else 424 /* On non-4xx, the reason for the machine check or program 425 exception is in the MSR. */ 426 #define get_reason(regs) ((regs)->msr) 427 #define REASON_TM SRR1_PROGTM 428 #define REASON_FP SRR1_PROGFPE 429 #define REASON_ILLEGAL SRR1_PROGILL 430 #define REASON_PRIVILEGED SRR1_PROGPRIV 431 #define REASON_TRAP SRR1_PROGTRAP 432 433 #define single_stepping(regs) ((regs)->msr & MSR_SE) 434 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 435 #endif 436 437 #if defined(CONFIG_E500) 438 int machine_check_e500mc(struct pt_regs *regs) 439 { 440 unsigned long mcsr = mfspr(SPRN_MCSR); 441 unsigned long pvr = mfspr(SPRN_PVR); 442 unsigned long reason = mcsr; 443 int recoverable = 1; 444 445 if (reason & MCSR_LD) { 446 recoverable = fsl_rio_mcheck_exception(regs); 447 if (recoverable == 1) 448 goto silent_out; 449 } 450 451 printk("Machine check in kernel mode.\n"); 452 printk("Caused by (from MCSR=%lx): ", reason); 453 454 if (reason & MCSR_MCP) 455 printk("Machine Check Signal\n"); 456 457 if (reason & MCSR_ICPERR) { 458 printk("Instruction Cache Parity Error\n"); 459 460 /* 461 * This is recoverable by invalidating the i-cache. 462 */ 463 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 464 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 465 ; 466 467 /* 468 * This will generally be accompanied by an instruction 469 * fetch error report -- only treat MCSR_IF as fatal 470 * if it wasn't due to an L1 parity error. 471 */ 472 reason &= ~MCSR_IF; 473 } 474 475 if (reason & MCSR_DCPERR_MC) { 476 printk("Data Cache Parity Error\n"); 477 478 /* 479 * In write shadow mode we auto-recover from the error, but it 480 * may still get logged and cause a machine check. We should 481 * only treat the non-write shadow case as non-recoverable. 482 */ 483 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 484 * is not implemented but L1 data cache always runs in write 485 * shadow mode. Hence on data cache parity errors HW will 486 * automatically invalidate the L1 Data Cache. 487 */ 488 if (PVR_VER(pvr) != PVR_VER_E6500) { 489 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 490 recoverable = 0; 491 } 492 } 493 494 if (reason & MCSR_L2MMU_MHIT) { 495 printk("Hit on multiple TLB entries\n"); 496 recoverable = 0; 497 } 498 499 if (reason & MCSR_NMI) 500 printk("Non-maskable interrupt\n"); 501 502 if (reason & MCSR_IF) { 503 printk("Instruction Fetch Error Report\n"); 504 recoverable = 0; 505 } 506 507 if (reason & MCSR_LD) { 508 printk("Load Error Report\n"); 509 recoverable = 0; 510 } 511 512 if (reason & MCSR_ST) { 513 printk("Store Error Report\n"); 514 recoverable = 0; 515 } 516 517 if (reason & MCSR_LDG) { 518 printk("Guarded Load Error Report\n"); 519 recoverable = 0; 520 } 521 522 if (reason & MCSR_TLBSYNC) 523 printk("Simultaneous tlbsync operations\n"); 524 525 if (reason & MCSR_BSL2_ERR) { 526 printk("Level 2 Cache Error\n"); 527 recoverable = 0; 528 } 529 530 if (reason & MCSR_MAV) { 531 u64 addr; 532 533 addr = mfspr(SPRN_MCAR); 534 addr |= (u64)mfspr(SPRN_MCARU) << 32; 535 536 printk("Machine Check %s Address: %#llx\n", 537 reason & MCSR_MEA ? "Effective" : "Physical", addr); 538 } 539 540 silent_out: 541 mtspr(SPRN_MCSR, mcsr); 542 return mfspr(SPRN_MCSR) == 0 && recoverable; 543 } 544 545 int machine_check_e500(struct pt_regs *regs) 546 { 547 unsigned long reason = mfspr(SPRN_MCSR); 548 549 if (reason & MCSR_BUS_RBERR) { 550 if (fsl_rio_mcheck_exception(regs)) 551 return 1; 552 if (fsl_pci_mcheck_exception(regs)) 553 return 1; 554 } 555 556 printk("Machine check in kernel mode.\n"); 557 printk("Caused by (from MCSR=%lx): ", reason); 558 559 if (reason & MCSR_MCP) 560 printk("Machine Check Signal\n"); 561 if (reason & MCSR_ICPERR) 562 printk("Instruction Cache Parity Error\n"); 563 if (reason & MCSR_DCP_PERR) 564 printk("Data Cache Push Parity Error\n"); 565 if (reason & MCSR_DCPERR) 566 printk("Data Cache Parity Error\n"); 567 if (reason & MCSR_BUS_IAERR) 568 printk("Bus - Instruction Address Error\n"); 569 if (reason & MCSR_BUS_RAERR) 570 printk("Bus - Read Address Error\n"); 571 if (reason & MCSR_BUS_WAERR) 572 printk("Bus - Write Address Error\n"); 573 if (reason & MCSR_BUS_IBERR) 574 printk("Bus - Instruction Data Error\n"); 575 if (reason & MCSR_BUS_RBERR) 576 printk("Bus - Read Data Bus Error\n"); 577 if (reason & MCSR_BUS_WBERR) 578 printk("Bus - Write Data Bus Error\n"); 579 if (reason & MCSR_BUS_IPERR) 580 printk("Bus - Instruction Parity Error\n"); 581 if (reason & MCSR_BUS_RPERR) 582 printk("Bus - Read Parity Error\n"); 583 584 return 0; 585 } 586 587 int machine_check_generic(struct pt_regs *regs) 588 { 589 return 0; 590 } 591 #elif defined(CONFIG_E200) 592 int machine_check_e200(struct pt_regs *regs) 593 { 594 unsigned long reason = mfspr(SPRN_MCSR); 595 596 printk("Machine check in kernel mode.\n"); 597 printk("Caused by (from MCSR=%lx): ", reason); 598 599 if (reason & MCSR_MCP) 600 printk("Machine Check Signal\n"); 601 if (reason & MCSR_CP_PERR) 602 printk("Cache Push Parity Error\n"); 603 if (reason & MCSR_CPERR) 604 printk("Cache Parity Error\n"); 605 if (reason & MCSR_EXCP_ERR) 606 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 607 if (reason & MCSR_BUS_IRERR) 608 printk("Bus - Read Bus Error on instruction fetch\n"); 609 if (reason & MCSR_BUS_DRERR) 610 printk("Bus - Read Bus Error on data load\n"); 611 if (reason & MCSR_BUS_WRERR) 612 printk("Bus - Write Bus Error on buffered store or cache line push\n"); 613 614 return 0; 615 } 616 #elif defined(CONFIG_PPC32) 617 int machine_check_generic(struct pt_regs *regs) 618 { 619 unsigned long reason = regs->msr; 620 621 printk("Machine check in kernel mode.\n"); 622 printk("Caused by (from SRR1=%lx): ", reason); 623 switch (reason & 0x601F0000) { 624 case 0x80000: 625 printk("Machine check signal\n"); 626 break; 627 case 0: /* for 601 */ 628 case 0x40000: 629 case 0x140000: /* 7450 MSS error and TEA */ 630 printk("Transfer error ack signal\n"); 631 break; 632 case 0x20000: 633 printk("Data parity error signal\n"); 634 break; 635 case 0x10000: 636 printk("Address parity error signal\n"); 637 break; 638 case 0x20000000: 639 printk("L1 Data Cache error\n"); 640 break; 641 case 0x40000000: 642 printk("L1 Instruction Cache error\n"); 643 break; 644 case 0x00100000: 645 printk("L2 data cache parity error\n"); 646 break; 647 default: 648 printk("Unknown values in msr\n"); 649 } 650 return 0; 651 } 652 #endif /* everything else */ 653 654 void machine_check_exception(struct pt_regs *regs) 655 { 656 int recover = 0; 657 bool nested = in_nmi(); 658 if (!nested) 659 nmi_enter(); 660 661 /* 64s accounts the mce in machine_check_early when in HVMODE */ 662 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE)) 663 __this_cpu_inc(irq_stat.mce_exceptions); 664 665 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 666 667 /* See if any machine dependent calls. In theory, we would want 668 * to call the CPU first, and call the ppc_md. one if the CPU 669 * one returns a positive number. However there is existing code 670 * that assumes the board gets a first chance, so let's keep it 671 * that way for now and fix things later. --BenH. 672 */ 673 if (ppc_md.machine_check_exception) 674 recover = ppc_md.machine_check_exception(regs); 675 else if (cur_cpu_spec->machine_check) 676 recover = cur_cpu_spec->machine_check(regs); 677 678 if (recover > 0) 679 goto bail; 680 681 if (debugger_fault_handler(regs)) 682 goto bail; 683 684 if (check_io_access(regs)) 685 goto bail; 686 687 die("Machine check", regs, SIGBUS); 688 689 /* Must die if the interrupt is not recoverable */ 690 if (!(regs->msr & MSR_RI)) 691 nmi_panic(regs, "Unrecoverable Machine check"); 692 693 bail: 694 if (!nested) 695 nmi_exit(); 696 } 697 698 void SMIException(struct pt_regs *regs) 699 { 700 die("System Management Interrupt", regs, SIGABRT); 701 } 702 703 #ifdef CONFIG_VSX 704 static void p9_hmi_special_emu(struct pt_regs *regs) 705 { 706 unsigned int ra, rb, t, i, sel, instr, rc; 707 const void __user *addr; 708 u8 vbuf[16], *vdst; 709 unsigned long ea, msr, msr_mask; 710 bool swap; 711 712 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip)) 713 return; 714 715 /* 716 * lxvb16x opcode: 0x7c0006d8 717 * lxvd2x opcode: 0x7c000698 718 * lxvh8x opcode: 0x7c000658 719 * lxvw4x opcode: 0x7c000618 720 */ 721 if ((instr & 0xfc00073e) != 0x7c000618) { 722 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 723 " instr=%08x\n", 724 smp_processor_id(), current->comm, current->pid, 725 regs->nip, instr); 726 return; 727 } 728 729 /* Grab vector registers into the task struct */ 730 msr = regs->msr; /* Grab msr before we flush the bits */ 731 flush_vsx_to_thread(current); 732 enable_kernel_altivec(); 733 734 /* 735 * Is userspace running with a different endian (this is rare but 736 * not impossible) 737 */ 738 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 739 740 /* Decode the instruction */ 741 ra = (instr >> 16) & 0x1f; 742 rb = (instr >> 11) & 0x1f; 743 t = (instr >> 21) & 0x1f; 744 if (instr & 1) 745 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 746 else 747 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 748 749 /* Grab the vector address */ 750 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 751 if (is_32bit_task()) 752 ea &= 0xfffffffful; 753 addr = (__force const void __user *)ea; 754 755 /* Check it */ 756 if (!access_ok(VERIFY_READ, addr, 16)) { 757 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 758 " instr=%08x addr=%016lx\n", 759 smp_processor_id(), current->comm, current->pid, 760 regs->nip, instr, (unsigned long)addr); 761 return; 762 } 763 764 /* Read the vector */ 765 rc = 0; 766 if ((unsigned long)addr & 0xfUL) 767 /* unaligned case */ 768 rc = __copy_from_user_inatomic(vbuf, addr, 16); 769 else 770 __get_user_atomic_128_aligned(vbuf, addr, rc); 771 if (rc) { 772 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 773 " instr=%08x addr=%016lx\n", 774 smp_processor_id(), current->comm, current->pid, 775 regs->nip, instr, (unsigned long)addr); 776 return; 777 } 778 779 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 780 " instr=%08x addr=%016lx\n", 781 smp_processor_id(), current->comm, current->pid, regs->nip, 782 instr, (unsigned long) addr); 783 784 /* Grab instruction "selector" */ 785 sel = (instr >> 6) & 3; 786 787 /* 788 * Check to make sure the facility is actually enabled. This 789 * could happen if we get a false positive hit. 790 * 791 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 792 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 793 */ 794 msr_mask = MSR_VSX; 795 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 796 msr_mask = MSR_VEC; 797 if (!(msr & msr_mask)) { 798 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 799 " instr=%08x msr:%016lx\n", 800 smp_processor_id(), current->comm, current->pid, 801 regs->nip, instr, msr); 802 return; 803 } 804 805 /* Do logging here before we modify sel based on endian */ 806 switch (sel) { 807 case 0: /* lxvw4x */ 808 PPC_WARN_EMULATED(lxvw4x, regs); 809 break; 810 case 1: /* lxvh8x */ 811 PPC_WARN_EMULATED(lxvh8x, regs); 812 break; 813 case 2: /* lxvd2x */ 814 PPC_WARN_EMULATED(lxvd2x, regs); 815 break; 816 case 3: /* lxvb16x */ 817 PPC_WARN_EMULATED(lxvb16x, regs); 818 break; 819 } 820 821 #ifdef __LITTLE_ENDIAN__ 822 /* 823 * An LE kernel stores the vector in the task struct as an LE 824 * byte array (effectively swapping both the components and 825 * the content of the components). Those instructions expect 826 * the components to remain in ascending address order, so we 827 * swap them back. 828 * 829 * If we are running a BE user space, the expectation is that 830 * of a simple memcpy, so forcing the emulation to look like 831 * a lxvb16x should do the trick. 832 */ 833 if (swap) 834 sel = 3; 835 836 switch (sel) { 837 case 0: /* lxvw4x */ 838 for (i = 0; i < 4; i++) 839 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 840 break; 841 case 1: /* lxvh8x */ 842 for (i = 0; i < 8; i++) 843 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 844 break; 845 case 2: /* lxvd2x */ 846 for (i = 0; i < 2; i++) 847 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 848 break; 849 case 3: /* lxvb16x */ 850 for (i = 0; i < 16; i++) 851 vdst[i] = vbuf[15-i]; 852 break; 853 } 854 #else /* __LITTLE_ENDIAN__ */ 855 /* On a big endian kernel, a BE userspace only needs a memcpy */ 856 if (!swap) 857 sel = 3; 858 859 /* Otherwise, we need to swap the content of the components */ 860 switch (sel) { 861 case 0: /* lxvw4x */ 862 for (i = 0; i < 4; i++) 863 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 864 break; 865 case 1: /* lxvh8x */ 866 for (i = 0; i < 8; i++) 867 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 868 break; 869 case 2: /* lxvd2x */ 870 for (i = 0; i < 2; i++) 871 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 872 break; 873 case 3: /* lxvb16x */ 874 memcpy(vdst, vbuf, 16); 875 break; 876 } 877 #endif /* !__LITTLE_ENDIAN__ */ 878 879 /* Go to next instruction */ 880 regs->nip += 4; 881 } 882 #endif /* CONFIG_VSX */ 883 884 void handle_hmi_exception(struct pt_regs *regs) 885 { 886 struct pt_regs *old_regs; 887 888 old_regs = set_irq_regs(regs); 889 irq_enter(); 890 891 #ifdef CONFIG_VSX 892 /* Real mode flagged P9 special emu is needed */ 893 if (local_paca->hmi_p9_special_emu) { 894 local_paca->hmi_p9_special_emu = 0; 895 896 /* 897 * We don't want to take page faults while doing the 898 * emulation, we just replay the instruction if necessary. 899 */ 900 pagefault_disable(); 901 p9_hmi_special_emu(regs); 902 pagefault_enable(); 903 } 904 #endif /* CONFIG_VSX */ 905 906 if (ppc_md.handle_hmi_exception) 907 ppc_md.handle_hmi_exception(regs); 908 909 irq_exit(); 910 set_irq_regs(old_regs); 911 } 912 913 void unknown_exception(struct pt_regs *regs) 914 { 915 enum ctx_state prev_state = exception_enter(); 916 917 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 918 regs->nip, regs->msr, regs->trap); 919 920 _exception(SIGTRAP, regs, 0, 0); 921 922 exception_exit(prev_state); 923 } 924 925 void instruction_breakpoint_exception(struct pt_regs *regs) 926 { 927 enum ctx_state prev_state = exception_enter(); 928 929 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 930 5, SIGTRAP) == NOTIFY_STOP) 931 goto bail; 932 if (debugger_iabr_match(regs)) 933 goto bail; 934 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 935 936 bail: 937 exception_exit(prev_state); 938 } 939 940 void RunModeException(struct pt_regs *regs) 941 { 942 _exception(SIGTRAP, regs, 0, 0); 943 } 944 945 void single_step_exception(struct pt_regs *regs) 946 { 947 enum ctx_state prev_state = exception_enter(); 948 949 clear_single_step(regs); 950 951 if (kprobe_post_handler(regs)) 952 return; 953 954 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 955 5, SIGTRAP) == NOTIFY_STOP) 956 goto bail; 957 if (debugger_sstep(regs)) 958 goto bail; 959 960 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 961 962 bail: 963 exception_exit(prev_state); 964 } 965 NOKPROBE_SYMBOL(single_step_exception); 966 967 /* 968 * After we have successfully emulated an instruction, we have to 969 * check if the instruction was being single-stepped, and if so, 970 * pretend we got a single-step exception. This was pointed out 971 * by Kumar Gala. -- paulus 972 */ 973 static void emulate_single_step(struct pt_regs *regs) 974 { 975 if (single_stepping(regs)) 976 single_step_exception(regs); 977 } 978 979 static inline int __parse_fpscr(unsigned long fpscr) 980 { 981 int ret = 0; 982 983 /* Invalid operation */ 984 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 985 ret = FPE_FLTINV; 986 987 /* Overflow */ 988 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 989 ret = FPE_FLTOVF; 990 991 /* Underflow */ 992 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 993 ret = FPE_FLTUND; 994 995 /* Divide by zero */ 996 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 997 ret = FPE_FLTDIV; 998 999 /* Inexact result */ 1000 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1001 ret = FPE_FLTRES; 1002 1003 return ret; 1004 } 1005 1006 static void parse_fpe(struct pt_regs *regs) 1007 { 1008 int code = 0; 1009 1010 flush_fp_to_thread(current); 1011 1012 code = __parse_fpscr(current->thread.fp_state.fpscr); 1013 1014 _exception(SIGFPE, regs, code, regs->nip); 1015 } 1016 1017 /* 1018 * Illegal instruction emulation support. Originally written to 1019 * provide the PVR to user applications using the mfspr rd, PVR. 1020 * Return non-zero if we can't emulate, or -EFAULT if the associated 1021 * memory access caused an access fault. Return zero on success. 1022 * 1023 * There are a couple of ways to do this, either "decode" the instruction 1024 * or directly match lots of bits. In this case, matching lots of 1025 * bits is faster and easier. 1026 * 1027 */ 1028 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1029 { 1030 u8 rT = (instword >> 21) & 0x1f; 1031 u8 rA = (instword >> 16) & 0x1f; 1032 u8 NB_RB = (instword >> 11) & 0x1f; 1033 u32 num_bytes; 1034 unsigned long EA; 1035 int pos = 0; 1036 1037 /* Early out if we are an invalid form of lswx */ 1038 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1039 if ((rT == rA) || (rT == NB_RB)) 1040 return -EINVAL; 1041 1042 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1043 1044 switch (instword & PPC_INST_STRING_MASK) { 1045 case PPC_INST_LSWX: 1046 case PPC_INST_STSWX: 1047 EA += NB_RB; 1048 num_bytes = regs->xer & 0x7f; 1049 break; 1050 case PPC_INST_LSWI: 1051 case PPC_INST_STSWI: 1052 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1053 break; 1054 default: 1055 return -EINVAL; 1056 } 1057 1058 while (num_bytes != 0) 1059 { 1060 u8 val; 1061 u32 shift = 8 * (3 - (pos & 0x3)); 1062 1063 /* if process is 32-bit, clear upper 32 bits of EA */ 1064 if ((regs->msr & MSR_64BIT) == 0) 1065 EA &= 0xFFFFFFFF; 1066 1067 switch ((instword & PPC_INST_STRING_MASK)) { 1068 case PPC_INST_LSWX: 1069 case PPC_INST_LSWI: 1070 if (get_user(val, (u8 __user *)EA)) 1071 return -EFAULT; 1072 /* first time updating this reg, 1073 * zero it out */ 1074 if (pos == 0) 1075 regs->gpr[rT] = 0; 1076 regs->gpr[rT] |= val << shift; 1077 break; 1078 case PPC_INST_STSWI: 1079 case PPC_INST_STSWX: 1080 val = regs->gpr[rT] >> shift; 1081 if (put_user(val, (u8 __user *)EA)) 1082 return -EFAULT; 1083 break; 1084 } 1085 /* move EA to next address */ 1086 EA += 1; 1087 num_bytes--; 1088 1089 /* manage our position within the register */ 1090 if (++pos == 4) { 1091 pos = 0; 1092 if (++rT == 32) 1093 rT = 0; 1094 } 1095 } 1096 1097 return 0; 1098 } 1099 1100 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1101 { 1102 u32 ra,rs; 1103 unsigned long tmp; 1104 1105 ra = (instword >> 16) & 0x1f; 1106 rs = (instword >> 21) & 0x1f; 1107 1108 tmp = regs->gpr[rs]; 1109 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1110 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1111 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1112 regs->gpr[ra] = tmp; 1113 1114 return 0; 1115 } 1116 1117 static int emulate_isel(struct pt_regs *regs, u32 instword) 1118 { 1119 u8 rT = (instword >> 21) & 0x1f; 1120 u8 rA = (instword >> 16) & 0x1f; 1121 u8 rB = (instword >> 11) & 0x1f; 1122 u8 BC = (instword >> 6) & 0x1f; 1123 u8 bit; 1124 unsigned long tmp; 1125 1126 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1127 bit = (regs->ccr >> (31 - BC)) & 0x1; 1128 1129 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1130 1131 return 0; 1132 } 1133 1134 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1135 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1136 { 1137 /* If we're emulating a load/store in an active transaction, we cannot 1138 * emulate it as the kernel operates in transaction suspended context. 1139 * We need to abort the transaction. This creates a persistent TM 1140 * abort so tell the user what caused it with a new code. 1141 */ 1142 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1143 tm_enable(); 1144 tm_abort(cause); 1145 return true; 1146 } 1147 return false; 1148 } 1149 #else 1150 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1151 { 1152 return false; 1153 } 1154 #endif 1155 1156 static int emulate_instruction(struct pt_regs *regs) 1157 { 1158 u32 instword; 1159 u32 rd; 1160 1161 if (!user_mode(regs)) 1162 return -EINVAL; 1163 CHECK_FULL_REGS(regs); 1164 1165 if (get_user(instword, (u32 __user *)(regs->nip))) 1166 return -EFAULT; 1167 1168 /* Emulate the mfspr rD, PVR. */ 1169 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1170 PPC_WARN_EMULATED(mfpvr, regs); 1171 rd = (instword >> 21) & 0x1f; 1172 regs->gpr[rd] = mfspr(SPRN_PVR); 1173 return 0; 1174 } 1175 1176 /* Emulating the dcba insn is just a no-op. */ 1177 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1178 PPC_WARN_EMULATED(dcba, regs); 1179 return 0; 1180 } 1181 1182 /* Emulate the mcrxr insn. */ 1183 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1184 int shift = (instword >> 21) & 0x1c; 1185 unsigned long msk = 0xf0000000UL >> shift; 1186 1187 PPC_WARN_EMULATED(mcrxr, regs); 1188 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1189 regs->xer &= ~0xf0000000UL; 1190 return 0; 1191 } 1192 1193 /* Emulate load/store string insn. */ 1194 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1195 if (tm_abort_check(regs, 1196 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1197 return -EINVAL; 1198 PPC_WARN_EMULATED(string, regs); 1199 return emulate_string_inst(regs, instword); 1200 } 1201 1202 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1203 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1204 PPC_WARN_EMULATED(popcntb, regs); 1205 return emulate_popcntb_inst(regs, instword); 1206 } 1207 1208 /* Emulate isel (Integer Select) instruction */ 1209 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1210 PPC_WARN_EMULATED(isel, regs); 1211 return emulate_isel(regs, instword); 1212 } 1213 1214 /* Emulate sync instruction variants */ 1215 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1216 PPC_WARN_EMULATED(sync, regs); 1217 asm volatile("sync"); 1218 return 0; 1219 } 1220 1221 #ifdef CONFIG_PPC64 1222 /* Emulate the mfspr rD, DSCR. */ 1223 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1224 PPC_INST_MFSPR_DSCR_USER) || 1225 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1226 PPC_INST_MFSPR_DSCR)) && 1227 cpu_has_feature(CPU_FTR_DSCR)) { 1228 PPC_WARN_EMULATED(mfdscr, regs); 1229 rd = (instword >> 21) & 0x1f; 1230 regs->gpr[rd] = mfspr(SPRN_DSCR); 1231 return 0; 1232 } 1233 /* Emulate the mtspr DSCR, rD. */ 1234 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1235 PPC_INST_MTSPR_DSCR_USER) || 1236 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1237 PPC_INST_MTSPR_DSCR)) && 1238 cpu_has_feature(CPU_FTR_DSCR)) { 1239 PPC_WARN_EMULATED(mtdscr, regs); 1240 rd = (instword >> 21) & 0x1f; 1241 current->thread.dscr = regs->gpr[rd]; 1242 current->thread.dscr_inherit = 1; 1243 mtspr(SPRN_DSCR, current->thread.dscr); 1244 return 0; 1245 } 1246 #endif 1247 1248 return -EINVAL; 1249 } 1250 1251 int is_valid_bugaddr(unsigned long addr) 1252 { 1253 return is_kernel_addr(addr); 1254 } 1255 1256 #ifdef CONFIG_MATH_EMULATION 1257 static int emulate_math(struct pt_regs *regs) 1258 { 1259 int ret; 1260 extern int do_mathemu(struct pt_regs *regs); 1261 1262 ret = do_mathemu(regs); 1263 if (ret >= 0) 1264 PPC_WARN_EMULATED(math, regs); 1265 1266 switch (ret) { 1267 case 0: 1268 emulate_single_step(regs); 1269 return 0; 1270 case 1: { 1271 int code = 0; 1272 code = __parse_fpscr(current->thread.fp_state.fpscr); 1273 _exception(SIGFPE, regs, code, regs->nip); 1274 return 0; 1275 } 1276 case -EFAULT: 1277 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1278 return 0; 1279 } 1280 1281 return -1; 1282 } 1283 #else 1284 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1285 #endif 1286 1287 void program_check_exception(struct pt_regs *regs) 1288 { 1289 enum ctx_state prev_state = exception_enter(); 1290 unsigned int reason = get_reason(regs); 1291 1292 /* We can now get here via a FP Unavailable exception if the core 1293 * has no FPU, in that case the reason flags will be 0 */ 1294 1295 if (reason & REASON_FP) { 1296 /* IEEE FP exception */ 1297 parse_fpe(regs); 1298 goto bail; 1299 } 1300 if (reason & REASON_TRAP) { 1301 unsigned long bugaddr; 1302 /* Debugger is first in line to stop recursive faults in 1303 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1304 if (debugger_bpt(regs)) 1305 goto bail; 1306 1307 if (kprobe_handler(regs)) 1308 goto bail; 1309 1310 /* trap exception */ 1311 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1312 == NOTIFY_STOP) 1313 goto bail; 1314 1315 bugaddr = regs->nip; 1316 /* 1317 * Fixup bugaddr for BUG_ON() in real mode 1318 */ 1319 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1320 bugaddr += PAGE_OFFSET; 1321 1322 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1323 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1324 regs->nip += 4; 1325 goto bail; 1326 } 1327 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1328 goto bail; 1329 } 1330 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1331 if (reason & REASON_TM) { 1332 /* This is a TM "Bad Thing Exception" program check. 1333 * This occurs when: 1334 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1335 * transition in TM states. 1336 * - A trechkpt is attempted when transactional. 1337 * - A treclaim is attempted when non transactional. 1338 * - A tend is illegally attempted. 1339 * - writing a TM SPR when transactional. 1340 */ 1341 if (!user_mode(regs) && 1342 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 1343 regs->nip += 4; 1344 goto bail; 1345 } 1346 /* If usermode caused this, it's done something illegal and 1347 * gets a SIGILL slap on the wrist. We call it an illegal 1348 * operand to distinguish from the instruction just being bad 1349 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1350 * illegal /placement/ of a valid instruction. 1351 */ 1352 if (user_mode(regs)) { 1353 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1354 goto bail; 1355 } else { 1356 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1357 "at %lx (msr 0x%x)\n", regs->nip, reason); 1358 die("Unrecoverable exception", regs, SIGABRT); 1359 } 1360 } 1361 #endif 1362 1363 /* 1364 * If we took the program check in the kernel skip down to sending a 1365 * SIGILL. The subsequent cases all relate to emulating instructions 1366 * which we should only do for userspace. We also do not want to enable 1367 * interrupts for kernel faults because that might lead to further 1368 * faults, and loose the context of the original exception. 1369 */ 1370 if (!user_mode(regs)) 1371 goto sigill; 1372 1373 /* We restore the interrupt state now */ 1374 if (!arch_irq_disabled_regs(regs)) 1375 local_irq_enable(); 1376 1377 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1378 * but there seems to be a hardware bug on the 405GP (RevD) 1379 * that means ESR is sometimes set incorrectly - either to 1380 * ESR_DST (!?) or 0. In the process of chasing this with the 1381 * hardware people - not sure if it can happen on any illegal 1382 * instruction or only on FP instructions, whether there is a 1383 * pattern to occurrences etc. -dgibson 31/Mar/2003 1384 */ 1385 if (!emulate_math(regs)) 1386 goto bail; 1387 1388 /* Try to emulate it if we should. */ 1389 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1390 switch (emulate_instruction(regs)) { 1391 case 0: 1392 regs->nip += 4; 1393 emulate_single_step(regs); 1394 goto bail; 1395 case -EFAULT: 1396 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1397 goto bail; 1398 } 1399 } 1400 1401 sigill: 1402 if (reason & REASON_PRIVILEGED) 1403 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1404 else 1405 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1406 1407 bail: 1408 exception_exit(prev_state); 1409 } 1410 NOKPROBE_SYMBOL(program_check_exception); 1411 1412 /* 1413 * This occurs when running in hypervisor mode on POWER6 or later 1414 * and an illegal instruction is encountered. 1415 */ 1416 void emulation_assist_interrupt(struct pt_regs *regs) 1417 { 1418 regs->msr |= REASON_ILLEGAL; 1419 program_check_exception(regs); 1420 } 1421 NOKPROBE_SYMBOL(emulation_assist_interrupt); 1422 1423 void alignment_exception(struct pt_regs *regs) 1424 { 1425 enum ctx_state prev_state = exception_enter(); 1426 int sig, code, fixed = 0; 1427 1428 /* We restore the interrupt state now */ 1429 if (!arch_irq_disabled_regs(regs)) 1430 local_irq_enable(); 1431 1432 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1433 goto bail; 1434 1435 /* we don't implement logging of alignment exceptions */ 1436 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1437 fixed = fix_alignment(regs); 1438 1439 if (fixed == 1) { 1440 regs->nip += 4; /* skip over emulated instruction */ 1441 emulate_single_step(regs); 1442 goto bail; 1443 } 1444 1445 /* Operand address was bad */ 1446 if (fixed == -EFAULT) { 1447 sig = SIGSEGV; 1448 code = SEGV_ACCERR; 1449 } else { 1450 sig = SIGBUS; 1451 code = BUS_ADRALN; 1452 } 1453 if (user_mode(regs)) 1454 _exception(sig, regs, code, regs->dar); 1455 else 1456 bad_page_fault(regs, regs->dar, sig); 1457 1458 bail: 1459 exception_exit(prev_state); 1460 } 1461 1462 void slb_miss_bad_addr(struct pt_regs *regs) 1463 { 1464 enum ctx_state prev_state = exception_enter(); 1465 1466 if (user_mode(regs)) 1467 _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar); 1468 else 1469 bad_page_fault(regs, regs->dar, SIGSEGV); 1470 1471 exception_exit(prev_state); 1472 } 1473 1474 void StackOverflow(struct pt_regs *regs) 1475 { 1476 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 1477 current, regs->gpr[1]); 1478 debugger(regs); 1479 show_regs(regs); 1480 panic("kernel stack overflow"); 1481 } 1482 1483 void nonrecoverable_exception(struct pt_regs *regs) 1484 { 1485 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 1486 regs->nip, regs->msr); 1487 debugger(regs); 1488 die("nonrecoverable exception", regs, SIGKILL); 1489 } 1490 1491 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1492 { 1493 enum ctx_state prev_state = exception_enter(); 1494 1495 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1496 "%lx at %lx\n", regs->trap, regs->nip); 1497 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1498 1499 exception_exit(prev_state); 1500 } 1501 1502 void altivec_unavailable_exception(struct pt_regs *regs) 1503 { 1504 enum ctx_state prev_state = exception_enter(); 1505 1506 if (user_mode(regs)) { 1507 /* A user program has executed an altivec instruction, 1508 but this kernel doesn't support altivec. */ 1509 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1510 goto bail; 1511 } 1512 1513 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1514 "%lx at %lx\n", regs->trap, regs->nip); 1515 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1516 1517 bail: 1518 exception_exit(prev_state); 1519 } 1520 1521 void vsx_unavailable_exception(struct pt_regs *regs) 1522 { 1523 if (user_mode(regs)) { 1524 /* A user program has executed an vsx instruction, 1525 but this kernel doesn't support vsx. */ 1526 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1527 return; 1528 } 1529 1530 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1531 "%lx at %lx\n", regs->trap, regs->nip); 1532 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1533 } 1534 1535 #ifdef CONFIG_PPC64 1536 static void tm_unavailable(struct pt_regs *regs) 1537 { 1538 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1539 if (user_mode(regs)) { 1540 current->thread.load_tm++; 1541 regs->msr |= MSR_TM; 1542 tm_enable(); 1543 tm_restore_sprs(¤t->thread); 1544 return; 1545 } 1546 #endif 1547 pr_emerg("Unrecoverable TM Unavailable Exception " 1548 "%lx at %lx\n", regs->trap, regs->nip); 1549 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1550 } 1551 1552 void facility_unavailable_exception(struct pt_regs *regs) 1553 { 1554 static char *facility_strings[] = { 1555 [FSCR_FP_LG] = "FPU", 1556 [FSCR_VECVSX_LG] = "VMX/VSX", 1557 [FSCR_DSCR_LG] = "DSCR", 1558 [FSCR_PM_LG] = "PMU SPRs", 1559 [FSCR_BHRB_LG] = "BHRB", 1560 [FSCR_TM_LG] = "TM", 1561 [FSCR_EBB_LG] = "EBB", 1562 [FSCR_TAR_LG] = "TAR", 1563 [FSCR_MSGP_LG] = "MSGP", 1564 [FSCR_SCV_LG] = "SCV", 1565 }; 1566 char *facility = "unknown"; 1567 u64 value; 1568 u32 instword, rd; 1569 u8 status; 1570 bool hv; 1571 1572 hv = (regs->trap == 0xf80); 1573 if (hv) 1574 value = mfspr(SPRN_HFSCR); 1575 else 1576 value = mfspr(SPRN_FSCR); 1577 1578 status = value >> 56; 1579 if (status == FSCR_DSCR_LG) { 1580 /* 1581 * User is accessing the DSCR register using the problem 1582 * state only SPR number (0x03) either through a mfspr or 1583 * a mtspr instruction. If it is a write attempt through 1584 * a mtspr, then we set the inherit bit. This also allows 1585 * the user to write or read the register directly in the 1586 * future by setting via the FSCR DSCR bit. But in case it 1587 * is a read DSCR attempt through a mfspr instruction, we 1588 * just emulate the instruction instead. This code path will 1589 * always emulate all the mfspr instructions till the user 1590 * has attempted at least one mtspr instruction. This way it 1591 * preserves the same behaviour when the user is accessing 1592 * the DSCR through privilege level only SPR number (0x11) 1593 * which is emulated through illegal instruction exception. 1594 * We always leave HFSCR DSCR set. 1595 */ 1596 if (get_user(instword, (u32 __user *)(regs->nip))) { 1597 pr_err("Failed to fetch the user instruction\n"); 1598 return; 1599 } 1600 1601 /* Write into DSCR (mtspr 0x03, RS) */ 1602 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1603 == PPC_INST_MTSPR_DSCR_USER) { 1604 rd = (instword >> 21) & 0x1f; 1605 current->thread.dscr = regs->gpr[rd]; 1606 current->thread.dscr_inherit = 1; 1607 current->thread.fscr |= FSCR_DSCR; 1608 mtspr(SPRN_FSCR, current->thread.fscr); 1609 } 1610 1611 /* Read from DSCR (mfspr RT, 0x03) */ 1612 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1613 == PPC_INST_MFSPR_DSCR_USER) { 1614 if (emulate_instruction(regs)) { 1615 pr_err("DSCR based mfspr emulation failed\n"); 1616 return; 1617 } 1618 regs->nip += 4; 1619 emulate_single_step(regs); 1620 } 1621 return; 1622 } 1623 1624 if (status == FSCR_TM_LG) { 1625 /* 1626 * If we're here then the hardware is TM aware because it 1627 * generated an exception with FSRM_TM set. 1628 * 1629 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1630 * told us not to do TM, or the kernel is not built with TM 1631 * support. 1632 * 1633 * If both of those things are true, then userspace can spam the 1634 * console by triggering the printk() below just by continually 1635 * doing tbegin (or any TM instruction). So in that case just 1636 * send the process a SIGILL immediately. 1637 */ 1638 if (!cpu_has_feature(CPU_FTR_TM)) 1639 goto out; 1640 1641 tm_unavailable(regs); 1642 return; 1643 } 1644 1645 if ((hv || status >= 2) && 1646 (status < ARRAY_SIZE(facility_strings)) && 1647 facility_strings[status]) 1648 facility = facility_strings[status]; 1649 1650 /* We restore the interrupt state now */ 1651 if (!arch_irq_disabled_regs(regs)) 1652 local_irq_enable(); 1653 1654 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1655 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1656 1657 out: 1658 if (user_mode(regs)) { 1659 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1660 return; 1661 } 1662 1663 die("Unexpected facility unavailable exception", regs, SIGABRT); 1664 } 1665 #endif 1666 1667 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1668 1669 void fp_unavailable_tm(struct pt_regs *regs) 1670 { 1671 /* Note: This does not handle any kind of FP laziness. */ 1672 1673 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1674 regs->nip, regs->msr); 1675 1676 /* We can only have got here if the task started using FP after 1677 * beginning the transaction. So, the transactional regs are just a 1678 * copy of the checkpointed ones. But, we still need to recheckpoint 1679 * as we're enabling FP for the process; it will return, abort the 1680 * transaction, and probably retry but now with FP enabled. So the 1681 * checkpointed FP registers need to be loaded. 1682 */ 1683 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1684 /* Reclaim didn't save out any FPRs to transact_fprs. */ 1685 1686 /* Enable FP for the task: */ 1687 regs->msr |= (MSR_FP | current->thread.fpexc_mode); 1688 1689 /* This loads and recheckpoints the FP registers from 1690 * thread.fpr[]. They will remain in registers after the 1691 * checkpoint so we don't need to reload them after. 1692 * If VMX is in use, the VRs now hold checkpointed values, 1693 * so we don't want to load the VRs from the thread_struct. 1694 */ 1695 tm_recheckpoint(¤t->thread, MSR_FP); 1696 1697 /* If VMX is in use, get the transactional values back */ 1698 if (regs->msr & MSR_VEC) { 1699 msr_check_and_set(MSR_VEC); 1700 load_vr_state(¤t->thread.vr_state); 1701 /* At this point all the VSX state is loaded, so enable it */ 1702 regs->msr |= MSR_VSX; 1703 } 1704 } 1705 1706 void altivec_unavailable_tm(struct pt_regs *regs) 1707 { 1708 /* See the comments in fp_unavailable_tm(). This function operates 1709 * the same way. 1710 */ 1711 1712 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1713 "MSR=%lx\n", 1714 regs->nip, regs->msr); 1715 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1716 regs->msr |= MSR_VEC; 1717 tm_recheckpoint(¤t->thread, MSR_VEC); 1718 current->thread.used_vr = 1; 1719 1720 if (regs->msr & MSR_FP) { 1721 msr_check_and_set(MSR_FP); 1722 load_fp_state(¤t->thread.fp_state); 1723 regs->msr |= MSR_VSX; 1724 } 1725 } 1726 1727 void vsx_unavailable_tm(struct pt_regs *regs) 1728 { 1729 unsigned long orig_msr = regs->msr; 1730 1731 /* See the comments in fp_unavailable_tm(). This works similarly, 1732 * though we're loading both FP and VEC registers in here. 1733 * 1734 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1735 * regs. Either way, set MSR_VSX. 1736 */ 1737 1738 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1739 "MSR=%lx\n", 1740 regs->nip, regs->msr); 1741 1742 current->thread.used_vsr = 1; 1743 1744 /* If FP and VMX are already loaded, we have all the state we need */ 1745 if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) { 1746 regs->msr |= MSR_VSX; 1747 return; 1748 } 1749 1750 /* This reclaims FP and/or VR regs if they're already enabled */ 1751 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1752 1753 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | 1754 MSR_VSX; 1755 1756 /* This loads & recheckpoints FP and VRs; but we have 1757 * to be sure not to overwrite previously-valid state. 1758 */ 1759 tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr); 1760 1761 msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC)); 1762 1763 if (orig_msr & MSR_FP) 1764 load_fp_state(¤t->thread.fp_state); 1765 if (orig_msr & MSR_VEC) 1766 load_vr_state(¤t->thread.vr_state); 1767 } 1768 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1769 1770 void performance_monitor_exception(struct pt_regs *regs) 1771 { 1772 __this_cpu_inc(irq_stat.pmu_irqs); 1773 1774 perf_irq(regs); 1775 } 1776 1777 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1778 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1779 { 1780 int changed = 0; 1781 /* 1782 * Determine the cause of the debug event, clear the 1783 * event flags and send a trap to the handler. Torez 1784 */ 1785 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1786 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1787 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1788 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1789 #endif 1790 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, 1791 5); 1792 changed |= 0x01; 1793 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1794 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1795 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, 1796 6); 1797 changed |= 0x01; 1798 } else if (debug_status & DBSR_IAC1) { 1799 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1800 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1801 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, 1802 1); 1803 changed |= 0x01; 1804 } else if (debug_status & DBSR_IAC2) { 1805 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1806 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, 1807 2); 1808 changed |= 0x01; 1809 } else if (debug_status & DBSR_IAC3) { 1810 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1811 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1812 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, 1813 3); 1814 changed |= 0x01; 1815 } else if (debug_status & DBSR_IAC4) { 1816 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1817 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, 1818 4); 1819 changed |= 0x01; 1820 } 1821 /* 1822 * At the point this routine was called, the MSR(DE) was turned off. 1823 * Check all other debug flags and see if that bit needs to be turned 1824 * back on or not. 1825 */ 1826 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1827 current->thread.debug.dbcr1)) 1828 regs->msr |= MSR_DE; 1829 else 1830 /* Make sure the IDM flag is off */ 1831 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1832 1833 if (changed & 0x01) 1834 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1835 } 1836 1837 void DebugException(struct pt_regs *regs, unsigned long debug_status) 1838 { 1839 current->thread.debug.dbsr = debug_status; 1840 1841 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1842 * on server, it stops on the target of the branch. In order to simulate 1843 * the server behaviour, we thus restart right away with a single step 1844 * instead of stopping here when hitting a BT 1845 */ 1846 if (debug_status & DBSR_BT) { 1847 regs->msr &= ~MSR_DE; 1848 1849 /* Disable BT */ 1850 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1851 /* Clear the BT event */ 1852 mtspr(SPRN_DBSR, DBSR_BT); 1853 1854 /* Do the single step trick only when coming from userspace */ 1855 if (user_mode(regs)) { 1856 current->thread.debug.dbcr0 &= ~DBCR0_BT; 1857 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1858 regs->msr |= MSR_DE; 1859 return; 1860 } 1861 1862 if (kprobe_post_handler(regs)) 1863 return; 1864 1865 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1866 5, SIGTRAP) == NOTIFY_STOP) { 1867 return; 1868 } 1869 if (debugger_sstep(regs)) 1870 return; 1871 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1872 regs->msr &= ~MSR_DE; 1873 1874 /* Disable instruction completion */ 1875 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1876 /* Clear the instruction completion event */ 1877 mtspr(SPRN_DBSR, DBSR_IC); 1878 1879 if (kprobe_post_handler(regs)) 1880 return; 1881 1882 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1883 5, SIGTRAP) == NOTIFY_STOP) { 1884 return; 1885 } 1886 1887 if (debugger_sstep(regs)) 1888 return; 1889 1890 if (user_mode(regs)) { 1891 current->thread.debug.dbcr0 &= ~DBCR0_IC; 1892 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1893 current->thread.debug.dbcr1)) 1894 regs->msr |= MSR_DE; 1895 else 1896 /* Make sure the IDM bit is off */ 1897 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1898 } 1899 1900 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1901 } else 1902 handle_debug(regs, debug_status); 1903 } 1904 NOKPROBE_SYMBOL(DebugException); 1905 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1906 1907 #if !defined(CONFIG_TAU_INT) 1908 void TAUException(struct pt_regs *regs) 1909 { 1910 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 1911 regs->nip, regs->msr, regs->trap, print_tainted()); 1912 } 1913 #endif /* CONFIG_INT_TAU */ 1914 1915 #ifdef CONFIG_ALTIVEC 1916 void altivec_assist_exception(struct pt_regs *regs) 1917 { 1918 int err; 1919 1920 if (!user_mode(regs)) { 1921 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 1922 " at %lx\n", regs->nip); 1923 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 1924 } 1925 1926 flush_altivec_to_thread(current); 1927 1928 PPC_WARN_EMULATED(altivec, regs); 1929 err = emulate_altivec(regs); 1930 if (err == 0) { 1931 regs->nip += 4; /* skip emulated instruction */ 1932 emulate_single_step(regs); 1933 return; 1934 } 1935 1936 if (err == -EFAULT) { 1937 /* got an error reading the instruction */ 1938 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1939 } else { 1940 /* didn't recognize the instruction */ 1941 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 1942 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 1943 "in %s at %lx\n", current->comm, regs->nip); 1944 current->thread.vr_state.vscr.u[3] |= 0x10000; 1945 } 1946 } 1947 #endif /* CONFIG_ALTIVEC */ 1948 1949 #ifdef CONFIG_FSL_BOOKE 1950 void CacheLockingException(struct pt_regs *regs, unsigned long address, 1951 unsigned long error_code) 1952 { 1953 /* We treat cache locking instructions from the user 1954 * as priv ops, in the future we could try to do 1955 * something smarter 1956 */ 1957 if (error_code & (ESR_DLK|ESR_ILK)) 1958 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1959 return; 1960 } 1961 #endif /* CONFIG_FSL_BOOKE */ 1962 1963 #ifdef CONFIG_SPE 1964 void SPEFloatingPointException(struct pt_regs *regs) 1965 { 1966 extern int do_spe_mathemu(struct pt_regs *regs); 1967 unsigned long spefscr; 1968 int fpexc_mode; 1969 int code = 0; 1970 int err; 1971 1972 flush_spe_to_thread(current); 1973 1974 spefscr = current->thread.spefscr; 1975 fpexc_mode = current->thread.fpexc_mode; 1976 1977 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1978 code = FPE_FLTOVF; 1979 } 1980 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1981 code = FPE_FLTUND; 1982 } 1983 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1984 code = FPE_FLTDIV; 1985 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1986 code = FPE_FLTINV; 1987 } 1988 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1989 code = FPE_FLTRES; 1990 1991 err = do_spe_mathemu(regs); 1992 if (err == 0) { 1993 regs->nip += 4; /* skip emulated instruction */ 1994 emulate_single_step(regs); 1995 return; 1996 } 1997 1998 if (err == -EFAULT) { 1999 /* got an error reading the instruction */ 2000 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2001 } else if (err == -EINVAL) { 2002 /* didn't recognize the instruction */ 2003 printk(KERN_ERR "unrecognized spe instruction " 2004 "in %s at %lx\n", current->comm, regs->nip); 2005 } else { 2006 _exception(SIGFPE, regs, code, regs->nip); 2007 } 2008 2009 return; 2010 } 2011 2012 void SPEFloatingPointRoundException(struct pt_regs *regs) 2013 { 2014 extern int speround_handler(struct pt_regs *regs); 2015 int err; 2016 2017 preempt_disable(); 2018 if (regs->msr & MSR_SPE) 2019 giveup_spe(current); 2020 preempt_enable(); 2021 2022 regs->nip -= 4; 2023 err = speround_handler(regs); 2024 if (err == 0) { 2025 regs->nip += 4; /* skip emulated instruction */ 2026 emulate_single_step(regs); 2027 return; 2028 } 2029 2030 if (err == -EFAULT) { 2031 /* got an error reading the instruction */ 2032 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2033 } else if (err == -EINVAL) { 2034 /* didn't recognize the instruction */ 2035 printk(KERN_ERR "unrecognized spe instruction " 2036 "in %s at %lx\n", current->comm, regs->nip); 2037 } else { 2038 _exception(SIGFPE, regs, 0, regs->nip); 2039 return; 2040 } 2041 } 2042 #endif 2043 2044 /* 2045 * We enter here if we get an unrecoverable exception, that is, one 2046 * that happened at a point where the RI (recoverable interrupt) bit 2047 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2048 * we therefore lost state by taking this exception. 2049 */ 2050 void unrecoverable_exception(struct pt_regs *regs) 2051 { 2052 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 2053 regs->trap, regs->nip); 2054 die("Unrecoverable exception", regs, SIGABRT); 2055 } 2056 NOKPROBE_SYMBOL(unrecoverable_exception); 2057 2058 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 2059 /* 2060 * Default handler for a Watchdog exception, 2061 * spins until a reboot occurs 2062 */ 2063 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 2064 { 2065 /* Generic WatchdogHandler, implement your own */ 2066 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 2067 return; 2068 } 2069 2070 void WatchdogException(struct pt_regs *regs) 2071 { 2072 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2073 WatchdogHandler(regs); 2074 } 2075 #endif 2076 2077 /* 2078 * We enter here if we discover during exception entry that we are 2079 * running in supervisor mode with a userspace value in the stack pointer. 2080 */ 2081 void kernel_bad_stack(struct pt_regs *regs) 2082 { 2083 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2084 regs->gpr[1], regs->nip); 2085 die("Bad kernel stack pointer", regs, SIGABRT); 2086 } 2087 NOKPROBE_SYMBOL(kernel_bad_stack); 2088 2089 void __init trap_init(void) 2090 { 2091 } 2092 2093 2094 #ifdef CONFIG_PPC_EMULATED_STATS 2095 2096 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2097 2098 struct ppc_emulated ppc_emulated = { 2099 #ifdef CONFIG_ALTIVEC 2100 WARN_EMULATED_SETUP(altivec), 2101 #endif 2102 WARN_EMULATED_SETUP(dcba), 2103 WARN_EMULATED_SETUP(dcbz), 2104 WARN_EMULATED_SETUP(fp_pair), 2105 WARN_EMULATED_SETUP(isel), 2106 WARN_EMULATED_SETUP(mcrxr), 2107 WARN_EMULATED_SETUP(mfpvr), 2108 WARN_EMULATED_SETUP(multiple), 2109 WARN_EMULATED_SETUP(popcntb), 2110 WARN_EMULATED_SETUP(spe), 2111 WARN_EMULATED_SETUP(string), 2112 WARN_EMULATED_SETUP(sync), 2113 WARN_EMULATED_SETUP(unaligned), 2114 #ifdef CONFIG_MATH_EMULATION 2115 WARN_EMULATED_SETUP(math), 2116 #endif 2117 #ifdef CONFIG_VSX 2118 WARN_EMULATED_SETUP(vsx), 2119 #endif 2120 #ifdef CONFIG_PPC64 2121 WARN_EMULATED_SETUP(mfdscr), 2122 WARN_EMULATED_SETUP(mtdscr), 2123 WARN_EMULATED_SETUP(lq_stq), 2124 WARN_EMULATED_SETUP(lxvw4x), 2125 WARN_EMULATED_SETUP(lxvh8x), 2126 WARN_EMULATED_SETUP(lxvd2x), 2127 WARN_EMULATED_SETUP(lxvb16x), 2128 #endif 2129 }; 2130 2131 u32 ppc_warn_emulated; 2132 2133 void ppc_warn_emulated_print(const char *type) 2134 { 2135 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2136 type); 2137 } 2138 2139 static int __init ppc_warn_emulated_init(void) 2140 { 2141 struct dentry *dir, *d; 2142 unsigned int i; 2143 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2144 2145 if (!powerpc_debugfs_root) 2146 return -ENODEV; 2147 2148 dir = debugfs_create_dir("emulated_instructions", 2149 powerpc_debugfs_root); 2150 if (!dir) 2151 return -ENOMEM; 2152 2153 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, 2154 &ppc_warn_emulated); 2155 if (!d) 2156 goto fail; 2157 2158 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 2159 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, 2160 (u32 *)&entries[i].val.counter); 2161 if (!d) 2162 goto fail; 2163 } 2164 2165 return 0; 2166 2167 fail: 2168 debugfs_remove_recursive(dir); 2169 return -ENOMEM; 2170 } 2171 2172 device_initcall(ppc_warn_emulated_init); 2173 2174 #endif /* CONFIG_PPC_EMULATED_STATS */ 2175