1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * Copyright 2007-2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * Modified by Cort Dougan (cort@cs.nmt.edu) 11 * and Paul Mackerras (paulus@samba.org) 12 */ 13 14 /* 15 * This file handles the architecture-dependent parts of hardware exceptions 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/kernel.h> 21 #include <linux/mm.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/user.h> 26 #include <linux/interrupt.h> 27 #include <linux/init.h> 28 #include <linux/module.h> 29 #include <linux/prctl.h> 30 #include <linux/delay.h> 31 #include <linux/kprobes.h> 32 #include <linux/kexec.h> 33 #include <linux/backlight.h> 34 #include <linux/bug.h> 35 #include <linux/kdebug.h> 36 #include <linux/debugfs.h> 37 #include <linux/ratelimit.h> 38 39 #include <asm/emulated_ops.h> 40 #include <asm/pgtable.h> 41 #include <asm/uaccess.h> 42 #include <asm/io.h> 43 #include <asm/machdep.h> 44 #include <asm/rtas.h> 45 #include <asm/pmc.h> 46 #ifdef CONFIG_PPC32 47 #include <asm/reg.h> 48 #endif 49 #ifdef CONFIG_PMAC_BACKLIGHT 50 #include <asm/backlight.h> 51 #endif 52 #ifdef CONFIG_PPC64 53 #include <asm/firmware.h> 54 #include <asm/processor.h> 55 #endif 56 #include <asm/kexec.h> 57 #include <asm/ppc-opcode.h> 58 #include <asm/rio.h> 59 #include <asm/fadump.h> 60 #include <asm/switch_to.h> 61 #include <asm/tm.h> 62 #include <asm/debug.h> 63 64 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) 65 int (*__debugger)(struct pt_regs *regs) __read_mostly; 66 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 67 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 68 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 69 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 70 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 71 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 72 73 EXPORT_SYMBOL(__debugger); 74 EXPORT_SYMBOL(__debugger_ipi); 75 EXPORT_SYMBOL(__debugger_bpt); 76 EXPORT_SYMBOL(__debugger_sstep); 77 EXPORT_SYMBOL(__debugger_iabr_match); 78 EXPORT_SYMBOL(__debugger_break_match); 79 EXPORT_SYMBOL(__debugger_fault_handler); 80 #endif 81 82 /* Transactional Memory trap debug */ 83 #ifdef TM_DEBUG_SW 84 #define TM_DEBUG(x...) printk(KERN_INFO x) 85 #else 86 #define TM_DEBUG(x...) do { } while(0) 87 #endif 88 89 /* 90 * Trap & Exception support 91 */ 92 93 #ifdef CONFIG_PMAC_BACKLIGHT 94 static void pmac_backlight_unblank(void) 95 { 96 mutex_lock(&pmac_backlight_mutex); 97 if (pmac_backlight) { 98 struct backlight_properties *props; 99 100 props = &pmac_backlight->props; 101 props->brightness = props->max_brightness; 102 props->power = FB_BLANK_UNBLANK; 103 backlight_update_status(pmac_backlight); 104 } 105 mutex_unlock(&pmac_backlight_mutex); 106 } 107 #else 108 static inline void pmac_backlight_unblank(void) { } 109 #endif 110 111 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 112 static int die_owner = -1; 113 static unsigned int die_nest_count; 114 static int die_counter; 115 116 static unsigned __kprobes long oops_begin(struct pt_regs *regs) 117 { 118 int cpu; 119 unsigned long flags; 120 121 if (debugger(regs)) 122 return 1; 123 124 oops_enter(); 125 126 /* racy, but better than risking deadlock. */ 127 raw_local_irq_save(flags); 128 cpu = smp_processor_id(); 129 if (!arch_spin_trylock(&die_lock)) { 130 if (cpu == die_owner) 131 /* nested oops. should stop eventually */; 132 else 133 arch_spin_lock(&die_lock); 134 } 135 die_nest_count++; 136 die_owner = cpu; 137 console_verbose(); 138 bust_spinlocks(1); 139 if (machine_is(powermac)) 140 pmac_backlight_unblank(); 141 return flags; 142 } 143 144 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, 145 int signr) 146 { 147 bust_spinlocks(0); 148 die_owner = -1; 149 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 150 die_nest_count--; 151 oops_exit(); 152 printk("\n"); 153 if (!die_nest_count) 154 /* Nest count reaches zero, release the lock. */ 155 arch_spin_unlock(&die_lock); 156 raw_local_irq_restore(flags); 157 158 crash_fadump(regs, "die oops"); 159 160 /* 161 * A system reset (0x100) is a request to dump, so we always send 162 * it through the crashdump code. 163 */ 164 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { 165 crash_kexec(regs); 166 167 /* 168 * We aren't the primary crash CPU. We need to send it 169 * to a holding pattern to avoid it ending up in the panic 170 * code. 171 */ 172 crash_kexec_secondary(regs); 173 } 174 175 if (!signr) 176 return; 177 178 /* 179 * While our oops output is serialised by a spinlock, output 180 * from panic() called below can race and corrupt it. If we 181 * know we are going to panic, delay for 1 second so we have a 182 * chance to get clean backtraces from all CPUs that are oopsing. 183 */ 184 if (in_interrupt() || panic_on_oops || !current->pid || 185 is_global_init(current)) { 186 mdelay(MSEC_PER_SEC); 187 } 188 189 if (in_interrupt()) 190 panic("Fatal exception in interrupt"); 191 if (panic_on_oops) 192 panic("Fatal exception"); 193 do_exit(signr); 194 } 195 196 static int __kprobes __die(const char *str, struct pt_regs *regs, long err) 197 { 198 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 199 #ifdef CONFIG_PREEMPT 200 printk("PREEMPT "); 201 #endif 202 #ifdef CONFIG_SMP 203 printk("SMP NR_CPUS=%d ", NR_CPUS); 204 #endif 205 #ifdef CONFIG_DEBUG_PAGEALLOC 206 printk("DEBUG_PAGEALLOC "); 207 #endif 208 #ifdef CONFIG_NUMA 209 printk("NUMA "); 210 #endif 211 printk("%s\n", ppc_md.name ? ppc_md.name : ""); 212 213 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 214 return 1; 215 216 print_modules(); 217 show_regs(regs); 218 219 return 0; 220 } 221 222 void die(const char *str, struct pt_regs *regs, long err) 223 { 224 unsigned long flags = oops_begin(regs); 225 226 if (__die(str, regs, err)) 227 err = 0; 228 oops_end(flags, regs, err); 229 } 230 231 void user_single_step_siginfo(struct task_struct *tsk, 232 struct pt_regs *regs, siginfo_t *info) 233 { 234 memset(info, 0, sizeof(*info)); 235 info->si_signo = SIGTRAP; 236 info->si_code = TRAP_TRACE; 237 info->si_addr = (void __user *)regs->nip; 238 } 239 240 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 241 { 242 siginfo_t info; 243 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 244 "at %08lx nip %08lx lr %08lx code %x\n"; 245 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 246 "at %016lx nip %016lx lr %016lx code %x\n"; 247 248 if (!user_mode(regs)) { 249 die("Exception in kernel mode", regs, signr); 250 return; 251 } 252 253 if (show_unhandled_signals && unhandled_signal(current, signr)) { 254 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, 255 current->comm, current->pid, signr, 256 addr, regs->nip, regs->link, code); 257 } 258 259 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 260 local_irq_enable(); 261 262 current->thread.trap_nr = code; 263 memset(&info, 0, sizeof(info)); 264 info.si_signo = signr; 265 info.si_code = code; 266 info.si_addr = (void __user *) addr; 267 force_sig_info(signr, &info, current); 268 } 269 270 #ifdef CONFIG_PPC64 271 void system_reset_exception(struct pt_regs *regs) 272 { 273 /* See if any machine dependent calls */ 274 if (ppc_md.system_reset_exception) { 275 if (ppc_md.system_reset_exception(regs)) 276 return; 277 } 278 279 die("System Reset", regs, SIGABRT); 280 281 /* Must die if the interrupt is not recoverable */ 282 if (!(regs->msr & MSR_RI)) 283 panic("Unrecoverable System Reset"); 284 285 /* What should we do here? We could issue a shutdown or hard reset. */ 286 } 287 #endif 288 289 /* 290 * I/O accesses can cause machine checks on powermacs. 291 * Check if the NIP corresponds to the address of a sync 292 * instruction for which there is an entry in the exception 293 * table. 294 * Note that the 601 only takes a machine check on TEA 295 * (transfer error ack) signal assertion, and does not 296 * set any of the top 16 bits of SRR1. 297 * -- paulus. 298 */ 299 static inline int check_io_access(struct pt_regs *regs) 300 { 301 #ifdef CONFIG_PPC32 302 unsigned long msr = regs->msr; 303 const struct exception_table_entry *entry; 304 unsigned int *nip = (unsigned int *)regs->nip; 305 306 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 307 && (entry = search_exception_tables(regs->nip)) != NULL) { 308 /* 309 * Check that it's a sync instruction, or somewhere 310 * in the twi; isync; nop sequence that inb/inw/inl uses. 311 * As the address is in the exception table 312 * we should be able to read the instr there. 313 * For the debug message, we look at the preceding 314 * load or store. 315 */ 316 if (*nip == 0x60000000) /* nop */ 317 nip -= 2; 318 else if (*nip == 0x4c00012c) /* isync */ 319 --nip; 320 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { 321 /* sync or twi */ 322 unsigned int rb; 323 324 --nip; 325 rb = (*nip >> 11) & 0x1f; 326 printk(KERN_DEBUG "%s bad port %lx at %p\n", 327 (*nip & 0x100)? "OUT to": "IN from", 328 regs->gpr[rb] - _IO_BASE, nip); 329 regs->msr |= MSR_RI; 330 regs->nip = entry->fixup; 331 return 1; 332 } 333 } 334 #endif /* CONFIG_PPC32 */ 335 return 0; 336 } 337 338 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 339 /* On 4xx, the reason for the machine check or program exception 340 is in the ESR. */ 341 #define get_reason(regs) ((regs)->dsisr) 342 #ifndef CONFIG_FSL_BOOKE 343 #define get_mc_reason(regs) ((regs)->dsisr) 344 #else 345 #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) 346 #endif 347 #define REASON_FP ESR_FP 348 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 349 #define REASON_PRIVILEGED ESR_PPR 350 #define REASON_TRAP ESR_PTR 351 352 /* single-step stuff */ 353 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) 354 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) 355 356 #else 357 /* On non-4xx, the reason for the machine check or program 358 exception is in the MSR. */ 359 #define get_reason(regs) ((regs)->msr) 360 #define get_mc_reason(regs) ((regs)->msr) 361 #define REASON_TM 0x200000 362 #define REASON_FP 0x100000 363 #define REASON_ILLEGAL 0x80000 364 #define REASON_PRIVILEGED 0x40000 365 #define REASON_TRAP 0x20000 366 367 #define single_stepping(regs) ((regs)->msr & MSR_SE) 368 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 369 #endif 370 371 #if defined(CONFIG_4xx) 372 int machine_check_4xx(struct pt_regs *regs) 373 { 374 unsigned long reason = get_mc_reason(regs); 375 376 if (reason & ESR_IMCP) { 377 printk("Instruction"); 378 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 379 } else 380 printk("Data"); 381 printk(" machine check in kernel mode.\n"); 382 383 return 0; 384 } 385 386 int machine_check_440A(struct pt_regs *regs) 387 { 388 unsigned long reason = get_mc_reason(regs); 389 390 printk("Machine check in kernel mode.\n"); 391 if (reason & ESR_IMCP){ 392 printk("Instruction Synchronous Machine Check exception\n"); 393 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 394 } 395 else { 396 u32 mcsr = mfspr(SPRN_MCSR); 397 if (mcsr & MCSR_IB) 398 printk("Instruction Read PLB Error\n"); 399 if (mcsr & MCSR_DRB) 400 printk("Data Read PLB Error\n"); 401 if (mcsr & MCSR_DWB) 402 printk("Data Write PLB Error\n"); 403 if (mcsr & MCSR_TLBP) 404 printk("TLB Parity Error\n"); 405 if (mcsr & MCSR_ICP){ 406 flush_instruction_cache(); 407 printk("I-Cache Parity Error\n"); 408 } 409 if (mcsr & MCSR_DCSP) 410 printk("D-Cache Search Parity Error\n"); 411 if (mcsr & MCSR_DCFP) 412 printk("D-Cache Flush Parity Error\n"); 413 if (mcsr & MCSR_IMPE) 414 printk("Machine Check exception is imprecise\n"); 415 416 /* Clear MCSR */ 417 mtspr(SPRN_MCSR, mcsr); 418 } 419 return 0; 420 } 421 422 int machine_check_47x(struct pt_regs *regs) 423 { 424 unsigned long reason = get_mc_reason(regs); 425 u32 mcsr; 426 427 printk(KERN_ERR "Machine check in kernel mode.\n"); 428 if (reason & ESR_IMCP) { 429 printk(KERN_ERR 430 "Instruction Synchronous Machine Check exception\n"); 431 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 432 return 0; 433 } 434 mcsr = mfspr(SPRN_MCSR); 435 if (mcsr & MCSR_IB) 436 printk(KERN_ERR "Instruction Read PLB Error\n"); 437 if (mcsr & MCSR_DRB) 438 printk(KERN_ERR "Data Read PLB Error\n"); 439 if (mcsr & MCSR_DWB) 440 printk(KERN_ERR "Data Write PLB Error\n"); 441 if (mcsr & MCSR_TLBP) 442 printk(KERN_ERR "TLB Parity Error\n"); 443 if (mcsr & MCSR_ICP) { 444 flush_instruction_cache(); 445 printk(KERN_ERR "I-Cache Parity Error\n"); 446 } 447 if (mcsr & MCSR_DCSP) 448 printk(KERN_ERR "D-Cache Search Parity Error\n"); 449 if (mcsr & PPC47x_MCSR_GPR) 450 printk(KERN_ERR "GPR Parity Error\n"); 451 if (mcsr & PPC47x_MCSR_FPR) 452 printk(KERN_ERR "FPR Parity Error\n"); 453 if (mcsr & PPC47x_MCSR_IPR) 454 printk(KERN_ERR "Machine Check exception is imprecise\n"); 455 456 /* Clear MCSR */ 457 mtspr(SPRN_MCSR, mcsr); 458 459 return 0; 460 } 461 #elif defined(CONFIG_E500) 462 int machine_check_e500mc(struct pt_regs *regs) 463 { 464 unsigned long mcsr = mfspr(SPRN_MCSR); 465 unsigned long reason = mcsr; 466 int recoverable = 1; 467 468 if (reason & MCSR_LD) { 469 recoverable = fsl_rio_mcheck_exception(regs); 470 if (recoverable == 1) 471 goto silent_out; 472 } 473 474 printk("Machine check in kernel mode.\n"); 475 printk("Caused by (from MCSR=%lx): ", reason); 476 477 if (reason & MCSR_MCP) 478 printk("Machine Check Signal\n"); 479 480 if (reason & MCSR_ICPERR) { 481 printk("Instruction Cache Parity Error\n"); 482 483 /* 484 * This is recoverable by invalidating the i-cache. 485 */ 486 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 487 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 488 ; 489 490 /* 491 * This will generally be accompanied by an instruction 492 * fetch error report -- only treat MCSR_IF as fatal 493 * if it wasn't due to an L1 parity error. 494 */ 495 reason &= ~MCSR_IF; 496 } 497 498 if (reason & MCSR_DCPERR_MC) { 499 printk("Data Cache Parity Error\n"); 500 501 /* 502 * In write shadow mode we auto-recover from the error, but it 503 * may still get logged and cause a machine check. We should 504 * only treat the non-write shadow case as non-recoverable. 505 */ 506 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 507 recoverable = 0; 508 } 509 510 if (reason & MCSR_L2MMU_MHIT) { 511 printk("Hit on multiple TLB entries\n"); 512 recoverable = 0; 513 } 514 515 if (reason & MCSR_NMI) 516 printk("Non-maskable interrupt\n"); 517 518 if (reason & MCSR_IF) { 519 printk("Instruction Fetch Error Report\n"); 520 recoverable = 0; 521 } 522 523 if (reason & MCSR_LD) { 524 printk("Load Error Report\n"); 525 recoverable = 0; 526 } 527 528 if (reason & MCSR_ST) { 529 printk("Store Error Report\n"); 530 recoverable = 0; 531 } 532 533 if (reason & MCSR_LDG) { 534 printk("Guarded Load Error Report\n"); 535 recoverable = 0; 536 } 537 538 if (reason & MCSR_TLBSYNC) 539 printk("Simultaneous tlbsync operations\n"); 540 541 if (reason & MCSR_BSL2_ERR) { 542 printk("Level 2 Cache Error\n"); 543 recoverable = 0; 544 } 545 546 if (reason & MCSR_MAV) { 547 u64 addr; 548 549 addr = mfspr(SPRN_MCAR); 550 addr |= (u64)mfspr(SPRN_MCARU) << 32; 551 552 printk("Machine Check %s Address: %#llx\n", 553 reason & MCSR_MEA ? "Effective" : "Physical", addr); 554 } 555 556 silent_out: 557 mtspr(SPRN_MCSR, mcsr); 558 return mfspr(SPRN_MCSR) == 0 && recoverable; 559 } 560 561 int machine_check_e500(struct pt_regs *regs) 562 { 563 unsigned long reason = get_mc_reason(regs); 564 565 if (reason & MCSR_BUS_RBERR) { 566 if (fsl_rio_mcheck_exception(regs)) 567 return 1; 568 } 569 570 printk("Machine check in kernel mode.\n"); 571 printk("Caused by (from MCSR=%lx): ", reason); 572 573 if (reason & MCSR_MCP) 574 printk("Machine Check Signal\n"); 575 if (reason & MCSR_ICPERR) 576 printk("Instruction Cache Parity Error\n"); 577 if (reason & MCSR_DCP_PERR) 578 printk("Data Cache Push Parity Error\n"); 579 if (reason & MCSR_DCPERR) 580 printk("Data Cache Parity Error\n"); 581 if (reason & MCSR_BUS_IAERR) 582 printk("Bus - Instruction Address Error\n"); 583 if (reason & MCSR_BUS_RAERR) 584 printk("Bus - Read Address Error\n"); 585 if (reason & MCSR_BUS_WAERR) 586 printk("Bus - Write Address Error\n"); 587 if (reason & MCSR_BUS_IBERR) 588 printk("Bus - Instruction Data Error\n"); 589 if (reason & MCSR_BUS_RBERR) 590 printk("Bus - Read Data Bus Error\n"); 591 if (reason & MCSR_BUS_WBERR) 592 printk("Bus - Read Data Bus Error\n"); 593 if (reason & MCSR_BUS_IPERR) 594 printk("Bus - Instruction Parity Error\n"); 595 if (reason & MCSR_BUS_RPERR) 596 printk("Bus - Read Parity Error\n"); 597 598 return 0; 599 } 600 601 int machine_check_generic(struct pt_regs *regs) 602 { 603 return 0; 604 } 605 #elif defined(CONFIG_E200) 606 int machine_check_e200(struct pt_regs *regs) 607 { 608 unsigned long reason = get_mc_reason(regs); 609 610 printk("Machine check in kernel mode.\n"); 611 printk("Caused by (from MCSR=%lx): ", reason); 612 613 if (reason & MCSR_MCP) 614 printk("Machine Check Signal\n"); 615 if (reason & MCSR_CP_PERR) 616 printk("Cache Push Parity Error\n"); 617 if (reason & MCSR_CPERR) 618 printk("Cache Parity Error\n"); 619 if (reason & MCSR_EXCP_ERR) 620 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 621 if (reason & MCSR_BUS_IRERR) 622 printk("Bus - Read Bus Error on instruction fetch\n"); 623 if (reason & MCSR_BUS_DRERR) 624 printk("Bus - Read Bus Error on data load\n"); 625 if (reason & MCSR_BUS_WRERR) 626 printk("Bus - Write Bus Error on buffered store or cache line push\n"); 627 628 return 0; 629 } 630 #else 631 int machine_check_generic(struct pt_regs *regs) 632 { 633 unsigned long reason = get_mc_reason(regs); 634 635 printk("Machine check in kernel mode.\n"); 636 printk("Caused by (from SRR1=%lx): ", reason); 637 switch (reason & 0x601F0000) { 638 case 0x80000: 639 printk("Machine check signal\n"); 640 break; 641 case 0: /* for 601 */ 642 case 0x40000: 643 case 0x140000: /* 7450 MSS error and TEA */ 644 printk("Transfer error ack signal\n"); 645 break; 646 case 0x20000: 647 printk("Data parity error signal\n"); 648 break; 649 case 0x10000: 650 printk("Address parity error signal\n"); 651 break; 652 case 0x20000000: 653 printk("L1 Data Cache error\n"); 654 break; 655 case 0x40000000: 656 printk("L1 Instruction Cache error\n"); 657 break; 658 case 0x00100000: 659 printk("L2 data cache parity error\n"); 660 break; 661 default: 662 printk("Unknown values in msr\n"); 663 } 664 return 0; 665 } 666 #endif /* everything else */ 667 668 void machine_check_exception(struct pt_regs *regs) 669 { 670 int recover = 0; 671 672 __get_cpu_var(irq_stat).mce_exceptions++; 673 674 /* See if any machine dependent calls. In theory, we would want 675 * to call the CPU first, and call the ppc_md. one if the CPU 676 * one returns a positive number. However there is existing code 677 * that assumes the board gets a first chance, so let's keep it 678 * that way for now and fix things later. --BenH. 679 */ 680 if (ppc_md.machine_check_exception) 681 recover = ppc_md.machine_check_exception(regs); 682 else if (cur_cpu_spec->machine_check) 683 recover = cur_cpu_spec->machine_check(regs); 684 685 if (recover > 0) 686 return; 687 688 #if defined(CONFIG_8xx) && defined(CONFIG_PCI) 689 /* the qspan pci read routines can cause machine checks -- Cort 690 * 691 * yuck !!! that totally needs to go away ! There are better ways 692 * to deal with that than having a wart in the mcheck handler. 693 * -- BenH 694 */ 695 bad_page_fault(regs, regs->dar, SIGBUS); 696 return; 697 #endif 698 699 if (debugger_fault_handler(regs)) 700 return; 701 702 if (check_io_access(regs)) 703 return; 704 705 die("Machine check", regs, SIGBUS); 706 707 /* Must die if the interrupt is not recoverable */ 708 if (!(regs->msr & MSR_RI)) 709 panic("Unrecoverable Machine check"); 710 } 711 712 void SMIException(struct pt_regs *regs) 713 { 714 die("System Management Interrupt", regs, SIGABRT); 715 } 716 717 void unknown_exception(struct pt_regs *regs) 718 { 719 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 720 regs->nip, regs->msr, regs->trap); 721 722 _exception(SIGTRAP, regs, 0, 0); 723 } 724 725 void instruction_breakpoint_exception(struct pt_regs *regs) 726 { 727 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 728 5, SIGTRAP) == NOTIFY_STOP) 729 return; 730 if (debugger_iabr_match(regs)) 731 return; 732 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 733 } 734 735 void RunModeException(struct pt_regs *regs) 736 { 737 _exception(SIGTRAP, regs, 0, 0); 738 } 739 740 void __kprobes single_step_exception(struct pt_regs *regs) 741 { 742 clear_single_step(regs); 743 744 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 745 5, SIGTRAP) == NOTIFY_STOP) 746 return; 747 if (debugger_sstep(regs)) 748 return; 749 750 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 751 } 752 753 /* 754 * After we have successfully emulated an instruction, we have to 755 * check if the instruction was being single-stepped, and if so, 756 * pretend we got a single-step exception. This was pointed out 757 * by Kumar Gala. -- paulus 758 */ 759 static void emulate_single_step(struct pt_regs *regs) 760 { 761 if (single_stepping(regs)) 762 single_step_exception(regs); 763 } 764 765 static inline int __parse_fpscr(unsigned long fpscr) 766 { 767 int ret = 0; 768 769 /* Invalid operation */ 770 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 771 ret = FPE_FLTINV; 772 773 /* Overflow */ 774 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 775 ret = FPE_FLTOVF; 776 777 /* Underflow */ 778 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 779 ret = FPE_FLTUND; 780 781 /* Divide by zero */ 782 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 783 ret = FPE_FLTDIV; 784 785 /* Inexact result */ 786 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 787 ret = FPE_FLTRES; 788 789 return ret; 790 } 791 792 static void parse_fpe(struct pt_regs *regs) 793 { 794 int code = 0; 795 796 flush_fp_to_thread(current); 797 798 code = __parse_fpscr(current->thread.fpscr.val); 799 800 _exception(SIGFPE, regs, code, regs->nip); 801 } 802 803 /* 804 * Illegal instruction emulation support. Originally written to 805 * provide the PVR to user applications using the mfspr rd, PVR. 806 * Return non-zero if we can't emulate, or -EFAULT if the associated 807 * memory access caused an access fault. Return zero on success. 808 * 809 * There are a couple of ways to do this, either "decode" the instruction 810 * or directly match lots of bits. In this case, matching lots of 811 * bits is faster and easier. 812 * 813 */ 814 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 815 { 816 u8 rT = (instword >> 21) & 0x1f; 817 u8 rA = (instword >> 16) & 0x1f; 818 u8 NB_RB = (instword >> 11) & 0x1f; 819 u32 num_bytes; 820 unsigned long EA; 821 int pos = 0; 822 823 /* Early out if we are an invalid form of lswx */ 824 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 825 if ((rT == rA) || (rT == NB_RB)) 826 return -EINVAL; 827 828 EA = (rA == 0) ? 0 : regs->gpr[rA]; 829 830 switch (instword & PPC_INST_STRING_MASK) { 831 case PPC_INST_LSWX: 832 case PPC_INST_STSWX: 833 EA += NB_RB; 834 num_bytes = regs->xer & 0x7f; 835 break; 836 case PPC_INST_LSWI: 837 case PPC_INST_STSWI: 838 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 839 break; 840 default: 841 return -EINVAL; 842 } 843 844 while (num_bytes != 0) 845 { 846 u8 val; 847 u32 shift = 8 * (3 - (pos & 0x3)); 848 849 switch ((instword & PPC_INST_STRING_MASK)) { 850 case PPC_INST_LSWX: 851 case PPC_INST_LSWI: 852 if (get_user(val, (u8 __user *)EA)) 853 return -EFAULT; 854 /* first time updating this reg, 855 * zero it out */ 856 if (pos == 0) 857 regs->gpr[rT] = 0; 858 regs->gpr[rT] |= val << shift; 859 break; 860 case PPC_INST_STSWI: 861 case PPC_INST_STSWX: 862 val = regs->gpr[rT] >> shift; 863 if (put_user(val, (u8 __user *)EA)) 864 return -EFAULT; 865 break; 866 } 867 /* move EA to next address */ 868 EA += 1; 869 num_bytes--; 870 871 /* manage our position within the register */ 872 if (++pos == 4) { 873 pos = 0; 874 if (++rT == 32) 875 rT = 0; 876 } 877 } 878 879 return 0; 880 } 881 882 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 883 { 884 u32 ra,rs; 885 unsigned long tmp; 886 887 ra = (instword >> 16) & 0x1f; 888 rs = (instword >> 21) & 0x1f; 889 890 tmp = regs->gpr[rs]; 891 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 892 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 893 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 894 regs->gpr[ra] = tmp; 895 896 return 0; 897 } 898 899 static int emulate_isel(struct pt_regs *regs, u32 instword) 900 { 901 u8 rT = (instword >> 21) & 0x1f; 902 u8 rA = (instword >> 16) & 0x1f; 903 u8 rB = (instword >> 11) & 0x1f; 904 u8 BC = (instword >> 6) & 0x1f; 905 u8 bit; 906 unsigned long tmp; 907 908 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 909 bit = (regs->ccr >> (31 - BC)) & 0x1; 910 911 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 912 913 return 0; 914 } 915 916 static int emulate_instruction(struct pt_regs *regs) 917 { 918 u32 instword; 919 u32 rd; 920 921 if (!user_mode(regs) || (regs->msr & MSR_LE)) 922 return -EINVAL; 923 CHECK_FULL_REGS(regs); 924 925 if (get_user(instword, (u32 __user *)(regs->nip))) 926 return -EFAULT; 927 928 /* Emulate the mfspr rD, PVR. */ 929 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 930 PPC_WARN_EMULATED(mfpvr, regs); 931 rd = (instword >> 21) & 0x1f; 932 regs->gpr[rd] = mfspr(SPRN_PVR); 933 return 0; 934 } 935 936 /* Emulating the dcba insn is just a no-op. */ 937 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 938 PPC_WARN_EMULATED(dcba, regs); 939 return 0; 940 } 941 942 /* Emulate the mcrxr insn. */ 943 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 944 int shift = (instword >> 21) & 0x1c; 945 unsigned long msk = 0xf0000000UL >> shift; 946 947 PPC_WARN_EMULATED(mcrxr, regs); 948 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 949 regs->xer &= ~0xf0000000UL; 950 return 0; 951 } 952 953 /* Emulate load/store string insn. */ 954 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 955 PPC_WARN_EMULATED(string, regs); 956 return emulate_string_inst(regs, instword); 957 } 958 959 /* Emulate the popcntb (Population Count Bytes) instruction. */ 960 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 961 PPC_WARN_EMULATED(popcntb, regs); 962 return emulate_popcntb_inst(regs, instword); 963 } 964 965 /* Emulate isel (Integer Select) instruction */ 966 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 967 PPC_WARN_EMULATED(isel, regs); 968 return emulate_isel(regs, instword); 969 } 970 971 #ifdef CONFIG_PPC64 972 /* Emulate the mfspr rD, DSCR. */ 973 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 974 PPC_INST_MFSPR_DSCR_USER) || 975 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 976 PPC_INST_MFSPR_DSCR)) && 977 cpu_has_feature(CPU_FTR_DSCR)) { 978 PPC_WARN_EMULATED(mfdscr, regs); 979 rd = (instword >> 21) & 0x1f; 980 regs->gpr[rd] = mfspr(SPRN_DSCR); 981 return 0; 982 } 983 /* Emulate the mtspr DSCR, rD. */ 984 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 985 PPC_INST_MTSPR_DSCR_USER) || 986 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 987 PPC_INST_MTSPR_DSCR)) && 988 cpu_has_feature(CPU_FTR_DSCR)) { 989 PPC_WARN_EMULATED(mtdscr, regs); 990 rd = (instword >> 21) & 0x1f; 991 current->thread.dscr = regs->gpr[rd]; 992 current->thread.dscr_inherit = 1; 993 mtspr(SPRN_DSCR, current->thread.dscr); 994 return 0; 995 } 996 #endif 997 998 return -EINVAL; 999 } 1000 1001 int is_valid_bugaddr(unsigned long addr) 1002 { 1003 return is_kernel_addr(addr); 1004 } 1005 1006 void __kprobes program_check_exception(struct pt_regs *regs) 1007 { 1008 unsigned int reason = get_reason(regs); 1009 extern int do_mathemu(struct pt_regs *regs); 1010 1011 /* We can now get here via a FP Unavailable exception if the core 1012 * has no FPU, in that case the reason flags will be 0 */ 1013 1014 if (reason & REASON_FP) { 1015 /* IEEE FP exception */ 1016 parse_fpe(regs); 1017 return; 1018 } 1019 if (reason & REASON_TRAP) { 1020 /* Debugger is first in line to stop recursive faults in 1021 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1022 if (debugger_bpt(regs)) 1023 return; 1024 1025 /* trap exception */ 1026 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1027 == NOTIFY_STOP) 1028 return; 1029 1030 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1031 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 1032 regs->nip += 4; 1033 return; 1034 } 1035 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1036 return; 1037 } 1038 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1039 if (reason & REASON_TM) { 1040 /* This is a TM "Bad Thing Exception" program check. 1041 * This occurs when: 1042 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1043 * transition in TM states. 1044 * - A trechkpt is attempted when transactional. 1045 * - A treclaim is attempted when non transactional. 1046 * - A tend is illegally attempted. 1047 * - writing a TM SPR when transactional. 1048 */ 1049 if (!user_mode(regs) && 1050 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 1051 regs->nip += 4; 1052 return; 1053 } 1054 /* If usermode caused this, it's done something illegal and 1055 * gets a SIGILL slap on the wrist. We call it an illegal 1056 * operand to distinguish from the instruction just being bad 1057 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1058 * illegal /placement/ of a valid instruction. 1059 */ 1060 if (user_mode(regs)) { 1061 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1062 return; 1063 } else { 1064 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1065 "at %lx (msr 0x%x)\n", regs->nip, reason); 1066 die("Unrecoverable exception", regs, SIGABRT); 1067 } 1068 } 1069 #endif 1070 1071 /* We restore the interrupt state now */ 1072 if (!arch_irq_disabled_regs(regs)) 1073 local_irq_enable(); 1074 1075 #ifdef CONFIG_MATH_EMULATION 1076 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1077 * but there seems to be a hardware bug on the 405GP (RevD) 1078 * that means ESR is sometimes set incorrectly - either to 1079 * ESR_DST (!?) or 0. In the process of chasing this with the 1080 * hardware people - not sure if it can happen on any illegal 1081 * instruction or only on FP instructions, whether there is a 1082 * pattern to occurrences etc. -dgibson 31/Mar/2003 */ 1083 switch (do_mathemu(regs)) { 1084 case 0: 1085 emulate_single_step(regs); 1086 return; 1087 case 1: { 1088 int code = 0; 1089 code = __parse_fpscr(current->thread.fpscr.val); 1090 _exception(SIGFPE, regs, code, regs->nip); 1091 return; 1092 } 1093 case -EFAULT: 1094 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1095 return; 1096 } 1097 /* fall through on any other errors */ 1098 #endif /* CONFIG_MATH_EMULATION */ 1099 1100 /* Try to emulate it if we should. */ 1101 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1102 switch (emulate_instruction(regs)) { 1103 case 0: 1104 regs->nip += 4; 1105 emulate_single_step(regs); 1106 return; 1107 case -EFAULT: 1108 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1109 return; 1110 } 1111 } 1112 1113 if (reason & REASON_PRIVILEGED) 1114 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1115 else 1116 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1117 } 1118 1119 void alignment_exception(struct pt_regs *regs) 1120 { 1121 int sig, code, fixed = 0; 1122 1123 /* We restore the interrupt state now */ 1124 if (!arch_irq_disabled_regs(regs)) 1125 local_irq_enable(); 1126 1127 /* we don't implement logging of alignment exceptions */ 1128 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1129 fixed = fix_alignment(regs); 1130 1131 if (fixed == 1) { 1132 regs->nip += 4; /* skip over emulated instruction */ 1133 emulate_single_step(regs); 1134 return; 1135 } 1136 1137 /* Operand address was bad */ 1138 if (fixed == -EFAULT) { 1139 sig = SIGSEGV; 1140 code = SEGV_ACCERR; 1141 } else { 1142 sig = SIGBUS; 1143 code = BUS_ADRALN; 1144 } 1145 if (user_mode(regs)) 1146 _exception(sig, regs, code, regs->dar); 1147 else 1148 bad_page_fault(regs, regs->dar, sig); 1149 } 1150 1151 void StackOverflow(struct pt_regs *regs) 1152 { 1153 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 1154 current, regs->gpr[1]); 1155 debugger(regs); 1156 show_regs(regs); 1157 panic("kernel stack overflow"); 1158 } 1159 1160 void nonrecoverable_exception(struct pt_regs *regs) 1161 { 1162 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 1163 regs->nip, regs->msr); 1164 debugger(regs); 1165 die("nonrecoverable exception", regs, SIGKILL); 1166 } 1167 1168 void trace_syscall(struct pt_regs *regs) 1169 { 1170 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", 1171 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], 1172 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); 1173 } 1174 1175 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1176 { 1177 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1178 "%lx at %lx\n", regs->trap, regs->nip); 1179 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1180 } 1181 1182 void altivec_unavailable_exception(struct pt_regs *regs) 1183 { 1184 if (user_mode(regs)) { 1185 /* A user program has executed an altivec instruction, 1186 but this kernel doesn't support altivec. */ 1187 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1188 return; 1189 } 1190 1191 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1192 "%lx at %lx\n", regs->trap, regs->nip); 1193 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1194 } 1195 1196 void vsx_unavailable_exception(struct pt_regs *regs) 1197 { 1198 if (user_mode(regs)) { 1199 /* A user program has executed an vsx instruction, 1200 but this kernel doesn't support vsx. */ 1201 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1202 return; 1203 } 1204 1205 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1206 "%lx at %lx\n", regs->trap, regs->nip); 1207 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1208 } 1209 1210 void tm_unavailable_exception(struct pt_regs *regs) 1211 { 1212 /* We restore the interrupt state now */ 1213 if (!arch_irq_disabled_regs(regs)) 1214 local_irq_enable(); 1215 1216 /* Currently we never expect a TMU exception. Catch 1217 * this and kill the process! 1218 */ 1219 printk(KERN_EMERG "Unexpected TM unavailable exception at %lx " 1220 "(msr %lx)\n", 1221 regs->nip, regs->msr); 1222 1223 if (user_mode(regs)) { 1224 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1225 return; 1226 } 1227 1228 die("Unexpected TM unavailable exception", regs, SIGABRT); 1229 } 1230 1231 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1232 1233 extern void do_load_up_fpu(struct pt_regs *regs); 1234 1235 void fp_unavailable_tm(struct pt_regs *regs) 1236 { 1237 /* Note: This does not handle any kind of FP laziness. */ 1238 1239 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1240 regs->nip, regs->msr); 1241 tm_enable(); 1242 1243 /* We can only have got here if the task started using FP after 1244 * beginning the transaction. So, the transactional regs are just a 1245 * copy of the checkpointed ones. But, we still need to recheckpoint 1246 * as we're enabling FP for the process; it will return, abort the 1247 * transaction, and probably retry but now with FP enabled. So the 1248 * checkpointed FP registers need to be loaded. 1249 */ 1250 tm_reclaim(¤t->thread, current->thread.regs->msr, 1251 TM_CAUSE_FAC_UNAV); 1252 /* Reclaim didn't save out any FPRs to transact_fprs. */ 1253 1254 /* Enable FP for the task: */ 1255 regs->msr |= (MSR_FP | current->thread.fpexc_mode); 1256 1257 /* This loads and recheckpoints the FP registers from 1258 * thread.fpr[]. They will remain in registers after the 1259 * checkpoint so we don't need to reload them after. 1260 */ 1261 tm_recheckpoint(¤t->thread, regs->msr); 1262 } 1263 1264 #ifdef CONFIG_ALTIVEC 1265 extern void do_load_up_altivec(struct pt_regs *regs); 1266 1267 void altivec_unavailable_tm(struct pt_regs *regs) 1268 { 1269 /* See the comments in fp_unavailable_tm(). This function operates 1270 * the same way. 1271 */ 1272 1273 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1274 "MSR=%lx\n", 1275 regs->nip, regs->msr); 1276 tm_enable(); 1277 tm_reclaim(¤t->thread, current->thread.regs->msr, 1278 TM_CAUSE_FAC_UNAV); 1279 regs->msr |= MSR_VEC; 1280 tm_recheckpoint(¤t->thread, regs->msr); 1281 current->thread.used_vr = 1; 1282 } 1283 #endif 1284 1285 #ifdef CONFIG_VSX 1286 void vsx_unavailable_tm(struct pt_regs *regs) 1287 { 1288 /* See the comments in fp_unavailable_tm(). This works similarly, 1289 * though we're loading both FP and VEC registers in here. 1290 * 1291 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1292 * regs. Either way, set MSR_VSX. 1293 */ 1294 1295 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1296 "MSR=%lx\n", 1297 regs->nip, regs->msr); 1298 1299 tm_enable(); 1300 /* This reclaims FP and/or VR regs if they're already enabled */ 1301 tm_reclaim(¤t->thread, current->thread.regs->msr, 1302 TM_CAUSE_FAC_UNAV); 1303 1304 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | 1305 MSR_VSX; 1306 /* This loads & recheckpoints FP and VRs. */ 1307 tm_recheckpoint(¤t->thread, regs->msr); 1308 current->thread.used_vsr = 1; 1309 } 1310 #endif 1311 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1312 1313 void performance_monitor_exception(struct pt_regs *regs) 1314 { 1315 __get_cpu_var(irq_stat).pmu_irqs++; 1316 1317 perf_irq(regs); 1318 } 1319 1320 #ifdef CONFIG_8xx 1321 void SoftwareEmulation(struct pt_regs *regs) 1322 { 1323 extern int do_mathemu(struct pt_regs *); 1324 extern int Soft_emulate_8xx(struct pt_regs *); 1325 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) 1326 int errcode; 1327 #endif 1328 1329 CHECK_FULL_REGS(regs); 1330 1331 if (!user_mode(regs)) { 1332 debugger(regs); 1333 die("Kernel Mode Software FPU Emulation", regs, SIGFPE); 1334 } 1335 1336 #ifdef CONFIG_MATH_EMULATION 1337 errcode = do_mathemu(regs); 1338 if (errcode >= 0) 1339 PPC_WARN_EMULATED(math, regs); 1340 1341 switch (errcode) { 1342 case 0: 1343 emulate_single_step(regs); 1344 return; 1345 case 1: { 1346 int code = 0; 1347 code = __parse_fpscr(current->thread.fpscr.val); 1348 _exception(SIGFPE, regs, code, regs->nip); 1349 return; 1350 } 1351 case -EFAULT: 1352 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1353 return; 1354 default: 1355 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1356 return; 1357 } 1358 1359 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1360 errcode = Soft_emulate_8xx(regs); 1361 if (errcode >= 0) 1362 PPC_WARN_EMULATED(8xx, regs); 1363 1364 switch (errcode) { 1365 case 0: 1366 emulate_single_step(regs); 1367 return; 1368 case 1: 1369 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1370 return; 1371 case -EFAULT: 1372 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1373 return; 1374 } 1375 #else 1376 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1377 #endif 1378 } 1379 #endif /* CONFIG_8xx */ 1380 1381 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1382 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1383 { 1384 int changed = 0; 1385 /* 1386 * Determine the cause of the debug event, clear the 1387 * event flags and send a trap to the handler. Torez 1388 */ 1389 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1390 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1391 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1392 current->thread.dbcr2 &= ~DBCR2_DAC12MODE; 1393 #endif 1394 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, 1395 5); 1396 changed |= 0x01; 1397 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1398 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1399 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, 1400 6); 1401 changed |= 0x01; 1402 } else if (debug_status & DBSR_IAC1) { 1403 current->thread.dbcr0 &= ~DBCR0_IAC1; 1404 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1405 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, 1406 1); 1407 changed |= 0x01; 1408 } else if (debug_status & DBSR_IAC2) { 1409 current->thread.dbcr0 &= ~DBCR0_IAC2; 1410 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, 1411 2); 1412 changed |= 0x01; 1413 } else if (debug_status & DBSR_IAC3) { 1414 current->thread.dbcr0 &= ~DBCR0_IAC3; 1415 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1416 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, 1417 3); 1418 changed |= 0x01; 1419 } else if (debug_status & DBSR_IAC4) { 1420 current->thread.dbcr0 &= ~DBCR0_IAC4; 1421 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, 1422 4); 1423 changed |= 0x01; 1424 } 1425 /* 1426 * At the point this routine was called, the MSR(DE) was turned off. 1427 * Check all other debug flags and see if that bit needs to be turned 1428 * back on or not. 1429 */ 1430 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) 1431 regs->msr |= MSR_DE; 1432 else 1433 /* Make sure the IDM flag is off */ 1434 current->thread.dbcr0 &= ~DBCR0_IDM; 1435 1436 if (changed & 0x01) 1437 mtspr(SPRN_DBCR0, current->thread.dbcr0); 1438 } 1439 1440 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) 1441 { 1442 current->thread.dbsr = debug_status; 1443 1444 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1445 * on server, it stops on the target of the branch. In order to simulate 1446 * the server behaviour, we thus restart right away with a single step 1447 * instead of stopping here when hitting a BT 1448 */ 1449 if (debug_status & DBSR_BT) { 1450 regs->msr &= ~MSR_DE; 1451 1452 /* Disable BT */ 1453 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1454 /* Clear the BT event */ 1455 mtspr(SPRN_DBSR, DBSR_BT); 1456 1457 /* Do the single step trick only when coming from userspace */ 1458 if (user_mode(regs)) { 1459 current->thread.dbcr0 &= ~DBCR0_BT; 1460 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1461 regs->msr |= MSR_DE; 1462 return; 1463 } 1464 1465 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1466 5, SIGTRAP) == NOTIFY_STOP) { 1467 return; 1468 } 1469 if (debugger_sstep(regs)) 1470 return; 1471 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1472 regs->msr &= ~MSR_DE; 1473 1474 /* Disable instruction completion */ 1475 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1476 /* Clear the instruction completion event */ 1477 mtspr(SPRN_DBSR, DBSR_IC); 1478 1479 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1480 5, SIGTRAP) == NOTIFY_STOP) { 1481 return; 1482 } 1483 1484 if (debugger_sstep(regs)) 1485 return; 1486 1487 if (user_mode(regs)) { 1488 current->thread.dbcr0 &= ~DBCR0_IC; 1489 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, 1490 current->thread.dbcr1)) 1491 regs->msr |= MSR_DE; 1492 else 1493 /* Make sure the IDM bit is off */ 1494 current->thread.dbcr0 &= ~DBCR0_IDM; 1495 } 1496 1497 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1498 } else 1499 handle_debug(regs, debug_status); 1500 } 1501 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1502 1503 #if !defined(CONFIG_TAU_INT) 1504 void TAUException(struct pt_regs *regs) 1505 { 1506 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 1507 regs->nip, regs->msr, regs->trap, print_tainted()); 1508 } 1509 #endif /* CONFIG_INT_TAU */ 1510 1511 #ifdef CONFIG_ALTIVEC 1512 void altivec_assist_exception(struct pt_regs *regs) 1513 { 1514 int err; 1515 1516 if (!user_mode(regs)) { 1517 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 1518 " at %lx\n", regs->nip); 1519 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 1520 } 1521 1522 flush_altivec_to_thread(current); 1523 1524 PPC_WARN_EMULATED(altivec, regs); 1525 err = emulate_altivec(regs); 1526 if (err == 0) { 1527 regs->nip += 4; /* skip emulated instruction */ 1528 emulate_single_step(regs); 1529 return; 1530 } 1531 1532 if (err == -EFAULT) { 1533 /* got an error reading the instruction */ 1534 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1535 } else { 1536 /* didn't recognize the instruction */ 1537 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 1538 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 1539 "in %s at %lx\n", current->comm, regs->nip); 1540 current->thread.vscr.u[3] |= 0x10000; 1541 } 1542 } 1543 #endif /* CONFIG_ALTIVEC */ 1544 1545 #ifdef CONFIG_VSX 1546 void vsx_assist_exception(struct pt_regs *regs) 1547 { 1548 if (!user_mode(regs)) { 1549 printk(KERN_EMERG "VSX assist exception in kernel mode" 1550 " at %lx\n", regs->nip); 1551 die("Kernel VSX assist exception", regs, SIGILL); 1552 } 1553 1554 flush_vsx_to_thread(current); 1555 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); 1556 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1557 } 1558 #endif /* CONFIG_VSX */ 1559 1560 #ifdef CONFIG_FSL_BOOKE 1561 void CacheLockingException(struct pt_regs *regs, unsigned long address, 1562 unsigned long error_code) 1563 { 1564 /* We treat cache locking instructions from the user 1565 * as priv ops, in the future we could try to do 1566 * something smarter 1567 */ 1568 if (error_code & (ESR_DLK|ESR_ILK)) 1569 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1570 return; 1571 } 1572 #endif /* CONFIG_FSL_BOOKE */ 1573 1574 #ifdef CONFIG_SPE 1575 void SPEFloatingPointException(struct pt_regs *regs) 1576 { 1577 extern int do_spe_mathemu(struct pt_regs *regs); 1578 unsigned long spefscr; 1579 int fpexc_mode; 1580 int code = 0; 1581 int err; 1582 1583 flush_spe_to_thread(current); 1584 1585 spefscr = current->thread.spefscr; 1586 fpexc_mode = current->thread.fpexc_mode; 1587 1588 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1589 code = FPE_FLTOVF; 1590 } 1591 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1592 code = FPE_FLTUND; 1593 } 1594 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1595 code = FPE_FLTDIV; 1596 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1597 code = FPE_FLTINV; 1598 } 1599 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1600 code = FPE_FLTRES; 1601 1602 err = do_spe_mathemu(regs); 1603 if (err == 0) { 1604 regs->nip += 4; /* skip emulated instruction */ 1605 emulate_single_step(regs); 1606 return; 1607 } 1608 1609 if (err == -EFAULT) { 1610 /* got an error reading the instruction */ 1611 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1612 } else if (err == -EINVAL) { 1613 /* didn't recognize the instruction */ 1614 printk(KERN_ERR "unrecognized spe instruction " 1615 "in %s at %lx\n", current->comm, regs->nip); 1616 } else { 1617 _exception(SIGFPE, regs, code, regs->nip); 1618 } 1619 1620 return; 1621 } 1622 1623 void SPEFloatingPointRoundException(struct pt_regs *regs) 1624 { 1625 extern int speround_handler(struct pt_regs *regs); 1626 int err; 1627 1628 preempt_disable(); 1629 if (regs->msr & MSR_SPE) 1630 giveup_spe(current); 1631 preempt_enable(); 1632 1633 regs->nip -= 4; 1634 err = speround_handler(regs); 1635 if (err == 0) { 1636 regs->nip += 4; /* skip emulated instruction */ 1637 emulate_single_step(regs); 1638 return; 1639 } 1640 1641 if (err == -EFAULT) { 1642 /* got an error reading the instruction */ 1643 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1644 } else if (err == -EINVAL) { 1645 /* didn't recognize the instruction */ 1646 printk(KERN_ERR "unrecognized spe instruction " 1647 "in %s at %lx\n", current->comm, regs->nip); 1648 } else { 1649 _exception(SIGFPE, regs, 0, regs->nip); 1650 return; 1651 } 1652 } 1653 #endif 1654 1655 /* 1656 * We enter here if we get an unrecoverable exception, that is, one 1657 * that happened at a point where the RI (recoverable interrupt) bit 1658 * in the MSR is 0. This indicates that SRR0/1 are live, and that 1659 * we therefore lost state by taking this exception. 1660 */ 1661 void unrecoverable_exception(struct pt_regs *regs) 1662 { 1663 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 1664 regs->trap, regs->nip); 1665 die("Unrecoverable exception", regs, SIGABRT); 1666 } 1667 1668 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 1669 /* 1670 * Default handler for a Watchdog exception, 1671 * spins until a reboot occurs 1672 */ 1673 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 1674 { 1675 /* Generic WatchdogHandler, implement your own */ 1676 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 1677 return; 1678 } 1679 1680 void WatchdogException(struct pt_regs *regs) 1681 { 1682 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 1683 WatchdogHandler(regs); 1684 } 1685 #endif 1686 1687 /* 1688 * We enter here if we discover during exception entry that we are 1689 * running in supervisor mode with a userspace value in the stack pointer. 1690 */ 1691 void kernel_bad_stack(struct pt_regs *regs) 1692 { 1693 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 1694 regs->gpr[1], regs->nip); 1695 die("Bad kernel stack pointer", regs, SIGABRT); 1696 } 1697 1698 void __init trap_init(void) 1699 { 1700 } 1701 1702 1703 #ifdef CONFIG_PPC_EMULATED_STATS 1704 1705 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 1706 1707 struct ppc_emulated ppc_emulated = { 1708 #ifdef CONFIG_ALTIVEC 1709 WARN_EMULATED_SETUP(altivec), 1710 #endif 1711 WARN_EMULATED_SETUP(dcba), 1712 WARN_EMULATED_SETUP(dcbz), 1713 WARN_EMULATED_SETUP(fp_pair), 1714 WARN_EMULATED_SETUP(isel), 1715 WARN_EMULATED_SETUP(mcrxr), 1716 WARN_EMULATED_SETUP(mfpvr), 1717 WARN_EMULATED_SETUP(multiple), 1718 WARN_EMULATED_SETUP(popcntb), 1719 WARN_EMULATED_SETUP(spe), 1720 WARN_EMULATED_SETUP(string), 1721 WARN_EMULATED_SETUP(unaligned), 1722 #ifdef CONFIG_MATH_EMULATION 1723 WARN_EMULATED_SETUP(math), 1724 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1725 WARN_EMULATED_SETUP(8xx), 1726 #endif 1727 #ifdef CONFIG_VSX 1728 WARN_EMULATED_SETUP(vsx), 1729 #endif 1730 #ifdef CONFIG_PPC64 1731 WARN_EMULATED_SETUP(mfdscr), 1732 WARN_EMULATED_SETUP(mtdscr), 1733 #endif 1734 }; 1735 1736 u32 ppc_warn_emulated; 1737 1738 void ppc_warn_emulated_print(const char *type) 1739 { 1740 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 1741 type); 1742 } 1743 1744 static int __init ppc_warn_emulated_init(void) 1745 { 1746 struct dentry *dir, *d; 1747 unsigned int i; 1748 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 1749 1750 if (!powerpc_debugfs_root) 1751 return -ENODEV; 1752 1753 dir = debugfs_create_dir("emulated_instructions", 1754 powerpc_debugfs_root); 1755 if (!dir) 1756 return -ENOMEM; 1757 1758 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, 1759 &ppc_warn_emulated); 1760 if (!d) 1761 goto fail; 1762 1763 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 1764 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, 1765 (u32 *)&entries[i].val.counter); 1766 if (!d) 1767 goto fail; 1768 } 1769 1770 return 0; 1771 1772 fail: 1773 debugfs_remove_recursive(dir); 1774 return -ENOMEM; 1775 } 1776 1777 device_initcall(ppc_warn_emulated_init); 1778 1779 #endif /* CONFIG_PPC_EMULATED_STATS */ 1780