xref: /linux/arch/powerpc/kernel/traps.c (revision 6e8331ac6973435b1e7604c30f2ad394035b46e1)
1 /*
2  *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
3  *
4  *  This program is free software; you can redistribute it and/or
5  *  modify it under the terms of the GNU General Public License
6  *  as published by the Free Software Foundation; either version
7  *  2 of the License, or (at your option) any later version.
8  *
9  *  Modified by Cort Dougan (cort@cs.nmt.edu)
10  *  and Paul Mackerras (paulus@samba.org)
11  */
12 
13 /*
14  * This file handles the architecture-dependent parts of hardware exceptions
15  */
16 
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/mm.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/a.out.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/prctl.h>
31 #include <linux/delay.h>
32 #include <linux/kprobes.h>
33 #include <linux/kexec.h>
34 #include <linux/backlight.h>
35 
36 #include <asm/kdebug.h>
37 #include <asm/pgtable.h>
38 #include <asm/uaccess.h>
39 #include <asm/system.h>
40 #include <asm/io.h>
41 #include <asm/machdep.h>
42 #include <asm/rtas.h>
43 #include <asm/pmc.h>
44 #ifdef CONFIG_PPC32
45 #include <asm/reg.h>
46 #endif
47 #ifdef CONFIG_PMAC_BACKLIGHT
48 #include <asm/backlight.h>
49 #endif
50 #ifdef CONFIG_PPC64
51 #include <asm/firmware.h>
52 #include <asm/processor.h>
53 #endif
54 #include <asm/kexec.h>
55 
56 #ifdef CONFIG_PPC64	/* XXX */
57 #define _IO_BASE	pci_io_base
58 #ifdef CONFIG_KEXEC
59 cpumask_t cpus_in_sr = CPU_MASK_NONE;
60 #endif
61 #endif
62 
63 #ifdef CONFIG_DEBUGGER
64 int (*__debugger)(struct pt_regs *regs);
65 int (*__debugger_ipi)(struct pt_regs *regs);
66 int (*__debugger_bpt)(struct pt_regs *regs);
67 int (*__debugger_sstep)(struct pt_regs *regs);
68 int (*__debugger_iabr_match)(struct pt_regs *regs);
69 int (*__debugger_dabr_match)(struct pt_regs *regs);
70 int (*__debugger_fault_handler)(struct pt_regs *regs);
71 
72 EXPORT_SYMBOL(__debugger);
73 EXPORT_SYMBOL(__debugger_ipi);
74 EXPORT_SYMBOL(__debugger_bpt);
75 EXPORT_SYMBOL(__debugger_sstep);
76 EXPORT_SYMBOL(__debugger_iabr_match);
77 EXPORT_SYMBOL(__debugger_dabr_match);
78 EXPORT_SYMBOL(__debugger_fault_handler);
79 #endif
80 
81 ATOMIC_NOTIFIER_HEAD(powerpc_die_chain);
82 
83 int register_die_notifier(struct notifier_block *nb)
84 {
85 	return atomic_notifier_chain_register(&powerpc_die_chain, nb);
86 }
87 EXPORT_SYMBOL(register_die_notifier);
88 
89 int unregister_die_notifier(struct notifier_block *nb)
90 {
91 	return atomic_notifier_chain_unregister(&powerpc_die_chain, nb);
92 }
93 EXPORT_SYMBOL(unregister_die_notifier);
94 
95 /*
96  * Trap & Exception support
97  */
98 
99 static DEFINE_SPINLOCK(die_lock);
100 
101 int die(const char *str, struct pt_regs *regs, long err)
102 {
103 	static int die_counter;
104 
105 	if (debugger(regs))
106 		return 1;
107 
108 	console_verbose();
109 	spin_lock_irq(&die_lock);
110 	bust_spinlocks(1);
111 #ifdef CONFIG_PMAC_BACKLIGHT
112 	mutex_lock(&pmac_backlight_mutex);
113 	if (machine_is(powermac) && pmac_backlight) {
114 		struct backlight_properties *props;
115 
116 		down(&pmac_backlight->sem);
117 		props = pmac_backlight->props;
118 		props->brightness = props->max_brightness;
119 		props->power = FB_BLANK_UNBLANK;
120 		props->update_status(pmac_backlight);
121 		up(&pmac_backlight->sem);
122 	}
123 	mutex_unlock(&pmac_backlight_mutex);
124 #endif
125 	printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
126 #ifdef CONFIG_PREEMPT
127 	printk("PREEMPT ");
128 #endif
129 #ifdef CONFIG_SMP
130 	printk("SMP NR_CPUS=%d ", NR_CPUS);
131 #endif
132 #ifdef CONFIG_DEBUG_PAGEALLOC
133 	printk("DEBUG_PAGEALLOC ");
134 #endif
135 #ifdef CONFIG_NUMA
136 	printk("NUMA ");
137 #endif
138 	printk("%s\n", ppc_md.name ? "" : ppc_md.name);
139 
140 	print_modules();
141 	show_regs(regs);
142 	bust_spinlocks(0);
143 	spin_unlock_irq(&die_lock);
144 
145 	if (kexec_should_crash(current) ||
146 		kexec_sr_activated(smp_processor_id()))
147 		crash_kexec(regs);
148 	crash_kexec_secondary(regs);
149 
150 	if (in_interrupt())
151 		panic("Fatal exception in interrupt");
152 
153 	if (panic_on_oops)
154 		panic("Fatal exception: panic_on_oops");
155 
156 	do_exit(err);
157 
158 	return 0;
159 }
160 
161 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
162 {
163 	siginfo_t info;
164 
165 	if (!user_mode(regs)) {
166 		if (die("Exception in kernel mode", regs, signr))
167 			return;
168 	}
169 
170 	memset(&info, 0, sizeof(info));
171 	info.si_signo = signr;
172 	info.si_code = code;
173 	info.si_addr = (void __user *) addr;
174 	force_sig_info(signr, &info, current);
175 
176 	/*
177 	 * Init gets no signals that it doesn't have a handler for.
178 	 * That's all very well, but if it has caused a synchronous
179 	 * exception and we ignore the resulting signal, it will just
180 	 * generate the same exception over and over again and we get
181 	 * nowhere.  Better to kill it and let the kernel panic.
182 	 */
183 	if (current->pid == 1) {
184 		__sighandler_t handler;
185 
186 		spin_lock_irq(&current->sighand->siglock);
187 		handler = current->sighand->action[signr-1].sa.sa_handler;
188 		spin_unlock_irq(&current->sighand->siglock);
189 		if (handler == SIG_DFL) {
190 			/* init has generated a synchronous exception
191 			   and it doesn't have a handler for the signal */
192 			printk(KERN_CRIT "init has generated signal %d "
193 			       "but has no handler for it\n", signr);
194 			do_exit(signr);
195 		}
196 	}
197 }
198 
199 #ifdef CONFIG_PPC64
200 void system_reset_exception(struct pt_regs *regs)
201 {
202 	/* See if any machine dependent calls */
203 	if (ppc_md.system_reset_exception) {
204 		if (ppc_md.system_reset_exception(regs))
205 			return;
206 	}
207 
208 #ifdef CONFIG_KEXEC
209 	cpu_set(smp_processor_id(), cpus_in_sr);
210 #endif
211 
212 	die("System Reset", regs, SIGABRT);
213 
214 	/* Must die if the interrupt is not recoverable */
215 	if (!(regs->msr & MSR_RI))
216 		panic("Unrecoverable System Reset");
217 
218 	/* What should we do here? We could issue a shutdown or hard reset. */
219 }
220 #endif
221 
222 /*
223  * I/O accesses can cause machine checks on powermacs.
224  * Check if the NIP corresponds to the address of a sync
225  * instruction for which there is an entry in the exception
226  * table.
227  * Note that the 601 only takes a machine check on TEA
228  * (transfer error ack) signal assertion, and does not
229  * set any of the top 16 bits of SRR1.
230  *  -- paulus.
231  */
232 static inline int check_io_access(struct pt_regs *regs)
233 {
234 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
235 	unsigned long msr = regs->msr;
236 	const struct exception_table_entry *entry;
237 	unsigned int *nip = (unsigned int *)regs->nip;
238 
239 	if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
240 	    && (entry = search_exception_tables(regs->nip)) != NULL) {
241 		/*
242 		 * Check that it's a sync instruction, or somewhere
243 		 * in the twi; isync; nop sequence that inb/inw/inl uses.
244 		 * As the address is in the exception table
245 		 * we should be able to read the instr there.
246 		 * For the debug message, we look at the preceding
247 		 * load or store.
248 		 */
249 		if (*nip == 0x60000000)		/* nop */
250 			nip -= 2;
251 		else if (*nip == 0x4c00012c)	/* isync */
252 			--nip;
253 		if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
254 			/* sync or twi */
255 			unsigned int rb;
256 
257 			--nip;
258 			rb = (*nip >> 11) & 0x1f;
259 			printk(KERN_DEBUG "%s bad port %lx at %p\n",
260 			       (*nip & 0x100)? "OUT to": "IN from",
261 			       regs->gpr[rb] - _IO_BASE, nip);
262 			regs->msr |= MSR_RI;
263 			regs->nip = entry->fixup;
264 			return 1;
265 		}
266 	}
267 #endif /* CONFIG_PPC_PMAC && CONFIG_PPC32 */
268 	return 0;
269 }
270 
271 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
272 /* On 4xx, the reason for the machine check or program exception
273    is in the ESR. */
274 #define get_reason(regs)	((regs)->dsisr)
275 #ifndef CONFIG_FSL_BOOKE
276 #define get_mc_reason(regs)	((regs)->dsisr)
277 #else
278 #define get_mc_reason(regs)	(mfspr(SPRN_MCSR))
279 #endif
280 #define REASON_FP		ESR_FP
281 #define REASON_ILLEGAL		(ESR_PIL | ESR_PUO)
282 #define REASON_PRIVILEGED	ESR_PPR
283 #define REASON_TRAP		ESR_PTR
284 
285 /* single-step stuff */
286 #define single_stepping(regs)	(current->thread.dbcr0 & DBCR0_IC)
287 #define clear_single_step(regs)	(current->thread.dbcr0 &= ~DBCR0_IC)
288 
289 #else
290 /* On non-4xx, the reason for the machine check or program
291    exception is in the MSR. */
292 #define get_reason(regs)	((regs)->msr)
293 #define get_mc_reason(regs)	((regs)->msr)
294 #define REASON_FP		0x100000
295 #define REASON_ILLEGAL		0x80000
296 #define REASON_PRIVILEGED	0x40000
297 #define REASON_TRAP		0x20000
298 
299 #define single_stepping(regs)	((regs)->msr & MSR_SE)
300 #define clear_single_step(regs)	((regs)->msr &= ~MSR_SE)
301 #endif
302 
303 /*
304  * This is "fall-back" implementation for configurations
305  * which don't provide platform-specific machine check info
306  */
307 void __attribute__ ((weak))
308 platform_machine_check(struct pt_regs *regs)
309 {
310 }
311 
312 void machine_check_exception(struct pt_regs *regs)
313 {
314 	int recover = 0;
315 	unsigned long reason = get_mc_reason(regs);
316 
317 	/* See if any machine dependent calls */
318 	if (ppc_md.machine_check_exception)
319 		recover = ppc_md.machine_check_exception(regs);
320 
321 	if (recover)
322 		return;
323 
324 	if (user_mode(regs)) {
325 		regs->msr |= MSR_RI;
326 		_exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
327 		return;
328 	}
329 
330 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
331 	/* the qspan pci read routines can cause machine checks -- Cort */
332 	bad_page_fault(regs, regs->dar, SIGBUS);
333 	return;
334 #endif
335 
336 	if (debugger_fault_handler(regs)) {
337 		regs->msr |= MSR_RI;
338 		return;
339 	}
340 
341 	if (check_io_access(regs))
342 		return;
343 
344 #if defined(CONFIG_4xx) && !defined(CONFIG_440A)
345 	if (reason & ESR_IMCP) {
346 		printk("Instruction");
347 		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
348 	} else
349 		printk("Data");
350 	printk(" machine check in kernel mode.\n");
351 #elif defined(CONFIG_440A)
352 	printk("Machine check in kernel mode.\n");
353 	if (reason & ESR_IMCP){
354 		printk("Instruction Synchronous Machine Check exception\n");
355 		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
356 	}
357 	else {
358 		u32 mcsr = mfspr(SPRN_MCSR);
359 		if (mcsr & MCSR_IB)
360 			printk("Instruction Read PLB Error\n");
361 		if (mcsr & MCSR_DRB)
362 			printk("Data Read PLB Error\n");
363 		if (mcsr & MCSR_DWB)
364 			printk("Data Write PLB Error\n");
365 		if (mcsr & MCSR_TLBP)
366 			printk("TLB Parity Error\n");
367 		if (mcsr & MCSR_ICP){
368 			flush_instruction_cache();
369 			printk("I-Cache Parity Error\n");
370 		}
371 		if (mcsr & MCSR_DCSP)
372 			printk("D-Cache Search Parity Error\n");
373 		if (mcsr & MCSR_DCFP)
374 			printk("D-Cache Flush Parity Error\n");
375 		if (mcsr & MCSR_IMPE)
376 			printk("Machine Check exception is imprecise\n");
377 
378 		/* Clear MCSR */
379 		mtspr(SPRN_MCSR, mcsr);
380 	}
381 #elif defined (CONFIG_E500)
382 	printk("Machine check in kernel mode.\n");
383 	printk("Caused by (from MCSR=%lx): ", reason);
384 
385 	if (reason & MCSR_MCP)
386 		printk("Machine Check Signal\n");
387 	if (reason & MCSR_ICPERR)
388 		printk("Instruction Cache Parity Error\n");
389 	if (reason & MCSR_DCP_PERR)
390 		printk("Data Cache Push Parity Error\n");
391 	if (reason & MCSR_DCPERR)
392 		printk("Data Cache Parity Error\n");
393 	if (reason & MCSR_GL_CI)
394 		printk("Guarded Load or Cache-Inhibited stwcx.\n");
395 	if (reason & MCSR_BUS_IAERR)
396 		printk("Bus - Instruction Address Error\n");
397 	if (reason & MCSR_BUS_RAERR)
398 		printk("Bus - Read Address Error\n");
399 	if (reason & MCSR_BUS_WAERR)
400 		printk("Bus - Write Address Error\n");
401 	if (reason & MCSR_BUS_IBERR)
402 		printk("Bus - Instruction Data Error\n");
403 	if (reason & MCSR_BUS_RBERR)
404 		printk("Bus - Read Data Bus Error\n");
405 	if (reason & MCSR_BUS_WBERR)
406 		printk("Bus - Read Data Bus Error\n");
407 	if (reason & MCSR_BUS_IPERR)
408 		printk("Bus - Instruction Parity Error\n");
409 	if (reason & MCSR_BUS_RPERR)
410 		printk("Bus - Read Parity Error\n");
411 #elif defined (CONFIG_E200)
412 	printk("Machine check in kernel mode.\n");
413 	printk("Caused by (from MCSR=%lx): ", reason);
414 
415 	if (reason & MCSR_MCP)
416 		printk("Machine Check Signal\n");
417 	if (reason & MCSR_CP_PERR)
418 		printk("Cache Push Parity Error\n");
419 	if (reason & MCSR_CPERR)
420 		printk("Cache Parity Error\n");
421 	if (reason & MCSR_EXCP_ERR)
422 		printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
423 	if (reason & MCSR_BUS_IRERR)
424 		printk("Bus - Read Bus Error on instruction fetch\n");
425 	if (reason & MCSR_BUS_DRERR)
426 		printk("Bus - Read Bus Error on data load\n");
427 	if (reason & MCSR_BUS_WRERR)
428 		printk("Bus - Write Bus Error on buffered store or cache line push\n");
429 #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
430 	printk("Machine check in kernel mode.\n");
431 	printk("Caused by (from SRR1=%lx): ", reason);
432 	switch (reason & 0x601F0000) {
433 	case 0x80000:
434 		printk("Machine check signal\n");
435 		break;
436 	case 0:		/* for 601 */
437 	case 0x40000:
438 	case 0x140000:	/* 7450 MSS error and TEA */
439 		printk("Transfer error ack signal\n");
440 		break;
441 	case 0x20000:
442 		printk("Data parity error signal\n");
443 		break;
444 	case 0x10000:
445 		printk("Address parity error signal\n");
446 		break;
447 	case 0x20000000:
448 		printk("L1 Data Cache error\n");
449 		break;
450 	case 0x40000000:
451 		printk("L1 Instruction Cache error\n");
452 		break;
453 	case 0x00100000:
454 		printk("L2 data cache parity error\n");
455 		break;
456 	default:
457 		printk("Unknown values in msr\n");
458 	}
459 #endif /* CONFIG_4xx */
460 
461 	/*
462 	 * Optional platform-provided routine to print out
463 	 * additional info, e.g. bus error registers.
464 	 */
465 	platform_machine_check(regs);
466 
467 	if (debugger_fault_handler(regs))
468 		return;
469 	die("Machine check", regs, SIGBUS);
470 
471 	/* Must die if the interrupt is not recoverable */
472 	if (!(regs->msr & MSR_RI))
473 		panic("Unrecoverable Machine check");
474 }
475 
476 void SMIException(struct pt_regs *regs)
477 {
478 	die("System Management Interrupt", regs, SIGABRT);
479 }
480 
481 void unknown_exception(struct pt_regs *regs)
482 {
483 	printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
484 	       regs->nip, regs->msr, regs->trap);
485 
486 	_exception(SIGTRAP, regs, 0, 0);
487 }
488 
489 void instruction_breakpoint_exception(struct pt_regs *regs)
490 {
491 	if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
492 					5, SIGTRAP) == NOTIFY_STOP)
493 		return;
494 	if (debugger_iabr_match(regs))
495 		return;
496 	_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
497 }
498 
499 void RunModeException(struct pt_regs *regs)
500 {
501 	_exception(SIGTRAP, regs, 0, 0);
502 }
503 
504 void __kprobes single_step_exception(struct pt_regs *regs)
505 {
506 	regs->msr &= ~(MSR_SE | MSR_BE);  /* Turn off 'trace' bits */
507 
508 	if (notify_die(DIE_SSTEP, "single_step", regs, 5,
509 					5, SIGTRAP) == NOTIFY_STOP)
510 		return;
511 	if (debugger_sstep(regs))
512 		return;
513 
514 	_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
515 }
516 
517 /*
518  * After we have successfully emulated an instruction, we have to
519  * check if the instruction was being single-stepped, and if so,
520  * pretend we got a single-step exception.  This was pointed out
521  * by Kumar Gala.  -- paulus
522  */
523 static void emulate_single_step(struct pt_regs *regs)
524 {
525 	if (single_stepping(regs)) {
526 		clear_single_step(regs);
527 		_exception(SIGTRAP, regs, TRAP_TRACE, 0);
528 	}
529 }
530 
531 static void parse_fpe(struct pt_regs *regs)
532 {
533 	int code = 0;
534 	unsigned long fpscr;
535 
536 	flush_fp_to_thread(current);
537 
538 	fpscr = current->thread.fpscr.val;
539 
540 	/* Invalid operation */
541 	if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
542 		code = FPE_FLTINV;
543 
544 	/* Overflow */
545 	else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
546 		code = FPE_FLTOVF;
547 
548 	/* Underflow */
549 	else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
550 		code = FPE_FLTUND;
551 
552 	/* Divide by zero */
553 	else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
554 		code = FPE_FLTDIV;
555 
556 	/* Inexact result */
557 	else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
558 		code = FPE_FLTRES;
559 
560 	_exception(SIGFPE, regs, code, regs->nip);
561 }
562 
563 /*
564  * Illegal instruction emulation support.  Originally written to
565  * provide the PVR to user applications using the mfspr rd, PVR.
566  * Return non-zero if we can't emulate, or -EFAULT if the associated
567  * memory access caused an access fault.  Return zero on success.
568  *
569  * There are a couple of ways to do this, either "decode" the instruction
570  * or directly match lots of bits.  In this case, matching lots of
571  * bits is faster and easier.
572  *
573  */
574 #define INST_MFSPR_PVR		0x7c1f42a6
575 #define INST_MFSPR_PVR_MASK	0xfc1fffff
576 
577 #define INST_DCBA		0x7c0005ec
578 #define INST_DCBA_MASK		0x7c0007fe
579 
580 #define INST_MCRXR		0x7c000400
581 #define INST_MCRXR_MASK		0x7c0007fe
582 
583 #define INST_STRING		0x7c00042a
584 #define INST_STRING_MASK	0x7c0007fe
585 #define INST_STRING_GEN_MASK	0x7c00067e
586 #define INST_LSWI		0x7c0004aa
587 #define INST_LSWX		0x7c00042a
588 #define INST_STSWI		0x7c0005aa
589 #define INST_STSWX		0x7c00052a
590 
591 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
592 {
593 	u8 rT = (instword >> 21) & 0x1f;
594 	u8 rA = (instword >> 16) & 0x1f;
595 	u8 NB_RB = (instword >> 11) & 0x1f;
596 	u32 num_bytes;
597 	unsigned long EA;
598 	int pos = 0;
599 
600 	/* Early out if we are an invalid form of lswx */
601 	if ((instword & INST_STRING_MASK) == INST_LSWX)
602 		if ((rT == rA) || (rT == NB_RB))
603 			return -EINVAL;
604 
605 	EA = (rA == 0) ? 0 : regs->gpr[rA];
606 
607 	switch (instword & INST_STRING_MASK) {
608 		case INST_LSWX:
609 		case INST_STSWX:
610 			EA += NB_RB;
611 			num_bytes = regs->xer & 0x7f;
612 			break;
613 		case INST_LSWI:
614 		case INST_STSWI:
615 			num_bytes = (NB_RB == 0) ? 32 : NB_RB;
616 			break;
617 		default:
618 			return -EINVAL;
619 	}
620 
621 	while (num_bytes != 0)
622 	{
623 		u8 val;
624 		u32 shift = 8 * (3 - (pos & 0x3));
625 
626 		switch ((instword & INST_STRING_MASK)) {
627 			case INST_LSWX:
628 			case INST_LSWI:
629 				if (get_user(val, (u8 __user *)EA))
630 					return -EFAULT;
631 				/* first time updating this reg,
632 				 * zero it out */
633 				if (pos == 0)
634 					regs->gpr[rT] = 0;
635 				regs->gpr[rT] |= val << shift;
636 				break;
637 			case INST_STSWI:
638 			case INST_STSWX:
639 				val = regs->gpr[rT] >> shift;
640 				if (put_user(val, (u8 __user *)EA))
641 					return -EFAULT;
642 				break;
643 		}
644 		/* move EA to next address */
645 		EA += 1;
646 		num_bytes--;
647 
648 		/* manage our position within the register */
649 		if (++pos == 4) {
650 			pos = 0;
651 			if (++rT == 32)
652 				rT = 0;
653 		}
654 	}
655 
656 	return 0;
657 }
658 
659 static int emulate_instruction(struct pt_regs *regs)
660 {
661 	u32 instword;
662 	u32 rd;
663 
664 	if (!user_mode(regs) || (regs->msr & MSR_LE))
665 		return -EINVAL;
666 	CHECK_FULL_REGS(regs);
667 
668 	if (get_user(instword, (u32 __user *)(regs->nip)))
669 		return -EFAULT;
670 
671 	/* Emulate the mfspr rD, PVR. */
672 	if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
673 		rd = (instword >> 21) & 0x1f;
674 		regs->gpr[rd] = mfspr(SPRN_PVR);
675 		return 0;
676 	}
677 
678 	/* Emulating the dcba insn is just a no-op.  */
679 	if ((instword & INST_DCBA_MASK) == INST_DCBA)
680 		return 0;
681 
682 	/* Emulate the mcrxr insn.  */
683 	if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
684 		int shift = (instword >> 21) & 0x1c;
685 		unsigned long msk = 0xf0000000UL >> shift;
686 
687 		regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
688 		regs->xer &= ~0xf0000000UL;
689 		return 0;
690 	}
691 
692 	/* Emulate load/store string insn. */
693 	if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
694 		return emulate_string_inst(regs, instword);
695 
696 	return -EINVAL;
697 }
698 
699 /*
700  * Look through the list of trap instructions that are used for BUG(),
701  * BUG_ON() and WARN_ON() and see if we hit one.  At this point we know
702  * that the exception was caused by a trap instruction of some kind.
703  * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
704  * otherwise.
705  */
706 extern struct bug_entry __start___bug_table[], __stop___bug_table[];
707 
708 #ifndef CONFIG_MODULES
709 #define module_find_bug(x)	NULL
710 #endif
711 
712 struct bug_entry *find_bug(unsigned long bugaddr)
713 {
714 	struct bug_entry *bug;
715 
716 	for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
717 		if (bugaddr == bug->bug_addr)
718 			return bug;
719 	return module_find_bug(bugaddr);
720 }
721 
722 static int check_bug_trap(struct pt_regs *regs)
723 {
724 	struct bug_entry *bug;
725 	unsigned long addr;
726 
727 	if (regs->msr & MSR_PR)
728 		return 0;	/* not in kernel */
729 	addr = regs->nip;	/* address of trap instruction */
730 	if (addr < PAGE_OFFSET)
731 		return 0;
732 	bug = find_bug(regs->nip);
733 	if (bug == NULL)
734 		return 0;
735 	if (bug->line & BUG_WARNING_TRAP) {
736 		/* this is a WARN_ON rather than BUG/BUG_ON */
737 		printk(KERN_ERR "Badness in %s at %s:%ld\n",
738 		       bug->function, bug->file,
739 		       bug->line & ~BUG_WARNING_TRAP);
740 		dump_stack();
741 		return 1;
742 	}
743 	printk(KERN_CRIT "kernel BUG in %s at %s:%ld!\n",
744 	       bug->function, bug->file, bug->line);
745 
746 	return 0;
747 }
748 
749 void __kprobes program_check_exception(struct pt_regs *regs)
750 {
751 	unsigned int reason = get_reason(regs);
752 	extern int do_mathemu(struct pt_regs *regs);
753 
754 #ifdef CONFIG_MATH_EMULATION
755 	/* (reason & REASON_ILLEGAL) would be the obvious thing here,
756 	 * but there seems to be a hardware bug on the 405GP (RevD)
757 	 * that means ESR is sometimes set incorrectly - either to
758 	 * ESR_DST (!?) or 0.  In the process of chasing this with the
759 	 * hardware people - not sure if it can happen on any illegal
760 	 * instruction or only on FP instructions, whether there is a
761 	 * pattern to occurences etc. -dgibson 31/Mar/2003 */
762 	if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
763 		emulate_single_step(regs);
764 		return;
765 	}
766 #endif /* CONFIG_MATH_EMULATION */
767 
768 	if (reason & REASON_FP) {
769 		/* IEEE FP exception */
770 		parse_fpe(regs);
771 		return;
772 	}
773 	if (reason & REASON_TRAP) {
774 		/* trap exception */
775 		if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
776 				== NOTIFY_STOP)
777 			return;
778 		if (debugger_bpt(regs))
779 			return;
780 		if (check_bug_trap(regs)) {
781 			regs->nip += 4;
782 			return;
783 		}
784 		_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
785 		return;
786 	}
787 
788 	local_irq_enable();
789 
790 	/* Try to emulate it if we should. */
791 	if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
792 		switch (emulate_instruction(regs)) {
793 		case 0:
794 			regs->nip += 4;
795 			emulate_single_step(regs);
796 			return;
797 		case -EFAULT:
798 			_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
799 			return;
800 		}
801 	}
802 
803 	if (reason & REASON_PRIVILEGED)
804 		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
805 	else
806 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
807 }
808 
809 void alignment_exception(struct pt_regs *regs)
810 {
811 	int fixed = 0;
812 
813 	/* we don't implement logging of alignment exceptions */
814 	if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
815 		fixed = fix_alignment(regs);
816 
817 	if (fixed == 1) {
818 		regs->nip += 4;	/* skip over emulated instruction */
819 		emulate_single_step(regs);
820 		return;
821 	}
822 
823 	/* Operand address was bad */
824 	if (fixed == -EFAULT) {
825 		if (user_mode(regs))
826 			_exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
827 		else
828 			/* Search exception table */
829 			bad_page_fault(regs, regs->dar, SIGSEGV);
830 		return;
831 	}
832 	_exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
833 }
834 
835 void StackOverflow(struct pt_regs *regs)
836 {
837 	printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
838 	       current, regs->gpr[1]);
839 	debugger(regs);
840 	show_regs(regs);
841 	panic("kernel stack overflow");
842 }
843 
844 void nonrecoverable_exception(struct pt_regs *regs)
845 {
846 	printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
847 	       regs->nip, regs->msr);
848 	debugger(regs);
849 	die("nonrecoverable exception", regs, SIGKILL);
850 }
851 
852 void trace_syscall(struct pt_regs *regs)
853 {
854 	printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld    %s\n",
855 	       current, current->pid, regs->nip, regs->link, regs->gpr[0],
856 	       regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
857 }
858 
859 void kernel_fp_unavailable_exception(struct pt_regs *regs)
860 {
861 	printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
862 			  "%lx at %lx\n", regs->trap, regs->nip);
863 	die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
864 }
865 
866 void altivec_unavailable_exception(struct pt_regs *regs)
867 {
868 #if !defined(CONFIG_ALTIVEC)
869 	if (user_mode(regs)) {
870 		/* A user program has executed an altivec instruction,
871 		   but this kernel doesn't support altivec. */
872 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
873 		return;
874 	}
875 #endif
876 	printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
877 			"%lx at %lx\n", regs->trap, regs->nip);
878 	die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
879 }
880 
881 void performance_monitor_exception(struct pt_regs *regs)
882 {
883 	perf_irq(regs);
884 }
885 
886 #ifdef CONFIG_8xx
887 void SoftwareEmulation(struct pt_regs *regs)
888 {
889 	extern int do_mathemu(struct pt_regs *);
890 	extern int Soft_emulate_8xx(struct pt_regs *);
891 	int errcode;
892 
893 	CHECK_FULL_REGS(regs);
894 
895 	if (!user_mode(regs)) {
896 		debugger(regs);
897 		die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
898 	}
899 
900 #ifdef CONFIG_MATH_EMULATION
901 	errcode = do_mathemu(regs);
902 #else
903 	errcode = Soft_emulate_8xx(regs);
904 #endif
905 	if (errcode) {
906 		if (errcode > 0)
907 			_exception(SIGFPE, regs, 0, 0);
908 		else if (errcode == -EFAULT)
909 			_exception(SIGSEGV, regs, 0, 0);
910 		else
911 			_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
912 	} else
913 		emulate_single_step(regs);
914 }
915 #endif /* CONFIG_8xx */
916 
917 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
918 
919 void DebugException(struct pt_regs *regs, unsigned long debug_status)
920 {
921 	if (debug_status & DBSR_IC) {	/* instruction completion */
922 		regs->msr &= ~MSR_DE;
923 		if (user_mode(regs)) {
924 			current->thread.dbcr0 &= ~DBCR0_IC;
925 		} else {
926 			/* Disable instruction completion */
927 			mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
928 			/* Clear the instruction completion event */
929 			mtspr(SPRN_DBSR, DBSR_IC);
930 			if (debugger_sstep(regs))
931 				return;
932 		}
933 		_exception(SIGTRAP, regs, TRAP_TRACE, 0);
934 	}
935 }
936 #endif /* CONFIG_4xx || CONFIG_BOOKE */
937 
938 #if !defined(CONFIG_TAU_INT)
939 void TAUException(struct pt_regs *regs)
940 {
941 	printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
942 	       regs->nip, regs->msr, regs->trap, print_tainted());
943 }
944 #endif /* CONFIG_INT_TAU */
945 
946 #ifdef CONFIG_ALTIVEC
947 void altivec_assist_exception(struct pt_regs *regs)
948 {
949 	int err;
950 
951 	if (!user_mode(regs)) {
952 		printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
953 		       " at %lx\n", regs->nip);
954 		die("Kernel VMX/Altivec assist exception", regs, SIGILL);
955 	}
956 
957 	flush_altivec_to_thread(current);
958 
959 	err = emulate_altivec(regs);
960 	if (err == 0) {
961 		regs->nip += 4;		/* skip emulated instruction */
962 		emulate_single_step(regs);
963 		return;
964 	}
965 
966 	if (err == -EFAULT) {
967 		/* got an error reading the instruction */
968 		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
969 	} else {
970 		/* didn't recognize the instruction */
971 		/* XXX quick hack for now: set the non-Java bit in the VSCR */
972 		if (printk_ratelimit())
973 			printk(KERN_ERR "Unrecognized altivec instruction "
974 			       "in %s at %lx\n", current->comm, regs->nip);
975 		current->thread.vscr.u[3] |= 0x10000;
976 	}
977 }
978 #endif /* CONFIG_ALTIVEC */
979 
980 #ifdef CONFIG_FSL_BOOKE
981 void CacheLockingException(struct pt_regs *regs, unsigned long address,
982 			   unsigned long error_code)
983 {
984 	/* We treat cache locking instructions from the user
985 	 * as priv ops, in the future we could try to do
986 	 * something smarter
987 	 */
988 	if (error_code & (ESR_DLK|ESR_ILK))
989 		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
990 	return;
991 }
992 #endif /* CONFIG_FSL_BOOKE */
993 
994 #ifdef CONFIG_SPE
995 void SPEFloatingPointException(struct pt_regs *regs)
996 {
997 	unsigned long spefscr;
998 	int fpexc_mode;
999 	int code = 0;
1000 
1001 	spefscr = current->thread.spefscr;
1002 	fpexc_mode = current->thread.fpexc_mode;
1003 
1004 	/* Hardware does not neccessarily set sticky
1005 	 * underflow/overflow/invalid flags */
1006 	if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1007 		code = FPE_FLTOVF;
1008 		spefscr |= SPEFSCR_FOVFS;
1009 	}
1010 	else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1011 		code = FPE_FLTUND;
1012 		spefscr |= SPEFSCR_FUNFS;
1013 	}
1014 	else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1015 		code = FPE_FLTDIV;
1016 	else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1017 		code = FPE_FLTINV;
1018 		spefscr |= SPEFSCR_FINVS;
1019 	}
1020 	else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1021 		code = FPE_FLTRES;
1022 
1023 	current->thread.spefscr = spefscr;
1024 
1025 	_exception(SIGFPE, regs, code, regs->nip);
1026 	return;
1027 }
1028 #endif
1029 
1030 /*
1031  * We enter here if we get an unrecoverable exception, that is, one
1032  * that happened at a point where the RI (recoverable interrupt) bit
1033  * in the MSR is 0.  This indicates that SRR0/1 are live, and that
1034  * we therefore lost state by taking this exception.
1035  */
1036 void unrecoverable_exception(struct pt_regs *regs)
1037 {
1038 	printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1039 	       regs->trap, regs->nip);
1040 	die("Unrecoverable exception", regs, SIGABRT);
1041 }
1042 
1043 #ifdef CONFIG_BOOKE_WDT
1044 /*
1045  * Default handler for a Watchdog exception,
1046  * spins until a reboot occurs
1047  */
1048 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1049 {
1050 	/* Generic WatchdogHandler, implement your own */
1051 	mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1052 	return;
1053 }
1054 
1055 void WatchdogException(struct pt_regs *regs)
1056 {
1057 	printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1058 	WatchdogHandler(regs);
1059 }
1060 #endif
1061 
1062 /*
1063  * We enter here if we discover during exception entry that we are
1064  * running in supervisor mode with a userspace value in the stack pointer.
1065  */
1066 void kernel_bad_stack(struct pt_regs *regs)
1067 {
1068 	printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1069 	       regs->gpr[1], regs->nip);
1070 	die("Bad kernel stack pointer", regs, SIGABRT);
1071 }
1072 
1073 void __init trap_init(void)
1074 {
1075 }
1076