1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * Copyright 2007-2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * Modified by Cort Dougan (cort@cs.nmt.edu) 11 * and Paul Mackerras (paulus@samba.org) 12 */ 13 14 /* 15 * This file handles the architecture-dependent parts of hardware exceptions 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/kernel.h> 21 #include <linux/mm.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/user.h> 26 #include <linux/interrupt.h> 27 #include <linux/init.h> 28 #include <linux/module.h> 29 #include <linux/prctl.h> 30 #include <linux/delay.h> 31 #include <linux/kprobes.h> 32 #include <linux/kexec.h> 33 #include <linux/backlight.h> 34 #include <linux/bug.h> 35 #include <linux/kdebug.h> 36 #include <linux/debugfs.h> 37 38 #include <asm/emulated_ops.h> 39 #include <asm/pgtable.h> 40 #include <asm/uaccess.h> 41 #include <asm/system.h> 42 #include <asm/io.h> 43 #include <asm/machdep.h> 44 #include <asm/rtas.h> 45 #include <asm/pmc.h> 46 #ifdef CONFIG_PPC32 47 #include <asm/reg.h> 48 #endif 49 #ifdef CONFIG_PMAC_BACKLIGHT 50 #include <asm/backlight.h> 51 #endif 52 #ifdef CONFIG_PPC64 53 #include <asm/firmware.h> 54 #include <asm/processor.h> 55 #endif 56 #include <asm/kexec.h> 57 #include <asm/ppc-opcode.h> 58 #ifdef CONFIG_FSL_BOOKE 59 #include <asm/dbell.h> 60 #endif 61 62 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) 63 int (*__debugger)(struct pt_regs *regs) __read_mostly; 64 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 65 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 66 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 67 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 68 int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly; 69 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 70 71 EXPORT_SYMBOL(__debugger); 72 EXPORT_SYMBOL(__debugger_ipi); 73 EXPORT_SYMBOL(__debugger_bpt); 74 EXPORT_SYMBOL(__debugger_sstep); 75 EXPORT_SYMBOL(__debugger_iabr_match); 76 EXPORT_SYMBOL(__debugger_dabr_match); 77 EXPORT_SYMBOL(__debugger_fault_handler); 78 #endif 79 80 /* 81 * Trap & Exception support 82 */ 83 84 #ifdef CONFIG_PMAC_BACKLIGHT 85 static void pmac_backlight_unblank(void) 86 { 87 mutex_lock(&pmac_backlight_mutex); 88 if (pmac_backlight) { 89 struct backlight_properties *props; 90 91 props = &pmac_backlight->props; 92 props->brightness = props->max_brightness; 93 props->power = FB_BLANK_UNBLANK; 94 backlight_update_status(pmac_backlight); 95 } 96 mutex_unlock(&pmac_backlight_mutex); 97 } 98 #else 99 static inline void pmac_backlight_unblank(void) { } 100 #endif 101 102 int die(const char *str, struct pt_regs *regs, long err) 103 { 104 static struct { 105 raw_spinlock_t lock; 106 u32 lock_owner; 107 int lock_owner_depth; 108 } die = { 109 .lock = __RAW_SPIN_LOCK_UNLOCKED(die.lock), 110 .lock_owner = -1, 111 .lock_owner_depth = 0 112 }; 113 static int die_counter; 114 unsigned long flags; 115 116 if (debugger(regs)) 117 return 1; 118 119 oops_enter(); 120 121 if (die.lock_owner != raw_smp_processor_id()) { 122 console_verbose(); 123 raw_spin_lock_irqsave(&die.lock, flags); 124 die.lock_owner = smp_processor_id(); 125 die.lock_owner_depth = 0; 126 bust_spinlocks(1); 127 if (machine_is(powermac)) 128 pmac_backlight_unblank(); 129 } else { 130 local_save_flags(flags); 131 } 132 133 if (++die.lock_owner_depth < 3) { 134 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 135 #ifdef CONFIG_PREEMPT 136 printk("PREEMPT "); 137 #endif 138 #ifdef CONFIG_SMP 139 printk("SMP NR_CPUS=%d ", NR_CPUS); 140 #endif 141 #ifdef CONFIG_DEBUG_PAGEALLOC 142 printk("DEBUG_PAGEALLOC "); 143 #endif 144 #ifdef CONFIG_NUMA 145 printk("NUMA "); 146 #endif 147 printk("%s\n", ppc_md.name ? ppc_md.name : ""); 148 149 sysfs_printk_last_file(); 150 if (notify_die(DIE_OOPS, str, regs, err, 255, 151 SIGSEGV) == NOTIFY_STOP) 152 return 1; 153 154 print_modules(); 155 show_regs(regs); 156 } else { 157 printk("Recursive die() failure, output suppressed\n"); 158 } 159 160 bust_spinlocks(0); 161 die.lock_owner = -1; 162 add_taint(TAINT_DIE); 163 raw_spin_unlock_irqrestore(&die.lock, flags); 164 165 if (kexec_should_crash(current) || 166 kexec_sr_activated(smp_processor_id())) 167 crash_kexec(regs); 168 crash_kexec_secondary(regs); 169 170 if (in_interrupt()) 171 panic("Fatal exception in interrupt"); 172 173 if (panic_on_oops) 174 panic("Fatal exception"); 175 176 oops_exit(); 177 do_exit(err); 178 179 return 0; 180 } 181 182 void user_single_step_siginfo(struct task_struct *tsk, 183 struct pt_regs *regs, siginfo_t *info) 184 { 185 memset(info, 0, sizeof(*info)); 186 info->si_signo = SIGTRAP; 187 info->si_code = TRAP_TRACE; 188 info->si_addr = (void __user *)regs->nip; 189 } 190 191 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 192 { 193 siginfo_t info; 194 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 195 "at %08lx nip %08lx lr %08lx code %x\n"; 196 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 197 "at %016lx nip %016lx lr %016lx code %x\n"; 198 199 if (!user_mode(regs)) { 200 if (die("Exception in kernel mode", regs, signr)) 201 return; 202 } else if (show_unhandled_signals && 203 unhandled_signal(current, signr) && 204 printk_ratelimit()) { 205 printk(regs->msr & MSR_SF ? fmt64 : fmt32, 206 current->comm, current->pid, signr, 207 addr, regs->nip, regs->link, code); 208 } 209 210 memset(&info, 0, sizeof(info)); 211 info.si_signo = signr; 212 info.si_code = code; 213 info.si_addr = (void __user *) addr; 214 force_sig_info(signr, &info, current); 215 } 216 217 #ifdef CONFIG_PPC64 218 void system_reset_exception(struct pt_regs *regs) 219 { 220 /* See if any machine dependent calls */ 221 if (ppc_md.system_reset_exception) { 222 if (ppc_md.system_reset_exception(regs)) 223 return; 224 } 225 226 #ifdef CONFIG_KEXEC 227 cpu_set(smp_processor_id(), cpus_in_sr); 228 #endif 229 230 die("System Reset", regs, SIGABRT); 231 232 /* 233 * Some CPUs when released from the debugger will execute this path. 234 * These CPUs entered the debugger via a soft-reset. If the CPU was 235 * hung before entering the debugger it will return to the hung 236 * state when exiting this function. This causes a problem in 237 * kdump since the hung CPU(s) will not respond to the IPI sent 238 * from kdump. To prevent the problem we call crash_kexec_secondary() 239 * here. If a kdump had not been initiated or we exit the debugger 240 * with the "exit and recover" command (x) crash_kexec_secondary() 241 * will return after 5ms and the CPU returns to its previous state. 242 */ 243 crash_kexec_secondary(regs); 244 245 /* Must die if the interrupt is not recoverable */ 246 if (!(regs->msr & MSR_RI)) 247 panic("Unrecoverable System Reset"); 248 249 /* What should we do here? We could issue a shutdown or hard reset. */ 250 } 251 #endif 252 253 /* 254 * I/O accesses can cause machine checks on powermacs. 255 * Check if the NIP corresponds to the address of a sync 256 * instruction for which there is an entry in the exception 257 * table. 258 * Note that the 601 only takes a machine check on TEA 259 * (transfer error ack) signal assertion, and does not 260 * set any of the top 16 bits of SRR1. 261 * -- paulus. 262 */ 263 static inline int check_io_access(struct pt_regs *regs) 264 { 265 #ifdef CONFIG_PPC32 266 unsigned long msr = regs->msr; 267 const struct exception_table_entry *entry; 268 unsigned int *nip = (unsigned int *)regs->nip; 269 270 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 271 && (entry = search_exception_tables(regs->nip)) != NULL) { 272 /* 273 * Check that it's a sync instruction, or somewhere 274 * in the twi; isync; nop sequence that inb/inw/inl uses. 275 * As the address is in the exception table 276 * we should be able to read the instr there. 277 * For the debug message, we look at the preceding 278 * load or store. 279 */ 280 if (*nip == 0x60000000) /* nop */ 281 nip -= 2; 282 else if (*nip == 0x4c00012c) /* isync */ 283 --nip; 284 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { 285 /* sync or twi */ 286 unsigned int rb; 287 288 --nip; 289 rb = (*nip >> 11) & 0x1f; 290 printk(KERN_DEBUG "%s bad port %lx at %p\n", 291 (*nip & 0x100)? "OUT to": "IN from", 292 regs->gpr[rb] - _IO_BASE, nip); 293 regs->msr |= MSR_RI; 294 regs->nip = entry->fixup; 295 return 1; 296 } 297 } 298 #endif /* CONFIG_PPC32 */ 299 return 0; 300 } 301 302 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 303 /* On 4xx, the reason for the machine check or program exception 304 is in the ESR. */ 305 #define get_reason(regs) ((regs)->dsisr) 306 #ifndef CONFIG_FSL_BOOKE 307 #define get_mc_reason(regs) ((regs)->dsisr) 308 #else 309 #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) 310 #endif 311 #define REASON_FP ESR_FP 312 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 313 #define REASON_PRIVILEGED ESR_PPR 314 #define REASON_TRAP ESR_PTR 315 316 /* single-step stuff */ 317 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) 318 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) 319 320 #else 321 /* On non-4xx, the reason for the machine check or program 322 exception is in the MSR. */ 323 #define get_reason(regs) ((regs)->msr) 324 #define get_mc_reason(regs) ((regs)->msr) 325 #define REASON_FP 0x100000 326 #define REASON_ILLEGAL 0x80000 327 #define REASON_PRIVILEGED 0x40000 328 #define REASON_TRAP 0x20000 329 330 #define single_stepping(regs) ((regs)->msr & MSR_SE) 331 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 332 #endif 333 334 #if defined(CONFIG_4xx) 335 int machine_check_4xx(struct pt_regs *regs) 336 { 337 unsigned long reason = get_mc_reason(regs); 338 339 if (reason & ESR_IMCP) { 340 printk("Instruction"); 341 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 342 } else 343 printk("Data"); 344 printk(" machine check in kernel mode.\n"); 345 346 return 0; 347 } 348 349 int machine_check_440A(struct pt_regs *regs) 350 { 351 unsigned long reason = get_mc_reason(regs); 352 353 printk("Machine check in kernel mode.\n"); 354 if (reason & ESR_IMCP){ 355 printk("Instruction Synchronous Machine Check exception\n"); 356 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 357 } 358 else { 359 u32 mcsr = mfspr(SPRN_MCSR); 360 if (mcsr & MCSR_IB) 361 printk("Instruction Read PLB Error\n"); 362 if (mcsr & MCSR_DRB) 363 printk("Data Read PLB Error\n"); 364 if (mcsr & MCSR_DWB) 365 printk("Data Write PLB Error\n"); 366 if (mcsr & MCSR_TLBP) 367 printk("TLB Parity Error\n"); 368 if (mcsr & MCSR_ICP){ 369 flush_instruction_cache(); 370 printk("I-Cache Parity Error\n"); 371 } 372 if (mcsr & MCSR_DCSP) 373 printk("D-Cache Search Parity Error\n"); 374 if (mcsr & MCSR_DCFP) 375 printk("D-Cache Flush Parity Error\n"); 376 if (mcsr & MCSR_IMPE) 377 printk("Machine Check exception is imprecise\n"); 378 379 /* Clear MCSR */ 380 mtspr(SPRN_MCSR, mcsr); 381 } 382 return 0; 383 } 384 385 int machine_check_47x(struct pt_regs *regs) 386 { 387 unsigned long reason = get_mc_reason(regs); 388 u32 mcsr; 389 390 printk(KERN_ERR "Machine check in kernel mode.\n"); 391 if (reason & ESR_IMCP) { 392 printk(KERN_ERR 393 "Instruction Synchronous Machine Check exception\n"); 394 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 395 return 0; 396 } 397 mcsr = mfspr(SPRN_MCSR); 398 if (mcsr & MCSR_IB) 399 printk(KERN_ERR "Instruction Read PLB Error\n"); 400 if (mcsr & MCSR_DRB) 401 printk(KERN_ERR "Data Read PLB Error\n"); 402 if (mcsr & MCSR_DWB) 403 printk(KERN_ERR "Data Write PLB Error\n"); 404 if (mcsr & MCSR_TLBP) 405 printk(KERN_ERR "TLB Parity Error\n"); 406 if (mcsr & MCSR_ICP) { 407 flush_instruction_cache(); 408 printk(KERN_ERR "I-Cache Parity Error\n"); 409 } 410 if (mcsr & MCSR_DCSP) 411 printk(KERN_ERR "D-Cache Search Parity Error\n"); 412 if (mcsr & PPC47x_MCSR_GPR) 413 printk(KERN_ERR "GPR Parity Error\n"); 414 if (mcsr & PPC47x_MCSR_FPR) 415 printk(KERN_ERR "FPR Parity Error\n"); 416 if (mcsr & PPC47x_MCSR_IPR) 417 printk(KERN_ERR "Machine Check exception is imprecise\n"); 418 419 /* Clear MCSR */ 420 mtspr(SPRN_MCSR, mcsr); 421 422 return 0; 423 } 424 #elif defined(CONFIG_E500) 425 int machine_check_e500mc(struct pt_regs *regs) 426 { 427 unsigned long mcsr = mfspr(SPRN_MCSR); 428 unsigned long reason = mcsr; 429 int recoverable = 1; 430 431 printk("Machine check in kernel mode.\n"); 432 printk("Caused by (from MCSR=%lx): ", reason); 433 434 if (reason & MCSR_MCP) 435 printk("Machine Check Signal\n"); 436 437 if (reason & MCSR_ICPERR) { 438 printk("Instruction Cache Parity Error\n"); 439 440 /* 441 * This is recoverable by invalidating the i-cache. 442 */ 443 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 444 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 445 ; 446 447 /* 448 * This will generally be accompanied by an instruction 449 * fetch error report -- only treat MCSR_IF as fatal 450 * if it wasn't due to an L1 parity error. 451 */ 452 reason &= ~MCSR_IF; 453 } 454 455 if (reason & MCSR_DCPERR_MC) { 456 printk("Data Cache Parity Error\n"); 457 recoverable = 0; 458 } 459 460 if (reason & MCSR_L2MMU_MHIT) { 461 printk("Hit on multiple TLB entries\n"); 462 recoverable = 0; 463 } 464 465 if (reason & MCSR_NMI) 466 printk("Non-maskable interrupt\n"); 467 468 if (reason & MCSR_IF) { 469 printk("Instruction Fetch Error Report\n"); 470 recoverable = 0; 471 } 472 473 if (reason & MCSR_LD) { 474 printk("Load Error Report\n"); 475 recoverable = 0; 476 } 477 478 if (reason & MCSR_ST) { 479 printk("Store Error Report\n"); 480 recoverable = 0; 481 } 482 483 if (reason & MCSR_LDG) { 484 printk("Guarded Load Error Report\n"); 485 recoverable = 0; 486 } 487 488 if (reason & MCSR_TLBSYNC) 489 printk("Simultaneous tlbsync operations\n"); 490 491 if (reason & MCSR_BSL2_ERR) { 492 printk("Level 2 Cache Error\n"); 493 recoverable = 0; 494 } 495 496 if (reason & MCSR_MAV) { 497 u64 addr; 498 499 addr = mfspr(SPRN_MCAR); 500 addr |= (u64)mfspr(SPRN_MCARU) << 32; 501 502 printk("Machine Check %s Address: %#llx\n", 503 reason & MCSR_MEA ? "Effective" : "Physical", addr); 504 } 505 506 mtspr(SPRN_MCSR, mcsr); 507 return mfspr(SPRN_MCSR) == 0 && recoverable; 508 } 509 510 int machine_check_e500(struct pt_regs *regs) 511 { 512 unsigned long reason = get_mc_reason(regs); 513 514 printk("Machine check in kernel mode.\n"); 515 printk("Caused by (from MCSR=%lx): ", reason); 516 517 if (reason & MCSR_MCP) 518 printk("Machine Check Signal\n"); 519 if (reason & MCSR_ICPERR) 520 printk("Instruction Cache Parity Error\n"); 521 if (reason & MCSR_DCP_PERR) 522 printk("Data Cache Push Parity Error\n"); 523 if (reason & MCSR_DCPERR) 524 printk("Data Cache Parity Error\n"); 525 if (reason & MCSR_BUS_IAERR) 526 printk("Bus - Instruction Address Error\n"); 527 if (reason & MCSR_BUS_RAERR) 528 printk("Bus - Read Address Error\n"); 529 if (reason & MCSR_BUS_WAERR) 530 printk("Bus - Write Address Error\n"); 531 if (reason & MCSR_BUS_IBERR) 532 printk("Bus - Instruction Data Error\n"); 533 if (reason & MCSR_BUS_RBERR) 534 printk("Bus - Read Data Bus Error\n"); 535 if (reason & MCSR_BUS_WBERR) 536 printk("Bus - Read Data Bus Error\n"); 537 if (reason & MCSR_BUS_IPERR) 538 printk("Bus - Instruction Parity Error\n"); 539 if (reason & MCSR_BUS_RPERR) 540 printk("Bus - Read Parity Error\n"); 541 542 return 0; 543 } 544 #elif defined(CONFIG_E200) 545 int machine_check_e200(struct pt_regs *regs) 546 { 547 unsigned long reason = get_mc_reason(regs); 548 549 printk("Machine check in kernel mode.\n"); 550 printk("Caused by (from MCSR=%lx): ", reason); 551 552 if (reason & MCSR_MCP) 553 printk("Machine Check Signal\n"); 554 if (reason & MCSR_CP_PERR) 555 printk("Cache Push Parity Error\n"); 556 if (reason & MCSR_CPERR) 557 printk("Cache Parity Error\n"); 558 if (reason & MCSR_EXCP_ERR) 559 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 560 if (reason & MCSR_BUS_IRERR) 561 printk("Bus - Read Bus Error on instruction fetch\n"); 562 if (reason & MCSR_BUS_DRERR) 563 printk("Bus - Read Bus Error on data load\n"); 564 if (reason & MCSR_BUS_WRERR) 565 printk("Bus - Write Bus Error on buffered store or cache line push\n"); 566 567 return 0; 568 } 569 #else 570 int machine_check_generic(struct pt_regs *regs) 571 { 572 unsigned long reason = get_mc_reason(regs); 573 574 printk("Machine check in kernel mode.\n"); 575 printk("Caused by (from SRR1=%lx): ", reason); 576 switch (reason & 0x601F0000) { 577 case 0x80000: 578 printk("Machine check signal\n"); 579 break; 580 case 0: /* for 601 */ 581 case 0x40000: 582 case 0x140000: /* 7450 MSS error and TEA */ 583 printk("Transfer error ack signal\n"); 584 break; 585 case 0x20000: 586 printk("Data parity error signal\n"); 587 break; 588 case 0x10000: 589 printk("Address parity error signal\n"); 590 break; 591 case 0x20000000: 592 printk("L1 Data Cache error\n"); 593 break; 594 case 0x40000000: 595 printk("L1 Instruction Cache error\n"); 596 break; 597 case 0x00100000: 598 printk("L2 data cache parity error\n"); 599 break; 600 default: 601 printk("Unknown values in msr\n"); 602 } 603 return 0; 604 } 605 #endif /* everything else */ 606 607 void machine_check_exception(struct pt_regs *regs) 608 { 609 int recover = 0; 610 611 __get_cpu_var(irq_stat).mce_exceptions++; 612 613 /* See if any machine dependent calls. In theory, we would want 614 * to call the CPU first, and call the ppc_md. one if the CPU 615 * one returns a positive number. However there is existing code 616 * that assumes the board gets a first chance, so let's keep it 617 * that way for now and fix things later. --BenH. 618 */ 619 if (ppc_md.machine_check_exception) 620 recover = ppc_md.machine_check_exception(regs); 621 else if (cur_cpu_spec->machine_check) 622 recover = cur_cpu_spec->machine_check(regs); 623 624 if (recover > 0) 625 return; 626 627 if (user_mode(regs)) { 628 regs->msr |= MSR_RI; 629 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); 630 return; 631 } 632 633 #if defined(CONFIG_8xx) && defined(CONFIG_PCI) 634 /* the qspan pci read routines can cause machine checks -- Cort 635 * 636 * yuck !!! that totally needs to go away ! There are better ways 637 * to deal with that than having a wart in the mcheck handler. 638 * -- BenH 639 */ 640 bad_page_fault(regs, regs->dar, SIGBUS); 641 return; 642 #endif 643 644 if (debugger_fault_handler(regs)) { 645 regs->msr |= MSR_RI; 646 return; 647 } 648 649 if (check_io_access(regs)) 650 return; 651 652 if (debugger_fault_handler(regs)) 653 return; 654 die("Machine check", regs, SIGBUS); 655 656 /* Must die if the interrupt is not recoverable */ 657 if (!(regs->msr & MSR_RI)) 658 panic("Unrecoverable Machine check"); 659 } 660 661 void SMIException(struct pt_regs *regs) 662 { 663 die("System Management Interrupt", regs, SIGABRT); 664 } 665 666 void unknown_exception(struct pt_regs *regs) 667 { 668 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 669 regs->nip, regs->msr, regs->trap); 670 671 _exception(SIGTRAP, regs, 0, 0); 672 } 673 674 void instruction_breakpoint_exception(struct pt_regs *regs) 675 { 676 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 677 5, SIGTRAP) == NOTIFY_STOP) 678 return; 679 if (debugger_iabr_match(regs)) 680 return; 681 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 682 } 683 684 void RunModeException(struct pt_regs *regs) 685 { 686 _exception(SIGTRAP, regs, 0, 0); 687 } 688 689 void __kprobes single_step_exception(struct pt_regs *regs) 690 { 691 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ 692 693 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 694 5, SIGTRAP) == NOTIFY_STOP) 695 return; 696 if (debugger_sstep(regs)) 697 return; 698 699 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 700 } 701 702 /* 703 * After we have successfully emulated an instruction, we have to 704 * check if the instruction was being single-stepped, and if so, 705 * pretend we got a single-step exception. This was pointed out 706 * by Kumar Gala. -- paulus 707 */ 708 static void emulate_single_step(struct pt_regs *regs) 709 { 710 if (single_stepping(regs)) { 711 clear_single_step(regs); 712 _exception(SIGTRAP, regs, TRAP_TRACE, 0); 713 } 714 } 715 716 static inline int __parse_fpscr(unsigned long fpscr) 717 { 718 int ret = 0; 719 720 /* Invalid operation */ 721 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 722 ret = FPE_FLTINV; 723 724 /* Overflow */ 725 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 726 ret = FPE_FLTOVF; 727 728 /* Underflow */ 729 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 730 ret = FPE_FLTUND; 731 732 /* Divide by zero */ 733 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 734 ret = FPE_FLTDIV; 735 736 /* Inexact result */ 737 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 738 ret = FPE_FLTRES; 739 740 return ret; 741 } 742 743 static void parse_fpe(struct pt_regs *regs) 744 { 745 int code = 0; 746 747 flush_fp_to_thread(current); 748 749 code = __parse_fpscr(current->thread.fpscr.val); 750 751 _exception(SIGFPE, regs, code, regs->nip); 752 } 753 754 /* 755 * Illegal instruction emulation support. Originally written to 756 * provide the PVR to user applications using the mfspr rd, PVR. 757 * Return non-zero if we can't emulate, or -EFAULT if the associated 758 * memory access caused an access fault. Return zero on success. 759 * 760 * There are a couple of ways to do this, either "decode" the instruction 761 * or directly match lots of bits. In this case, matching lots of 762 * bits is faster and easier. 763 * 764 */ 765 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 766 { 767 u8 rT = (instword >> 21) & 0x1f; 768 u8 rA = (instword >> 16) & 0x1f; 769 u8 NB_RB = (instword >> 11) & 0x1f; 770 u32 num_bytes; 771 unsigned long EA; 772 int pos = 0; 773 774 /* Early out if we are an invalid form of lswx */ 775 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 776 if ((rT == rA) || (rT == NB_RB)) 777 return -EINVAL; 778 779 EA = (rA == 0) ? 0 : regs->gpr[rA]; 780 781 switch (instword & PPC_INST_STRING_MASK) { 782 case PPC_INST_LSWX: 783 case PPC_INST_STSWX: 784 EA += NB_RB; 785 num_bytes = regs->xer & 0x7f; 786 break; 787 case PPC_INST_LSWI: 788 case PPC_INST_STSWI: 789 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 790 break; 791 default: 792 return -EINVAL; 793 } 794 795 while (num_bytes != 0) 796 { 797 u8 val; 798 u32 shift = 8 * (3 - (pos & 0x3)); 799 800 switch ((instword & PPC_INST_STRING_MASK)) { 801 case PPC_INST_LSWX: 802 case PPC_INST_LSWI: 803 if (get_user(val, (u8 __user *)EA)) 804 return -EFAULT; 805 /* first time updating this reg, 806 * zero it out */ 807 if (pos == 0) 808 regs->gpr[rT] = 0; 809 regs->gpr[rT] |= val << shift; 810 break; 811 case PPC_INST_STSWI: 812 case PPC_INST_STSWX: 813 val = regs->gpr[rT] >> shift; 814 if (put_user(val, (u8 __user *)EA)) 815 return -EFAULT; 816 break; 817 } 818 /* move EA to next address */ 819 EA += 1; 820 num_bytes--; 821 822 /* manage our position within the register */ 823 if (++pos == 4) { 824 pos = 0; 825 if (++rT == 32) 826 rT = 0; 827 } 828 } 829 830 return 0; 831 } 832 833 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 834 { 835 u32 ra,rs; 836 unsigned long tmp; 837 838 ra = (instword >> 16) & 0x1f; 839 rs = (instword >> 21) & 0x1f; 840 841 tmp = regs->gpr[rs]; 842 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 843 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 844 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 845 regs->gpr[ra] = tmp; 846 847 return 0; 848 } 849 850 static int emulate_isel(struct pt_regs *regs, u32 instword) 851 { 852 u8 rT = (instword >> 21) & 0x1f; 853 u8 rA = (instword >> 16) & 0x1f; 854 u8 rB = (instword >> 11) & 0x1f; 855 u8 BC = (instword >> 6) & 0x1f; 856 u8 bit; 857 unsigned long tmp; 858 859 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 860 bit = (regs->ccr >> (31 - BC)) & 0x1; 861 862 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 863 864 return 0; 865 } 866 867 static int emulate_instruction(struct pt_regs *regs) 868 { 869 u32 instword; 870 u32 rd; 871 872 if (!user_mode(regs) || (regs->msr & MSR_LE)) 873 return -EINVAL; 874 CHECK_FULL_REGS(regs); 875 876 if (get_user(instword, (u32 __user *)(regs->nip))) 877 return -EFAULT; 878 879 /* Emulate the mfspr rD, PVR. */ 880 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 881 PPC_WARN_EMULATED(mfpvr, regs); 882 rd = (instword >> 21) & 0x1f; 883 regs->gpr[rd] = mfspr(SPRN_PVR); 884 return 0; 885 } 886 887 /* Emulating the dcba insn is just a no-op. */ 888 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 889 PPC_WARN_EMULATED(dcba, regs); 890 return 0; 891 } 892 893 /* Emulate the mcrxr insn. */ 894 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 895 int shift = (instword >> 21) & 0x1c; 896 unsigned long msk = 0xf0000000UL >> shift; 897 898 PPC_WARN_EMULATED(mcrxr, regs); 899 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 900 regs->xer &= ~0xf0000000UL; 901 return 0; 902 } 903 904 /* Emulate load/store string insn. */ 905 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 906 PPC_WARN_EMULATED(string, regs); 907 return emulate_string_inst(regs, instword); 908 } 909 910 /* Emulate the popcntb (Population Count Bytes) instruction. */ 911 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 912 PPC_WARN_EMULATED(popcntb, regs); 913 return emulate_popcntb_inst(regs, instword); 914 } 915 916 /* Emulate isel (Integer Select) instruction */ 917 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 918 PPC_WARN_EMULATED(isel, regs); 919 return emulate_isel(regs, instword); 920 } 921 922 return -EINVAL; 923 } 924 925 int is_valid_bugaddr(unsigned long addr) 926 { 927 return is_kernel_addr(addr); 928 } 929 930 void __kprobes program_check_exception(struct pt_regs *regs) 931 { 932 unsigned int reason = get_reason(regs); 933 extern int do_mathemu(struct pt_regs *regs); 934 935 /* We can now get here via a FP Unavailable exception if the core 936 * has no FPU, in that case the reason flags will be 0 */ 937 938 if (reason & REASON_FP) { 939 /* IEEE FP exception */ 940 parse_fpe(regs); 941 return; 942 } 943 if (reason & REASON_TRAP) { 944 /* Debugger is first in line to stop recursive faults in 945 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 946 if (debugger_bpt(regs)) 947 return; 948 949 /* trap exception */ 950 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 951 == NOTIFY_STOP) 952 return; 953 954 if (!(regs->msr & MSR_PR) && /* not user-mode */ 955 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 956 regs->nip += 4; 957 return; 958 } 959 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 960 return; 961 } 962 963 local_irq_enable(); 964 965 #ifdef CONFIG_MATH_EMULATION 966 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 967 * but there seems to be a hardware bug on the 405GP (RevD) 968 * that means ESR is sometimes set incorrectly - either to 969 * ESR_DST (!?) or 0. In the process of chasing this with the 970 * hardware people - not sure if it can happen on any illegal 971 * instruction or only on FP instructions, whether there is a 972 * pattern to occurences etc. -dgibson 31/Mar/2003 */ 973 switch (do_mathemu(regs)) { 974 case 0: 975 emulate_single_step(regs); 976 return; 977 case 1: { 978 int code = 0; 979 code = __parse_fpscr(current->thread.fpscr.val); 980 _exception(SIGFPE, regs, code, regs->nip); 981 return; 982 } 983 case -EFAULT: 984 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 985 return; 986 } 987 /* fall through on any other errors */ 988 #endif /* CONFIG_MATH_EMULATION */ 989 990 /* Try to emulate it if we should. */ 991 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 992 switch (emulate_instruction(regs)) { 993 case 0: 994 regs->nip += 4; 995 emulate_single_step(regs); 996 return; 997 case -EFAULT: 998 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 999 return; 1000 } 1001 } 1002 1003 if (reason & REASON_PRIVILEGED) 1004 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1005 else 1006 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1007 } 1008 1009 void alignment_exception(struct pt_regs *regs) 1010 { 1011 int sig, code, fixed = 0; 1012 1013 /* we don't implement logging of alignment exceptions */ 1014 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1015 fixed = fix_alignment(regs); 1016 1017 if (fixed == 1) { 1018 regs->nip += 4; /* skip over emulated instruction */ 1019 emulate_single_step(regs); 1020 return; 1021 } 1022 1023 /* Operand address was bad */ 1024 if (fixed == -EFAULT) { 1025 sig = SIGSEGV; 1026 code = SEGV_ACCERR; 1027 } else { 1028 sig = SIGBUS; 1029 code = BUS_ADRALN; 1030 } 1031 if (user_mode(regs)) 1032 _exception(sig, regs, code, regs->dar); 1033 else 1034 bad_page_fault(regs, regs->dar, sig); 1035 } 1036 1037 void StackOverflow(struct pt_regs *regs) 1038 { 1039 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 1040 current, regs->gpr[1]); 1041 debugger(regs); 1042 show_regs(regs); 1043 panic("kernel stack overflow"); 1044 } 1045 1046 void nonrecoverable_exception(struct pt_regs *regs) 1047 { 1048 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 1049 regs->nip, regs->msr); 1050 debugger(regs); 1051 die("nonrecoverable exception", regs, SIGKILL); 1052 } 1053 1054 void trace_syscall(struct pt_regs *regs) 1055 { 1056 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", 1057 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], 1058 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); 1059 } 1060 1061 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1062 { 1063 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1064 "%lx at %lx\n", regs->trap, regs->nip); 1065 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1066 } 1067 1068 void altivec_unavailable_exception(struct pt_regs *regs) 1069 { 1070 if (user_mode(regs)) { 1071 /* A user program has executed an altivec instruction, 1072 but this kernel doesn't support altivec. */ 1073 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1074 return; 1075 } 1076 1077 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1078 "%lx at %lx\n", regs->trap, regs->nip); 1079 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1080 } 1081 1082 void vsx_unavailable_exception(struct pt_regs *regs) 1083 { 1084 if (user_mode(regs)) { 1085 /* A user program has executed an vsx instruction, 1086 but this kernel doesn't support vsx. */ 1087 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1088 return; 1089 } 1090 1091 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1092 "%lx at %lx\n", regs->trap, regs->nip); 1093 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1094 } 1095 1096 void performance_monitor_exception(struct pt_regs *regs) 1097 { 1098 __get_cpu_var(irq_stat).pmu_irqs++; 1099 1100 perf_irq(regs); 1101 } 1102 1103 #ifdef CONFIG_8xx 1104 void SoftwareEmulation(struct pt_regs *regs) 1105 { 1106 extern int do_mathemu(struct pt_regs *); 1107 extern int Soft_emulate_8xx(struct pt_regs *); 1108 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) 1109 int errcode; 1110 #endif 1111 1112 CHECK_FULL_REGS(regs); 1113 1114 if (!user_mode(regs)) { 1115 debugger(regs); 1116 die("Kernel Mode Software FPU Emulation", regs, SIGFPE); 1117 } 1118 1119 #ifdef CONFIG_MATH_EMULATION 1120 errcode = do_mathemu(regs); 1121 if (errcode >= 0) 1122 PPC_WARN_EMULATED(math, regs); 1123 1124 switch (errcode) { 1125 case 0: 1126 emulate_single_step(regs); 1127 return; 1128 case 1: { 1129 int code = 0; 1130 code = __parse_fpscr(current->thread.fpscr.val); 1131 _exception(SIGFPE, regs, code, regs->nip); 1132 return; 1133 } 1134 case -EFAULT: 1135 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1136 return; 1137 default: 1138 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1139 return; 1140 } 1141 1142 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1143 errcode = Soft_emulate_8xx(regs); 1144 if (errcode >= 0) 1145 PPC_WARN_EMULATED(8xx, regs); 1146 1147 switch (errcode) { 1148 case 0: 1149 emulate_single_step(regs); 1150 return; 1151 case 1: 1152 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1153 return; 1154 case -EFAULT: 1155 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1156 return; 1157 } 1158 #else 1159 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1160 #endif 1161 } 1162 #endif /* CONFIG_8xx */ 1163 1164 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1165 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1166 { 1167 int changed = 0; 1168 /* 1169 * Determine the cause of the debug event, clear the 1170 * event flags and send a trap to the handler. Torez 1171 */ 1172 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1173 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1174 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1175 current->thread.dbcr2 &= ~DBCR2_DAC12MODE; 1176 #endif 1177 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, 1178 5); 1179 changed |= 0x01; 1180 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1181 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1182 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, 1183 6); 1184 changed |= 0x01; 1185 } else if (debug_status & DBSR_IAC1) { 1186 current->thread.dbcr0 &= ~DBCR0_IAC1; 1187 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1188 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, 1189 1); 1190 changed |= 0x01; 1191 } else if (debug_status & DBSR_IAC2) { 1192 current->thread.dbcr0 &= ~DBCR0_IAC2; 1193 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, 1194 2); 1195 changed |= 0x01; 1196 } else if (debug_status & DBSR_IAC3) { 1197 current->thread.dbcr0 &= ~DBCR0_IAC3; 1198 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1199 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, 1200 3); 1201 changed |= 0x01; 1202 } else if (debug_status & DBSR_IAC4) { 1203 current->thread.dbcr0 &= ~DBCR0_IAC4; 1204 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, 1205 4); 1206 changed |= 0x01; 1207 } 1208 /* 1209 * At the point this routine was called, the MSR(DE) was turned off. 1210 * Check all other debug flags and see if that bit needs to be turned 1211 * back on or not. 1212 */ 1213 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) 1214 regs->msr |= MSR_DE; 1215 else 1216 /* Make sure the IDM flag is off */ 1217 current->thread.dbcr0 &= ~DBCR0_IDM; 1218 1219 if (changed & 0x01) 1220 mtspr(SPRN_DBCR0, current->thread.dbcr0); 1221 } 1222 1223 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) 1224 { 1225 current->thread.dbsr = debug_status; 1226 1227 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1228 * on server, it stops on the target of the branch. In order to simulate 1229 * the server behaviour, we thus restart right away with a single step 1230 * instead of stopping here when hitting a BT 1231 */ 1232 if (debug_status & DBSR_BT) { 1233 regs->msr &= ~MSR_DE; 1234 1235 /* Disable BT */ 1236 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1237 /* Clear the BT event */ 1238 mtspr(SPRN_DBSR, DBSR_BT); 1239 1240 /* Do the single step trick only when coming from userspace */ 1241 if (user_mode(regs)) { 1242 current->thread.dbcr0 &= ~DBCR0_BT; 1243 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1244 regs->msr |= MSR_DE; 1245 return; 1246 } 1247 1248 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1249 5, SIGTRAP) == NOTIFY_STOP) { 1250 return; 1251 } 1252 if (debugger_sstep(regs)) 1253 return; 1254 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1255 regs->msr &= ~MSR_DE; 1256 1257 /* Disable instruction completion */ 1258 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1259 /* Clear the instruction completion event */ 1260 mtspr(SPRN_DBSR, DBSR_IC); 1261 1262 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1263 5, SIGTRAP) == NOTIFY_STOP) { 1264 return; 1265 } 1266 1267 if (debugger_sstep(regs)) 1268 return; 1269 1270 if (user_mode(regs)) { 1271 current->thread.dbcr0 &= ~DBCR0_IC; 1272 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1273 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, 1274 current->thread.dbcr1)) 1275 regs->msr |= MSR_DE; 1276 else 1277 /* Make sure the IDM bit is off */ 1278 current->thread.dbcr0 &= ~DBCR0_IDM; 1279 #endif 1280 } 1281 1282 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1283 } else 1284 handle_debug(regs, debug_status); 1285 } 1286 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1287 1288 #if !defined(CONFIG_TAU_INT) 1289 void TAUException(struct pt_regs *regs) 1290 { 1291 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 1292 regs->nip, regs->msr, regs->trap, print_tainted()); 1293 } 1294 #endif /* CONFIG_INT_TAU */ 1295 1296 #ifdef CONFIG_ALTIVEC 1297 void altivec_assist_exception(struct pt_regs *regs) 1298 { 1299 int err; 1300 1301 if (!user_mode(regs)) { 1302 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 1303 " at %lx\n", regs->nip); 1304 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 1305 } 1306 1307 flush_altivec_to_thread(current); 1308 1309 PPC_WARN_EMULATED(altivec, regs); 1310 err = emulate_altivec(regs); 1311 if (err == 0) { 1312 regs->nip += 4; /* skip emulated instruction */ 1313 emulate_single_step(regs); 1314 return; 1315 } 1316 1317 if (err == -EFAULT) { 1318 /* got an error reading the instruction */ 1319 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1320 } else { 1321 /* didn't recognize the instruction */ 1322 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 1323 if (printk_ratelimit()) 1324 printk(KERN_ERR "Unrecognized altivec instruction " 1325 "in %s at %lx\n", current->comm, regs->nip); 1326 current->thread.vscr.u[3] |= 0x10000; 1327 } 1328 } 1329 #endif /* CONFIG_ALTIVEC */ 1330 1331 #ifdef CONFIG_VSX 1332 void vsx_assist_exception(struct pt_regs *regs) 1333 { 1334 if (!user_mode(regs)) { 1335 printk(KERN_EMERG "VSX assist exception in kernel mode" 1336 " at %lx\n", regs->nip); 1337 die("Kernel VSX assist exception", regs, SIGILL); 1338 } 1339 1340 flush_vsx_to_thread(current); 1341 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); 1342 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1343 } 1344 #endif /* CONFIG_VSX */ 1345 1346 #ifdef CONFIG_FSL_BOOKE 1347 1348 void doorbell_exception(struct pt_regs *regs) 1349 { 1350 #ifdef CONFIG_SMP 1351 int cpu = smp_processor_id(); 1352 int msg; 1353 1354 if (num_online_cpus() < 2) 1355 return; 1356 1357 for (msg = 0; msg < 4; msg++) 1358 if (test_and_clear_bit(msg, &dbell_smp_message[cpu])) 1359 smp_message_recv(msg); 1360 #else 1361 printk(KERN_WARNING "Received doorbell on non-smp system\n"); 1362 #endif 1363 } 1364 1365 void CacheLockingException(struct pt_regs *regs, unsigned long address, 1366 unsigned long error_code) 1367 { 1368 /* We treat cache locking instructions from the user 1369 * as priv ops, in the future we could try to do 1370 * something smarter 1371 */ 1372 if (error_code & (ESR_DLK|ESR_ILK)) 1373 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1374 return; 1375 } 1376 #endif /* CONFIG_FSL_BOOKE */ 1377 1378 #ifdef CONFIG_SPE 1379 void SPEFloatingPointException(struct pt_regs *regs) 1380 { 1381 extern int do_spe_mathemu(struct pt_regs *regs); 1382 unsigned long spefscr; 1383 int fpexc_mode; 1384 int code = 0; 1385 int err; 1386 1387 preempt_disable(); 1388 if (regs->msr & MSR_SPE) 1389 giveup_spe(current); 1390 preempt_enable(); 1391 1392 spefscr = current->thread.spefscr; 1393 fpexc_mode = current->thread.fpexc_mode; 1394 1395 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1396 code = FPE_FLTOVF; 1397 } 1398 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1399 code = FPE_FLTUND; 1400 } 1401 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1402 code = FPE_FLTDIV; 1403 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1404 code = FPE_FLTINV; 1405 } 1406 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1407 code = FPE_FLTRES; 1408 1409 err = do_spe_mathemu(regs); 1410 if (err == 0) { 1411 regs->nip += 4; /* skip emulated instruction */ 1412 emulate_single_step(regs); 1413 return; 1414 } 1415 1416 if (err == -EFAULT) { 1417 /* got an error reading the instruction */ 1418 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1419 } else if (err == -EINVAL) { 1420 /* didn't recognize the instruction */ 1421 printk(KERN_ERR "unrecognized spe instruction " 1422 "in %s at %lx\n", current->comm, regs->nip); 1423 } else { 1424 _exception(SIGFPE, regs, code, regs->nip); 1425 } 1426 1427 return; 1428 } 1429 1430 void SPEFloatingPointRoundException(struct pt_regs *regs) 1431 { 1432 extern int speround_handler(struct pt_regs *regs); 1433 int err; 1434 1435 preempt_disable(); 1436 if (regs->msr & MSR_SPE) 1437 giveup_spe(current); 1438 preempt_enable(); 1439 1440 regs->nip -= 4; 1441 err = speround_handler(regs); 1442 if (err == 0) { 1443 regs->nip += 4; /* skip emulated instruction */ 1444 emulate_single_step(regs); 1445 return; 1446 } 1447 1448 if (err == -EFAULT) { 1449 /* got an error reading the instruction */ 1450 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1451 } else if (err == -EINVAL) { 1452 /* didn't recognize the instruction */ 1453 printk(KERN_ERR "unrecognized spe instruction " 1454 "in %s at %lx\n", current->comm, regs->nip); 1455 } else { 1456 _exception(SIGFPE, regs, 0, regs->nip); 1457 return; 1458 } 1459 } 1460 #endif 1461 1462 /* 1463 * We enter here if we get an unrecoverable exception, that is, one 1464 * that happened at a point where the RI (recoverable interrupt) bit 1465 * in the MSR is 0. This indicates that SRR0/1 are live, and that 1466 * we therefore lost state by taking this exception. 1467 */ 1468 void unrecoverable_exception(struct pt_regs *regs) 1469 { 1470 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 1471 regs->trap, regs->nip); 1472 die("Unrecoverable exception", regs, SIGABRT); 1473 } 1474 1475 #ifdef CONFIG_BOOKE_WDT 1476 /* 1477 * Default handler for a Watchdog exception, 1478 * spins until a reboot occurs 1479 */ 1480 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 1481 { 1482 /* Generic WatchdogHandler, implement your own */ 1483 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 1484 return; 1485 } 1486 1487 void WatchdogException(struct pt_regs *regs) 1488 { 1489 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 1490 WatchdogHandler(regs); 1491 } 1492 #endif 1493 1494 /* 1495 * We enter here if we discover during exception entry that we are 1496 * running in supervisor mode with a userspace value in the stack pointer. 1497 */ 1498 void kernel_bad_stack(struct pt_regs *regs) 1499 { 1500 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 1501 regs->gpr[1], regs->nip); 1502 die("Bad kernel stack pointer", regs, SIGABRT); 1503 } 1504 1505 void __init trap_init(void) 1506 { 1507 } 1508 1509 1510 #ifdef CONFIG_PPC_EMULATED_STATS 1511 1512 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 1513 1514 struct ppc_emulated ppc_emulated = { 1515 #ifdef CONFIG_ALTIVEC 1516 WARN_EMULATED_SETUP(altivec), 1517 #endif 1518 WARN_EMULATED_SETUP(dcba), 1519 WARN_EMULATED_SETUP(dcbz), 1520 WARN_EMULATED_SETUP(fp_pair), 1521 WARN_EMULATED_SETUP(isel), 1522 WARN_EMULATED_SETUP(mcrxr), 1523 WARN_EMULATED_SETUP(mfpvr), 1524 WARN_EMULATED_SETUP(multiple), 1525 WARN_EMULATED_SETUP(popcntb), 1526 WARN_EMULATED_SETUP(spe), 1527 WARN_EMULATED_SETUP(string), 1528 WARN_EMULATED_SETUP(unaligned), 1529 #ifdef CONFIG_MATH_EMULATION 1530 WARN_EMULATED_SETUP(math), 1531 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1532 WARN_EMULATED_SETUP(8xx), 1533 #endif 1534 #ifdef CONFIG_VSX 1535 WARN_EMULATED_SETUP(vsx), 1536 #endif 1537 }; 1538 1539 u32 ppc_warn_emulated; 1540 1541 void ppc_warn_emulated_print(const char *type) 1542 { 1543 if (printk_ratelimit()) 1544 pr_warning("%s used emulated %s instruction\n", current->comm, 1545 type); 1546 } 1547 1548 static int __init ppc_warn_emulated_init(void) 1549 { 1550 struct dentry *dir, *d; 1551 unsigned int i; 1552 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 1553 1554 if (!powerpc_debugfs_root) 1555 return -ENODEV; 1556 1557 dir = debugfs_create_dir("emulated_instructions", 1558 powerpc_debugfs_root); 1559 if (!dir) 1560 return -ENOMEM; 1561 1562 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, 1563 &ppc_warn_emulated); 1564 if (!d) 1565 goto fail; 1566 1567 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 1568 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, 1569 (u32 *)&entries[i].val.counter); 1570 if (!d) 1571 goto fail; 1572 } 1573 1574 return 0; 1575 1576 fail: 1577 debugfs_remove_recursive(dir); 1578 return -ENOMEM; 1579 } 1580 1581 device_initcall(ppc_warn_emulated_init); 1582 1583 #endif /* CONFIG_PPC_EMULATED_STATS */ 1584