1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * and Paul Mackerras (paulus@samba.org) 8 */ 9 10 /* 11 * This file handles the architecture-dependent parts of hardware exceptions 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sched/debug.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/pkeys.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/ptrace.h> 23 #include <linux/user.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/extable.h> 27 #include <linux/module.h> /* print_modules */ 28 #include <linux/prctl.h> 29 #include <linux/delay.h> 30 #include <linux/kprobes.h> 31 #include <linux/kexec.h> 32 #include <linux/backlight.h> 33 #include <linux/bug.h> 34 #include <linux/kdebug.h> 35 #include <linux/ratelimit.h> 36 #include <linux/context_tracking.h> 37 #include <linux/smp.h> 38 #include <linux/console.h> 39 #include <linux/kmsg_dump.h> 40 #include <linux/debugfs.h> 41 42 #include <asm/emulated_ops.h> 43 #include <linux/uaccess.h> 44 #include <asm/interrupt.h> 45 #include <asm/io.h> 46 #include <asm/machdep.h> 47 #include <asm/rtas.h> 48 #include <asm/pmc.h> 49 #include <asm/reg.h> 50 #ifdef CONFIG_PMAC_BACKLIGHT 51 #include <asm/backlight.h> 52 #endif 53 #ifdef CONFIG_PPC64 54 #include <asm/firmware.h> 55 #include <asm/processor.h> 56 #endif 57 #include <asm/kexec.h> 58 #include <asm/ppc-opcode.h> 59 #include <asm/rio.h> 60 #include <asm/fadump.h> 61 #include <asm/switch_to.h> 62 #include <asm/tm.h> 63 #include <asm/debug.h> 64 #include <asm/asm-prototypes.h> 65 #include <asm/hmi.h> 66 #include <sysdev/fsl_pci.h> 67 #include <asm/kprobes.h> 68 #include <asm/stacktrace.h> 69 #include <asm/nmi.h> 70 #include <asm/disassemble.h> 71 #include <asm/udbg.h> 72 73 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 74 int (*__debugger)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 79 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 80 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 81 82 EXPORT_SYMBOL(__debugger); 83 EXPORT_SYMBOL(__debugger_ipi); 84 EXPORT_SYMBOL(__debugger_bpt); 85 EXPORT_SYMBOL(__debugger_sstep); 86 EXPORT_SYMBOL(__debugger_iabr_match); 87 EXPORT_SYMBOL(__debugger_break_match); 88 EXPORT_SYMBOL(__debugger_fault_handler); 89 #endif 90 91 /* Transactional Memory trap debug */ 92 #ifdef TM_DEBUG_SW 93 #define TM_DEBUG(x...) printk(KERN_INFO x) 94 #else 95 #define TM_DEBUG(x...) do { } while(0) 96 #endif 97 98 static const char *signame(int signr) 99 { 100 switch (signr) { 101 case SIGBUS: return "bus error"; 102 case SIGFPE: return "floating point exception"; 103 case SIGILL: return "illegal instruction"; 104 case SIGSEGV: return "segfault"; 105 case SIGTRAP: return "unhandled trap"; 106 } 107 108 return "unknown signal"; 109 } 110 111 /* 112 * Trap & Exception support 113 */ 114 115 #ifdef CONFIG_PMAC_BACKLIGHT 116 static void pmac_backlight_unblank(void) 117 { 118 mutex_lock(&pmac_backlight_mutex); 119 if (pmac_backlight) { 120 struct backlight_properties *props; 121 122 props = &pmac_backlight->props; 123 props->brightness = props->max_brightness; 124 props->power = BACKLIGHT_POWER_ON; 125 backlight_update_status(pmac_backlight); 126 } 127 mutex_unlock(&pmac_backlight_mutex); 128 } 129 #else 130 static inline void pmac_backlight_unblank(void) { } 131 #endif 132 133 /* 134 * If oops/die is expected to crash the machine, return true here. 135 * 136 * This should not be expected to be 100% accurate, there may be 137 * notifiers registered or other unexpected conditions that may bring 138 * down the kernel. Or if the current process in the kernel is holding 139 * locks or has other critical state, the kernel may become effectively 140 * unusable anyway. 141 */ 142 bool die_will_crash(void) 143 { 144 if (should_fadump_crash()) 145 return true; 146 if (kexec_should_crash(current)) 147 return true; 148 if (in_interrupt() || panic_on_oops || 149 !current->pid || is_global_init(current)) 150 return true; 151 152 return false; 153 } 154 155 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 156 static int die_owner = -1; 157 static unsigned int die_nest_count; 158 static int die_counter; 159 160 void panic_flush_kmsg_start(void) 161 { 162 /* 163 * These are mostly taken from kernel/panic.c, but tries to do 164 * relatively minimal work. Don't use delay functions (TB may 165 * be broken), don't crash dump (need to set a firmware log), 166 * don't run notifiers. We do want to get some information to 167 * Linux console. 168 */ 169 console_verbose(); 170 bust_spinlocks(1); 171 } 172 173 void panic_flush_kmsg_end(void) 174 { 175 kmsg_dump(KMSG_DUMP_PANIC); 176 bust_spinlocks(0); 177 debug_locks_off(); 178 console_flush_on_panic(CONSOLE_FLUSH_PENDING); 179 } 180 181 static unsigned long oops_begin(struct pt_regs *regs) 182 { 183 int cpu; 184 unsigned long flags; 185 186 oops_enter(); 187 188 /* racy, but better than risking deadlock. */ 189 raw_local_irq_save(flags); 190 cpu = smp_processor_id(); 191 if (!arch_spin_trylock(&die_lock)) { 192 if (cpu == die_owner) 193 /* nested oops. should stop eventually */; 194 else 195 arch_spin_lock(&die_lock); 196 } 197 die_nest_count++; 198 die_owner = cpu; 199 console_verbose(); 200 bust_spinlocks(1); 201 if (machine_is(powermac)) 202 pmac_backlight_unblank(); 203 return flags; 204 } 205 NOKPROBE_SYMBOL(oops_begin); 206 207 static void oops_end(unsigned long flags, struct pt_regs *regs, 208 int signr) 209 { 210 bust_spinlocks(0); 211 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 212 die_nest_count--; 213 oops_exit(); 214 printk("\n"); 215 if (!die_nest_count) { 216 /* Nest count reaches zero, release the lock. */ 217 die_owner = -1; 218 arch_spin_unlock(&die_lock); 219 } 220 raw_local_irq_restore(flags); 221 222 /* 223 * system_reset_excption handles debugger, crash dump, panic, for 0x100 224 */ 225 if (TRAP(regs) == INTERRUPT_SYSTEM_RESET) 226 return; 227 228 crash_fadump(regs, "die oops"); 229 230 if (kexec_should_crash(current)) 231 crash_kexec(regs); 232 233 if (!signr) 234 return; 235 236 /* 237 * While our oops output is serialised by a spinlock, output 238 * from panic() called below can race and corrupt it. If we 239 * know we are going to panic, delay for 1 second so we have a 240 * chance to get clean backtraces from all CPUs that are oopsing. 241 */ 242 if (in_interrupt() || panic_on_oops || !current->pid || 243 is_global_init(current)) { 244 mdelay(MSEC_PER_SEC); 245 } 246 247 if (panic_on_oops) 248 panic("Fatal exception"); 249 make_task_dead(signr); 250 } 251 NOKPROBE_SYMBOL(oops_end); 252 253 static char *get_mmu_str(void) 254 { 255 if (early_radix_enabled()) 256 return " MMU=Radix"; 257 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE)) 258 return " MMU=Hash"; 259 return ""; 260 } 261 262 static int __die(const char *str, struct pt_regs *regs, long err) 263 { 264 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 265 266 printk("%s PAGE_SIZE=%luK%s %s%s%s%s %s\n", 267 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 268 PAGE_SIZE / 1024, get_mmu_str(), 269 IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 270 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 271 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 272 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 273 ppc_md.name ? ppc_md.name : ""); 274 275 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 276 return 1; 277 278 print_modules(); 279 show_regs(regs); 280 281 return 0; 282 } 283 NOKPROBE_SYMBOL(__die); 284 285 void die(const char *str, struct pt_regs *regs, long err) 286 { 287 unsigned long flags; 288 289 /* 290 * system_reset_excption handles debugger, crash dump, panic, for 0x100 291 */ 292 if (TRAP(regs) != INTERRUPT_SYSTEM_RESET) { 293 if (debugger(regs)) 294 return; 295 } 296 297 flags = oops_begin(regs); 298 if (__die(str, regs, err)) 299 err = 0; 300 oops_end(flags, regs, err); 301 } 302 NOKPROBE_SYMBOL(die); 303 304 void user_single_step_report(struct pt_regs *regs) 305 { 306 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip); 307 } 308 309 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 310 unsigned long addr) 311 { 312 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 313 DEFAULT_RATELIMIT_BURST); 314 315 if (!show_unhandled_signals) 316 return; 317 318 if (!unhandled_signal(current, signr)) 319 return; 320 321 if (!__ratelimit(&rs)) 322 return; 323 324 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 325 current->comm, current->pid, signame(signr), signr, 326 addr, regs->nip, regs->link, code); 327 328 print_vma_addr(KERN_CONT " in ", regs->nip); 329 330 pr_cont("\n"); 331 332 show_user_instructions(regs); 333 } 334 335 static bool exception_common(int signr, struct pt_regs *regs, int code, 336 unsigned long addr) 337 { 338 if (!user_mode(regs)) { 339 die("Exception in kernel mode", regs, signr); 340 return false; 341 } 342 343 /* 344 * Must not enable interrupts even for user-mode exception, because 345 * this can be called from machine check, which may be a NMI or IRQ 346 * which don't like interrupts being enabled. Could check for 347 * in_hardirq || in_nmi perhaps, but there doesn't seem to be a good 348 * reason why _exception() should enable irqs for an exception handler, 349 * the handlers themselves do that directly. 350 */ 351 352 show_signal_msg(signr, regs, code, addr); 353 354 current->thread.trap_nr = code; 355 356 return true; 357 } 358 359 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 360 { 361 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 362 return; 363 364 force_sig_pkuerr((void __user *) addr, key); 365 } 366 367 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 368 { 369 if (!exception_common(signr, regs, code, addr)) 370 return; 371 372 force_sig_fault(signr, code, (void __user *)addr); 373 } 374 375 /* 376 * The interrupt architecture has a quirk in that the HV interrupts excluding 377 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing 378 * that an interrupt handler must do is save off a GPR into a scratch register, 379 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch. 380 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing 381 * that it is non-reentrant, which leads to random data corruption. 382 * 383 * The solution is for NMI interrupts in HV mode to check if they originated 384 * from these critical HV interrupt regions. If so, then mark them not 385 * recoverable. 386 * 387 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the 388 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux 389 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so 390 * that would work. However any other guest OS that may have the SPRG live 391 * and MSR[RI]=1 could encounter silent corruption. 392 * 393 * Builds that do not support KVM could take this second option to increase 394 * the recoverability of NMIs. 395 */ 396 noinstr void hv_nmi_check_nonrecoverable(struct pt_regs *regs) 397 { 398 #ifdef CONFIG_PPC_POWERNV 399 unsigned long kbase = (unsigned long)_stext; 400 unsigned long nip = regs->nip; 401 402 if (!(regs->msr & MSR_RI)) 403 return; 404 if (!(regs->msr & MSR_HV)) 405 return; 406 if (user_mode(regs)) 407 return; 408 409 /* 410 * Now test if the interrupt has hit a range that may be using 411 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The 412 * problem ranges all run un-relocated. Test real and virt modes 413 * at the same time by dropping the high bit of the nip (virt mode 414 * entry points still have the +0x4000 offset). 415 */ 416 nip &= ~0xc000000000000000ULL; 417 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600)) 418 goto nonrecoverable; 419 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00)) 420 goto nonrecoverable; 421 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0)) 422 goto nonrecoverable; 423 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0)) 424 goto nonrecoverable; 425 426 /* Trampoline code runs un-relocated so subtract kbase. */ 427 if (nip >= (unsigned long)(start_real_trampolines - kbase) && 428 nip < (unsigned long)(end_real_trampolines - kbase)) 429 goto nonrecoverable; 430 if (nip >= (unsigned long)(start_virt_trampolines - kbase) && 431 nip < (unsigned long)(end_virt_trampolines - kbase)) 432 goto nonrecoverable; 433 return; 434 435 nonrecoverable: 436 regs->msr &= ~MSR_RI; 437 local_paca->hsrr_valid = 0; 438 local_paca->srr_valid = 0; 439 #endif 440 } 441 DEFINE_INTERRUPT_HANDLER_NMI(system_reset_exception) 442 { 443 unsigned long hsrr0, hsrr1; 444 bool saved_hsrrs = false; 445 446 /* 447 * System reset can interrupt code where HSRRs are live and MSR[RI]=1. 448 * The system reset interrupt itself may clobber HSRRs (e.g., to call 449 * OPAL), so save them here and restore them before returning. 450 * 451 * Machine checks don't need to save HSRRs, as the real mode handler 452 * is careful to avoid them, and the regular handler is not delivered 453 * as an NMI. 454 */ 455 if (cpu_has_feature(CPU_FTR_HVMODE)) { 456 hsrr0 = mfspr(SPRN_HSRR0); 457 hsrr1 = mfspr(SPRN_HSRR1); 458 saved_hsrrs = true; 459 } 460 461 hv_nmi_check_nonrecoverable(regs); 462 inc_irq_stat_and_enable(IRQ_COUNT_NMI_SRESET); 463 464 /* See if any machine dependent calls */ 465 if (ppc_md.system_reset_exception) { 466 if (ppc_md.system_reset_exception(regs)) 467 goto out; 468 } 469 470 if (debugger(regs)) 471 goto out; 472 473 kmsg_dump(KMSG_DUMP_OOPS); 474 /* 475 * A system reset is a request to dump, so we always send 476 * it through the crashdump code (if fadump or kdump are 477 * registered). 478 */ 479 crash_fadump(regs, "System Reset"); 480 481 crash_kexec(regs); 482 483 /* 484 * We aren't the primary crash CPU. We need to send it 485 * to a holding pattern to avoid it ending up in the panic 486 * code. 487 */ 488 crash_kexec_secondary(regs); 489 490 /* 491 * No debugger or crash dump registered, print logs then 492 * panic. 493 */ 494 die("System Reset", regs, SIGABRT); 495 496 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 497 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 498 nmi_panic(regs, "System Reset"); 499 500 out: 501 #ifdef CONFIG_PPC_BOOK3S_64 502 BUG_ON(get_paca()->in_nmi == 0); 503 if (get_paca()->in_nmi > 1) 504 die("Unrecoverable nested System Reset", regs, SIGABRT); 505 #endif 506 /* Must die if the interrupt is not recoverable */ 507 if (regs_is_unrecoverable(regs)) { 508 /* For the reason explained in die_mce, nmi_exit before die */ 509 nmi_exit(); 510 die("Unrecoverable System Reset", regs, SIGABRT); 511 } 512 513 if (saved_hsrrs) { 514 mtspr(SPRN_HSRR0, hsrr0); 515 mtspr(SPRN_HSRR1, hsrr1); 516 } 517 518 /* What should we do here? We could issue a shutdown or hard reset. */ 519 520 return 0; 521 } 522 523 /* 524 * I/O accesses can cause machine checks on powermacs. 525 * Check if the NIP corresponds to the address of a sync 526 * instruction for which there is an entry in the exception 527 * table. 528 * -- paulus. 529 */ 530 static inline int check_io_access(struct pt_regs *regs) 531 { 532 #ifdef CONFIG_PPC32 533 unsigned long msr = regs->msr; 534 const struct exception_table_entry *entry; 535 unsigned int *nip = (unsigned int *)regs->nip; 536 537 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 538 && (entry = search_exception_tables(regs->nip)) != NULL) { 539 /* 540 * Check that it's a sync instruction, or somewhere 541 * in the twi; isync; nop sequence that inb/inw/inl uses. 542 * As the address is in the exception table 543 * we should be able to read the instr there. 544 * For the debug message, we look at the preceding 545 * load or store. 546 */ 547 if (*nip == PPC_RAW_NOP()) 548 nip -= 2; 549 else if (*nip == PPC_RAW_ISYNC()) 550 --nip; 551 if (*nip == PPC_RAW_SYNC() || get_op(*nip) == OP_TRAP) { 552 unsigned int rb; 553 554 --nip; 555 rb = (*nip >> 11) & 0x1f; 556 printk(KERN_DEBUG "%s bad port %lx at %p\n", 557 (*nip & 0x100)? "OUT to": "IN from", 558 regs->gpr[rb] - _IO_BASE, nip); 559 regs_set_recoverable(regs); 560 regs_set_return_ip(regs, extable_fixup(entry)); 561 return 1; 562 } 563 } 564 #endif /* CONFIG_PPC32 */ 565 return 0; 566 } 567 568 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 569 /* On 4xx, the reason for the machine check or program exception 570 is in the ESR. */ 571 #define get_reason(regs) ((regs)->esr) 572 #define REASON_FP ESR_FP 573 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 574 #define REASON_PRIVILEGED ESR_PPR 575 #define REASON_TRAP ESR_PTR 576 #define REASON_PREFIXED 0 577 #define REASON_BOUNDARY 0 578 579 /* single-step stuff */ 580 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 581 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 582 #define clear_br_trace(regs) do {} while(0) 583 #else 584 /* On non-4xx, the reason for the machine check or program 585 exception is in the MSR. */ 586 #define get_reason(regs) ((regs)->msr) 587 #define REASON_TM SRR1_PROGTM 588 #define REASON_FP SRR1_PROGFPE 589 #define REASON_ILLEGAL SRR1_PROGILL 590 #define REASON_PRIVILEGED SRR1_PROGPRIV 591 #define REASON_TRAP SRR1_PROGTRAP 592 #define REASON_PREFIXED SRR1_PREFIXED 593 #define REASON_BOUNDARY SRR1_BOUNDARY 594 595 #define single_stepping(regs) ((regs)->msr & MSR_SE) 596 #define clear_single_step(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_SE)) 597 #define clear_br_trace(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_BE)) 598 #endif 599 600 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) 601 602 #if defined(CONFIG_PPC_E500) 603 int machine_check_e500mc(struct pt_regs *regs) 604 { 605 unsigned long mcsr = mfspr(SPRN_MCSR); 606 unsigned long pvr = mfspr(SPRN_PVR); 607 unsigned long reason = mcsr; 608 int recoverable = 1; 609 610 if (reason & MCSR_LD) { 611 recoverable = fsl_rio_mcheck_exception(regs); 612 if (recoverable == 1) 613 goto silent_out; 614 } 615 616 printk("Machine check in kernel mode.\n"); 617 printk("Caused by (from MCSR=%lx): ", reason); 618 619 if (reason & MCSR_MCP) 620 pr_cont("Machine Check Signal\n"); 621 622 if (reason & MCSR_ICPERR) { 623 pr_cont("Instruction Cache Parity Error\n"); 624 625 /* 626 * This is recoverable by invalidating the i-cache. 627 */ 628 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 629 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 630 ; 631 632 /* 633 * This will generally be accompanied by an instruction 634 * fetch error report -- only treat MCSR_IF as fatal 635 * if it wasn't due to an L1 parity error. 636 */ 637 reason &= ~MCSR_IF; 638 } 639 640 if (reason & MCSR_DCPERR_MC) { 641 pr_cont("Data Cache Parity Error\n"); 642 643 /* 644 * In write shadow mode we auto-recover from the error, but it 645 * may still get logged and cause a machine check. We should 646 * only treat the non-write shadow case as non-recoverable. 647 */ 648 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 649 * is not implemented but L1 data cache always runs in write 650 * shadow mode. Hence on data cache parity errors HW will 651 * automatically invalidate the L1 Data Cache. 652 */ 653 if (PVR_VER(pvr) != PVR_VER_E6500) { 654 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 655 recoverable = 0; 656 } 657 } 658 659 if (reason & MCSR_L2MMU_MHIT) { 660 pr_cont("Hit on multiple TLB entries\n"); 661 recoverable = 0; 662 } 663 664 if (reason & MCSR_NMI) 665 pr_cont("Non-maskable interrupt\n"); 666 667 if (reason & MCSR_IF) { 668 pr_cont("Instruction Fetch Error Report\n"); 669 recoverable = 0; 670 } 671 672 if (reason & MCSR_LD) { 673 pr_cont("Load Error Report\n"); 674 recoverable = 0; 675 } 676 677 if (reason & MCSR_ST) { 678 pr_cont("Store Error Report\n"); 679 recoverable = 0; 680 } 681 682 if (reason & MCSR_LDG) { 683 pr_cont("Guarded Load Error Report\n"); 684 recoverable = 0; 685 } 686 687 if (reason & MCSR_TLBSYNC) 688 pr_cont("Simultaneous tlbsync operations\n"); 689 690 if (reason & MCSR_BSL2_ERR) { 691 pr_cont("Level 2 Cache Error\n"); 692 recoverable = 0; 693 } 694 695 if (reason & MCSR_MAV) { 696 u64 addr; 697 698 addr = mfspr(SPRN_MCAR); 699 addr |= (u64)mfspr(SPRN_MCARU) << 32; 700 701 pr_cont("Machine Check %s Address: %#llx\n", 702 reason & MCSR_MEA ? "Effective" : "Physical", addr); 703 } 704 705 silent_out: 706 mtspr(SPRN_MCSR, mcsr); 707 return mfspr(SPRN_MCSR) == 0 && recoverable; 708 } 709 710 int machine_check_e500(struct pt_regs *regs) 711 { 712 unsigned long reason = mfspr(SPRN_MCSR); 713 714 if (reason & MCSR_BUS_RBERR) { 715 if (fsl_rio_mcheck_exception(regs)) 716 return 1; 717 if (fsl_pci_mcheck_exception(regs)) 718 return 1; 719 } 720 721 printk("Machine check in kernel mode.\n"); 722 printk("Caused by (from MCSR=%lx): ", reason); 723 724 if (reason & MCSR_MCP) 725 pr_cont("Machine Check Signal\n"); 726 if (reason & MCSR_ICPERR) 727 pr_cont("Instruction Cache Parity Error\n"); 728 if (reason & MCSR_DCP_PERR) 729 pr_cont("Data Cache Push Parity Error\n"); 730 if (reason & MCSR_DCPERR) 731 pr_cont("Data Cache Parity Error\n"); 732 if (reason & MCSR_BUS_IAERR) 733 pr_cont("Bus - Instruction Address Error\n"); 734 if (reason & MCSR_BUS_RAERR) 735 pr_cont("Bus - Read Address Error\n"); 736 if (reason & MCSR_BUS_WAERR) 737 pr_cont("Bus - Write Address Error\n"); 738 if (reason & MCSR_BUS_IBERR) 739 pr_cont("Bus - Instruction Data Error\n"); 740 if (reason & MCSR_BUS_RBERR) 741 pr_cont("Bus - Read Data Bus Error\n"); 742 if (reason & MCSR_BUS_WBERR) 743 pr_cont("Bus - Write Data Bus Error\n"); 744 if (reason & MCSR_BUS_IPERR) 745 pr_cont("Bus - Instruction Parity Error\n"); 746 if (reason & MCSR_BUS_RPERR) 747 pr_cont("Bus - Read Parity Error\n"); 748 749 return 0; 750 } 751 752 int machine_check_generic(struct pt_regs *regs) 753 { 754 return 0; 755 } 756 #elif defined(CONFIG_PPC32) 757 int machine_check_generic(struct pt_regs *regs) 758 { 759 unsigned long reason = regs->msr; 760 761 printk("Machine check in kernel mode.\n"); 762 printk("Caused by (from SRR1=%lx): ", reason); 763 switch (reason & 0x601F0000) { 764 case 0x80000: 765 pr_cont("Machine check signal\n"); 766 break; 767 case 0x40000: 768 case 0x140000: /* 7450 MSS error and TEA */ 769 pr_cont("Transfer error ack signal\n"); 770 break; 771 case 0x20000: 772 pr_cont("Data parity error signal\n"); 773 break; 774 case 0x10000: 775 pr_cont("Address parity error signal\n"); 776 break; 777 case 0x20000000: 778 pr_cont("L1 Data Cache error\n"); 779 break; 780 case 0x40000000: 781 pr_cont("L1 Instruction Cache error\n"); 782 break; 783 case 0x00100000: 784 pr_cont("L2 data cache parity error\n"); 785 break; 786 default: 787 pr_cont("Unknown values in msr\n"); 788 } 789 return 0; 790 } 791 #endif /* everything else */ 792 793 void die_mce(const char *str, struct pt_regs *regs, long err) 794 { 795 /* 796 * The machine check wants to kill the interrupted context, 797 * but make_task_dead() checks for in_interrupt() and panics 798 * in that case, so exit the irq/nmi before calling die. 799 */ 800 if (in_nmi()) 801 nmi_exit(); 802 else 803 irq_exit(); 804 die(str, regs, err); 805 } 806 807 /* 808 * BOOK3S_64 does not usually call this handler as a non-maskable interrupt 809 * (it uses its own early real-mode handler to handle the MCE proper 810 * and then raises irq_work to call this handler when interrupts are 811 * enabled). The only time when this is not true is if the early handler 812 * is unrecoverable, then it does call this directly to try to get a 813 * message out. 814 */ 815 static void __machine_check_exception(struct pt_regs *regs) 816 { 817 int recover = 0; 818 819 inc_irq_stat_and_enable(IRQ_COUNT_MCE); 820 821 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 822 823 /* See if any machine dependent calls. In theory, we would want 824 * to call the CPU first, and call the ppc_md. one if the CPU 825 * one returns a positive number. However there is existing code 826 * that assumes the board gets a first chance, so let's keep it 827 * that way for now and fix things later. --BenH. 828 */ 829 if (ppc_md.machine_check_exception) 830 recover = ppc_md.machine_check_exception(regs); 831 else if (cur_cpu_spec->machine_check) 832 recover = cur_cpu_spec->machine_check(regs); 833 834 if (recover > 0) 835 goto bail; 836 837 if (debugger_fault_handler(regs)) 838 goto bail; 839 840 if (check_io_access(regs)) 841 goto bail; 842 843 die_mce("Machine check", regs, SIGBUS); 844 845 bail: 846 /* Must die if the interrupt is not recoverable */ 847 if (regs_is_unrecoverable(regs)) 848 die_mce("Unrecoverable Machine check", regs, SIGBUS); 849 } 850 851 #ifdef CONFIG_PPC_BOOK3S_64 852 DEFINE_INTERRUPT_HANDLER_RAW(machine_check_early_boot) 853 { 854 udbg_printf("Machine check (early boot)\n"); 855 udbg_printf("SRR0=0x%016lx SRR1=0x%016lx\n", regs->nip, regs->msr); 856 udbg_printf(" DAR=0x%016lx DSISR=0x%08lx\n", regs->dar, regs->dsisr); 857 udbg_printf(" LR=0x%016lx R1=0x%08lx\n", regs->link, regs->gpr[1]); 858 udbg_printf("------\n"); 859 die("Machine check (early boot)", regs, SIGBUS); 860 for (;;) 861 ; 862 return 0; 863 } 864 865 DEFINE_INTERRUPT_HANDLER_ASYNC(machine_check_exception_async) 866 { 867 __machine_check_exception(regs); 868 } 869 #endif 870 DEFINE_INTERRUPT_HANDLER_NMI(machine_check_exception) 871 { 872 __machine_check_exception(regs); 873 874 return 0; 875 } 876 877 DEFINE_INTERRUPT_HANDLER(SMIException) /* async? */ 878 { 879 die("System Management Interrupt", regs, SIGABRT); 880 } 881 882 #ifdef CONFIG_VSX 883 static void p9_hmi_special_emu(struct pt_regs *regs) 884 { 885 unsigned int ra, rb, t, i, sel, instr, rc; 886 const void __user *addr; 887 u8 vbuf[16] __aligned(16), *vdst; 888 unsigned long ea, msr, msr_mask; 889 bool swap; 890 891 if (__get_user(instr, (unsigned int __user *)regs->nip)) 892 return; 893 894 /* 895 * lxvb16x opcode: 0x7c0006d8 896 * lxvd2x opcode: 0x7c000698 897 * lxvh8x opcode: 0x7c000658 898 * lxvw4x opcode: 0x7c000618 899 */ 900 if ((instr & 0xfc00073e) != 0x7c000618) { 901 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 902 " instr=%08x\n", 903 smp_processor_id(), current->comm, current->pid, 904 regs->nip, instr); 905 return; 906 } 907 908 /* Grab vector registers into the task struct */ 909 msr = regs->msr; /* Grab msr before we flush the bits */ 910 flush_vsx_to_thread(current); 911 enable_kernel_altivec(); 912 913 /* 914 * Is userspace running with a different endian (this is rare but 915 * not impossible) 916 */ 917 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 918 919 /* Decode the instruction */ 920 ra = (instr >> 16) & 0x1f; 921 rb = (instr >> 11) & 0x1f; 922 t = (instr >> 21) & 0x1f; 923 if (instr & 1) 924 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 925 else 926 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 927 928 /* Grab the vector address */ 929 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 930 if (is_32bit_task()) 931 ea &= 0xfffffffful; 932 addr = (__force const void __user *)ea; 933 934 /* Check it */ 935 if (!access_ok(addr, 16)) { 936 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 937 " instr=%08x addr=%016lx\n", 938 smp_processor_id(), current->comm, current->pid, 939 regs->nip, instr, (unsigned long)addr); 940 return; 941 } 942 943 /* Read the vector */ 944 rc = 0; 945 if ((unsigned long)addr & 0xfUL) 946 /* unaligned case */ 947 rc = __copy_from_user_inatomic(vbuf, addr, 16); 948 else 949 __get_user_atomic_128_aligned(vbuf, addr, rc); 950 if (rc) { 951 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 952 " instr=%08x addr=%016lx\n", 953 smp_processor_id(), current->comm, current->pid, 954 regs->nip, instr, (unsigned long)addr); 955 return; 956 } 957 958 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 959 " instr=%08x addr=%016lx\n", 960 smp_processor_id(), current->comm, current->pid, regs->nip, 961 instr, (unsigned long) addr); 962 963 /* Grab instruction "selector" */ 964 sel = (instr >> 6) & 3; 965 966 /* 967 * Check to make sure the facility is actually enabled. This 968 * could happen if we get a false positive hit. 969 * 970 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 971 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 972 */ 973 msr_mask = MSR_VSX; 974 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 975 msr_mask = MSR_VEC; 976 if (!(msr & msr_mask)) { 977 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 978 " instr=%08x msr:%016lx\n", 979 smp_processor_id(), current->comm, current->pid, 980 regs->nip, instr, msr); 981 return; 982 } 983 984 /* Do logging here before we modify sel based on endian */ 985 switch (sel) { 986 case 0: /* lxvw4x */ 987 PPC_WARN_EMULATED(lxvw4x, regs); 988 break; 989 case 1: /* lxvh8x */ 990 PPC_WARN_EMULATED(lxvh8x, regs); 991 break; 992 case 2: /* lxvd2x */ 993 PPC_WARN_EMULATED(lxvd2x, regs); 994 break; 995 case 3: /* lxvb16x */ 996 PPC_WARN_EMULATED(lxvb16x, regs); 997 break; 998 } 999 1000 #ifdef __LITTLE_ENDIAN__ 1001 /* 1002 * An LE kernel stores the vector in the task struct as an LE 1003 * byte array (effectively swapping both the components and 1004 * the content of the components). Those instructions expect 1005 * the components to remain in ascending address order, so we 1006 * swap them back. 1007 * 1008 * If we are running a BE user space, the expectation is that 1009 * of a simple memcpy, so forcing the emulation to look like 1010 * a lxvb16x should do the trick. 1011 */ 1012 if (swap) 1013 sel = 3; 1014 1015 switch (sel) { 1016 case 0: /* lxvw4x */ 1017 for (i = 0; i < 4; i++) 1018 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 1019 break; 1020 case 1: /* lxvh8x */ 1021 for (i = 0; i < 8; i++) 1022 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 1023 break; 1024 case 2: /* lxvd2x */ 1025 for (i = 0; i < 2; i++) 1026 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 1027 break; 1028 case 3: /* lxvb16x */ 1029 for (i = 0; i < 16; i++) 1030 vdst[i] = vbuf[15-i]; 1031 break; 1032 } 1033 #else /* __LITTLE_ENDIAN__ */ 1034 /* On a big endian kernel, a BE userspace only needs a memcpy */ 1035 if (!swap) 1036 sel = 3; 1037 1038 /* Otherwise, we need to swap the content of the components */ 1039 switch (sel) { 1040 case 0: /* lxvw4x */ 1041 for (i = 0; i < 4; i++) 1042 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 1043 break; 1044 case 1: /* lxvh8x */ 1045 for (i = 0; i < 8; i++) 1046 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 1047 break; 1048 case 2: /* lxvd2x */ 1049 for (i = 0; i < 2; i++) 1050 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 1051 break; 1052 case 3: /* lxvb16x */ 1053 memcpy(vdst, vbuf, 16); 1054 break; 1055 } 1056 #endif /* !__LITTLE_ENDIAN__ */ 1057 1058 /* Go to next instruction */ 1059 regs_add_return_ip(regs, 4); 1060 } 1061 #endif /* CONFIG_VSX */ 1062 1063 DEFINE_INTERRUPT_HANDLER_ASYNC(handle_hmi_exception) 1064 { 1065 struct pt_regs *old_regs; 1066 1067 old_regs = set_irq_regs(regs); 1068 1069 #ifdef CONFIG_VSX 1070 /* Real mode flagged P9 special emu is needed */ 1071 if (local_paca->hmi_p9_special_emu) { 1072 local_paca->hmi_p9_special_emu = 0; 1073 1074 /* 1075 * We don't want to take page faults while doing the 1076 * emulation, we just replay the instruction if necessary. 1077 */ 1078 pagefault_disable(); 1079 p9_hmi_special_emu(regs); 1080 pagefault_enable(); 1081 } 1082 #endif /* CONFIG_VSX */ 1083 1084 if (ppc_md.handle_hmi_exception) 1085 ppc_md.handle_hmi_exception(regs); 1086 1087 set_irq_regs(old_regs); 1088 } 1089 1090 DEFINE_INTERRUPT_HANDLER(unknown_exception) 1091 { 1092 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1093 regs->nip, regs->msr, regs->trap); 1094 1095 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1096 } 1097 1098 DEFINE_INTERRUPT_HANDLER_ASYNC(unknown_async_exception) 1099 { 1100 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1101 regs->nip, regs->msr, regs->trap); 1102 1103 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1104 } 1105 1106 DEFINE_INTERRUPT_HANDLER_NMI(unknown_nmi_exception) 1107 { 1108 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1109 regs->nip, regs->msr, regs->trap); 1110 1111 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1112 1113 return 0; 1114 } 1115 1116 DEFINE_INTERRUPT_HANDLER(instruction_breakpoint_exception) 1117 { 1118 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 1119 5, SIGTRAP) == NOTIFY_STOP) 1120 return; 1121 if (debugger_iabr_match(regs)) 1122 return; 1123 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1124 } 1125 1126 DEFINE_INTERRUPT_HANDLER(RunModeException) 1127 { 1128 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1129 } 1130 1131 static void __single_step_exception(struct pt_regs *regs) 1132 { 1133 clear_single_step(regs); 1134 clear_br_trace(regs); 1135 1136 if (kprobe_post_handler(regs)) 1137 return; 1138 1139 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1140 5, SIGTRAP) == NOTIFY_STOP) 1141 return; 1142 if (debugger_sstep(regs)) 1143 return; 1144 1145 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1146 } 1147 1148 DEFINE_INTERRUPT_HANDLER(single_step_exception) 1149 { 1150 __single_step_exception(regs); 1151 } 1152 1153 /* 1154 * After we have successfully emulated an instruction, we have to 1155 * check if the instruction was being single-stepped, and if so, 1156 * pretend we got a single-step exception. This was pointed out 1157 * by Kumar Gala. -- paulus 1158 */ 1159 void emulate_single_step(struct pt_regs *regs) 1160 { 1161 if (single_stepping(regs)) 1162 __single_step_exception(regs); 1163 } 1164 1165 #ifdef CONFIG_PPC_FPU_REGS 1166 static inline int __parse_fpscr(unsigned long fpscr) 1167 { 1168 int ret = FPE_FLTUNK; 1169 1170 /* Invalid operation */ 1171 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 1172 ret = FPE_FLTINV; 1173 1174 /* Overflow */ 1175 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 1176 ret = FPE_FLTOVF; 1177 1178 /* Underflow */ 1179 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 1180 ret = FPE_FLTUND; 1181 1182 /* Divide by zero */ 1183 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 1184 ret = FPE_FLTDIV; 1185 1186 /* Inexact result */ 1187 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1188 ret = FPE_FLTRES; 1189 1190 return ret; 1191 } 1192 #endif 1193 1194 static void parse_fpe(struct pt_regs *regs) 1195 { 1196 int code = 0; 1197 1198 flush_fp_to_thread(current); 1199 1200 #ifdef CONFIG_PPC_FPU_REGS 1201 code = __parse_fpscr(current->thread.fp_state.fpscr); 1202 #endif 1203 1204 _exception(SIGFPE, regs, code, regs->nip); 1205 } 1206 1207 /* 1208 * Illegal instruction emulation support. Originally written to 1209 * provide the PVR to user applications using the mfspr rd, PVR. 1210 * Return non-zero if we can't emulate, or -EFAULT if the associated 1211 * memory access caused an access fault. Return zero on success. 1212 * 1213 * There are a couple of ways to do this, either "decode" the instruction 1214 * or directly match lots of bits. In this case, matching lots of 1215 * bits is faster and easier. 1216 * 1217 */ 1218 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1219 { 1220 u8 rT = (instword >> 21) & 0x1f; 1221 u8 rA = (instword >> 16) & 0x1f; 1222 u8 NB_RB = (instword >> 11) & 0x1f; 1223 u32 num_bytes; 1224 unsigned long EA; 1225 int pos = 0; 1226 1227 /* Early out if we are an invalid form of lswx */ 1228 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1229 if ((rT == rA) || (rT == NB_RB)) 1230 return -EINVAL; 1231 1232 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1233 1234 switch (instword & PPC_INST_STRING_MASK) { 1235 case PPC_INST_LSWX: 1236 case PPC_INST_STSWX: 1237 EA += NB_RB; 1238 num_bytes = regs->xer & 0x7f; 1239 break; 1240 case PPC_INST_LSWI: 1241 case PPC_INST_STSWI: 1242 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1243 break; 1244 default: 1245 return -EINVAL; 1246 } 1247 1248 while (num_bytes != 0) 1249 { 1250 u8 val; 1251 u32 shift = 8 * (3 - (pos & 0x3)); 1252 1253 /* if process is 32-bit, clear upper 32 bits of EA */ 1254 if ((regs->msr & MSR_64BIT) == 0) 1255 EA &= 0xFFFFFFFF; 1256 1257 switch ((instword & PPC_INST_STRING_MASK)) { 1258 case PPC_INST_LSWX: 1259 case PPC_INST_LSWI: 1260 if (get_user(val, (u8 __user *)EA)) 1261 return -EFAULT; 1262 /* first time updating this reg, 1263 * zero it out */ 1264 if (pos == 0) 1265 regs->gpr[rT] = 0; 1266 regs->gpr[rT] |= val << shift; 1267 break; 1268 case PPC_INST_STSWI: 1269 case PPC_INST_STSWX: 1270 val = regs->gpr[rT] >> shift; 1271 if (put_user(val, (u8 __user *)EA)) 1272 return -EFAULT; 1273 break; 1274 } 1275 /* move EA to next address */ 1276 EA += 1; 1277 num_bytes--; 1278 1279 /* manage our position within the register */ 1280 if (++pos == 4) { 1281 pos = 0; 1282 if (++rT == 32) 1283 rT = 0; 1284 } 1285 } 1286 1287 return 0; 1288 } 1289 1290 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1291 { 1292 u32 ra,rs; 1293 unsigned long tmp; 1294 1295 ra = (instword >> 16) & 0x1f; 1296 rs = (instword >> 21) & 0x1f; 1297 1298 tmp = regs->gpr[rs]; 1299 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1300 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1301 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1302 regs->gpr[ra] = tmp; 1303 1304 return 0; 1305 } 1306 1307 static int emulate_isel(struct pt_regs *regs, u32 instword) 1308 { 1309 u8 rT = (instword >> 21) & 0x1f; 1310 u8 rA = (instword >> 16) & 0x1f; 1311 u8 rB = (instword >> 11) & 0x1f; 1312 u8 BC = (instword >> 6) & 0x1f; 1313 u8 bit; 1314 unsigned long tmp; 1315 1316 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1317 bit = (regs->ccr >> (31 - BC)) & 0x1; 1318 1319 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1320 1321 return 0; 1322 } 1323 1324 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1325 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1326 { 1327 /* If we're emulating a load/store in an active transaction, we cannot 1328 * emulate it as the kernel operates in transaction suspended context. 1329 * We need to abort the transaction. This creates a persistent TM 1330 * abort so tell the user what caused it with a new code. 1331 */ 1332 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1333 tm_enable(); 1334 tm_abort(cause); 1335 return true; 1336 } 1337 return false; 1338 } 1339 #else 1340 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1341 { 1342 return false; 1343 } 1344 #endif 1345 1346 static int emulate_instruction(struct pt_regs *regs) 1347 { 1348 u32 instword; 1349 u32 rd; 1350 1351 if (!user_mode(regs)) 1352 return -EINVAL; 1353 1354 if (get_user(instword, (u32 __user *)(regs->nip))) 1355 return -EFAULT; 1356 1357 /* Emulate the mfspr rD, PVR. */ 1358 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1359 PPC_WARN_EMULATED(mfpvr, regs); 1360 rd = (instword >> 21) & 0x1f; 1361 regs->gpr[rd] = mfspr(SPRN_PVR); 1362 return 0; 1363 } 1364 1365 /* Emulating the dcba insn is just a no-op. */ 1366 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1367 PPC_WARN_EMULATED(dcba, regs); 1368 return 0; 1369 } 1370 1371 /* Emulate the mcrxr insn. */ 1372 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1373 int shift = (instword >> 21) & 0x1c; 1374 unsigned long msk = 0xf0000000UL >> shift; 1375 1376 PPC_WARN_EMULATED(mcrxr, regs); 1377 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1378 regs->xer &= ~0xf0000000UL; 1379 return 0; 1380 } 1381 1382 /* Emulate load/store string insn. */ 1383 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1384 if (tm_abort_check(regs, 1385 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1386 return -EINVAL; 1387 PPC_WARN_EMULATED(string, regs); 1388 return emulate_string_inst(regs, instword); 1389 } 1390 1391 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1392 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1393 PPC_WARN_EMULATED(popcntb, regs); 1394 return emulate_popcntb_inst(regs, instword); 1395 } 1396 1397 /* Emulate isel (Integer Select) instruction */ 1398 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1399 PPC_WARN_EMULATED(isel, regs); 1400 return emulate_isel(regs, instword); 1401 } 1402 1403 /* Emulate sync instruction variants */ 1404 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1405 PPC_WARN_EMULATED(sync, regs); 1406 asm volatile("sync"); 1407 return 0; 1408 } 1409 1410 #ifdef CONFIG_PPC64 1411 /* Emulate the mfspr rD, DSCR. */ 1412 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1413 PPC_INST_MFSPR_DSCR_USER) || 1414 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1415 PPC_INST_MFSPR_DSCR)) && 1416 cpu_has_feature(CPU_FTR_DSCR)) { 1417 PPC_WARN_EMULATED(mfdscr, regs); 1418 rd = (instword >> 21) & 0x1f; 1419 regs->gpr[rd] = mfspr(SPRN_DSCR); 1420 return 0; 1421 } 1422 /* Emulate the mtspr DSCR, rD. */ 1423 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1424 PPC_INST_MTSPR_DSCR_USER) || 1425 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1426 PPC_INST_MTSPR_DSCR)) && 1427 cpu_has_feature(CPU_FTR_DSCR)) { 1428 PPC_WARN_EMULATED(mtdscr, regs); 1429 rd = (instword >> 21) & 0x1f; 1430 current->thread.dscr = regs->gpr[rd]; 1431 current->thread.dscr_inherit = 1; 1432 mtspr(SPRN_DSCR, current->thread.dscr); 1433 return 0; 1434 } 1435 #endif 1436 1437 return -EINVAL; 1438 } 1439 1440 #ifdef CONFIG_GENERIC_BUG 1441 int is_valid_bugaddr(unsigned long addr) 1442 { 1443 return is_kernel_addr(addr); 1444 } 1445 #endif 1446 1447 #ifdef CONFIG_MATH_EMULATION 1448 static int emulate_math(struct pt_regs *regs) 1449 { 1450 int ret; 1451 1452 ret = do_mathemu(regs); 1453 if (ret >= 0) 1454 PPC_WARN_EMULATED(math, regs); 1455 1456 switch (ret) { 1457 case 0: 1458 emulate_single_step(regs); 1459 return 0; 1460 case 1: { 1461 int code = 0; 1462 code = __parse_fpscr(current->thread.fp_state.fpscr); 1463 _exception(SIGFPE, regs, code, regs->nip); 1464 return 0; 1465 } 1466 case -EFAULT: 1467 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1468 return 0; 1469 } 1470 1471 return -1; 1472 } 1473 #else 1474 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1475 #endif 1476 1477 static void do_program_check(struct pt_regs *regs) 1478 { 1479 unsigned int reason = get_reason(regs); 1480 1481 /* We can now get here via a FP Unavailable exception if the core 1482 * has no FPU, in that case the reason flags will be 0 */ 1483 1484 if (reason & REASON_FP) { 1485 /* IEEE FP exception */ 1486 parse_fpe(regs); 1487 return; 1488 } 1489 if (reason & REASON_TRAP) { 1490 unsigned long bugaddr; 1491 /* Debugger is first in line to stop recursive faults in 1492 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1493 if (debugger_bpt(regs)) 1494 return; 1495 1496 if (kprobe_handler(regs)) 1497 return; 1498 1499 /* trap exception */ 1500 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1501 == NOTIFY_STOP) 1502 return; 1503 1504 bugaddr = regs->nip; 1505 /* 1506 * Fixup bugaddr for BUG_ON() in real mode 1507 */ 1508 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1509 bugaddr += PAGE_OFFSET; 1510 1511 if (!user_mode(regs) && 1512 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1513 regs_add_return_ip(regs, 4); 1514 return; 1515 } 1516 1517 /* User mode considers other cases after enabling IRQs */ 1518 if (!user_mode(regs)) { 1519 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1520 return; 1521 } 1522 } 1523 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1524 if (reason & REASON_TM) { 1525 /* This is a TM "Bad Thing Exception" program check. 1526 * This occurs when: 1527 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1528 * transition in TM states. 1529 * - A trechkpt is attempted when transactional. 1530 * - A treclaim is attempted when non transactional. 1531 * - A tend is illegally attempted. 1532 * - writing a TM SPR when transactional. 1533 * 1534 * If usermode caused this, it's done something illegal and 1535 * gets a SIGILL slap on the wrist. We call it an illegal 1536 * operand to distinguish from the instruction just being bad 1537 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1538 * illegal /placement/ of a valid instruction. 1539 */ 1540 if (user_mode(regs)) { 1541 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1542 return; 1543 } else { 1544 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1545 "at %lx (msr 0x%lx) tm_scratch=%llx\n", 1546 regs->nip, regs->msr, get_paca()->tm_scratch); 1547 die("Unrecoverable exception", regs, SIGABRT); 1548 } 1549 } 1550 #endif 1551 1552 /* 1553 * If we took the program check in the kernel skip down to sending a 1554 * SIGILL. The subsequent cases all relate to user space, such as 1555 * emulating instructions which we should only do for user space. We 1556 * also do not want to enable interrupts for kernel faults because that 1557 * might lead to further faults, and loose the context of the original 1558 * exception. 1559 */ 1560 if (!user_mode(regs)) 1561 goto sigill; 1562 1563 interrupt_cond_local_irq_enable(regs); 1564 1565 /* 1566 * (reason & REASON_TRAP) is mostly handled before enabling IRQs, 1567 * except get_user_instr() can sleep so we cannot reliably inspect the 1568 * current instruction in that context. Now that we know we are 1569 * handling a user space trap and can sleep, we can check if the trap 1570 * was a hashchk failure. 1571 */ 1572 if (reason & REASON_TRAP) { 1573 if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE)) { 1574 ppc_inst_t insn; 1575 1576 if (get_user_instr(insn, (void __user *)regs->nip)) { 1577 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1578 return; 1579 } 1580 1581 if (ppc_inst_primary_opcode(insn) == 31 && 1582 get_xop(ppc_inst_val(insn)) == OP_31_XOP_HASHCHK) { 1583 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1584 return; 1585 } 1586 } 1587 1588 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1589 return; 1590 } 1591 1592 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1593 * but there seems to be a hardware bug on the 405GP (RevD) 1594 * that means ESR is sometimes set incorrectly - either to 1595 * ESR_DST (!?) or 0. In the process of chasing this with the 1596 * hardware people - not sure if it can happen on any illegal 1597 * instruction or only on FP instructions, whether there is a 1598 * pattern to occurrences etc. -dgibson 31/Mar/2003 1599 */ 1600 if (!emulate_math(regs)) 1601 return; 1602 1603 /* Try to emulate it if we should. */ 1604 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1605 switch (emulate_instruction(regs)) { 1606 case 0: 1607 regs_add_return_ip(regs, 4); 1608 emulate_single_step(regs); 1609 return; 1610 case -EFAULT: 1611 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1612 return; 1613 } 1614 } 1615 1616 sigill: 1617 if (reason & REASON_PRIVILEGED) 1618 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1619 else 1620 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1621 1622 } 1623 1624 DEFINE_INTERRUPT_HANDLER(program_check_exception) 1625 { 1626 do_program_check(regs); 1627 } 1628 1629 /* 1630 * This occurs when running in hypervisor mode on POWER6 or later 1631 * and an illegal instruction is encountered. 1632 */ 1633 DEFINE_INTERRUPT_HANDLER(emulation_assist_interrupt) 1634 { 1635 regs_set_return_msr(regs, regs->msr | REASON_ILLEGAL); 1636 do_program_check(regs); 1637 } 1638 1639 DEFINE_INTERRUPT_HANDLER(alignment_exception) 1640 { 1641 int sig, code, fixed = 0; 1642 unsigned long reason; 1643 1644 interrupt_cond_local_irq_enable(regs); 1645 1646 reason = get_reason(regs); 1647 if (reason & REASON_BOUNDARY) { 1648 sig = SIGBUS; 1649 code = BUS_ADRALN; 1650 goto bad; 1651 } 1652 1653 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1654 return; 1655 1656 /* we don't implement logging of alignment exceptions */ 1657 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1658 fixed = fix_alignment(regs); 1659 1660 if (fixed == 1) { 1661 /* skip over emulated instruction */ 1662 regs_add_return_ip(regs, inst_length(reason)); 1663 emulate_single_step(regs); 1664 return; 1665 } 1666 1667 /* Operand address was bad */ 1668 if (fixed == -EFAULT) { 1669 sig = SIGSEGV; 1670 code = SEGV_ACCERR; 1671 } else { 1672 sig = SIGBUS; 1673 code = BUS_ADRALN; 1674 } 1675 bad: 1676 if (user_mode(regs)) 1677 _exception(sig, regs, code, regs->dar); 1678 else 1679 bad_page_fault(regs, sig); 1680 } 1681 1682 DEFINE_INTERRUPT_HANDLER(stack_overflow_exception) 1683 { 1684 die("Kernel stack overflow", regs, SIGSEGV); 1685 } 1686 1687 DEFINE_INTERRUPT_HANDLER(kernel_fp_unavailable_exception) 1688 { 1689 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1690 "%lx at %lx\n", regs->trap, regs->nip); 1691 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1692 } 1693 1694 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_exception) 1695 { 1696 if (user_mode(regs)) { 1697 /* A user program has executed an altivec instruction, 1698 but this kernel doesn't support altivec. */ 1699 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1700 return; 1701 } 1702 1703 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1704 "%lx at %lx\n", regs->trap, regs->nip); 1705 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1706 } 1707 1708 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_exception) 1709 { 1710 if (user_mode(regs)) { 1711 /* A user program has executed an vsx instruction, 1712 but this kernel doesn't support vsx. */ 1713 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1714 return; 1715 } 1716 1717 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1718 "%lx at %lx\n", regs->trap, regs->nip); 1719 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1720 } 1721 1722 #ifdef CONFIG_PPC_BOOK3S_64 1723 static void tm_unavailable(struct pt_regs *regs) 1724 { 1725 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1726 if (user_mode(regs)) { 1727 current->thread.load_tm++; 1728 regs_set_return_msr(regs, regs->msr | MSR_TM); 1729 tm_enable(); 1730 tm_restore_sprs(¤t->thread); 1731 return; 1732 } 1733 #endif 1734 pr_emerg("Unrecoverable TM Unavailable Exception " 1735 "%lx at %lx\n", regs->trap, regs->nip); 1736 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1737 } 1738 1739 DEFINE_INTERRUPT_HANDLER(facility_unavailable_exception) 1740 { 1741 static char *facility_strings[] = { 1742 [FSCR_FP_LG] = "FPU", 1743 [FSCR_VECVSX_LG] = "VMX/VSX", 1744 [FSCR_DSCR_LG] = "DSCR", 1745 [FSCR_PM_LG] = "PMU SPRs", 1746 [FSCR_BHRB_LG] = "BHRB", 1747 [FSCR_TM_LG] = "TM", 1748 [FSCR_EBB_LG] = "EBB", 1749 [FSCR_TAR_LG] = "TAR", 1750 [FSCR_MSGP_LG] = "MSGP", 1751 [FSCR_SCV_LG] = "SCV", 1752 [FSCR_PREFIX_LG] = "PREFIX", 1753 }; 1754 char *facility = "unknown"; 1755 u64 value; 1756 u32 instword, rd; 1757 u8 status; 1758 bool hv; 1759 1760 hv = (TRAP(regs) == INTERRUPT_H_FAC_UNAVAIL); 1761 if (hv) 1762 value = mfspr(SPRN_HFSCR); 1763 else 1764 value = mfspr(SPRN_FSCR); 1765 1766 status = value >> 56; 1767 if ((hv || status >= 2) && 1768 (status < ARRAY_SIZE(facility_strings)) && 1769 facility_strings[status]) 1770 facility = facility_strings[status]; 1771 1772 /* We should not have taken this interrupt in kernel */ 1773 if (!user_mode(regs)) { 1774 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1775 facility, status, regs->nip); 1776 die("Unexpected facility unavailable exception", regs, SIGABRT); 1777 } 1778 1779 interrupt_cond_local_irq_enable(regs); 1780 1781 if (status == FSCR_DSCR_LG) { 1782 /* 1783 * User is accessing the DSCR register using the problem 1784 * state only SPR number (0x03) either through a mfspr or 1785 * a mtspr instruction. If it is a write attempt through 1786 * a mtspr, then we set the inherit bit. This also allows 1787 * the user to write or read the register directly in the 1788 * future by setting via the FSCR DSCR bit. But in case it 1789 * is a read DSCR attempt through a mfspr instruction, we 1790 * just emulate the instruction instead. This code path will 1791 * always emulate all the mfspr instructions till the user 1792 * has attempted at least one mtspr instruction. This way it 1793 * preserves the same behaviour when the user is accessing 1794 * the DSCR through privilege level only SPR number (0x11) 1795 * which is emulated through illegal instruction exception. 1796 * We always leave HFSCR DSCR set. 1797 */ 1798 if (get_user(instword, (u32 __user *)(regs->nip))) { 1799 pr_err("Failed to fetch the user instruction\n"); 1800 return; 1801 } 1802 1803 /* Write into DSCR (mtspr 0x03, RS) */ 1804 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1805 == PPC_INST_MTSPR_DSCR_USER) { 1806 rd = (instword >> 21) & 0x1f; 1807 current->thread.dscr = regs->gpr[rd]; 1808 current->thread.dscr_inherit = 1; 1809 current->thread.fscr |= FSCR_DSCR; 1810 mtspr(SPRN_FSCR, current->thread.fscr); 1811 } 1812 1813 /* Read from DSCR (mfspr RT, 0x03) */ 1814 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1815 == PPC_INST_MFSPR_DSCR_USER) { 1816 if (emulate_instruction(regs)) { 1817 pr_err("DSCR based mfspr emulation failed\n"); 1818 return; 1819 } 1820 regs_add_return_ip(regs, 4); 1821 emulate_single_step(regs); 1822 } 1823 return; 1824 } 1825 1826 if (status == FSCR_TM_LG) { 1827 /* 1828 * If we're here then the hardware is TM aware because it 1829 * generated an exception with FSRM_TM set. 1830 * 1831 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1832 * told us not to do TM, or the kernel is not built with TM 1833 * support. 1834 * 1835 * If both of those things are true, then userspace can spam the 1836 * console by triggering the printk() below just by continually 1837 * doing tbegin (or any TM instruction). So in that case just 1838 * send the process a SIGILL immediately. 1839 */ 1840 if (!cpu_has_feature(CPU_FTR_TM)) 1841 goto out; 1842 1843 tm_unavailable(regs); 1844 return; 1845 } 1846 1847 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1848 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1849 1850 out: 1851 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1852 } 1853 #endif 1854 1855 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1856 1857 DEFINE_INTERRUPT_HANDLER(fp_unavailable_tm) 1858 { 1859 /* Note: This does not handle any kind of FP laziness. */ 1860 1861 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1862 regs->nip, regs->msr); 1863 1864 /* We can only have got here if the task started using FP after 1865 * beginning the transaction. So, the transactional regs are just a 1866 * copy of the checkpointed ones. But, we still need to recheckpoint 1867 * as we're enabling FP for the process; it will return, abort the 1868 * transaction, and probably retry but now with FP enabled. So the 1869 * checkpointed FP registers need to be loaded. 1870 */ 1871 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1872 1873 /* 1874 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 1875 * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 1876 * 1877 * At this point, ck{fp,vr}_state contains the exact values we want to 1878 * recheckpoint. 1879 */ 1880 1881 /* Enable FP for the task: */ 1882 current->thread.load_fp = 1; 1883 1884 /* 1885 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1886 */ 1887 tm_recheckpoint(¤t->thread); 1888 } 1889 1890 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_tm) 1891 { 1892 /* See the comments in fp_unavailable_tm(). This function operates 1893 * the same way. 1894 */ 1895 1896 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1897 "MSR=%lx\n", 1898 regs->nip, regs->msr); 1899 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1900 current->thread.load_vec = 1; 1901 tm_recheckpoint(¤t->thread); 1902 current->thread.used_vr = 1; 1903 } 1904 1905 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_tm) 1906 { 1907 /* See the comments in fp_unavailable_tm(). This works similarly, 1908 * though we're loading both FP and VEC registers in here. 1909 * 1910 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1911 * regs. Either way, set MSR_VSX. 1912 */ 1913 1914 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1915 "MSR=%lx\n", 1916 regs->nip, regs->msr); 1917 1918 current->thread.used_vsr = 1; 1919 1920 /* This reclaims FP and/or VR regs if they're already enabled */ 1921 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1922 1923 current->thread.load_vec = 1; 1924 current->thread.load_fp = 1; 1925 1926 tm_recheckpoint(¤t->thread); 1927 } 1928 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1929 1930 #ifdef CONFIG_PPC64 1931 DECLARE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi); 1932 DEFINE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi) 1933 { 1934 inc_irq_stat(PMI); 1935 perf_irq(regs); 1936 1937 return 0; 1938 } 1939 #endif 1940 1941 DECLARE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async); 1942 DEFINE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async) 1943 { 1944 inc_irq_stat(PMI); 1945 perf_irq(regs); 1946 } 1947 1948 DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exception) 1949 { 1950 /* 1951 * On 64-bit, if perf interrupts hit in a local_irq_disable 1952 * (soft-masked) region, we consider them as NMIs. This is required to 1953 * prevent hash faults on user addresses when reading callchains (and 1954 * looks better from an irq tracing perspective). 1955 */ 1956 if (IS_ENABLED(CONFIG_PPC64) && unlikely(regs_irqs_disabled(regs))) 1957 performance_monitor_exception_nmi(regs); 1958 else 1959 performance_monitor_exception_async(regs); 1960 1961 return 0; 1962 } 1963 1964 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1965 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1966 { 1967 int changed = 0; 1968 /* 1969 * Determine the cause of the debug event, clear the 1970 * event flags and send a trap to the handler. Torez 1971 */ 1972 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1973 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1974 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1975 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1976 #endif 1977 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 1978 5); 1979 changed |= 0x01; 1980 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1981 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1982 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 1983 6); 1984 changed |= 0x01; 1985 } else if (debug_status & DBSR_IAC1) { 1986 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1987 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1988 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 1989 1); 1990 changed |= 0x01; 1991 } else if (debug_status & DBSR_IAC2) { 1992 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1993 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 1994 2); 1995 changed |= 0x01; 1996 } else if (debug_status & DBSR_IAC3) { 1997 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1998 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1999 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 2000 3); 2001 changed |= 0x01; 2002 } else if (debug_status & DBSR_IAC4) { 2003 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 2004 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 2005 4); 2006 changed |= 0x01; 2007 } 2008 /* 2009 * At the point this routine was called, the MSR(DE) was turned off. 2010 * Check all other debug flags and see if that bit needs to be turned 2011 * back on or not. 2012 */ 2013 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 2014 current->thread.debug.dbcr1)) 2015 regs_set_return_msr(regs, regs->msr | MSR_DE); 2016 else 2017 /* Make sure the IDM flag is off */ 2018 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 2019 2020 if (changed & 0x01) 2021 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 2022 } 2023 2024 DEFINE_INTERRUPT_HANDLER(DebugException) 2025 { 2026 unsigned long debug_status = regs->dsisr; 2027 2028 current->thread.debug.dbsr = debug_status; 2029 2030 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 2031 * on server, it stops on the target of the branch. In order to simulate 2032 * the server behaviour, we thus restart right away with a single step 2033 * instead of stopping here when hitting a BT 2034 */ 2035 if (debug_status & DBSR_BT) { 2036 regs_set_return_msr(regs, regs->msr & ~MSR_DE); 2037 2038 /* Disable BT */ 2039 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 2040 /* Clear the BT event */ 2041 mtspr(SPRN_DBSR, DBSR_BT); 2042 2043 /* Do the single step trick only when coming from userspace */ 2044 if (user_mode(regs)) { 2045 current->thread.debug.dbcr0 &= ~DBCR0_BT; 2046 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 2047 regs_set_return_msr(regs, regs->msr | MSR_DE); 2048 return; 2049 } 2050 2051 if (kprobe_post_handler(regs)) 2052 return; 2053 2054 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 2055 5, SIGTRAP) == NOTIFY_STOP) { 2056 return; 2057 } 2058 if (debugger_sstep(regs)) 2059 return; 2060 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 2061 regs_set_return_msr(regs, regs->msr & ~MSR_DE); 2062 2063 /* Disable instruction completion */ 2064 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 2065 /* Clear the instruction completion event */ 2066 mtspr(SPRN_DBSR, DBSR_IC); 2067 2068 if (kprobe_post_handler(regs)) 2069 return; 2070 2071 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 2072 5, SIGTRAP) == NOTIFY_STOP) { 2073 return; 2074 } 2075 2076 if (debugger_sstep(regs)) 2077 return; 2078 2079 if (user_mode(regs)) { 2080 current->thread.debug.dbcr0 &= ~DBCR0_IC; 2081 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 2082 current->thread.debug.dbcr1)) 2083 regs_set_return_msr(regs, regs->msr | MSR_DE); 2084 else 2085 /* Make sure the IDM bit is off */ 2086 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 2087 } 2088 2089 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 2090 } else 2091 handle_debug(regs, debug_status); 2092 } 2093 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 2094 2095 #ifdef CONFIG_ALTIVEC 2096 DEFINE_INTERRUPT_HANDLER(altivec_assist_exception) 2097 { 2098 int err; 2099 2100 if (!user_mode(regs)) { 2101 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 2102 " at %lx\n", regs->nip); 2103 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 2104 } 2105 2106 flush_altivec_to_thread(current); 2107 2108 PPC_WARN_EMULATED(altivec, regs); 2109 err = emulate_altivec(regs); 2110 if (err == 0) { 2111 regs_add_return_ip(regs, 4); /* skip emulated instruction */ 2112 emulate_single_step(regs); 2113 return; 2114 } 2115 2116 if (err == -EFAULT) { 2117 /* got an error reading the instruction */ 2118 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2119 } else { 2120 /* didn't recognize the instruction */ 2121 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 2122 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 2123 "in %s at %lx\n", current->comm, regs->nip); 2124 current->thread.vr_state.vscr.u[3] |= 0x10000; 2125 } 2126 } 2127 #endif /* CONFIG_ALTIVEC */ 2128 2129 #ifdef CONFIG_PPC_85xx 2130 DEFINE_INTERRUPT_HANDLER(CacheLockingException) 2131 { 2132 unsigned long error_code = regs->dsisr; 2133 2134 /* We treat cache locking instructions from the user 2135 * as priv ops, in the future we could try to do 2136 * something smarter 2137 */ 2138 if (error_code & (ESR_DLK|ESR_ILK)) 2139 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 2140 return; 2141 } 2142 #endif /* CONFIG_PPC_85xx */ 2143 2144 #ifdef CONFIG_SPE 2145 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException) 2146 { 2147 unsigned long spefscr; 2148 int fpexc_mode; 2149 int code = FPE_FLTUNK; 2150 int err; 2151 2152 interrupt_cond_local_irq_enable(regs); 2153 2154 flush_spe_to_thread(current); 2155 2156 spefscr = current->thread.spefscr; 2157 fpexc_mode = current->thread.fpexc_mode; 2158 2159 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 2160 code = FPE_FLTOVF; 2161 } 2162 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 2163 code = FPE_FLTUND; 2164 } 2165 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 2166 code = FPE_FLTDIV; 2167 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 2168 code = FPE_FLTINV; 2169 } 2170 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 2171 code = FPE_FLTRES; 2172 2173 err = do_spe_mathemu(regs); 2174 if (err == 0) { 2175 regs_add_return_ip(regs, 4); /* skip emulated instruction */ 2176 emulate_single_step(regs); 2177 return; 2178 } 2179 2180 if (err == -EFAULT) { 2181 /* got an error reading the instruction */ 2182 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2183 } else if (err == -EINVAL) { 2184 /* didn't recognize the instruction */ 2185 printk(KERN_ERR "unrecognized spe instruction " 2186 "in %s at %lx\n", current->comm, regs->nip); 2187 } else { 2188 _exception(SIGFPE, regs, code, regs->nip); 2189 } 2190 2191 return; 2192 } 2193 2194 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException) 2195 { 2196 int err; 2197 2198 interrupt_cond_local_irq_enable(regs); 2199 2200 preempt_disable(); 2201 if (regs->msr & MSR_SPE) 2202 giveup_spe(current); 2203 preempt_enable(); 2204 2205 regs_add_return_ip(regs, -4); 2206 err = speround_handler(regs); 2207 if (err == 0) { 2208 regs_add_return_ip(regs, 4); /* skip emulated instruction */ 2209 emulate_single_step(regs); 2210 return; 2211 } 2212 2213 if (err == -EFAULT) { 2214 /* got an error reading the instruction */ 2215 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2216 } else if (err == -EINVAL) { 2217 /* didn't recognize the instruction */ 2218 printk(KERN_ERR "unrecognized spe instruction " 2219 "in %s at %lx\n", current->comm, regs->nip); 2220 } else { 2221 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 2222 return; 2223 } 2224 } 2225 #endif 2226 2227 /* 2228 * We enter here if we get an unrecoverable exception, that is, one 2229 * that happened at a point where the RI (recoverable interrupt) bit 2230 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2231 * we therefore lost state by taking this exception. 2232 */ 2233 void __noreturn unrecoverable_exception(struct pt_regs *regs) 2234 { 2235 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 2236 regs->trap, regs->nip, regs->msr); 2237 die("Unrecoverable exception", regs, SIGABRT); 2238 /* die() should not return */ 2239 for (;;) 2240 ; 2241 } 2242 2243 #ifdef CONFIG_BOOKE_WDT 2244 DEFINE_INTERRUPT_HANDLER_NMI(WatchdogException) 2245 { 2246 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2247 mtspr(SPRN_TCR, mfspr(SPRN_TCR) & ~TCR_WIE); 2248 return 0; 2249 } 2250 #endif 2251 2252 /* 2253 * We enter here if we discover during exception entry that we are 2254 * running in supervisor mode with a userspace value in the stack pointer. 2255 */ 2256 DEFINE_INTERRUPT_HANDLER(kernel_bad_stack) 2257 { 2258 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2259 regs->gpr[1], regs->nip); 2260 die("Bad kernel stack pointer", regs, SIGABRT); 2261 } 2262 2263 #ifdef CONFIG_PPC_EMULATED_STATS 2264 2265 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2266 2267 struct ppc_emulated ppc_emulated = { 2268 #ifdef CONFIG_ALTIVEC 2269 WARN_EMULATED_SETUP(altivec), 2270 #endif 2271 WARN_EMULATED_SETUP(dcba), 2272 WARN_EMULATED_SETUP(dcbz), 2273 WARN_EMULATED_SETUP(fp_pair), 2274 WARN_EMULATED_SETUP(isel), 2275 WARN_EMULATED_SETUP(mcrxr), 2276 WARN_EMULATED_SETUP(mfpvr), 2277 WARN_EMULATED_SETUP(multiple), 2278 WARN_EMULATED_SETUP(popcntb), 2279 WARN_EMULATED_SETUP(spe), 2280 WARN_EMULATED_SETUP(string), 2281 WARN_EMULATED_SETUP(sync), 2282 WARN_EMULATED_SETUP(unaligned), 2283 #ifdef CONFIG_MATH_EMULATION 2284 WARN_EMULATED_SETUP(math), 2285 #endif 2286 #ifdef CONFIG_VSX 2287 WARN_EMULATED_SETUP(vsx), 2288 #endif 2289 #ifdef CONFIG_PPC64 2290 WARN_EMULATED_SETUP(mfdscr), 2291 WARN_EMULATED_SETUP(mtdscr), 2292 WARN_EMULATED_SETUP(lq_stq), 2293 WARN_EMULATED_SETUP(lxvw4x), 2294 WARN_EMULATED_SETUP(lxvh8x), 2295 WARN_EMULATED_SETUP(lxvd2x), 2296 WARN_EMULATED_SETUP(lxvb16x), 2297 #endif 2298 }; 2299 2300 u32 ppc_warn_emulated; 2301 2302 void ppc_warn_emulated_print(const char *type) 2303 { 2304 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2305 type); 2306 } 2307 2308 static int __init ppc_warn_emulated_init(void) 2309 { 2310 struct dentry *dir; 2311 unsigned int i; 2312 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2313 2314 dir = debugfs_create_dir("emulated_instructions", 2315 arch_debugfs_dir); 2316 2317 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated); 2318 2319 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) 2320 debugfs_create_u32(entries[i].name, 0644, dir, 2321 (u32 *)&entries[i].val.counter); 2322 2323 return 0; 2324 } 2325 2326 device_initcall(ppc_warn_emulated_init); 2327 2328 #endif /* CONFIG_PPC_EMULATED_STATS */ 2329