12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 214cf11afSPaul Mackerras /* 314cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4fe04b112SScott Wood * Copyright 2007-2010 Freescale Semiconductor, Inc. 514cf11afSPaul Mackerras * 614cf11afSPaul Mackerras * Modified by Cort Dougan (cort@cs.nmt.edu) 714cf11afSPaul Mackerras * and Paul Mackerras (paulus@samba.org) 814cf11afSPaul Mackerras */ 914cf11afSPaul Mackerras 1014cf11afSPaul Mackerras /* 1114cf11afSPaul Mackerras * This file handles the architecture-dependent parts of hardware exceptions 1214cf11afSPaul Mackerras */ 1314cf11afSPaul Mackerras 1414cf11afSPaul Mackerras #include <linux/errno.h> 1514cf11afSPaul Mackerras #include <linux/sched.h> 16b17b0153SIngo Molnar #include <linux/sched/debug.h> 1714cf11afSPaul Mackerras #include <linux/kernel.h> 1814cf11afSPaul Mackerras #include <linux/mm.h> 1999cd1302SRam Pai #include <linux/pkeys.h> 2014cf11afSPaul Mackerras #include <linux/stddef.h> 2114cf11afSPaul Mackerras #include <linux/unistd.h> 228dad3f92SPaul Mackerras #include <linux/ptrace.h> 2314cf11afSPaul Mackerras #include <linux/user.h> 2414cf11afSPaul Mackerras #include <linux/interrupt.h> 2514cf11afSPaul Mackerras #include <linux/init.h> 268a39b05fSPaul Gortmaker #include <linux/extable.h> 278a39b05fSPaul Gortmaker #include <linux/module.h> /* print_modules */ 288dad3f92SPaul Mackerras #include <linux/prctl.h> 2914cf11afSPaul Mackerras #include <linux/delay.h> 3014cf11afSPaul Mackerras #include <linux/kprobes.h> 31cc532915SMichael Ellerman #include <linux/kexec.h> 325474c120SMichael Hanselmann #include <linux/backlight.h> 3373c9ceabSJeremy Fitzhardinge #include <linux/bug.h> 341eeb66a1SChristoph Hellwig #include <linux/kdebug.h> 3576462232SChristian Dietrich #include <linux/ratelimit.h> 36ba12eedeSLi Zhong #include <linux/context_tracking.h> 375080332cSMichael Neuling #include <linux/smp.h> 3835adacd6SNicholas Piggin #include <linux/console.h> 3935adacd6SNicholas Piggin #include <linux/kmsg_dump.h> 40dbf77fedSAneesh Kumar K.V #include <linux/debugfs.h> 4114cf11afSPaul Mackerras 4280947e7cSGeert Uytterhoeven #include <asm/emulated_ops.h> 437c0f6ba6SLinus Torvalds #include <linux/uaccess.h> 443a96570fSNicholas Piggin #include <asm/interrupt.h> 4514cf11afSPaul Mackerras #include <asm/io.h> 4686417780SPaul Mackerras #include <asm/machdep.h> 4786417780SPaul Mackerras #include <asm/rtas.h> 48f7f6f4feSDavid Gibson #include <asm/pmc.h> 4914cf11afSPaul Mackerras #include <asm/reg.h> 5014cf11afSPaul Mackerras #ifdef CONFIG_PMAC_BACKLIGHT 5114cf11afSPaul Mackerras #include <asm/backlight.h> 5214cf11afSPaul Mackerras #endif 53dc1c1ca3SStephen Rothwell #ifdef CONFIG_PPC64 5486417780SPaul Mackerras #include <asm/firmware.h> 55dc1c1ca3SStephen Rothwell #include <asm/processor.h> 56dc1c1ca3SStephen Rothwell #endif 57c0ce7d08SDavid Wilder #include <asm/kexec.h> 5816c57b36SKumar Gala #include <asm/ppc-opcode.h> 59cce1f106SShaohui Xie #include <asm/rio.h> 60ebaeb5aeSMahesh Salgaonkar #include <asm/fadump.h> 61ae3a197eSDavid Howells #include <asm/switch_to.h> 62f54db641SMichael Neuling #include <asm/tm.h> 63ae3a197eSDavid Howells #include <asm/debug.h> 6442f5b4caSDaniel Axtens #include <asm/asm-prototypes.h> 65fd7bacbcSMahesh Salgaonkar #include <asm/hmi.h> 664e0e3435SHongtao Jia #include <sysdev/fsl_pci.h> 676cc89badSNaveen N. Rao #include <asm/kprobes.h> 68a99b9c5eSMurilo Opsfelder Araujo #include <asm/stacktrace.h> 69de3c83c2SMathieu Malaterre #include <asm/nmi.h> 70deefd0aeSChristophe Leroy #include <asm/disassemble.h> 71dc1c1ca3SStephen Rothwell 72da665885SThiago Jung Bauermann #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 735be3492fSAnton Blanchard int (*__debugger)(struct pt_regs *regs) __read_mostly; 745be3492fSAnton Blanchard int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 755be3492fSAnton Blanchard int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 765be3492fSAnton Blanchard int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 775be3492fSAnton Blanchard int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 789422de3eSMichael Neuling int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 795be3492fSAnton Blanchard int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 8014cf11afSPaul Mackerras 8114cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger); 8214cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_ipi); 8314cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_bpt); 8414cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_sstep); 8514cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_iabr_match); 869422de3eSMichael Neuling EXPORT_SYMBOL(__debugger_break_match); 8714cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_fault_handler); 8814cf11afSPaul Mackerras #endif 8914cf11afSPaul Mackerras 908b3c34cfSMichael Neuling /* Transactional Memory trap debug */ 918b3c34cfSMichael Neuling #ifdef TM_DEBUG_SW 928b3c34cfSMichael Neuling #define TM_DEBUG(x...) printk(KERN_INFO x) 938b3c34cfSMichael Neuling #else 948b3c34cfSMichael Neuling #define TM_DEBUG(x...) do { } while(0) 958b3c34cfSMichael Neuling #endif 968b3c34cfSMichael Neuling 970f642d61SMurilo Opsfelder Araujo static const char *signame(int signr) 980f642d61SMurilo Opsfelder Araujo { 990f642d61SMurilo Opsfelder Araujo switch (signr) { 1000f642d61SMurilo Opsfelder Araujo case SIGBUS: return "bus error"; 1010f642d61SMurilo Opsfelder Araujo case SIGFPE: return "floating point exception"; 1020f642d61SMurilo Opsfelder Araujo case SIGILL: return "illegal instruction"; 1030f642d61SMurilo Opsfelder Araujo case SIGSEGV: return "segfault"; 1040f642d61SMurilo Opsfelder Araujo case SIGTRAP: return "unhandled trap"; 1050f642d61SMurilo Opsfelder Araujo } 1060f642d61SMurilo Opsfelder Araujo 1070f642d61SMurilo Opsfelder Araujo return "unknown signal"; 1080f642d61SMurilo Opsfelder Araujo } 1090f642d61SMurilo Opsfelder Araujo 11014cf11afSPaul Mackerras /* 11114cf11afSPaul Mackerras * Trap & Exception support 11214cf11afSPaul Mackerras */ 11314cf11afSPaul Mackerras 1146031d9d9Santon@samba.org #ifdef CONFIG_PMAC_BACKLIGHT 1156031d9d9Santon@samba.org static void pmac_backlight_unblank(void) 1166031d9d9Santon@samba.org { 1176031d9d9Santon@samba.org mutex_lock(&pmac_backlight_mutex); 1186031d9d9Santon@samba.org if (pmac_backlight) { 1196031d9d9Santon@samba.org struct backlight_properties *props; 1206031d9d9Santon@samba.org 1216031d9d9Santon@samba.org props = &pmac_backlight->props; 1226031d9d9Santon@samba.org props->brightness = props->max_brightness; 1236031d9d9Santon@samba.org props->power = FB_BLANK_UNBLANK; 1246031d9d9Santon@samba.org backlight_update_status(pmac_backlight); 1256031d9d9Santon@samba.org } 1266031d9d9Santon@samba.org mutex_unlock(&pmac_backlight_mutex); 1276031d9d9Santon@samba.org } 1286031d9d9Santon@samba.org #else 1296031d9d9Santon@samba.org static inline void pmac_backlight_unblank(void) { } 1306031d9d9Santon@samba.org #endif 1316031d9d9Santon@samba.org 1326fcd6baaSNicholas Piggin /* 1336fcd6baaSNicholas Piggin * If oops/die is expected to crash the machine, return true here. 1346fcd6baaSNicholas Piggin * 1356fcd6baaSNicholas Piggin * This should not be expected to be 100% accurate, there may be 1366fcd6baaSNicholas Piggin * notifiers registered or other unexpected conditions that may bring 1376fcd6baaSNicholas Piggin * down the kernel. Or if the current process in the kernel is holding 1386fcd6baaSNicholas Piggin * locks or has other critical state, the kernel may become effectively 1396fcd6baaSNicholas Piggin * unusable anyway. 1406fcd6baaSNicholas Piggin */ 1416fcd6baaSNicholas Piggin bool die_will_crash(void) 1426fcd6baaSNicholas Piggin { 1436fcd6baaSNicholas Piggin if (should_fadump_crash()) 1446fcd6baaSNicholas Piggin return true; 1456fcd6baaSNicholas Piggin if (kexec_should_crash(current)) 1466fcd6baaSNicholas Piggin return true; 1476fcd6baaSNicholas Piggin if (in_interrupt() || panic_on_oops || 1486fcd6baaSNicholas Piggin !current->pid || is_global_init(current)) 1496fcd6baaSNicholas Piggin return true; 1506fcd6baaSNicholas Piggin 1516fcd6baaSNicholas Piggin return false; 1526fcd6baaSNicholas Piggin } 1536fcd6baaSNicholas Piggin 154760ca4dcSAnton Blanchard static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 155760ca4dcSAnton Blanchard static int die_owner = -1; 156760ca4dcSAnton Blanchard static unsigned int die_nest_count; 157c0ce7d08SDavid Wilder static int die_counter; 158760ca4dcSAnton Blanchard 15935adacd6SNicholas Piggin extern void panic_flush_kmsg_start(void) 16035adacd6SNicholas Piggin { 16135adacd6SNicholas Piggin /* 16235adacd6SNicholas Piggin * These are mostly taken from kernel/panic.c, but tries to do 16335adacd6SNicholas Piggin * relatively minimal work. Don't use delay functions (TB may 16435adacd6SNicholas Piggin * be broken), don't crash dump (need to set a firmware log), 16535adacd6SNicholas Piggin * don't run notifiers. We do want to get some information to 16635adacd6SNicholas Piggin * Linux console. 16735adacd6SNicholas Piggin */ 16835adacd6SNicholas Piggin console_verbose(); 16935adacd6SNicholas Piggin bust_spinlocks(1); 17035adacd6SNicholas Piggin } 17135adacd6SNicholas Piggin 17235adacd6SNicholas Piggin extern void panic_flush_kmsg_end(void) 17335adacd6SNicholas Piggin { 17435adacd6SNicholas Piggin kmsg_dump(KMSG_DUMP_PANIC); 17535adacd6SNicholas Piggin bust_spinlocks(0); 17635adacd6SNicholas Piggin debug_locks_off(); 177de6da1e8SFeng Tang console_flush_on_panic(CONSOLE_FLUSH_PENDING); 17835adacd6SNicholas Piggin } 17935adacd6SNicholas Piggin 18003465f89SNicholas Piggin static unsigned long oops_begin(struct pt_regs *regs) 181760ca4dcSAnton Blanchard { 182760ca4dcSAnton Blanchard int cpu; 18334c2a14fSanton@samba.org unsigned long flags; 18414cf11afSPaul Mackerras 185293e4688Santon@samba.org oops_enter(); 186293e4688Santon@samba.org 187760ca4dcSAnton Blanchard /* racy, but better than risking deadlock. */ 188760ca4dcSAnton Blanchard raw_local_irq_save(flags); 189760ca4dcSAnton Blanchard cpu = smp_processor_id(); 190760ca4dcSAnton Blanchard if (!arch_spin_trylock(&die_lock)) { 191760ca4dcSAnton Blanchard if (cpu == die_owner) 192760ca4dcSAnton Blanchard /* nested oops. should stop eventually */; 193760ca4dcSAnton Blanchard else 194760ca4dcSAnton Blanchard arch_spin_lock(&die_lock); 195760ca4dcSAnton Blanchard } 196760ca4dcSAnton Blanchard die_nest_count++; 197760ca4dcSAnton Blanchard die_owner = cpu; 19814cf11afSPaul Mackerras console_verbose(); 19914cf11afSPaul Mackerras bust_spinlocks(1); 2006031d9d9Santon@samba.org if (machine_is(powermac)) 2016031d9d9Santon@samba.org pmac_backlight_unblank(); 202760ca4dcSAnton Blanchard return flags; 20334c2a14fSanton@samba.org } 20403465f89SNicholas Piggin NOKPROBE_SYMBOL(oops_begin); 2055474c120SMichael Hanselmann 20603465f89SNicholas Piggin static void oops_end(unsigned long flags, struct pt_regs *regs, 207760ca4dcSAnton Blanchard int signr) 208760ca4dcSAnton Blanchard { 20914cf11afSPaul Mackerras bust_spinlocks(0); 210373d4d09SRusty Russell add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 211760ca4dcSAnton Blanchard die_nest_count--; 21258154c8cSAnton Blanchard oops_exit(); 21358154c8cSAnton Blanchard printk("\n"); 2147458e8b2SNicholas Piggin if (!die_nest_count) { 215760ca4dcSAnton Blanchard /* Nest count reaches zero, release the lock. */ 2167458e8b2SNicholas Piggin die_owner = -1; 217760ca4dcSAnton Blanchard arch_spin_unlock(&die_lock); 2187458e8b2SNicholas Piggin } 219760ca4dcSAnton Blanchard raw_local_irq_restore(flags); 220cc532915SMichael Ellerman 221d40b6768SNicholas Piggin /* 222d40b6768SNicholas Piggin * system_reset_excption handles debugger, crash dump, panic, for 0x100 223d40b6768SNicholas Piggin */ 2247153d4bfSXiongwei Song if (TRAP(regs) == INTERRUPT_SYSTEM_RESET) 225d40b6768SNicholas Piggin return; 226d40b6768SNicholas Piggin 227ebaeb5aeSMahesh Salgaonkar crash_fadump(regs, "die oops"); 228ebaeb5aeSMahesh Salgaonkar 2294388c9b3SNicholas Piggin if (kexec_should_crash(current)) 230cc532915SMichael Ellerman crash_kexec(regs); 2319b00ac06SAnton Blanchard 232760ca4dcSAnton Blanchard if (!signr) 233760ca4dcSAnton Blanchard return; 234760ca4dcSAnton Blanchard 23558154c8cSAnton Blanchard /* 23658154c8cSAnton Blanchard * While our oops output is serialised by a spinlock, output 23758154c8cSAnton Blanchard * from panic() called below can race and corrupt it. If we 23858154c8cSAnton Blanchard * know we are going to panic, delay for 1 second so we have a 23958154c8cSAnton Blanchard * chance to get clean backtraces from all CPUs that are oopsing. 24058154c8cSAnton Blanchard */ 24158154c8cSAnton Blanchard if (in_interrupt() || panic_on_oops || !current->pid || 24258154c8cSAnton Blanchard is_global_init(current)) { 24358154c8cSAnton Blanchard mdelay(MSEC_PER_SEC); 24458154c8cSAnton Blanchard } 24558154c8cSAnton Blanchard 246cea6a4baSHorms if (panic_on_oops) 247012c437dSHorms panic("Fatal exception"); 248760ca4dcSAnton Blanchard do_exit(signr); 249760ca4dcSAnton Blanchard } 25003465f89SNicholas Piggin NOKPROBE_SYMBOL(oops_end); 251cea6a4baSHorms 252d7e02f7bSAneesh Kumar K.V static char *get_mmu_str(void) 253d7e02f7bSAneesh Kumar K.V { 254d7e02f7bSAneesh Kumar K.V if (early_radix_enabled()) 255d7e02f7bSAneesh Kumar K.V return " MMU=Radix"; 256d7e02f7bSAneesh Kumar K.V if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE)) 257d7e02f7bSAneesh Kumar K.V return " MMU=Hash"; 258d7e02f7bSAneesh Kumar K.V return ""; 259d7e02f7bSAneesh Kumar K.V } 260d7e02f7bSAneesh Kumar K.V 26103465f89SNicholas Piggin static int __die(const char *str, struct pt_regs *regs, long err) 262760ca4dcSAnton Blanchard { 263760ca4dcSAnton Blanchard printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 2642e82ca3cSMichael Ellerman 265d7e02f7bSAneesh Kumar K.V printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n", 26678227443SMichael Ellerman IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 267d7e02f7bSAneesh Kumar K.V PAGE_SIZE / 1024, get_mmu_str(), 26878227443SMichael Ellerman IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "", 26978227443SMichael Ellerman IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 27078227443SMichael Ellerman IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 27178227443SMichael Ellerman debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 27278227443SMichael Ellerman IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 27378227443SMichael Ellerman ppc_md.name ? ppc_md.name : ""); 274760ca4dcSAnton Blanchard 275760ca4dcSAnton Blanchard if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 276760ca4dcSAnton Blanchard return 1; 277760ca4dcSAnton Blanchard 278760ca4dcSAnton Blanchard print_modules(); 279760ca4dcSAnton Blanchard show_regs(regs); 28014cf11afSPaul Mackerras 28114cf11afSPaul Mackerras return 0; 28214cf11afSPaul Mackerras } 28303465f89SNicholas Piggin NOKPROBE_SYMBOL(__die); 28414cf11afSPaul Mackerras 285760ca4dcSAnton Blanchard void die(const char *str, struct pt_regs *regs, long err) 286760ca4dcSAnton Blanchard { 2876f44b20eSNicholas Piggin unsigned long flags; 288760ca4dcSAnton Blanchard 289d40b6768SNicholas Piggin /* 290d40b6768SNicholas Piggin * system_reset_excption handles debugger, crash dump, panic, for 0x100 291d40b6768SNicholas Piggin */ 2927153d4bfSXiongwei Song if (TRAP(regs) != INTERRUPT_SYSTEM_RESET) { 2936f44b20eSNicholas Piggin if (debugger(regs)) 2946f44b20eSNicholas Piggin return; 295d40b6768SNicholas Piggin } 2966f44b20eSNicholas Piggin 2976f44b20eSNicholas Piggin flags = oops_begin(regs); 298760ca4dcSAnton Blanchard if (__die(str, regs, err)) 299760ca4dcSAnton Blanchard err = 0; 300760ca4dcSAnton Blanchard oops_end(flags, regs, err); 301760ca4dcSAnton Blanchard } 30215770a13SNaveen N. Rao NOKPROBE_SYMBOL(die); 303760ca4dcSAnton Blanchard 304efc463adSEric W. Biederman void user_single_step_report(struct pt_regs *regs) 30525baa35bSOleg Nesterov { 3062e1661d2SEric W. Biederman force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip); 30725baa35bSOleg Nesterov } 30825baa35bSOleg Nesterov 309658b0f92SMurilo Opsfelder Araujo static void show_signal_msg(int signr, struct pt_regs *regs, int code, 310658b0f92SMurilo Opsfelder Araujo unsigned long addr) 31114cf11afSPaul Mackerras { 312997dd26cSMichael Ellerman static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 313997dd26cSMichael Ellerman DEFAULT_RATELIMIT_BURST); 314997dd26cSMichael Ellerman 315997dd26cSMichael Ellerman if (!show_unhandled_signals) 31635a52a10SMurilo Opsfelder Araujo return; 31735a52a10SMurilo Opsfelder Araujo 31835a52a10SMurilo Opsfelder Araujo if (!unhandled_signal(current, signr)) 31935a52a10SMurilo Opsfelder Araujo return; 32035a52a10SMurilo Opsfelder Araujo 321997dd26cSMichael Ellerman if (!__ratelimit(&rs)) 322997dd26cSMichael Ellerman return; 323997dd26cSMichael Ellerman 3240f642d61SMurilo Opsfelder Araujo pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 3250f642d61SMurilo Opsfelder Araujo current->comm, current->pid, signame(signr), signr, 326d0c3d534SOlof Johansson addr, regs->nip, regs->link, code); 3270f642d61SMurilo Opsfelder Araujo 3280f642d61SMurilo Opsfelder Araujo print_vma_addr(KERN_CONT " in ", regs->nip); 3290f642d61SMurilo Opsfelder Araujo 3300f642d61SMurilo Opsfelder Araujo pr_cont("\n"); 331a99b9c5eSMurilo Opsfelder Araujo 332a99b9c5eSMurilo Opsfelder Araujo show_user_instructions(regs); 33314cf11afSPaul Mackerras } 334658b0f92SMurilo Opsfelder Araujo 3352c44ce28SEric W. Biederman static bool exception_common(int signr, struct pt_regs *regs, int code, 3362c44ce28SEric W. Biederman unsigned long addr) 337658b0f92SMurilo Opsfelder Araujo { 338658b0f92SMurilo Opsfelder Araujo if (!user_mode(regs)) { 339658b0f92SMurilo Opsfelder Araujo die("Exception in kernel mode", regs, signr); 3402c44ce28SEric W. Biederman return false; 341658b0f92SMurilo Opsfelder Araujo } 342658b0f92SMurilo Opsfelder Araujo 343*d0afd44cSNicholas Piggin /* 344*d0afd44cSNicholas Piggin * Must not enable interrupts even for user-mode exception, because 345*d0afd44cSNicholas Piggin * this can be called from machine check, which may be a NMI or IRQ 346*d0afd44cSNicholas Piggin * which don't like interrupts being enabled. Could check for 347*d0afd44cSNicholas Piggin * in_hardirq || in_nmi perhaps, but there doesn't seem to be a good 348*d0afd44cSNicholas Piggin * reason why _exception() should enable irqs for an exception handler, 349*d0afd44cSNicholas Piggin * the handlers themselves do that directly. 350*d0afd44cSNicholas Piggin */ 35114cf11afSPaul Mackerras 352*d0afd44cSNicholas Piggin show_signal_msg(signr, regs, code, addr); 3539f2f79e3SBenjamin Herrenschmidt 35441ab5266SAnanth N Mavinakayanahalli current->thread.trap_nr = code; 355c5cc1f4dSThiago Jung Bauermann 3562c44ce28SEric W. Biederman return true; 3572c44ce28SEric W. Biederman } 3582c44ce28SEric W. Biederman 3595d8fb8a5SEric W. Biederman void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 3602c44ce28SEric W. Biederman { 3615d8fb8a5SEric W. Biederman if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 3622c44ce28SEric W. Biederman return; 3632c44ce28SEric W. Biederman 36477c70728SEric W. Biederman force_sig_pkuerr((void __user *) addr, key); 36514cf11afSPaul Mackerras } 36614cf11afSPaul Mackerras 36799cd1302SRam Pai void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 36899cd1302SRam Pai { 369c1c7c85cSEric W. Biederman if (!exception_common(signr, regs, code, addr)) 370c1c7c85cSEric W. Biederman return; 371c1c7c85cSEric W. Biederman 3722e1661d2SEric W. Biederman force_sig_fault(signr, code, (void __user *)addr); 37399cd1302SRam Pai } 37499cd1302SRam Pai 375ccd47702SNicholas Piggin /* 376ccd47702SNicholas Piggin * The interrupt architecture has a quirk in that the HV interrupts excluding 377ccd47702SNicholas Piggin * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing 378ccd47702SNicholas Piggin * that an interrupt handler must do is save off a GPR into a scratch register, 379ccd47702SNicholas Piggin * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch. 380ccd47702SNicholas Piggin * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing 381ccd47702SNicholas Piggin * that it is non-reentrant, which leads to random data corruption. 382ccd47702SNicholas Piggin * 383ccd47702SNicholas Piggin * The solution is for NMI interrupts in HV mode to check if they originated 384ccd47702SNicholas Piggin * from these critical HV interrupt regions. If so, then mark them not 385ccd47702SNicholas Piggin * recoverable. 386ccd47702SNicholas Piggin * 387ccd47702SNicholas Piggin * An alternative would be for HV NMIs to use SPRG for scratch to avoid the 388ccd47702SNicholas Piggin * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux 389ccd47702SNicholas Piggin * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so 390ccd47702SNicholas Piggin * that would work. However any other guest OS that may have the SPRG live 391ccd47702SNicholas Piggin * and MSR[RI]=1 could encounter silent corruption. 392ccd47702SNicholas Piggin * 393ccd47702SNicholas Piggin * Builds that do not support KVM could take this second option to increase 394ccd47702SNicholas Piggin * the recoverability of NMIs. 395ccd47702SNicholas Piggin */ 396ccd47702SNicholas Piggin void hv_nmi_check_nonrecoverable(struct pt_regs *regs) 397ccd47702SNicholas Piggin { 398ccd47702SNicholas Piggin #ifdef CONFIG_PPC_POWERNV 399ccd47702SNicholas Piggin unsigned long kbase = (unsigned long)_stext; 400ccd47702SNicholas Piggin unsigned long nip = regs->nip; 401ccd47702SNicholas Piggin 402ccd47702SNicholas Piggin if (!(regs->msr & MSR_RI)) 403ccd47702SNicholas Piggin return; 404ccd47702SNicholas Piggin if (!(regs->msr & MSR_HV)) 405ccd47702SNicholas Piggin return; 406ccd47702SNicholas Piggin if (regs->msr & MSR_PR) 407ccd47702SNicholas Piggin return; 408ccd47702SNicholas Piggin 409ccd47702SNicholas Piggin /* 410ccd47702SNicholas Piggin * Now test if the interrupt has hit a range that may be using 411ccd47702SNicholas Piggin * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The 412ccd47702SNicholas Piggin * problem ranges all run un-relocated. Test real and virt modes 4135c4a4802SBhaskar Chowdhury * at the same time by dropping the high bit of the nip (virt mode 414ccd47702SNicholas Piggin * entry points still have the +0x4000 offset). 415ccd47702SNicholas Piggin */ 416ccd47702SNicholas Piggin nip &= ~0xc000000000000000ULL; 417ccd47702SNicholas Piggin if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600)) 418ccd47702SNicholas Piggin goto nonrecoverable; 419ccd47702SNicholas Piggin if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00)) 420ccd47702SNicholas Piggin goto nonrecoverable; 421ccd47702SNicholas Piggin if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0)) 422ccd47702SNicholas Piggin goto nonrecoverable; 423ccd47702SNicholas Piggin if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0)) 424ccd47702SNicholas Piggin goto nonrecoverable; 425bd3524feSNicholas Piggin 426ccd47702SNicholas Piggin /* Trampoline code runs un-relocated so subtract kbase. */ 427bd3524feSNicholas Piggin if (nip >= (unsigned long)(start_real_trampolines - kbase) && 428bd3524feSNicholas Piggin nip < (unsigned long)(end_real_trampolines - kbase)) 429ccd47702SNicholas Piggin goto nonrecoverable; 430bd3524feSNicholas Piggin if (nip >= (unsigned long)(start_virt_trampolines - kbase) && 431bd3524feSNicholas Piggin nip < (unsigned long)(end_virt_trampolines - kbase)) 432ccd47702SNicholas Piggin goto nonrecoverable; 433ccd47702SNicholas Piggin return; 434ccd47702SNicholas Piggin 435ccd47702SNicholas Piggin nonrecoverable: 436806c0e6eSChristophe Leroy regs_set_unrecoverable(regs); 437ccd47702SNicholas Piggin #endif 438ccd47702SNicholas Piggin } 4393a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER_NMI(system_reset_exception) 44014cf11afSPaul Mackerras { 441cbf2ba95SNicholas Piggin unsigned long hsrr0, hsrr1; 442cbf2ba95SNicholas Piggin bool saved_hsrrs = false; 4432b4f3ac5SNicholas Piggin 444cbf2ba95SNicholas Piggin /* 445cbf2ba95SNicholas Piggin * System reset can interrupt code where HSRRs are live and MSR[RI]=1. 446cbf2ba95SNicholas Piggin * The system reset interrupt itself may clobber HSRRs (e.g., to call 447cbf2ba95SNicholas Piggin * OPAL), so save them here and restore them before returning. 448cbf2ba95SNicholas Piggin * 449cbf2ba95SNicholas Piggin * Machine checks don't need to save HSRRs, as the real mode handler 450cbf2ba95SNicholas Piggin * is careful to avoid them, and the regular handler is not delivered 451cbf2ba95SNicholas Piggin * as an NMI. 452cbf2ba95SNicholas Piggin */ 453cbf2ba95SNicholas Piggin if (cpu_has_feature(CPU_FTR_HVMODE)) { 454cbf2ba95SNicholas Piggin hsrr0 = mfspr(SPRN_HSRR0); 455cbf2ba95SNicholas Piggin hsrr1 = mfspr(SPRN_HSRR1); 456cbf2ba95SNicholas Piggin saved_hsrrs = true; 457cbf2ba95SNicholas Piggin } 458cbf2ba95SNicholas Piggin 459ccd47702SNicholas Piggin hv_nmi_check_nonrecoverable(regs); 460ccd47702SNicholas Piggin 461ca41ad43SNicholas Piggin __this_cpu_inc(irq_stat.sreset_irqs); 462ca41ad43SNicholas Piggin 46314cf11afSPaul Mackerras /* See if any machine dependent calls */ 464c902be71SArnd Bergmann if (ppc_md.system_reset_exception) { 465c902be71SArnd Bergmann if (ppc_md.system_reset_exception(regs)) 466c4f3b52cSNicholas Piggin goto out; 467c902be71SArnd Bergmann } 46814cf11afSPaul Mackerras 4694388c9b3SNicholas Piggin if (debugger(regs)) 4704388c9b3SNicholas Piggin goto out; 4714388c9b3SNicholas Piggin 472e7ca44edSGanesh Goudar kmsg_dump(KMSG_DUMP_OOPS); 4734388c9b3SNicholas Piggin /* 4744388c9b3SNicholas Piggin * A system reset is a request to dump, so we always send 4754388c9b3SNicholas Piggin * it through the crashdump code (if fadump or kdump are 4764388c9b3SNicholas Piggin * registered). 4774388c9b3SNicholas Piggin */ 4784388c9b3SNicholas Piggin crash_fadump(regs, "System Reset"); 4794388c9b3SNicholas Piggin 4804388c9b3SNicholas Piggin crash_kexec(regs); 4814388c9b3SNicholas Piggin 4824388c9b3SNicholas Piggin /* 4834388c9b3SNicholas Piggin * We aren't the primary crash CPU. We need to send it 4844388c9b3SNicholas Piggin * to a holding pattern to avoid it ending up in the panic 4854388c9b3SNicholas Piggin * code. 4864388c9b3SNicholas Piggin */ 4874388c9b3SNicholas Piggin crash_kexec_secondary(regs); 4884388c9b3SNicholas Piggin 4894388c9b3SNicholas Piggin /* 4904388c9b3SNicholas Piggin * No debugger or crash dump registered, print logs then 4914388c9b3SNicholas Piggin * panic. 4924388c9b3SNicholas Piggin */ 4934552d128SNicholas Piggin die("System Reset", regs, SIGABRT); 4944388c9b3SNicholas Piggin 4954388c9b3SNicholas Piggin mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 4964388c9b3SNicholas Piggin add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 4974388c9b3SNicholas Piggin nmi_panic(regs, "System Reset"); 49814cf11afSPaul Mackerras 499c4f3b52cSNicholas Piggin out: 500c4f3b52cSNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 501c4f3b52cSNicholas Piggin BUG_ON(get_paca()->in_nmi == 0); 502c4f3b52cSNicholas Piggin if (get_paca()->in_nmi > 1) 503265d6e58SNicholas Piggin die("Unrecoverable nested System Reset", regs, SIGABRT); 504c4f3b52cSNicholas Piggin #endif 50514cf11afSPaul Mackerras /* Must die if the interrupt is not recoverable */ 506806c0e6eSChristophe Leroy if (regs_is_unrecoverable(regs)) { 50711cb0a25SNicholas Piggin /* For the reason explained in die_mce, nmi_exit before die */ 50811cb0a25SNicholas Piggin nmi_exit(); 509265d6e58SNicholas Piggin die("Unrecoverable System Reset", regs, SIGABRT); 51011cb0a25SNicholas Piggin } 51114cf11afSPaul Mackerras 512cbf2ba95SNicholas Piggin if (saved_hsrrs) { 513cbf2ba95SNicholas Piggin mtspr(SPRN_HSRR0, hsrr0); 514cbf2ba95SNicholas Piggin mtspr(SPRN_HSRR1, hsrr1); 515cbf2ba95SNicholas Piggin } 516cbf2ba95SNicholas Piggin 51714cf11afSPaul Mackerras /* What should we do here? We could issue a shutdown or hard reset. */ 5183a96570fSNicholas Piggin 5193a96570fSNicholas Piggin return 0; 52014cf11afSPaul Mackerras } 5211e9b4507SMahesh Salgaonkar 52214cf11afSPaul Mackerras /* 52314cf11afSPaul Mackerras * I/O accesses can cause machine checks on powermacs. 52414cf11afSPaul Mackerras * Check if the NIP corresponds to the address of a sync 52514cf11afSPaul Mackerras * instruction for which there is an entry in the exception 52614cf11afSPaul Mackerras * table. 52714cf11afSPaul Mackerras * -- paulus. 52814cf11afSPaul Mackerras */ 52914cf11afSPaul Mackerras static inline int check_io_access(struct pt_regs *regs) 53014cf11afSPaul Mackerras { 53168a64357SBenjamin Herrenschmidt #ifdef CONFIG_PPC32 53214cf11afSPaul Mackerras unsigned long msr = regs->msr; 53314cf11afSPaul Mackerras const struct exception_table_entry *entry; 53414cf11afSPaul Mackerras unsigned int *nip = (unsigned int *)regs->nip; 53514cf11afSPaul Mackerras 53614cf11afSPaul Mackerras if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 53714cf11afSPaul Mackerras && (entry = search_exception_tables(regs->nip)) != NULL) { 53814cf11afSPaul Mackerras /* 53914cf11afSPaul Mackerras * Check that it's a sync instruction, or somewhere 54014cf11afSPaul Mackerras * in the twi; isync; nop sequence that inb/inw/inl uses. 54114cf11afSPaul Mackerras * As the address is in the exception table 54214cf11afSPaul Mackerras * we should be able to read the instr there. 54314cf11afSPaul Mackerras * For the debug message, we look at the preceding 54414cf11afSPaul Mackerras * load or store. 54514cf11afSPaul Mackerras */ 546deefd0aeSChristophe Leroy if (*nip == PPC_RAW_NOP()) 54714cf11afSPaul Mackerras nip -= 2; 548deefd0aeSChristophe Leroy else if (*nip == PPC_RAW_ISYNC()) 54914cf11afSPaul Mackerras --nip; 550deefd0aeSChristophe Leroy if (*nip == PPC_RAW_SYNC() || get_op(*nip) == OP_TRAP) { 55114cf11afSPaul Mackerras unsigned int rb; 55214cf11afSPaul Mackerras 55314cf11afSPaul Mackerras --nip; 55414cf11afSPaul Mackerras rb = (*nip >> 11) & 0x1f; 55514cf11afSPaul Mackerras printk(KERN_DEBUG "%s bad port %lx at %p\n", 55614cf11afSPaul Mackerras (*nip & 0x100)? "OUT to": "IN from", 55714cf11afSPaul Mackerras regs->gpr[rb] - _IO_BASE, nip); 558806c0e6eSChristophe Leroy regs_set_recoverable(regs); 55959dc5bfcSNicholas Piggin regs_set_return_ip(regs, extable_fixup(entry)); 56014cf11afSPaul Mackerras return 1; 56114cf11afSPaul Mackerras } 56214cf11afSPaul Mackerras } 56368a64357SBenjamin Herrenschmidt #endif /* CONFIG_PPC32 */ 56414cf11afSPaul Mackerras return 0; 56514cf11afSPaul Mackerras } 56614cf11afSPaul Mackerras 567172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 56814cf11afSPaul Mackerras /* On 4xx, the reason for the machine check or program exception 56914cf11afSPaul Mackerras is in the ESR. */ 5704f8e78c0SXiongwei Song #define get_reason(regs) ((regs)->esr) 57114cf11afSPaul Mackerras #define REASON_FP ESR_FP 57214cf11afSPaul Mackerras #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 57314cf11afSPaul Mackerras #define REASON_PRIVILEGED ESR_PPR 57414cf11afSPaul Mackerras #define REASON_TRAP ESR_PTR 5759409d2f9SJordan Niethe #define REASON_PREFIXED 0 5769409d2f9SJordan Niethe #define REASON_BOUNDARY 0 57714cf11afSPaul Mackerras 57814cf11afSPaul Mackerras /* single-step stuff */ 57951ae8d4aSBharat Bhushan #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 58051ae8d4aSBharat Bhushan #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 5810e524e76SMatt Evans #define clear_br_trace(regs) do {} while(0) 58214cf11afSPaul Mackerras #else 58314cf11afSPaul Mackerras /* On non-4xx, the reason for the machine check or program 58414cf11afSPaul Mackerras exception is in the MSR. */ 58514cf11afSPaul Mackerras #define get_reason(regs) ((regs)->msr) 586d30a5a52SMichael Ellerman #define REASON_TM SRR1_PROGTM 587d30a5a52SMichael Ellerman #define REASON_FP SRR1_PROGFPE 588d30a5a52SMichael Ellerman #define REASON_ILLEGAL SRR1_PROGILL 589d30a5a52SMichael Ellerman #define REASON_PRIVILEGED SRR1_PROGPRIV 590d30a5a52SMichael Ellerman #define REASON_TRAP SRR1_PROGTRAP 5919409d2f9SJordan Niethe #define REASON_PREFIXED SRR1_PREFIXED 5929409d2f9SJordan Niethe #define REASON_BOUNDARY SRR1_BOUNDARY 59314cf11afSPaul Mackerras 59414cf11afSPaul Mackerras #define single_stepping(regs) ((regs)->msr & MSR_SE) 59559dc5bfcSNicholas Piggin #define clear_single_step(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_SE)) 59659dc5bfcSNicholas Piggin #define clear_br_trace(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_BE)) 59714cf11afSPaul Mackerras #endif 59814cf11afSPaul Mackerras 5999409d2f9SJordan Niethe #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) 6009409d2f9SJordan Niethe 6010d0935b3SMichael Ellerman #if defined(CONFIG_E500) 602fe04b112SScott Wood int machine_check_e500mc(struct pt_regs *regs) 603fe04b112SScott Wood { 604fe04b112SScott Wood unsigned long mcsr = mfspr(SPRN_MCSR); 605a4e89ffbSMatt Weber unsigned long pvr = mfspr(SPRN_PVR); 606fe04b112SScott Wood unsigned long reason = mcsr; 607fe04b112SScott Wood int recoverable = 1; 608fe04b112SScott Wood 60982a9a480SScott Wood if (reason & MCSR_LD) { 610cce1f106SShaohui Xie recoverable = fsl_rio_mcheck_exception(regs); 611cce1f106SShaohui Xie if (recoverable == 1) 612cce1f106SShaohui Xie goto silent_out; 613cce1f106SShaohui Xie } 614cce1f106SShaohui Xie 615fe04b112SScott Wood printk("Machine check in kernel mode.\n"); 616fe04b112SScott Wood printk("Caused by (from MCSR=%lx): ", reason); 617fe04b112SScott Wood 618fe04b112SScott Wood if (reason & MCSR_MCP) 619422123ccSChristophe Leroy pr_cont("Machine Check Signal\n"); 620fe04b112SScott Wood 621fe04b112SScott Wood if (reason & MCSR_ICPERR) { 622422123ccSChristophe Leroy pr_cont("Instruction Cache Parity Error\n"); 623fe04b112SScott Wood 624fe04b112SScott Wood /* 625fe04b112SScott Wood * This is recoverable by invalidating the i-cache. 626fe04b112SScott Wood */ 627fe04b112SScott Wood mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 628fe04b112SScott Wood while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 629fe04b112SScott Wood ; 630fe04b112SScott Wood 631fe04b112SScott Wood /* 632fe04b112SScott Wood * This will generally be accompanied by an instruction 633fe04b112SScott Wood * fetch error report -- only treat MCSR_IF as fatal 634fe04b112SScott Wood * if it wasn't due to an L1 parity error. 635fe04b112SScott Wood */ 636fe04b112SScott Wood reason &= ~MCSR_IF; 637fe04b112SScott Wood } 638fe04b112SScott Wood 639fe04b112SScott Wood if (reason & MCSR_DCPERR_MC) { 640422123ccSChristophe Leroy pr_cont("Data Cache Parity Error\n"); 64137caf9f2SKumar Gala 64237caf9f2SKumar Gala /* 64337caf9f2SKumar Gala * In write shadow mode we auto-recover from the error, but it 64437caf9f2SKumar Gala * may still get logged and cause a machine check. We should 64537caf9f2SKumar Gala * only treat the non-write shadow case as non-recoverable. 64637caf9f2SKumar Gala */ 647a4e89ffbSMatt Weber /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 648a4e89ffbSMatt Weber * is not implemented but L1 data cache always runs in write 649a4e89ffbSMatt Weber * shadow mode. Hence on data cache parity errors HW will 650a4e89ffbSMatt Weber * automatically invalidate the L1 Data Cache. 651a4e89ffbSMatt Weber */ 652a4e89ffbSMatt Weber if (PVR_VER(pvr) != PVR_VER_E6500) { 65337caf9f2SKumar Gala if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 654fe04b112SScott Wood recoverable = 0; 655fe04b112SScott Wood } 656a4e89ffbSMatt Weber } 657fe04b112SScott Wood 658fe04b112SScott Wood if (reason & MCSR_L2MMU_MHIT) { 659422123ccSChristophe Leroy pr_cont("Hit on multiple TLB entries\n"); 660fe04b112SScott Wood recoverable = 0; 661fe04b112SScott Wood } 662fe04b112SScott Wood 663fe04b112SScott Wood if (reason & MCSR_NMI) 664422123ccSChristophe Leroy pr_cont("Non-maskable interrupt\n"); 665fe04b112SScott Wood 666fe04b112SScott Wood if (reason & MCSR_IF) { 667422123ccSChristophe Leroy pr_cont("Instruction Fetch Error Report\n"); 668fe04b112SScott Wood recoverable = 0; 669fe04b112SScott Wood } 670fe04b112SScott Wood 671fe04b112SScott Wood if (reason & MCSR_LD) { 672422123ccSChristophe Leroy pr_cont("Load Error Report\n"); 673fe04b112SScott Wood recoverable = 0; 674fe04b112SScott Wood } 675fe04b112SScott Wood 676fe04b112SScott Wood if (reason & MCSR_ST) { 677422123ccSChristophe Leroy pr_cont("Store Error Report\n"); 678fe04b112SScott Wood recoverable = 0; 679fe04b112SScott Wood } 680fe04b112SScott Wood 681fe04b112SScott Wood if (reason & MCSR_LDG) { 682422123ccSChristophe Leroy pr_cont("Guarded Load Error Report\n"); 683fe04b112SScott Wood recoverable = 0; 684fe04b112SScott Wood } 685fe04b112SScott Wood 686fe04b112SScott Wood if (reason & MCSR_TLBSYNC) 687422123ccSChristophe Leroy pr_cont("Simultaneous tlbsync operations\n"); 688fe04b112SScott Wood 689fe04b112SScott Wood if (reason & MCSR_BSL2_ERR) { 690422123ccSChristophe Leroy pr_cont("Level 2 Cache Error\n"); 691fe04b112SScott Wood recoverable = 0; 692fe04b112SScott Wood } 693fe04b112SScott Wood 694fe04b112SScott Wood if (reason & MCSR_MAV) { 695fe04b112SScott Wood u64 addr; 696fe04b112SScott Wood 697fe04b112SScott Wood addr = mfspr(SPRN_MCAR); 698fe04b112SScott Wood addr |= (u64)mfspr(SPRN_MCARU) << 32; 699fe04b112SScott Wood 700422123ccSChristophe Leroy pr_cont("Machine Check %s Address: %#llx\n", 701fe04b112SScott Wood reason & MCSR_MEA ? "Effective" : "Physical", addr); 702fe04b112SScott Wood } 703fe04b112SScott Wood 704cce1f106SShaohui Xie silent_out: 705fe04b112SScott Wood mtspr(SPRN_MCSR, mcsr); 706fe04b112SScott Wood return mfspr(SPRN_MCSR) == 0 && recoverable; 707fe04b112SScott Wood } 708fe04b112SScott Wood 70947c0bd1aSBenjamin Herrenschmidt int machine_check_e500(struct pt_regs *regs) 71047c0bd1aSBenjamin Herrenschmidt { 71142bff234SMichael Ellerman unsigned long reason = mfspr(SPRN_MCSR); 71247c0bd1aSBenjamin Herrenschmidt 713cce1f106SShaohui Xie if (reason & MCSR_BUS_RBERR) { 714cce1f106SShaohui Xie if (fsl_rio_mcheck_exception(regs)) 715cce1f106SShaohui Xie return 1; 7164e0e3435SHongtao Jia if (fsl_pci_mcheck_exception(regs)) 7174e0e3435SHongtao Jia return 1; 718cce1f106SShaohui Xie } 719cce1f106SShaohui Xie 72014cf11afSPaul Mackerras printk("Machine check in kernel mode.\n"); 72114cf11afSPaul Mackerras printk("Caused by (from MCSR=%lx): ", reason); 72214cf11afSPaul Mackerras 72314cf11afSPaul Mackerras if (reason & MCSR_MCP) 724422123ccSChristophe Leroy pr_cont("Machine Check Signal\n"); 72514cf11afSPaul Mackerras if (reason & MCSR_ICPERR) 726422123ccSChristophe Leroy pr_cont("Instruction Cache Parity Error\n"); 72714cf11afSPaul Mackerras if (reason & MCSR_DCP_PERR) 728422123ccSChristophe Leroy pr_cont("Data Cache Push Parity Error\n"); 72914cf11afSPaul Mackerras if (reason & MCSR_DCPERR) 730422123ccSChristophe Leroy pr_cont("Data Cache Parity Error\n"); 73114cf11afSPaul Mackerras if (reason & MCSR_BUS_IAERR) 732422123ccSChristophe Leroy pr_cont("Bus - Instruction Address Error\n"); 73314cf11afSPaul Mackerras if (reason & MCSR_BUS_RAERR) 734422123ccSChristophe Leroy pr_cont("Bus - Read Address Error\n"); 73514cf11afSPaul Mackerras if (reason & MCSR_BUS_WAERR) 736422123ccSChristophe Leroy pr_cont("Bus - Write Address Error\n"); 73714cf11afSPaul Mackerras if (reason & MCSR_BUS_IBERR) 738422123ccSChristophe Leroy pr_cont("Bus - Instruction Data Error\n"); 73914cf11afSPaul Mackerras if (reason & MCSR_BUS_RBERR) 740422123ccSChristophe Leroy pr_cont("Bus - Read Data Bus Error\n"); 74114cf11afSPaul Mackerras if (reason & MCSR_BUS_WBERR) 742422123ccSChristophe Leroy pr_cont("Bus - Write Data Bus Error\n"); 74314cf11afSPaul Mackerras if (reason & MCSR_BUS_IPERR) 744422123ccSChristophe Leroy pr_cont("Bus - Instruction Parity Error\n"); 74514cf11afSPaul Mackerras if (reason & MCSR_BUS_RPERR) 746422123ccSChristophe Leroy pr_cont("Bus - Read Parity Error\n"); 74747c0bd1aSBenjamin Herrenschmidt 74847c0bd1aSBenjamin Herrenschmidt return 0; 74947c0bd1aSBenjamin Herrenschmidt } 7504490c06bSKumar Gala 7514490c06bSKumar Gala int machine_check_generic(struct pt_regs *regs) 7524490c06bSKumar Gala { 7534490c06bSKumar Gala return 0; 7544490c06bSKumar Gala } 7557f3f819eSMichael Ellerman #elif defined(CONFIG_PPC32) 75647c0bd1aSBenjamin Herrenschmidt int machine_check_generic(struct pt_regs *regs) 75747c0bd1aSBenjamin Herrenschmidt { 75842bff234SMichael Ellerman unsigned long reason = regs->msr; 75947c0bd1aSBenjamin Herrenschmidt 76014cf11afSPaul Mackerras printk("Machine check in kernel mode.\n"); 76114cf11afSPaul Mackerras printk("Caused by (from SRR1=%lx): ", reason); 76214cf11afSPaul Mackerras switch (reason & 0x601F0000) { 76314cf11afSPaul Mackerras case 0x80000: 764422123ccSChristophe Leroy pr_cont("Machine check signal\n"); 76514cf11afSPaul Mackerras break; 76614cf11afSPaul Mackerras case 0x40000: 76714cf11afSPaul Mackerras case 0x140000: /* 7450 MSS error and TEA */ 768422123ccSChristophe Leroy pr_cont("Transfer error ack signal\n"); 76914cf11afSPaul Mackerras break; 77014cf11afSPaul Mackerras case 0x20000: 771422123ccSChristophe Leroy pr_cont("Data parity error signal\n"); 77214cf11afSPaul Mackerras break; 77314cf11afSPaul Mackerras case 0x10000: 774422123ccSChristophe Leroy pr_cont("Address parity error signal\n"); 77514cf11afSPaul Mackerras break; 77614cf11afSPaul Mackerras case 0x20000000: 777422123ccSChristophe Leroy pr_cont("L1 Data Cache error\n"); 77814cf11afSPaul Mackerras break; 77914cf11afSPaul Mackerras case 0x40000000: 780422123ccSChristophe Leroy pr_cont("L1 Instruction Cache error\n"); 78114cf11afSPaul Mackerras break; 78214cf11afSPaul Mackerras case 0x00100000: 783422123ccSChristophe Leroy pr_cont("L2 data cache parity error\n"); 78414cf11afSPaul Mackerras break; 78514cf11afSPaul Mackerras default: 786422123ccSChristophe Leroy pr_cont("Unknown values in msr\n"); 78714cf11afSPaul Mackerras } 78875918a4bSOlof Johansson return 0; 78975918a4bSOlof Johansson } 79047c0bd1aSBenjamin Herrenschmidt #endif /* everything else */ 79175918a4bSOlof Johansson 792209e9d50SNicholas Piggin void die_mce(const char *str, struct pt_regs *regs, long err) 793209e9d50SNicholas Piggin { 794209e9d50SNicholas Piggin /* 795209e9d50SNicholas Piggin * The machine check wants to kill the interrupted context, but 796209e9d50SNicholas Piggin * do_exit() checks for in_interrupt() and panics in that case, so 797209e9d50SNicholas Piggin * exit the irq/nmi before calling die. 798209e9d50SNicholas Piggin */ 7991b1b6a6fSNicholas Piggin if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) 8001b1b6a6fSNicholas Piggin irq_exit(); 8011b1b6a6fSNicholas Piggin else 802209e9d50SNicholas Piggin nmi_exit(); 803209e9d50SNicholas Piggin die(str, regs, err); 804209e9d50SNicholas Piggin } 805209e9d50SNicholas Piggin 806118178e6SNicholas Piggin /* 807118178e6SNicholas Piggin * BOOK3S_64 does not call this handler as a non-maskable interrupt 808118178e6SNicholas Piggin * (it uses its own early real-mode handler to handle the MCE proper 809118178e6SNicholas Piggin * and then raises irq_work to call this handler when interrupts are 810118178e6SNicholas Piggin * enabled). 811118178e6SNicholas Piggin */ 8123a96570fSNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 8133a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER_ASYNC(machine_check_exception) 8143a96570fSNicholas Piggin #else 8153a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER_NMI(machine_check_exception) 8163a96570fSNicholas Piggin #endif 81775918a4bSOlof Johansson { 81875918a4bSOlof Johansson int recover = 0; 81969ea03b5SPeter Zijlstra 82069111bacSChristoph Lameter __this_cpu_inc(irq_stat.mce_exceptions); 82189713ed1SAnton Blanchard 822d93b0ac0SMahesh Salgaonkar add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 823d93b0ac0SMahesh Salgaonkar 82447c0bd1aSBenjamin Herrenschmidt /* See if any machine dependent calls. In theory, we would want 82547c0bd1aSBenjamin Herrenschmidt * to call the CPU first, and call the ppc_md. one if the CPU 82647c0bd1aSBenjamin Herrenschmidt * one returns a positive number. However there is existing code 82747c0bd1aSBenjamin Herrenschmidt * that assumes the board gets a first chance, so let's keep it 82847c0bd1aSBenjamin Herrenschmidt * that way for now and fix things later. --BenH. 82947c0bd1aSBenjamin Herrenschmidt */ 83075918a4bSOlof Johansson if (ppc_md.machine_check_exception) 83175918a4bSOlof Johansson recover = ppc_md.machine_check_exception(regs); 83247c0bd1aSBenjamin Herrenschmidt else if (cur_cpu_spec->machine_check) 83347c0bd1aSBenjamin Herrenschmidt recover = cur_cpu_spec->machine_check(regs); 83475918a4bSOlof Johansson 83547c0bd1aSBenjamin Herrenschmidt if (recover > 0) 836ba12eedeSLi Zhong goto bail; 83775918a4bSOlof Johansson 838a443506bSAnton Blanchard if (debugger_fault_handler(regs)) 839ba12eedeSLi Zhong goto bail; 84075918a4bSOlof Johansson 84175918a4bSOlof Johansson if (check_io_access(regs)) 842ba12eedeSLi Zhong goto bail; 84375918a4bSOlof Johansson 844209e9d50SNicholas Piggin die_mce("Machine check", regs, SIGBUS); 845daf00ae7SChristophe Leroy 846c538938fSNicholas Piggin bail: 8470bbea75cSChristophe Leroy /* Must die if the interrupt is not recoverable */ 848806c0e6eSChristophe Leroy if (regs_is_unrecoverable(regs)) 849209e9d50SNicholas Piggin die_mce("Unrecoverable Machine check", regs, SIGBUS); 850daf00ae7SChristophe Leroy 8513a96570fSNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 8523a96570fSNicholas Piggin return; 8533a96570fSNicholas Piggin #else 8543a96570fSNicholas Piggin return 0; 8553a96570fSNicholas Piggin #endif 85614cf11afSPaul Mackerras } 85714cf11afSPaul Mackerras 8583a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(SMIException) /* async? */ 85914cf11afSPaul Mackerras { 86014cf11afSPaul Mackerras die("System Management Interrupt", regs, SIGABRT); 86114cf11afSPaul Mackerras } 86214cf11afSPaul Mackerras 8635080332cSMichael Neuling #ifdef CONFIG_VSX 8645080332cSMichael Neuling static void p9_hmi_special_emu(struct pt_regs *regs) 8655080332cSMichael Neuling { 8665080332cSMichael Neuling unsigned int ra, rb, t, i, sel, instr, rc; 8675080332cSMichael Neuling const void __user *addr; 8681da4a027SMichael Neuling u8 vbuf[16] __aligned(16), *vdst; 8695080332cSMichael Neuling unsigned long ea, msr, msr_mask; 8705080332cSMichael Neuling bool swap; 8715080332cSMichael Neuling 872bad956b8SChristophe Leroy if (__get_user(instr, (unsigned int __user *)regs->nip)) 8735080332cSMichael Neuling return; 8745080332cSMichael Neuling 8755080332cSMichael Neuling /* 8765080332cSMichael Neuling * lxvb16x opcode: 0x7c0006d8 8775080332cSMichael Neuling * lxvd2x opcode: 0x7c000698 8785080332cSMichael Neuling * lxvh8x opcode: 0x7c000658 8795080332cSMichael Neuling * lxvw4x opcode: 0x7c000618 8805080332cSMichael Neuling */ 8815080332cSMichael Neuling if ((instr & 0xfc00073e) != 0x7c000618) { 8825080332cSMichael Neuling pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 8835080332cSMichael Neuling " instr=%08x\n", 8845080332cSMichael Neuling smp_processor_id(), current->comm, current->pid, 8855080332cSMichael Neuling regs->nip, instr); 8865080332cSMichael Neuling return; 8875080332cSMichael Neuling } 8885080332cSMichael Neuling 8895080332cSMichael Neuling /* Grab vector registers into the task struct */ 8905080332cSMichael Neuling msr = regs->msr; /* Grab msr before we flush the bits */ 8915080332cSMichael Neuling flush_vsx_to_thread(current); 8925080332cSMichael Neuling enable_kernel_altivec(); 8935080332cSMichael Neuling 8945080332cSMichael Neuling /* 8955080332cSMichael Neuling * Is userspace running with a different endian (this is rare but 8965080332cSMichael Neuling * not impossible) 8975080332cSMichael Neuling */ 8985080332cSMichael Neuling swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 8995080332cSMichael Neuling 9005080332cSMichael Neuling /* Decode the instruction */ 9015080332cSMichael Neuling ra = (instr >> 16) & 0x1f; 9025080332cSMichael Neuling rb = (instr >> 11) & 0x1f; 9035080332cSMichael Neuling t = (instr >> 21) & 0x1f; 9045080332cSMichael Neuling if (instr & 1) 9055080332cSMichael Neuling vdst = (u8 *)¤t->thread.vr_state.vr[t]; 9065080332cSMichael Neuling else 9075080332cSMichael Neuling vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 9085080332cSMichael Neuling 9095080332cSMichael Neuling /* Grab the vector address */ 9105080332cSMichael Neuling ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 9115080332cSMichael Neuling if (is_32bit_task()) 9125080332cSMichael Neuling ea &= 0xfffffffful; 9135080332cSMichael Neuling addr = (__force const void __user *)ea; 9145080332cSMichael Neuling 9155080332cSMichael Neuling /* Check it */ 91696d4f267SLinus Torvalds if (!access_ok(addr, 16)) { 9175080332cSMichael Neuling pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 9185080332cSMichael Neuling " instr=%08x addr=%016lx\n", 9195080332cSMichael Neuling smp_processor_id(), current->comm, current->pid, 9205080332cSMichael Neuling regs->nip, instr, (unsigned long)addr); 9215080332cSMichael Neuling return; 9225080332cSMichael Neuling } 9235080332cSMichael Neuling 9245080332cSMichael Neuling /* Read the vector */ 9255080332cSMichael Neuling rc = 0; 9265080332cSMichael Neuling if ((unsigned long)addr & 0xfUL) 9275080332cSMichael Neuling /* unaligned case */ 9285080332cSMichael Neuling rc = __copy_from_user_inatomic(vbuf, addr, 16); 9295080332cSMichael Neuling else 9305080332cSMichael Neuling __get_user_atomic_128_aligned(vbuf, addr, rc); 9315080332cSMichael Neuling if (rc) { 9325080332cSMichael Neuling pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 9335080332cSMichael Neuling " instr=%08x addr=%016lx\n", 9345080332cSMichael Neuling smp_processor_id(), current->comm, current->pid, 9355080332cSMichael Neuling regs->nip, instr, (unsigned long)addr); 9365080332cSMichael Neuling return; 9375080332cSMichael Neuling } 9385080332cSMichael Neuling 9395080332cSMichael Neuling pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 9405080332cSMichael Neuling " instr=%08x addr=%016lx\n", 9415080332cSMichael Neuling smp_processor_id(), current->comm, current->pid, regs->nip, 9425080332cSMichael Neuling instr, (unsigned long) addr); 9435080332cSMichael Neuling 9445080332cSMichael Neuling /* Grab instruction "selector" */ 9455080332cSMichael Neuling sel = (instr >> 6) & 3; 9465080332cSMichael Neuling 9475080332cSMichael Neuling /* 9485080332cSMichael Neuling * Check to make sure the facility is actually enabled. This 9495080332cSMichael Neuling * could happen if we get a false positive hit. 9505080332cSMichael Neuling * 9515080332cSMichael Neuling * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 9525080332cSMichael Neuling * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 9535080332cSMichael Neuling */ 9545080332cSMichael Neuling msr_mask = MSR_VSX; 9555080332cSMichael Neuling if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 9565080332cSMichael Neuling msr_mask = MSR_VEC; 9575080332cSMichael Neuling if (!(msr & msr_mask)) { 9585080332cSMichael Neuling pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 9595080332cSMichael Neuling " instr=%08x msr:%016lx\n", 9605080332cSMichael Neuling smp_processor_id(), current->comm, current->pid, 9615080332cSMichael Neuling regs->nip, instr, msr); 9625080332cSMichael Neuling return; 9635080332cSMichael Neuling } 9645080332cSMichael Neuling 9655080332cSMichael Neuling /* Do logging here before we modify sel based on endian */ 9665080332cSMichael Neuling switch (sel) { 9675080332cSMichael Neuling case 0: /* lxvw4x */ 9685080332cSMichael Neuling PPC_WARN_EMULATED(lxvw4x, regs); 9695080332cSMichael Neuling break; 9705080332cSMichael Neuling case 1: /* lxvh8x */ 9715080332cSMichael Neuling PPC_WARN_EMULATED(lxvh8x, regs); 9725080332cSMichael Neuling break; 9735080332cSMichael Neuling case 2: /* lxvd2x */ 9745080332cSMichael Neuling PPC_WARN_EMULATED(lxvd2x, regs); 9755080332cSMichael Neuling break; 9765080332cSMichael Neuling case 3: /* lxvb16x */ 9775080332cSMichael Neuling PPC_WARN_EMULATED(lxvb16x, regs); 9785080332cSMichael Neuling break; 9795080332cSMichael Neuling } 9805080332cSMichael Neuling 9815080332cSMichael Neuling #ifdef __LITTLE_ENDIAN__ 9825080332cSMichael Neuling /* 9835080332cSMichael Neuling * An LE kernel stores the vector in the task struct as an LE 9845080332cSMichael Neuling * byte array (effectively swapping both the components and 9855080332cSMichael Neuling * the content of the components). Those instructions expect 9865080332cSMichael Neuling * the components to remain in ascending address order, so we 9875080332cSMichael Neuling * swap them back. 9885080332cSMichael Neuling * 9895080332cSMichael Neuling * If we are running a BE user space, the expectation is that 9905080332cSMichael Neuling * of a simple memcpy, so forcing the emulation to look like 9915080332cSMichael Neuling * a lxvb16x should do the trick. 9925080332cSMichael Neuling */ 9935080332cSMichael Neuling if (swap) 9945080332cSMichael Neuling sel = 3; 9955080332cSMichael Neuling 9965080332cSMichael Neuling switch (sel) { 9975080332cSMichael Neuling case 0: /* lxvw4x */ 9985080332cSMichael Neuling for (i = 0; i < 4; i++) 9995080332cSMichael Neuling ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 10005080332cSMichael Neuling break; 10015080332cSMichael Neuling case 1: /* lxvh8x */ 10025080332cSMichael Neuling for (i = 0; i < 8; i++) 10035080332cSMichael Neuling ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 10045080332cSMichael Neuling break; 10055080332cSMichael Neuling case 2: /* lxvd2x */ 10065080332cSMichael Neuling for (i = 0; i < 2; i++) 10075080332cSMichael Neuling ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 10085080332cSMichael Neuling break; 10095080332cSMichael Neuling case 3: /* lxvb16x */ 10105080332cSMichael Neuling for (i = 0; i < 16; i++) 10115080332cSMichael Neuling vdst[i] = vbuf[15-i]; 10125080332cSMichael Neuling break; 10135080332cSMichael Neuling } 10145080332cSMichael Neuling #else /* __LITTLE_ENDIAN__ */ 10155080332cSMichael Neuling /* On a big endian kernel, a BE userspace only needs a memcpy */ 10165080332cSMichael Neuling if (!swap) 10175080332cSMichael Neuling sel = 3; 10185080332cSMichael Neuling 10195080332cSMichael Neuling /* Otherwise, we need to swap the content of the components */ 10205080332cSMichael Neuling switch (sel) { 10215080332cSMichael Neuling case 0: /* lxvw4x */ 10225080332cSMichael Neuling for (i = 0; i < 4; i++) 10235080332cSMichael Neuling ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 10245080332cSMichael Neuling break; 10255080332cSMichael Neuling case 1: /* lxvh8x */ 10265080332cSMichael Neuling for (i = 0; i < 8; i++) 10275080332cSMichael Neuling ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 10285080332cSMichael Neuling break; 10295080332cSMichael Neuling case 2: /* lxvd2x */ 10305080332cSMichael Neuling for (i = 0; i < 2; i++) 10315080332cSMichael Neuling ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 10325080332cSMichael Neuling break; 10335080332cSMichael Neuling case 3: /* lxvb16x */ 10345080332cSMichael Neuling memcpy(vdst, vbuf, 16); 10355080332cSMichael Neuling break; 10365080332cSMichael Neuling } 10375080332cSMichael Neuling #endif /* !__LITTLE_ENDIAN__ */ 10385080332cSMichael Neuling 10395080332cSMichael Neuling /* Go to next instruction */ 104059dc5bfcSNicholas Piggin regs_add_return_ip(regs, 4); 10415080332cSMichael Neuling } 10425080332cSMichael Neuling #endif /* CONFIG_VSX */ 10435080332cSMichael Neuling 10443a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER_ASYNC(handle_hmi_exception) 10450869b6fdSMahesh Salgaonkar { 10460869b6fdSMahesh Salgaonkar struct pt_regs *old_regs; 10470869b6fdSMahesh Salgaonkar 10480869b6fdSMahesh Salgaonkar old_regs = set_irq_regs(regs); 10490869b6fdSMahesh Salgaonkar 10505080332cSMichael Neuling #ifdef CONFIG_VSX 10515080332cSMichael Neuling /* Real mode flagged P9 special emu is needed */ 10525080332cSMichael Neuling if (local_paca->hmi_p9_special_emu) { 10535080332cSMichael Neuling local_paca->hmi_p9_special_emu = 0; 10545080332cSMichael Neuling 10555080332cSMichael Neuling /* 10565080332cSMichael Neuling * We don't want to take page faults while doing the 10575080332cSMichael Neuling * emulation, we just replay the instruction if necessary. 10585080332cSMichael Neuling */ 10595080332cSMichael Neuling pagefault_disable(); 10605080332cSMichael Neuling p9_hmi_special_emu(regs); 10615080332cSMichael Neuling pagefault_enable(); 10625080332cSMichael Neuling } 10635080332cSMichael Neuling #endif /* CONFIG_VSX */ 10645080332cSMichael Neuling 10650869b6fdSMahesh Salgaonkar if (ppc_md.handle_hmi_exception) 10660869b6fdSMahesh Salgaonkar ppc_md.handle_hmi_exception(regs); 10670869b6fdSMahesh Salgaonkar 10680869b6fdSMahesh Salgaonkar set_irq_regs(old_regs); 10690869b6fdSMahesh Salgaonkar } 10700869b6fdSMahesh Salgaonkar 10713a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(unknown_exception) 107214cf11afSPaul Mackerras { 107314cf11afSPaul Mackerras printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 107414cf11afSPaul Mackerras regs->nip, regs->msr, regs->trap); 107514cf11afSPaul Mackerras 1076e821fa42SEric W. Biederman _exception(SIGTRAP, regs, TRAP_UNK, 0); 107714cf11afSPaul Mackerras } 107814cf11afSPaul Mackerras 10793a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER_ASYNC(unknown_async_exception) 10806c6aee00SNicholas Piggin { 10816c6aee00SNicholas Piggin printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 10826c6aee00SNicholas Piggin regs->nip, regs->msr, regs->trap); 10836c6aee00SNicholas Piggin 10846c6aee00SNicholas Piggin _exception(SIGTRAP, regs, TRAP_UNK, 0); 10856c6aee00SNicholas Piggin } 10866c6aee00SNicholas Piggin 10873db8aa10SNicholas Piggin DEFINE_INTERRUPT_HANDLER_NMI(unknown_nmi_exception) 10883db8aa10SNicholas Piggin { 10893db8aa10SNicholas Piggin printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 10903db8aa10SNicholas Piggin regs->nip, regs->msr, regs->trap); 10913db8aa10SNicholas Piggin 10923db8aa10SNicholas Piggin _exception(SIGTRAP, regs, TRAP_UNK, 0); 10933db8aa10SNicholas Piggin 10943db8aa10SNicholas Piggin return 0; 10953db8aa10SNicholas Piggin } 10963db8aa10SNicholas Piggin 10973a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(instruction_breakpoint_exception) 109814cf11afSPaul Mackerras { 109914cf11afSPaul Mackerras if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 110014cf11afSPaul Mackerras 5, SIGTRAP) == NOTIFY_STOP) 1101540d4d34SNicholas Piggin return; 110214cf11afSPaul Mackerras if (debugger_iabr_match(regs)) 1103540d4d34SNicholas Piggin return; 110414cf11afSPaul Mackerras _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 110514cf11afSPaul Mackerras } 110614cf11afSPaul Mackerras 11073a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(RunModeException) 110814cf11afSPaul Mackerras { 1109e821fa42SEric W. Biederman _exception(SIGTRAP, regs, TRAP_UNK, 0); 111014cf11afSPaul Mackerras } 111114cf11afSPaul Mackerras 111201fcac8eSChristophe Leroy static void __single_step_exception(struct pt_regs *regs) 111314cf11afSPaul Mackerras { 11142538c2d0SK.Prasad clear_single_step(regs); 11150e524e76SMatt Evans clear_br_trace(regs); 111614cf11afSPaul Mackerras 11176cc89badSNaveen N. Rao if (kprobe_post_handler(regs)) 11186cc89badSNaveen N. Rao return; 11196cc89badSNaveen N. Rao 112014cf11afSPaul Mackerras if (notify_die(DIE_SSTEP, "single_step", regs, 5, 112114cf11afSPaul Mackerras 5, SIGTRAP) == NOTIFY_STOP) 1122540d4d34SNicholas Piggin return; 112314cf11afSPaul Mackerras if (debugger_sstep(regs)) 1124540d4d34SNicholas Piggin return; 112514cf11afSPaul Mackerras 112614cf11afSPaul Mackerras _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 112714cf11afSPaul Mackerras } 112814cf11afSPaul Mackerras 112901fcac8eSChristophe Leroy DEFINE_INTERRUPT_HANDLER(single_step_exception) 113001fcac8eSChristophe Leroy { 113101fcac8eSChristophe Leroy __single_step_exception(regs); 113201fcac8eSChristophe Leroy } 113301fcac8eSChristophe Leroy 113414cf11afSPaul Mackerras /* 113514cf11afSPaul Mackerras * After we have successfully emulated an instruction, we have to 113614cf11afSPaul Mackerras * check if the instruction was being single-stepped, and if so, 113714cf11afSPaul Mackerras * pretend we got a single-step exception. This was pointed out 113814cf11afSPaul Mackerras * by Kumar Gala. -- paulus 113914cf11afSPaul Mackerras */ 11408dad3f92SPaul Mackerras static void emulate_single_step(struct pt_regs *regs) 114114cf11afSPaul Mackerras { 11422538c2d0SK.Prasad if (single_stepping(regs)) 114301fcac8eSChristophe Leroy __single_step_exception(regs); 114414cf11afSPaul Mackerras } 114514cf11afSPaul Mackerras 11465fad293bSKumar Gala static inline int __parse_fpscr(unsigned long fpscr) 1147dc1c1ca3SStephen Rothwell { 1148aeb1c0f6SEric W. Biederman int ret = FPE_FLTUNK; 1149dc1c1ca3SStephen Rothwell 1150dc1c1ca3SStephen Rothwell /* Invalid operation */ 1151dc1c1ca3SStephen Rothwell if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 11525fad293bSKumar Gala ret = FPE_FLTINV; 1153dc1c1ca3SStephen Rothwell 1154dc1c1ca3SStephen Rothwell /* Overflow */ 1155dc1c1ca3SStephen Rothwell else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 11565fad293bSKumar Gala ret = FPE_FLTOVF; 1157dc1c1ca3SStephen Rothwell 1158dc1c1ca3SStephen Rothwell /* Underflow */ 1159dc1c1ca3SStephen Rothwell else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 11605fad293bSKumar Gala ret = FPE_FLTUND; 1161dc1c1ca3SStephen Rothwell 1162dc1c1ca3SStephen Rothwell /* Divide by zero */ 1163dc1c1ca3SStephen Rothwell else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 11645fad293bSKumar Gala ret = FPE_FLTDIV; 1165dc1c1ca3SStephen Rothwell 1166dc1c1ca3SStephen Rothwell /* Inexact result */ 1167dc1c1ca3SStephen Rothwell else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 11685fad293bSKumar Gala ret = FPE_FLTRES; 11695fad293bSKumar Gala 11705fad293bSKumar Gala return ret; 11715fad293bSKumar Gala } 11725fad293bSKumar Gala 11735fad293bSKumar Gala static void parse_fpe(struct pt_regs *regs) 11745fad293bSKumar Gala { 11755fad293bSKumar Gala int code = 0; 11765fad293bSKumar Gala 11775fad293bSKumar Gala flush_fp_to_thread(current); 11785fad293bSKumar Gala 1179b6254cedSChristophe Leroy #ifdef CONFIG_PPC_FPU_REGS 1180de79f7b9SPaul Mackerras code = __parse_fpscr(current->thread.fp_state.fpscr); 1181b6254cedSChristophe Leroy #endif 1182dc1c1ca3SStephen Rothwell 1183dc1c1ca3SStephen Rothwell _exception(SIGFPE, regs, code, regs->nip); 1184dc1c1ca3SStephen Rothwell } 1185dc1c1ca3SStephen Rothwell 1186dc1c1ca3SStephen Rothwell /* 1187dc1c1ca3SStephen Rothwell * Illegal instruction emulation support. Originally written to 118814cf11afSPaul Mackerras * provide the PVR to user applications using the mfspr rd, PVR. 118914cf11afSPaul Mackerras * Return non-zero if we can't emulate, or -EFAULT if the associated 119014cf11afSPaul Mackerras * memory access caused an access fault. Return zero on success. 119114cf11afSPaul Mackerras * 119214cf11afSPaul Mackerras * There are a couple of ways to do this, either "decode" the instruction 119314cf11afSPaul Mackerras * or directly match lots of bits. In this case, matching lots of 119414cf11afSPaul Mackerras * bits is faster and easier. 119586417780SPaul Mackerras * 119614cf11afSPaul Mackerras */ 119714cf11afSPaul Mackerras static int emulate_string_inst(struct pt_regs *regs, u32 instword) 119814cf11afSPaul Mackerras { 119914cf11afSPaul Mackerras u8 rT = (instword >> 21) & 0x1f; 120014cf11afSPaul Mackerras u8 rA = (instword >> 16) & 0x1f; 120114cf11afSPaul Mackerras u8 NB_RB = (instword >> 11) & 0x1f; 120214cf11afSPaul Mackerras u32 num_bytes; 120314cf11afSPaul Mackerras unsigned long EA; 120414cf11afSPaul Mackerras int pos = 0; 120514cf11afSPaul Mackerras 120614cf11afSPaul Mackerras /* Early out if we are an invalid form of lswx */ 120716c57b36SKumar Gala if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 120814cf11afSPaul Mackerras if ((rT == rA) || (rT == NB_RB)) 120914cf11afSPaul Mackerras return -EINVAL; 121014cf11afSPaul Mackerras 121114cf11afSPaul Mackerras EA = (rA == 0) ? 0 : regs->gpr[rA]; 121214cf11afSPaul Mackerras 121316c57b36SKumar Gala switch (instword & PPC_INST_STRING_MASK) { 121416c57b36SKumar Gala case PPC_INST_LSWX: 121516c57b36SKumar Gala case PPC_INST_STSWX: 121614cf11afSPaul Mackerras EA += NB_RB; 121714cf11afSPaul Mackerras num_bytes = regs->xer & 0x7f; 121814cf11afSPaul Mackerras break; 121916c57b36SKumar Gala case PPC_INST_LSWI: 122016c57b36SKumar Gala case PPC_INST_STSWI: 122114cf11afSPaul Mackerras num_bytes = (NB_RB == 0) ? 32 : NB_RB; 122214cf11afSPaul Mackerras break; 122314cf11afSPaul Mackerras default: 122414cf11afSPaul Mackerras return -EINVAL; 122514cf11afSPaul Mackerras } 122614cf11afSPaul Mackerras 122714cf11afSPaul Mackerras while (num_bytes != 0) 122814cf11afSPaul Mackerras { 122914cf11afSPaul Mackerras u8 val; 123014cf11afSPaul Mackerras u32 shift = 8 * (3 - (pos & 0x3)); 123114cf11afSPaul Mackerras 123280aa0fb4SJames Yang /* if process is 32-bit, clear upper 32 bits of EA */ 123380aa0fb4SJames Yang if ((regs->msr & MSR_64BIT) == 0) 123480aa0fb4SJames Yang EA &= 0xFFFFFFFF; 123580aa0fb4SJames Yang 123616c57b36SKumar Gala switch ((instword & PPC_INST_STRING_MASK)) { 123716c57b36SKumar Gala case PPC_INST_LSWX: 123816c57b36SKumar Gala case PPC_INST_LSWI: 123914cf11afSPaul Mackerras if (get_user(val, (u8 __user *)EA)) 124014cf11afSPaul Mackerras return -EFAULT; 124114cf11afSPaul Mackerras /* first time updating this reg, 124214cf11afSPaul Mackerras * zero it out */ 124314cf11afSPaul Mackerras if (pos == 0) 124414cf11afSPaul Mackerras regs->gpr[rT] = 0; 124514cf11afSPaul Mackerras regs->gpr[rT] |= val << shift; 124614cf11afSPaul Mackerras break; 124716c57b36SKumar Gala case PPC_INST_STSWI: 124816c57b36SKumar Gala case PPC_INST_STSWX: 124914cf11afSPaul Mackerras val = regs->gpr[rT] >> shift; 125014cf11afSPaul Mackerras if (put_user(val, (u8 __user *)EA)) 125114cf11afSPaul Mackerras return -EFAULT; 125214cf11afSPaul Mackerras break; 125314cf11afSPaul Mackerras } 125414cf11afSPaul Mackerras /* move EA to next address */ 125514cf11afSPaul Mackerras EA += 1; 125614cf11afSPaul Mackerras num_bytes--; 125714cf11afSPaul Mackerras 125814cf11afSPaul Mackerras /* manage our position within the register */ 125914cf11afSPaul Mackerras if (++pos == 4) { 126014cf11afSPaul Mackerras pos = 0; 126114cf11afSPaul Mackerras if (++rT == 32) 126214cf11afSPaul Mackerras rT = 0; 126314cf11afSPaul Mackerras } 126414cf11afSPaul Mackerras } 126514cf11afSPaul Mackerras 126614cf11afSPaul Mackerras return 0; 126714cf11afSPaul Mackerras } 126814cf11afSPaul Mackerras 1269c3412dcbSWill Schmidt static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1270c3412dcbSWill Schmidt { 1271c3412dcbSWill Schmidt u32 ra,rs; 1272c3412dcbSWill Schmidt unsigned long tmp; 1273c3412dcbSWill Schmidt 1274c3412dcbSWill Schmidt ra = (instword >> 16) & 0x1f; 1275c3412dcbSWill Schmidt rs = (instword >> 21) & 0x1f; 1276c3412dcbSWill Schmidt 1277c3412dcbSWill Schmidt tmp = regs->gpr[rs]; 1278c3412dcbSWill Schmidt tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1279c3412dcbSWill Schmidt tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1280c3412dcbSWill Schmidt tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1281c3412dcbSWill Schmidt regs->gpr[ra] = tmp; 1282c3412dcbSWill Schmidt 1283c3412dcbSWill Schmidt return 0; 1284c3412dcbSWill Schmidt } 1285c3412dcbSWill Schmidt 1286c1469f13SKumar Gala static int emulate_isel(struct pt_regs *regs, u32 instword) 1287c1469f13SKumar Gala { 1288c1469f13SKumar Gala u8 rT = (instword >> 21) & 0x1f; 1289c1469f13SKumar Gala u8 rA = (instword >> 16) & 0x1f; 1290c1469f13SKumar Gala u8 rB = (instword >> 11) & 0x1f; 1291c1469f13SKumar Gala u8 BC = (instword >> 6) & 0x1f; 1292c1469f13SKumar Gala u8 bit; 1293c1469f13SKumar Gala unsigned long tmp; 1294c1469f13SKumar Gala 1295c1469f13SKumar Gala tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1296c1469f13SKumar Gala bit = (regs->ccr >> (31 - BC)) & 0x1; 1297c1469f13SKumar Gala 1298c1469f13SKumar Gala regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1299c1469f13SKumar Gala 1300c1469f13SKumar Gala return 0; 1301c1469f13SKumar Gala } 1302c1469f13SKumar Gala 13036ce6c629SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 13046ce6c629SMichael Neuling static inline bool tm_abort_check(struct pt_regs *regs, int cause) 13056ce6c629SMichael Neuling { 13066ce6c629SMichael Neuling /* If we're emulating a load/store in an active transaction, we cannot 13076ce6c629SMichael Neuling * emulate it as the kernel operates in transaction suspended context. 13086ce6c629SMichael Neuling * We need to abort the transaction. This creates a persistent TM 13096ce6c629SMichael Neuling * abort so tell the user what caused it with a new code. 13106ce6c629SMichael Neuling */ 13116ce6c629SMichael Neuling if (MSR_TM_TRANSACTIONAL(regs->msr)) { 13126ce6c629SMichael Neuling tm_enable(); 13136ce6c629SMichael Neuling tm_abort(cause); 13146ce6c629SMichael Neuling return true; 13156ce6c629SMichael Neuling } 13166ce6c629SMichael Neuling return false; 13176ce6c629SMichael Neuling } 13186ce6c629SMichael Neuling #else 13196ce6c629SMichael Neuling static inline bool tm_abort_check(struct pt_regs *regs, int reason) 13206ce6c629SMichael Neuling { 13216ce6c629SMichael Neuling return false; 13226ce6c629SMichael Neuling } 13236ce6c629SMichael Neuling #endif 13246ce6c629SMichael Neuling 132514cf11afSPaul Mackerras static int emulate_instruction(struct pt_regs *regs) 132614cf11afSPaul Mackerras { 132714cf11afSPaul Mackerras u32 instword; 132814cf11afSPaul Mackerras u32 rd; 132914cf11afSPaul Mackerras 13304288e343SAnton Blanchard if (!user_mode(regs)) 133114cf11afSPaul Mackerras return -EINVAL; 133214cf11afSPaul Mackerras 133314cf11afSPaul Mackerras if (get_user(instword, (u32 __user *)(regs->nip))) 133414cf11afSPaul Mackerras return -EFAULT; 133514cf11afSPaul Mackerras 133614cf11afSPaul Mackerras /* Emulate the mfspr rD, PVR. */ 133716c57b36SKumar Gala if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1338eecff81dSAnton Blanchard PPC_WARN_EMULATED(mfpvr, regs); 133914cf11afSPaul Mackerras rd = (instword >> 21) & 0x1f; 134014cf11afSPaul Mackerras regs->gpr[rd] = mfspr(SPRN_PVR); 134114cf11afSPaul Mackerras return 0; 134214cf11afSPaul Mackerras } 134314cf11afSPaul Mackerras 134414cf11afSPaul Mackerras /* Emulating the dcba insn is just a no-op. */ 134580947e7cSGeert Uytterhoeven if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1346eecff81dSAnton Blanchard PPC_WARN_EMULATED(dcba, regs); 134714cf11afSPaul Mackerras return 0; 134880947e7cSGeert Uytterhoeven } 134914cf11afSPaul Mackerras 135014cf11afSPaul Mackerras /* Emulate the mcrxr insn. */ 135116c57b36SKumar Gala if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 135286417780SPaul Mackerras int shift = (instword >> 21) & 0x1c; 135314cf11afSPaul Mackerras unsigned long msk = 0xf0000000UL >> shift; 135414cf11afSPaul Mackerras 1355eecff81dSAnton Blanchard PPC_WARN_EMULATED(mcrxr, regs); 135614cf11afSPaul Mackerras regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 135714cf11afSPaul Mackerras regs->xer &= ~0xf0000000UL; 135814cf11afSPaul Mackerras return 0; 135914cf11afSPaul Mackerras } 136014cf11afSPaul Mackerras 136114cf11afSPaul Mackerras /* Emulate load/store string insn. */ 136280947e7cSGeert Uytterhoeven if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 13636ce6c629SMichael Neuling if (tm_abort_check(regs, 13646ce6c629SMichael Neuling TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 13656ce6c629SMichael Neuling return -EINVAL; 1366eecff81dSAnton Blanchard PPC_WARN_EMULATED(string, regs); 136714cf11afSPaul Mackerras return emulate_string_inst(regs, instword); 136880947e7cSGeert Uytterhoeven } 136914cf11afSPaul Mackerras 1370c3412dcbSWill Schmidt /* Emulate the popcntb (Population Count Bytes) instruction. */ 137116c57b36SKumar Gala if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1372eecff81dSAnton Blanchard PPC_WARN_EMULATED(popcntb, regs); 1373c3412dcbSWill Schmidt return emulate_popcntb_inst(regs, instword); 1374c3412dcbSWill Schmidt } 1375c3412dcbSWill Schmidt 1376c1469f13SKumar Gala /* Emulate isel (Integer Select) instruction */ 137716c57b36SKumar Gala if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1378eecff81dSAnton Blanchard PPC_WARN_EMULATED(isel, regs); 1379c1469f13SKumar Gala return emulate_isel(regs, instword); 1380c1469f13SKumar Gala } 1381c1469f13SKumar Gala 13829863c28aSJames Yang /* Emulate sync instruction variants */ 13839863c28aSJames Yang if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 13849863c28aSJames Yang PPC_WARN_EMULATED(sync, regs); 13859863c28aSJames Yang asm volatile("sync"); 13869863c28aSJames Yang return 0; 13879863c28aSJames Yang } 13889863c28aSJames Yang 1389efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64 1390efcac658SAlexey Kardashevskiy /* Emulate the mfspr rD, DSCR. */ 139173d2fb75SAnton Blanchard if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 139273d2fb75SAnton Blanchard PPC_INST_MFSPR_DSCR_USER) || 139373d2fb75SAnton Blanchard ((instword & PPC_INST_MFSPR_DSCR_MASK) == 139473d2fb75SAnton Blanchard PPC_INST_MFSPR_DSCR)) && 1395efcac658SAlexey Kardashevskiy cpu_has_feature(CPU_FTR_DSCR)) { 1396efcac658SAlexey Kardashevskiy PPC_WARN_EMULATED(mfdscr, regs); 1397efcac658SAlexey Kardashevskiy rd = (instword >> 21) & 0x1f; 1398efcac658SAlexey Kardashevskiy regs->gpr[rd] = mfspr(SPRN_DSCR); 1399efcac658SAlexey Kardashevskiy return 0; 1400efcac658SAlexey Kardashevskiy } 1401efcac658SAlexey Kardashevskiy /* Emulate the mtspr DSCR, rD. */ 140273d2fb75SAnton Blanchard if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 140373d2fb75SAnton Blanchard PPC_INST_MTSPR_DSCR_USER) || 140473d2fb75SAnton Blanchard ((instword & PPC_INST_MTSPR_DSCR_MASK) == 140573d2fb75SAnton Blanchard PPC_INST_MTSPR_DSCR)) && 1406efcac658SAlexey Kardashevskiy cpu_has_feature(CPU_FTR_DSCR)) { 1407efcac658SAlexey Kardashevskiy PPC_WARN_EMULATED(mtdscr, regs); 1408efcac658SAlexey Kardashevskiy rd = (instword >> 21) & 0x1f; 140900ca0de0SAnton Blanchard current->thread.dscr = regs->gpr[rd]; 1410efcac658SAlexey Kardashevskiy current->thread.dscr_inherit = 1; 141100ca0de0SAnton Blanchard mtspr(SPRN_DSCR, current->thread.dscr); 1412efcac658SAlexey Kardashevskiy return 0; 1413efcac658SAlexey Kardashevskiy } 1414efcac658SAlexey Kardashevskiy #endif 1415efcac658SAlexey Kardashevskiy 141614cf11afSPaul Mackerras return -EINVAL; 141714cf11afSPaul Mackerras } 141814cf11afSPaul Mackerras 141973c9ceabSJeremy Fitzhardinge int is_valid_bugaddr(unsigned long addr) 142014cf11afSPaul Mackerras { 142173c9ceabSJeremy Fitzhardinge return is_kernel_addr(addr); 142214cf11afSPaul Mackerras } 142314cf11afSPaul Mackerras 14243a3b5aa6SKevin Hao #ifdef CONFIG_MATH_EMULATION 14253a3b5aa6SKevin Hao static int emulate_math(struct pt_regs *regs) 14263a3b5aa6SKevin Hao { 14273a3b5aa6SKevin Hao int ret; 14283a3b5aa6SKevin Hao 14293a3b5aa6SKevin Hao ret = do_mathemu(regs); 14303a3b5aa6SKevin Hao if (ret >= 0) 14313a3b5aa6SKevin Hao PPC_WARN_EMULATED(math, regs); 14323a3b5aa6SKevin Hao 14333a3b5aa6SKevin Hao switch (ret) { 14343a3b5aa6SKevin Hao case 0: 14353a3b5aa6SKevin Hao emulate_single_step(regs); 14363a3b5aa6SKevin Hao return 0; 14373a3b5aa6SKevin Hao case 1: { 14383a3b5aa6SKevin Hao int code = 0; 1439de79f7b9SPaul Mackerras code = __parse_fpscr(current->thread.fp_state.fpscr); 14403a3b5aa6SKevin Hao _exception(SIGFPE, regs, code, regs->nip); 14413a3b5aa6SKevin Hao return 0; 14423a3b5aa6SKevin Hao } 14433a3b5aa6SKevin Hao case -EFAULT: 14443a3b5aa6SKevin Hao _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 14453a3b5aa6SKevin Hao return 0; 14463a3b5aa6SKevin Hao } 14473a3b5aa6SKevin Hao 14483a3b5aa6SKevin Hao return -1; 14493a3b5aa6SKevin Hao } 14503a3b5aa6SKevin Hao #else 14513a3b5aa6SKevin Hao static inline int emulate_math(struct pt_regs *regs) { return -1; } 14523a3b5aa6SKevin Hao #endif 14533a3b5aa6SKevin Hao 1454fd3f1e0fSNicholas Piggin static void do_program_check(struct pt_regs *regs) 145514cf11afSPaul Mackerras { 145614cf11afSPaul Mackerras unsigned int reason = get_reason(regs); 145714cf11afSPaul Mackerras 1458aa42c69cSKim Phillips /* We can now get here via a FP Unavailable exception if the core 145904903a30SKumar Gala * has no FPU, in that case the reason flags will be 0 */ 146014cf11afSPaul Mackerras 146114cf11afSPaul Mackerras if (reason & REASON_FP) { 146214cf11afSPaul Mackerras /* IEEE FP exception */ 1463dc1c1ca3SStephen Rothwell parse_fpe(regs); 1464fd3f1e0fSNicholas Piggin return; 14658dad3f92SPaul Mackerras } 14668dad3f92SPaul Mackerras if (reason & REASON_TRAP) { 1467a4c3f909SBalbir Singh unsigned long bugaddr; 1468ba797b28SJason Wessel /* Debugger is first in line to stop recursive faults in 1469ba797b28SJason Wessel * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1470ba797b28SJason Wessel if (debugger_bpt(regs)) 1471fd3f1e0fSNicholas Piggin return; 1472ba797b28SJason Wessel 14736cc89badSNaveen N. Rao if (kprobe_handler(regs)) 1474fd3f1e0fSNicholas Piggin return; 14756cc89badSNaveen N. Rao 147614cf11afSPaul Mackerras /* trap exception */ 1477dc1c1ca3SStephen Rothwell if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1478dc1c1ca3SStephen Rothwell == NOTIFY_STOP) 1479fd3f1e0fSNicholas Piggin return; 148073c9ceabSJeremy Fitzhardinge 1481a4c3f909SBalbir Singh bugaddr = regs->nip; 1482a4c3f909SBalbir Singh /* 1483a4c3f909SBalbir Singh * Fixup bugaddr for BUG_ON() in real mode 1484a4c3f909SBalbir Singh */ 1485a4c3f909SBalbir Singh if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1486a4c3f909SBalbir Singh bugaddr += PAGE_OFFSET; 1487a4c3f909SBalbir Singh 148873c9ceabSJeremy Fitzhardinge if (!(regs->msr & MSR_PR) && /* not user-mode */ 1489a4c3f909SBalbir Singh report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 14901e688dd2SChristophe Leroy const struct exception_table_entry *entry; 14911e688dd2SChristophe Leroy 14921e688dd2SChristophe Leroy entry = search_exception_tables(bugaddr); 14931e688dd2SChristophe Leroy if (entry) { 14941e688dd2SChristophe Leroy regs_set_return_ip(regs, extable_fixup(entry) + regs->nip - bugaddr); 1495fd3f1e0fSNicholas Piggin return; 149614cf11afSPaul Mackerras } 14971e688dd2SChristophe Leroy } 14988dad3f92SPaul Mackerras _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1499fd3f1e0fSNicholas Piggin return; 15008dad3f92SPaul Mackerras } 1501bc2a9408SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1502bc2a9408SMichael Neuling if (reason & REASON_TM) { 1503bc2a9408SMichael Neuling /* This is a TM "Bad Thing Exception" program check. 1504bc2a9408SMichael Neuling * This occurs when: 1505bc2a9408SMichael Neuling * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1506bc2a9408SMichael Neuling * transition in TM states. 1507bc2a9408SMichael Neuling * - A trechkpt is attempted when transactional. 1508bc2a9408SMichael Neuling * - A treclaim is attempted when non transactional. 1509bc2a9408SMichael Neuling * - A tend is illegally attempted. 1510bc2a9408SMichael Neuling * - writing a TM SPR when transactional. 1511632f0574SMichael Ellerman * 1512632f0574SMichael Ellerman * If usermode caused this, it's done something illegal and 1513bc2a9408SMichael Neuling * gets a SIGILL slap on the wrist. We call it an illegal 1514bc2a9408SMichael Neuling * operand to distinguish from the instruction just being bad 1515bc2a9408SMichael Neuling * (e.g. executing a 'tend' on a CPU without TM!); it's an 1516bc2a9408SMichael Neuling * illegal /placement/ of a valid instruction. 1517bc2a9408SMichael Neuling */ 1518bc2a9408SMichael Neuling if (user_mode(regs)) { 1519bc2a9408SMichael Neuling _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1520fd3f1e0fSNicholas Piggin return; 1521bc2a9408SMichael Neuling } else { 1522bc2a9408SMichael Neuling printk(KERN_EMERG "Unexpected TM Bad Thing exception " 152311be3958SBreno Leitao "at %lx (msr 0x%lx) tm_scratch=%llx\n", 152411be3958SBreno Leitao regs->nip, regs->msr, get_paca()->tm_scratch); 1525bc2a9408SMichael Neuling die("Unrecoverable exception", regs, SIGABRT); 1526bc2a9408SMichael Neuling } 1527bc2a9408SMichael Neuling } 1528bc2a9408SMichael Neuling #endif 15298dad3f92SPaul Mackerras 1530b3f6a459SMichael Ellerman /* 1531b3f6a459SMichael Ellerman * If we took the program check in the kernel skip down to sending a 1532b3f6a459SMichael Ellerman * SIGILL. The subsequent cases all relate to emulating instructions 1533b3f6a459SMichael Ellerman * which we should only do for userspace. We also do not want to enable 1534b3f6a459SMichael Ellerman * interrupts for kernel faults because that might lead to further 1535b3f6a459SMichael Ellerman * faults, and loose the context of the original exception. 1536b3f6a459SMichael Ellerman */ 1537b3f6a459SMichael Ellerman if (!user_mode(regs)) 1538b3f6a459SMichael Ellerman goto sigill; 1539b3f6a459SMichael Ellerman 1540e6f8a6c8SNicholas Piggin interrupt_cond_local_irq_enable(regs); 1541cd8a5673SPaul Mackerras 154204903a30SKumar Gala /* (reason & REASON_ILLEGAL) would be the obvious thing here, 154304903a30SKumar Gala * but there seems to be a hardware bug on the 405GP (RevD) 154404903a30SKumar Gala * that means ESR is sometimes set incorrectly - either to 154504903a30SKumar Gala * ESR_DST (!?) or 0. In the process of chasing this with the 154604903a30SKumar Gala * hardware people - not sure if it can happen on any illegal 154704903a30SKumar Gala * instruction or only on FP instructions, whether there is a 15484e63f8edSBenjamin Herrenschmidt * pattern to occurrences etc. -dgibson 31/Mar/2003 15494e63f8edSBenjamin Herrenschmidt */ 15503a3b5aa6SKevin Hao if (!emulate_math(regs)) 1551fd3f1e0fSNicholas Piggin return; 155204903a30SKumar Gala 15538dad3f92SPaul Mackerras /* Try to emulate it if we should. */ 15548dad3f92SPaul Mackerras if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 155514cf11afSPaul Mackerras switch (emulate_instruction(regs)) { 155614cf11afSPaul Mackerras case 0: 155759dc5bfcSNicholas Piggin regs_add_return_ip(regs, 4); 155814cf11afSPaul Mackerras emulate_single_step(regs); 1559fd3f1e0fSNicholas Piggin return; 156014cf11afSPaul Mackerras case -EFAULT: 156114cf11afSPaul Mackerras _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1562fd3f1e0fSNicholas Piggin return; 15638dad3f92SPaul Mackerras } 15648dad3f92SPaul Mackerras } 15658dad3f92SPaul Mackerras 1566b3f6a459SMichael Ellerman sigill: 156714cf11afSPaul Mackerras if (reason & REASON_PRIVILEGED) 156814cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 156914cf11afSPaul Mackerras else 157014cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1571ba12eedeSLi Zhong 1572fd3f1e0fSNicholas Piggin } 1573fd3f1e0fSNicholas Piggin 15743a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(program_check_exception) 1575fd3f1e0fSNicholas Piggin { 1576fd3f1e0fSNicholas Piggin do_program_check(regs); 157714cf11afSPaul Mackerras } 157814cf11afSPaul Mackerras 1579bf593907SPaul Mackerras /* 1580bf593907SPaul Mackerras * This occurs when running in hypervisor mode on POWER6 or later 1581bf593907SPaul Mackerras * and an illegal instruction is encountered. 1582bf593907SPaul Mackerras */ 15833a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(emulation_assist_interrupt) 1584bf593907SPaul Mackerras { 158559dc5bfcSNicholas Piggin regs_set_return_msr(regs, regs->msr | REASON_ILLEGAL); 1586fd3f1e0fSNicholas Piggin do_program_check(regs); 1587bf593907SPaul Mackerras } 1588bf593907SPaul Mackerras 15893a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(alignment_exception) 159014cf11afSPaul Mackerras { 15914393c4f6SBenjamin Herrenschmidt int sig, code, fixed = 0; 15929409d2f9SJordan Niethe unsigned long reason; 159314cf11afSPaul Mackerras 1594e6f8a6c8SNicholas Piggin interrupt_cond_local_irq_enable(regs); 1595a3512b2dSBenjamin Herrenschmidt 15969409d2f9SJordan Niethe reason = get_reason(regs); 15979409d2f9SJordan Niethe if (reason & REASON_BOUNDARY) { 15989409d2f9SJordan Niethe sig = SIGBUS; 15999409d2f9SJordan Niethe code = BUS_ADRALN; 16009409d2f9SJordan Niethe goto bad; 16019409d2f9SJordan Niethe } 16029409d2f9SJordan Niethe 16036ce6c629SMichael Neuling if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1604540d4d34SNicholas Piggin return; 16056ce6c629SMichael Neuling 1606e9370ae1SPaul Mackerras /* we don't implement logging of alignment exceptions */ 1607e9370ae1SPaul Mackerras if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 160814cf11afSPaul Mackerras fixed = fix_alignment(regs); 160914cf11afSPaul Mackerras 161014cf11afSPaul Mackerras if (fixed == 1) { 16119409d2f9SJordan Niethe /* skip over emulated instruction */ 161259dc5bfcSNicholas Piggin regs_add_return_ip(regs, inst_length(reason)); 161314cf11afSPaul Mackerras emulate_single_step(regs); 1614540d4d34SNicholas Piggin return; 161514cf11afSPaul Mackerras } 161614cf11afSPaul Mackerras 161714cf11afSPaul Mackerras /* Operand address was bad */ 161814cf11afSPaul Mackerras if (fixed == -EFAULT) { 16194393c4f6SBenjamin Herrenschmidt sig = SIGSEGV; 16204393c4f6SBenjamin Herrenschmidt code = SEGV_ACCERR; 16214393c4f6SBenjamin Herrenschmidt } else { 16224393c4f6SBenjamin Herrenschmidt sig = SIGBUS; 16234393c4f6SBenjamin Herrenschmidt code = BUS_ADRALN; 162414cf11afSPaul Mackerras } 16259409d2f9SJordan Niethe bad: 16264393c4f6SBenjamin Herrenschmidt if (user_mode(regs)) 16274393c4f6SBenjamin Herrenschmidt _exception(sig, regs, code, regs->dar); 16284393c4f6SBenjamin Herrenschmidt else 16298458c628SNicholas Piggin bad_page_fault(regs, sig); 163014cf11afSPaul Mackerras } 163114cf11afSPaul Mackerras 16323a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(stack_overflow_exception) 16333978eb78SChristophe Leroy { 16343978eb78SChristophe Leroy die("Kernel stack overflow", regs, SIGSEGV); 16353978eb78SChristophe Leroy } 16363978eb78SChristophe Leroy 16373a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(kernel_fp_unavailable_exception) 1638dc1c1ca3SStephen Rothwell { 1639dc1c1ca3SStephen Rothwell printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1640dc1c1ca3SStephen Rothwell "%lx at %lx\n", regs->trap, regs->nip); 1641dc1c1ca3SStephen Rothwell die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1642dc1c1ca3SStephen Rothwell } 1643dc1c1ca3SStephen Rothwell 16443a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(altivec_unavailable_exception) 1645dc1c1ca3SStephen Rothwell { 1646dc1c1ca3SStephen Rothwell if (user_mode(regs)) { 1647dc1c1ca3SStephen Rothwell /* A user program has executed an altivec instruction, 1648dc1c1ca3SStephen Rothwell but this kernel doesn't support altivec. */ 1649dc1c1ca3SStephen Rothwell _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1650540d4d34SNicholas Piggin return; 1651dc1c1ca3SStephen Rothwell } 16526c4841c2SAnton Blanchard 1653dc1c1ca3SStephen Rothwell printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1654dc1c1ca3SStephen Rothwell "%lx at %lx\n", regs->trap, regs->nip); 1655dc1c1ca3SStephen Rothwell die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1656dc1c1ca3SStephen Rothwell } 1657dc1c1ca3SStephen Rothwell 16583a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(vsx_unavailable_exception) 1659ce48b210SMichael Neuling { 1660ce48b210SMichael Neuling if (user_mode(regs)) { 1661ce48b210SMichael Neuling /* A user program has executed an vsx instruction, 1662ce48b210SMichael Neuling but this kernel doesn't support vsx. */ 1663ce48b210SMichael Neuling _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1664ce48b210SMichael Neuling return; 1665ce48b210SMichael Neuling } 1666ce48b210SMichael Neuling 1667ce48b210SMichael Neuling printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1668ce48b210SMichael Neuling "%lx at %lx\n", regs->trap, regs->nip); 1669ce48b210SMichael Neuling die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1670ce48b210SMichael Neuling } 1671ce48b210SMichael Neuling 16722517617eSMichael Neuling #ifdef CONFIG_PPC64 1673172f7aaaSCyril Bur static void tm_unavailable(struct pt_regs *regs) 1674172f7aaaSCyril Bur { 16755d176f75SCyril Bur #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 16765d176f75SCyril Bur if (user_mode(regs)) { 16775d176f75SCyril Bur current->thread.load_tm++; 167859dc5bfcSNicholas Piggin regs_set_return_msr(regs, regs->msr | MSR_TM); 16795d176f75SCyril Bur tm_enable(); 16805d176f75SCyril Bur tm_restore_sprs(¤t->thread); 16815d176f75SCyril Bur return; 16825d176f75SCyril Bur } 16835d176f75SCyril Bur #endif 1684172f7aaaSCyril Bur pr_emerg("Unrecoverable TM Unavailable Exception " 1685172f7aaaSCyril Bur "%lx at %lx\n", regs->trap, regs->nip); 1686172f7aaaSCyril Bur die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1687172f7aaaSCyril Bur } 1688172f7aaaSCyril Bur 16893a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(facility_unavailable_exception) 1690d0c0c9a1SMichael Neuling { 1691021424a1SMichael Ellerman static char *facility_strings[] = { 16922517617eSMichael Neuling [FSCR_FP_LG] = "FPU", 16932517617eSMichael Neuling [FSCR_VECVSX_LG] = "VMX/VSX", 16942517617eSMichael Neuling [FSCR_DSCR_LG] = "DSCR", 16952517617eSMichael Neuling [FSCR_PM_LG] = "PMU SPRs", 16962517617eSMichael Neuling [FSCR_BHRB_LG] = "BHRB", 16972517617eSMichael Neuling [FSCR_TM_LG] = "TM", 16982517617eSMichael Neuling [FSCR_EBB_LG] = "EBB", 16992517617eSMichael Neuling [FSCR_TAR_LG] = "TAR", 1700794464f4SNicholas Piggin [FSCR_MSGP_LG] = "MSGP", 17019b7ff0c6SNicholas Piggin [FSCR_SCV_LG] = "SCV", 17022aa6195eSAlistair Popple [FSCR_PREFIX_LG] = "PREFIX", 1703021424a1SMichael Ellerman }; 17042517617eSMichael Neuling char *facility = "unknown"; 1705021424a1SMichael Ellerman u64 value; 1706c952c1c4SAnshuman Khandual u32 instword, rd; 17072517617eSMichael Neuling u8 status; 17082517617eSMichael Neuling bool hv; 1709021424a1SMichael Ellerman 17107153d4bfSXiongwei Song hv = (TRAP(regs) == INTERRUPT_H_FAC_UNAVAIL); 17112517617eSMichael Neuling if (hv) 1712b14b6260SMichael Ellerman value = mfspr(SPRN_HFSCR); 17132517617eSMichael Neuling else 17142517617eSMichael Neuling value = mfspr(SPRN_FSCR); 17152517617eSMichael Neuling 17162517617eSMichael Neuling status = value >> 56; 1717709b973cSAnshuman Khandual if ((hv || status >= 2) && 1718709b973cSAnshuman Khandual (status < ARRAY_SIZE(facility_strings)) && 1719709b973cSAnshuman Khandual facility_strings[status]) 1720709b973cSAnshuman Khandual facility = facility_strings[status]; 1721709b973cSAnshuman Khandual 1722709b973cSAnshuman Khandual /* We should not have taken this interrupt in kernel */ 1723709b973cSAnshuman Khandual if (!user_mode(regs)) { 1724709b973cSAnshuman Khandual pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1725709b973cSAnshuman Khandual facility, status, regs->nip); 1726709b973cSAnshuman Khandual die("Unexpected facility unavailable exception", regs, SIGABRT); 1727709b973cSAnshuman Khandual } 1728709b973cSAnshuman Khandual 1729e6f8a6c8SNicholas Piggin interrupt_cond_local_irq_enable(regs); 1730709b973cSAnshuman Khandual 17312517617eSMichael Neuling if (status == FSCR_DSCR_LG) { 1732c952c1c4SAnshuman Khandual /* 1733c952c1c4SAnshuman Khandual * User is accessing the DSCR register using the problem 1734c952c1c4SAnshuman Khandual * state only SPR number (0x03) either through a mfspr or 1735c952c1c4SAnshuman Khandual * a mtspr instruction. If it is a write attempt through 1736c952c1c4SAnshuman Khandual * a mtspr, then we set the inherit bit. This also allows 1737c952c1c4SAnshuman Khandual * the user to write or read the register directly in the 1738c952c1c4SAnshuman Khandual * future by setting via the FSCR DSCR bit. But in case it 1739c952c1c4SAnshuman Khandual * is a read DSCR attempt through a mfspr instruction, we 1740c952c1c4SAnshuman Khandual * just emulate the instruction instead. This code path will 1741c952c1c4SAnshuman Khandual * always emulate all the mfspr instructions till the user 1742c952c1c4SAnshuman Khandual * has attempted at least one mtspr instruction. This way it 1743c952c1c4SAnshuman Khandual * preserves the same behaviour when the user is accessing 1744c952c1c4SAnshuman Khandual * the DSCR through privilege level only SPR number (0x11) 1745c952c1c4SAnshuman Khandual * which is emulated through illegal instruction exception. 1746c952c1c4SAnshuman Khandual * We always leave HFSCR DSCR set. 17472517617eSMichael Neuling */ 1748c952c1c4SAnshuman Khandual if (get_user(instword, (u32 __user *)(regs->nip))) { 1749c952c1c4SAnshuman Khandual pr_err("Failed to fetch the user instruction\n"); 1750c952c1c4SAnshuman Khandual return; 1751c952c1c4SAnshuman Khandual } 1752c952c1c4SAnshuman Khandual 1753c952c1c4SAnshuman Khandual /* Write into DSCR (mtspr 0x03, RS) */ 1754c952c1c4SAnshuman Khandual if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1755c952c1c4SAnshuman Khandual == PPC_INST_MTSPR_DSCR_USER) { 1756c952c1c4SAnshuman Khandual rd = (instword >> 21) & 0x1f; 1757c952c1c4SAnshuman Khandual current->thread.dscr = regs->gpr[rd]; 17582517617eSMichael Neuling current->thread.dscr_inherit = 1; 1759b57bd2deSMichael Neuling current->thread.fscr |= FSCR_DSCR; 1760b57bd2deSMichael Neuling mtspr(SPRN_FSCR, current->thread.fscr); 1761c952c1c4SAnshuman Khandual } 1762c952c1c4SAnshuman Khandual 1763c952c1c4SAnshuman Khandual /* Read from DSCR (mfspr RT, 0x03) */ 1764c952c1c4SAnshuman Khandual if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1765c952c1c4SAnshuman Khandual == PPC_INST_MFSPR_DSCR_USER) { 1766c952c1c4SAnshuman Khandual if (emulate_instruction(regs)) { 1767c952c1c4SAnshuman Khandual pr_err("DSCR based mfspr emulation failed\n"); 1768c952c1c4SAnshuman Khandual return; 1769c952c1c4SAnshuman Khandual } 177059dc5bfcSNicholas Piggin regs_add_return_ip(regs, 4); 1771c952c1c4SAnshuman Khandual emulate_single_step(regs); 1772c952c1c4SAnshuman Khandual } 17732517617eSMichael Neuling return; 1774b14b6260SMichael Ellerman } 1775b14b6260SMichael Ellerman 1776172f7aaaSCyril Bur if (status == FSCR_TM_LG) { 1777172f7aaaSCyril Bur /* 1778172f7aaaSCyril Bur * If we're here then the hardware is TM aware because it 1779172f7aaaSCyril Bur * generated an exception with FSRM_TM set. 1780172f7aaaSCyril Bur * 1781172f7aaaSCyril Bur * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1782172f7aaaSCyril Bur * told us not to do TM, or the kernel is not built with TM 1783172f7aaaSCyril Bur * support. 1784172f7aaaSCyril Bur * 1785172f7aaaSCyril Bur * If both of those things are true, then userspace can spam the 1786172f7aaaSCyril Bur * console by triggering the printk() below just by continually 1787172f7aaaSCyril Bur * doing tbegin (or any TM instruction). So in that case just 1788172f7aaaSCyril Bur * send the process a SIGILL immediately. 1789172f7aaaSCyril Bur */ 1790172f7aaaSCyril Bur if (!cpu_has_feature(CPU_FTR_TM)) 1791172f7aaaSCyril Bur goto out; 1792172f7aaaSCyril Bur 1793172f7aaaSCyril Bur tm_unavailable(regs); 1794172f7aaaSCyril Bur return; 1795172f7aaaSCyril Bur } 1796172f7aaaSCyril Bur 179793c2ec0fSBalbir Singh pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 179893c2ec0fSBalbir Singh hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1799d0c0c9a1SMichael Neuling 1800172f7aaaSCyril Bur out: 1801d0c0c9a1SMichael Neuling _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1802d0c0c9a1SMichael Neuling } 18032517617eSMichael Neuling #endif 1804d0c0c9a1SMichael Neuling 1805f54db641SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1806f54db641SMichael Neuling 18073a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(fp_unavailable_tm) 1808f54db641SMichael Neuling { 1809f54db641SMichael Neuling /* Note: This does not handle any kind of FP laziness. */ 1810f54db641SMichael Neuling 1811f54db641SMichael Neuling TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1812f54db641SMichael Neuling regs->nip, regs->msr); 1813f54db641SMichael Neuling 1814f54db641SMichael Neuling /* We can only have got here if the task started using FP after 1815f54db641SMichael Neuling * beginning the transaction. So, the transactional regs are just a 1816f54db641SMichael Neuling * copy of the checkpointed ones. But, we still need to recheckpoint 1817f54db641SMichael Neuling * as we're enabling FP for the process; it will return, abort the 1818f54db641SMichael Neuling * transaction, and probably retry but now with FP enabled. So the 1819f54db641SMichael Neuling * checkpointed FP registers need to be loaded. 1820f54db641SMichael Neuling */ 1821d31626f7SPaul Mackerras tm_reclaim_current(TM_CAUSE_FAC_UNAV); 182296695563SBreno Leitao 182396695563SBreno Leitao /* 182496695563SBreno Leitao * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 182596695563SBreno Leitao * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 182696695563SBreno Leitao * 182796695563SBreno Leitao * At this point, ck{fp,vr}_state contains the exact values we want to 182896695563SBreno Leitao * recheckpoint. 182996695563SBreno Leitao */ 1830f54db641SMichael Neuling 1831f54db641SMichael Neuling /* Enable FP for the task: */ 1832a7771176SCyril Bur current->thread.load_fp = 1; 1833f54db641SMichael Neuling 183496695563SBreno Leitao /* 183596695563SBreno Leitao * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1836f54db641SMichael Neuling */ 1837eb5c3f1cSCyril Bur tm_recheckpoint(¤t->thread); 1838f54db641SMichael Neuling } 1839f54db641SMichael Neuling 18403a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(altivec_unavailable_tm) 1841f54db641SMichael Neuling { 1842f54db641SMichael Neuling /* See the comments in fp_unavailable_tm(). This function operates 1843f54db641SMichael Neuling * the same way. 1844f54db641SMichael Neuling */ 1845f54db641SMichael Neuling 1846f54db641SMichael Neuling TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1847f54db641SMichael Neuling "MSR=%lx\n", 1848f54db641SMichael Neuling regs->nip, regs->msr); 1849d31626f7SPaul Mackerras tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1850a7771176SCyril Bur current->thread.load_vec = 1; 1851eb5c3f1cSCyril Bur tm_recheckpoint(¤t->thread); 1852f54db641SMichael Neuling current->thread.used_vr = 1; 18533ac8ff1cSPaul Mackerras } 18543ac8ff1cSPaul Mackerras 18553a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(vsx_unavailable_tm) 1856f54db641SMichael Neuling { 1857f54db641SMichael Neuling /* See the comments in fp_unavailable_tm(). This works similarly, 1858f54db641SMichael Neuling * though we're loading both FP and VEC registers in here. 1859f54db641SMichael Neuling * 1860f54db641SMichael Neuling * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1861f54db641SMichael Neuling * regs. Either way, set MSR_VSX. 1862f54db641SMichael Neuling */ 1863f54db641SMichael Neuling 1864f54db641SMichael Neuling TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1865f54db641SMichael Neuling "MSR=%lx\n", 1866f54db641SMichael Neuling regs->nip, regs->msr); 1867f54db641SMichael Neuling 18683ac8ff1cSPaul Mackerras current->thread.used_vsr = 1; 18693ac8ff1cSPaul Mackerras 1870f54db641SMichael Neuling /* This reclaims FP and/or VR regs if they're already enabled */ 1871d31626f7SPaul Mackerras tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1872f54db641SMichael Neuling 1873a7771176SCyril Bur current->thread.load_vec = 1; 1874a7771176SCyril Bur current->thread.load_fp = 1; 18753ac8ff1cSPaul Mackerras 1876eb5c3f1cSCyril Bur tm_recheckpoint(¤t->thread); 1877f54db641SMichael Neuling } 1878f54db641SMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1879f54db641SMichael Neuling 18803a96570fSNicholas Piggin #ifdef CONFIG_PPC64 18813a96570fSNicholas Piggin DECLARE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi); 18823a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi) 1883dc1c1ca3SStephen Rothwell { 188469111bacSChristoph Lameter __this_cpu_inc(irq_stat.pmu_irqs); 188589713ed1SAnton Blanchard 1886dc1c1ca3SStephen Rothwell perf_irq(regs); 1887156b5371SNicholas Piggin 18883a96570fSNicholas Piggin return 0; 18893a96570fSNicholas Piggin } 18903a96570fSNicholas Piggin #endif 18913a96570fSNicholas Piggin 18923a96570fSNicholas Piggin DECLARE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async); 18933a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async) 1894156b5371SNicholas Piggin { 1895156b5371SNicholas Piggin __this_cpu_inc(irq_stat.pmu_irqs); 1896156b5371SNicholas Piggin 1897156b5371SNicholas Piggin perf_irq(regs); 1898156b5371SNicholas Piggin } 1899156b5371SNicholas Piggin 19003a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exception) 1901156b5371SNicholas Piggin { 1902156b5371SNicholas Piggin /* 1903156b5371SNicholas Piggin * On 64-bit, if perf interrupts hit in a local_irq_disable 1904156b5371SNicholas Piggin * (soft-masked) region, we consider them as NMIs. This is required to 1905156b5371SNicholas Piggin * prevent hash faults on user addresses when reading callchains (and 1906156b5371SNicholas Piggin * looks better from an irq tracing perspective). 1907156b5371SNicholas Piggin */ 1908156b5371SNicholas Piggin if (IS_ENABLED(CONFIG_PPC64) && unlikely(arch_irq_disabled_regs(regs))) 1909156b5371SNicholas Piggin performance_monitor_exception_nmi(regs); 1910156b5371SNicholas Piggin else 1911156b5371SNicholas Piggin performance_monitor_exception_async(regs); 19123a96570fSNicholas Piggin 19133a96570fSNicholas Piggin return 0; 1914dc1c1ca3SStephen Rothwell } 1915dc1c1ca3SStephen Rothwell 1916172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 19173bffb652SDave Kleikamp static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 19183bffb652SDave Kleikamp { 19193bffb652SDave Kleikamp int changed = 0; 19203bffb652SDave Kleikamp /* 19213bffb652SDave Kleikamp * Determine the cause of the debug event, clear the 19223bffb652SDave Kleikamp * event flags and send a trap to the handler. Torez 19233bffb652SDave Kleikamp */ 19243bffb652SDave Kleikamp if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 19253bffb652SDave Kleikamp dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 19263bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 192751ae8d4aSBharat Bhushan current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 19283bffb652SDave Kleikamp #endif 192947355040SEric W. Biederman do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 19303bffb652SDave Kleikamp 5); 19313bffb652SDave Kleikamp changed |= 0x01; 19323bffb652SDave Kleikamp } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 19333bffb652SDave Kleikamp dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 193447355040SEric W. Biederman do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 19353bffb652SDave Kleikamp 6); 19363bffb652SDave Kleikamp changed |= 0x01; 19373bffb652SDave Kleikamp } else if (debug_status & DBSR_IAC1) { 193851ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 19393bffb652SDave Kleikamp dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 194047355040SEric W. Biederman do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 19413bffb652SDave Kleikamp 1); 19423bffb652SDave Kleikamp changed |= 0x01; 19433bffb652SDave Kleikamp } else if (debug_status & DBSR_IAC2) { 194451ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 194547355040SEric W. Biederman do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 19463bffb652SDave Kleikamp 2); 19473bffb652SDave Kleikamp changed |= 0x01; 19483bffb652SDave Kleikamp } else if (debug_status & DBSR_IAC3) { 194951ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 19503bffb652SDave Kleikamp dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 195147355040SEric W. Biederman do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 19523bffb652SDave Kleikamp 3); 19533bffb652SDave Kleikamp changed |= 0x01; 19543bffb652SDave Kleikamp } else if (debug_status & DBSR_IAC4) { 195551ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 195647355040SEric W. Biederman do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 19573bffb652SDave Kleikamp 4); 19583bffb652SDave Kleikamp changed |= 0x01; 19593bffb652SDave Kleikamp } 19603bffb652SDave Kleikamp /* 19613bffb652SDave Kleikamp * At the point this routine was called, the MSR(DE) was turned off. 19623bffb652SDave Kleikamp * Check all other debug flags and see if that bit needs to be turned 19633bffb652SDave Kleikamp * back on or not. 19643bffb652SDave Kleikamp */ 196551ae8d4aSBharat Bhushan if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 196651ae8d4aSBharat Bhushan current->thread.debug.dbcr1)) 196759dc5bfcSNicholas Piggin regs_set_return_msr(regs, regs->msr | MSR_DE); 19683bffb652SDave Kleikamp else 19693bffb652SDave Kleikamp /* Make sure the IDM flag is off */ 197051ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IDM; 19713bffb652SDave Kleikamp 19723bffb652SDave Kleikamp if (changed & 0x01) 197351ae8d4aSBharat Bhushan mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 19743bffb652SDave Kleikamp } 197514cf11afSPaul Mackerras 19763a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(DebugException) 197714cf11afSPaul Mackerras { 1978755d6641SNicholas Piggin unsigned long debug_status = regs->dsisr; 1979755d6641SNicholas Piggin 198051ae8d4aSBharat Bhushan current->thread.debug.dbsr = debug_status; 19813bffb652SDave Kleikamp 1982ec097c84SRoland McGrath /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1983ec097c84SRoland McGrath * on server, it stops on the target of the branch. In order to simulate 1984ec097c84SRoland McGrath * the server behaviour, we thus restart right away with a single step 1985ec097c84SRoland McGrath * instead of stopping here when hitting a BT 1986ec097c84SRoland McGrath */ 1987ec097c84SRoland McGrath if (debug_status & DBSR_BT) { 198859dc5bfcSNicholas Piggin regs_set_return_msr(regs, regs->msr & ~MSR_DE); 1989ec097c84SRoland McGrath 1990ec097c84SRoland McGrath /* Disable BT */ 1991ec097c84SRoland McGrath mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1992ec097c84SRoland McGrath /* Clear the BT event */ 1993ec097c84SRoland McGrath mtspr(SPRN_DBSR, DBSR_BT); 1994ec097c84SRoland McGrath 1995ec097c84SRoland McGrath /* Do the single step trick only when coming from userspace */ 1996ec097c84SRoland McGrath if (user_mode(regs)) { 199751ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_BT; 199851ae8d4aSBharat Bhushan current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 199959dc5bfcSNicholas Piggin regs_set_return_msr(regs, regs->msr | MSR_DE); 2000ec097c84SRoland McGrath return; 2001ec097c84SRoland McGrath } 2002ec097c84SRoland McGrath 20036cc89badSNaveen N. Rao if (kprobe_post_handler(regs)) 20046cc89badSNaveen N. Rao return; 20056cc89badSNaveen N. Rao 2006ec097c84SRoland McGrath if (notify_die(DIE_SSTEP, "block_step", regs, 5, 2007ec097c84SRoland McGrath 5, SIGTRAP) == NOTIFY_STOP) { 2008ec097c84SRoland McGrath return; 2009ec097c84SRoland McGrath } 2010ec097c84SRoland McGrath if (debugger_sstep(regs)) 2011ec097c84SRoland McGrath return; 2012ec097c84SRoland McGrath } else if (debug_status & DBSR_IC) { /* Instruction complete */ 201359dc5bfcSNicholas Piggin regs_set_return_msr(regs, regs->msr & ~MSR_DE); 2014f8279621SKumar Gala 201514cf11afSPaul Mackerras /* Disable instruction completion */ 201614cf11afSPaul Mackerras mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 201714cf11afSPaul Mackerras /* Clear the instruction completion event */ 201814cf11afSPaul Mackerras mtspr(SPRN_DBSR, DBSR_IC); 2019f8279621SKumar Gala 20206cc89badSNaveen N. Rao if (kprobe_post_handler(regs)) 20216cc89badSNaveen N. Rao return; 20226cc89badSNaveen N. Rao 2023f8279621SKumar Gala if (notify_die(DIE_SSTEP, "single_step", regs, 5, 2024f8279621SKumar Gala 5, SIGTRAP) == NOTIFY_STOP) { 202514cf11afSPaul Mackerras return; 202614cf11afSPaul Mackerras } 2027f8279621SKumar Gala 2028f8279621SKumar Gala if (debugger_sstep(regs)) 2029f8279621SKumar Gala return; 2030f8279621SKumar Gala 20313bffb652SDave Kleikamp if (user_mode(regs)) { 203251ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IC; 203351ae8d4aSBharat Bhushan if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 203451ae8d4aSBharat Bhushan current->thread.debug.dbcr1)) 203559dc5bfcSNicholas Piggin regs_set_return_msr(regs, regs->msr | MSR_DE); 20363bffb652SDave Kleikamp else 20373bffb652SDave Kleikamp /* Make sure the IDM bit is off */ 203851ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IDM; 20393bffb652SDave Kleikamp } 2040f8279621SKumar Gala 2041f8279621SKumar Gala _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 20423bffb652SDave Kleikamp } else 20433bffb652SDave Kleikamp handle_debug(regs, debug_status); 204414cf11afSPaul Mackerras } 2045172ae2e7SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 204614cf11afSPaul Mackerras 204714cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 20483a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(altivec_assist_exception) 204914cf11afSPaul Mackerras { 205014cf11afSPaul Mackerras int err; 205114cf11afSPaul Mackerras 205214cf11afSPaul Mackerras if (!user_mode(regs)) { 205314cf11afSPaul Mackerras printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 205414cf11afSPaul Mackerras " at %lx\n", regs->nip); 20558dad3f92SPaul Mackerras die("Kernel VMX/Altivec assist exception", regs, SIGILL); 205614cf11afSPaul Mackerras } 205714cf11afSPaul Mackerras 2058dc1c1ca3SStephen Rothwell flush_altivec_to_thread(current); 2059dc1c1ca3SStephen Rothwell 2060eecff81dSAnton Blanchard PPC_WARN_EMULATED(altivec, regs); 206114cf11afSPaul Mackerras err = emulate_altivec(regs); 206214cf11afSPaul Mackerras if (err == 0) { 206359dc5bfcSNicholas Piggin regs_add_return_ip(regs, 4); /* skip emulated instruction */ 206414cf11afSPaul Mackerras emulate_single_step(regs); 206514cf11afSPaul Mackerras return; 206614cf11afSPaul Mackerras } 206714cf11afSPaul Mackerras 206814cf11afSPaul Mackerras if (err == -EFAULT) { 206914cf11afSPaul Mackerras /* got an error reading the instruction */ 207014cf11afSPaul Mackerras _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 207114cf11afSPaul Mackerras } else { 207214cf11afSPaul Mackerras /* didn't recognize the instruction */ 207314cf11afSPaul Mackerras /* XXX quick hack for now: set the non-Java bit in the VSCR */ 207476462232SChristian Dietrich printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 207514cf11afSPaul Mackerras "in %s at %lx\n", current->comm, regs->nip); 2076de79f7b9SPaul Mackerras current->thread.vr_state.vscr.u[3] |= 0x10000; 207714cf11afSPaul Mackerras } 207814cf11afSPaul Mackerras } 207914cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 208014cf11afSPaul Mackerras 208114cf11afSPaul Mackerras #ifdef CONFIG_FSL_BOOKE 20823a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(CacheLockingException) 208314cf11afSPaul Mackerras { 2084b4ced803SNicholas Piggin unsigned long error_code = regs->dsisr; 2085b4ced803SNicholas Piggin 208614cf11afSPaul Mackerras /* We treat cache locking instructions from the user 208714cf11afSPaul Mackerras * as priv ops, in the future we could try to do 208814cf11afSPaul Mackerras * something smarter 208914cf11afSPaul Mackerras */ 209014cf11afSPaul Mackerras if (error_code & (ESR_DLK|ESR_ILK)) 209114cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 209214cf11afSPaul Mackerras return; 209314cf11afSPaul Mackerras } 209414cf11afSPaul Mackerras #endif /* CONFIG_FSL_BOOKE */ 209514cf11afSPaul Mackerras 209614cf11afSPaul Mackerras #ifdef CONFIG_SPE 20973a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException) 209814cf11afSPaul Mackerras { 20996a800f36SLiu Yu extern int do_spe_mathemu(struct pt_regs *regs); 210014cf11afSPaul Mackerras unsigned long spefscr; 210114cf11afSPaul Mackerras int fpexc_mode; 2102aeb1c0f6SEric W. Biederman int code = FPE_FLTUNK; 21036a800f36SLiu Yu int err; 21046a800f36SLiu Yu 2105e6f8a6c8SNicholas Piggin interrupt_cond_local_irq_enable(regs); 2106ef429124SChristophe Leroy 2107685659eeSyu liu flush_spe_to_thread(current); 210814cf11afSPaul Mackerras 210914cf11afSPaul Mackerras spefscr = current->thread.spefscr; 211014cf11afSPaul Mackerras fpexc_mode = current->thread.fpexc_mode; 211114cf11afSPaul Mackerras 211214cf11afSPaul Mackerras if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 211314cf11afSPaul Mackerras code = FPE_FLTOVF; 211414cf11afSPaul Mackerras } 211514cf11afSPaul Mackerras else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 211614cf11afSPaul Mackerras code = FPE_FLTUND; 211714cf11afSPaul Mackerras } 211814cf11afSPaul Mackerras else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 211914cf11afSPaul Mackerras code = FPE_FLTDIV; 212014cf11afSPaul Mackerras else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 212114cf11afSPaul Mackerras code = FPE_FLTINV; 212214cf11afSPaul Mackerras } 212314cf11afSPaul Mackerras else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 212414cf11afSPaul Mackerras code = FPE_FLTRES; 212514cf11afSPaul Mackerras 21266a800f36SLiu Yu err = do_spe_mathemu(regs); 21276a800f36SLiu Yu if (err == 0) { 212859dc5bfcSNicholas Piggin regs_add_return_ip(regs, 4); /* skip emulated instruction */ 21296a800f36SLiu Yu emulate_single_step(regs); 213014cf11afSPaul Mackerras return; 213114cf11afSPaul Mackerras } 21326a800f36SLiu Yu 21336a800f36SLiu Yu if (err == -EFAULT) { 21346a800f36SLiu Yu /* got an error reading the instruction */ 21356a800f36SLiu Yu _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 21366a800f36SLiu Yu } else if (err == -EINVAL) { 21376a800f36SLiu Yu /* didn't recognize the instruction */ 21386a800f36SLiu Yu printk(KERN_ERR "unrecognized spe instruction " 21396a800f36SLiu Yu "in %s at %lx\n", current->comm, regs->nip); 21406a800f36SLiu Yu } else { 21416a800f36SLiu Yu _exception(SIGFPE, regs, code, regs->nip); 21426a800f36SLiu Yu } 21436a800f36SLiu Yu 21446a800f36SLiu Yu return; 21456a800f36SLiu Yu } 21466a800f36SLiu Yu 21473a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException) 21486a800f36SLiu Yu { 21496a800f36SLiu Yu extern int speround_handler(struct pt_regs *regs); 21506a800f36SLiu Yu int err; 21516a800f36SLiu Yu 2152e6f8a6c8SNicholas Piggin interrupt_cond_local_irq_enable(regs); 2153ef429124SChristophe Leroy 21546a800f36SLiu Yu preempt_disable(); 21556a800f36SLiu Yu if (regs->msr & MSR_SPE) 21566a800f36SLiu Yu giveup_spe(current); 21576a800f36SLiu Yu preempt_enable(); 21586a800f36SLiu Yu 215959dc5bfcSNicholas Piggin regs_add_return_ip(regs, -4); 21606a800f36SLiu Yu err = speround_handler(regs); 21616a800f36SLiu Yu if (err == 0) { 216259dc5bfcSNicholas Piggin regs_add_return_ip(regs, 4); /* skip emulated instruction */ 21636a800f36SLiu Yu emulate_single_step(regs); 21646a800f36SLiu Yu return; 21656a800f36SLiu Yu } 21666a800f36SLiu Yu 21676a800f36SLiu Yu if (err == -EFAULT) { 21686a800f36SLiu Yu /* got an error reading the instruction */ 21696a800f36SLiu Yu _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 21706a800f36SLiu Yu } else if (err == -EINVAL) { 21716a800f36SLiu Yu /* didn't recognize the instruction */ 21726a800f36SLiu Yu printk(KERN_ERR "unrecognized spe instruction " 21736a800f36SLiu Yu "in %s at %lx\n", current->comm, regs->nip); 21746a800f36SLiu Yu } else { 2175aeb1c0f6SEric W. Biederman _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 21766a800f36SLiu Yu return; 21776a800f36SLiu Yu } 21786a800f36SLiu Yu } 217914cf11afSPaul Mackerras #endif 218014cf11afSPaul Mackerras 2181dc1c1ca3SStephen Rothwell /* 2182dc1c1ca3SStephen Rothwell * We enter here if we get an unrecoverable exception, that is, one 2183dc1c1ca3SStephen Rothwell * that happened at a point where the RI (recoverable interrupt) bit 2184dc1c1ca3SStephen Rothwell * in the MSR is 0. This indicates that SRR0/1 are live, and that 2185dc1c1ca3SStephen Rothwell * we therefore lost state by taking this exception. 2186dc1c1ca3SStephen Rothwell */ 2187a58cbed6SChristophe Leroy void __noreturn unrecoverable_exception(struct pt_regs *regs) 2188dc1c1ca3SStephen Rothwell { 218951423a9cSChristophe Leroy pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 219051423a9cSChristophe Leroy regs->trap, regs->nip, regs->msr); 2191dc1c1ca3SStephen Rothwell die("Unrecoverable exception", regs, SIGABRT); 2192a58cbed6SChristophe Leroy /* die() should not return */ 2193a58cbed6SChristophe Leroy for (;;) 2194a58cbed6SChristophe Leroy ; 2195dc1c1ca3SStephen Rothwell } 2196dc1c1ca3SStephen Rothwell 21971e18c17aSJason Gunthorpe #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 219814cf11afSPaul Mackerras /* 219914cf11afSPaul Mackerras * Default handler for a Watchdog exception, 220014cf11afSPaul Mackerras * spins until a reboot occurs 220114cf11afSPaul Mackerras */ 220214cf11afSPaul Mackerras void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 220314cf11afSPaul Mackerras { 220414cf11afSPaul Mackerras /* Generic WatchdogHandler, implement your own */ 220514cf11afSPaul Mackerras mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 220614cf11afSPaul Mackerras return; 220714cf11afSPaul Mackerras } 220814cf11afSPaul Mackerras 22093db8aa10SNicholas Piggin DEFINE_INTERRUPT_HANDLER_NMI(WatchdogException) 221014cf11afSPaul Mackerras { 221114cf11afSPaul Mackerras printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 221214cf11afSPaul Mackerras WatchdogHandler(regs); 22133db8aa10SNicholas Piggin return 0; 221414cf11afSPaul Mackerras } 221514cf11afSPaul Mackerras #endif 2216dc1c1ca3SStephen Rothwell 2217dc1c1ca3SStephen Rothwell /* 2218dc1c1ca3SStephen Rothwell * We enter here if we discover during exception entry that we are 2219dc1c1ca3SStephen Rothwell * running in supervisor mode with a userspace value in the stack pointer. 2220dc1c1ca3SStephen Rothwell */ 22213a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(kernel_bad_stack) 2222dc1c1ca3SStephen Rothwell { 2223dc1c1ca3SStephen Rothwell printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2224dc1c1ca3SStephen Rothwell regs->gpr[1], regs->nip); 2225dc1c1ca3SStephen Rothwell die("Bad kernel stack pointer", regs, SIGABRT); 2226dc1c1ca3SStephen Rothwell } 222714cf11afSPaul Mackerras 222880947e7cSGeert Uytterhoeven #ifdef CONFIG_PPC_EMULATED_STATS 222980947e7cSGeert Uytterhoeven 223080947e7cSGeert Uytterhoeven #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 223180947e7cSGeert Uytterhoeven 223280947e7cSGeert Uytterhoeven struct ppc_emulated ppc_emulated = { 223380947e7cSGeert Uytterhoeven #ifdef CONFIG_ALTIVEC 223480947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(altivec), 223580947e7cSGeert Uytterhoeven #endif 223680947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(dcba), 223780947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(dcbz), 223880947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(fp_pair), 223980947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(isel), 224080947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(mcrxr), 224180947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(mfpvr), 224280947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(multiple), 224380947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(popcntb), 224480947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(spe), 224580947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(string), 2246a3821b2aSScott Wood WARN_EMULATED_SETUP(sync), 224780947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(unaligned), 224880947e7cSGeert Uytterhoeven #ifdef CONFIG_MATH_EMULATION 224980947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(math), 225080947e7cSGeert Uytterhoeven #endif 225180947e7cSGeert Uytterhoeven #ifdef CONFIG_VSX 225280947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(vsx), 225380947e7cSGeert Uytterhoeven #endif 2254efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64 2255efcac658SAlexey Kardashevskiy WARN_EMULATED_SETUP(mfdscr), 2256efcac658SAlexey Kardashevskiy WARN_EMULATED_SETUP(mtdscr), 2257f83319d7SAnton Blanchard WARN_EMULATED_SETUP(lq_stq), 22585080332cSMichael Neuling WARN_EMULATED_SETUP(lxvw4x), 22595080332cSMichael Neuling WARN_EMULATED_SETUP(lxvh8x), 22605080332cSMichael Neuling WARN_EMULATED_SETUP(lxvd2x), 22615080332cSMichael Neuling WARN_EMULATED_SETUP(lxvb16x), 2262efcac658SAlexey Kardashevskiy #endif 226380947e7cSGeert Uytterhoeven }; 226480947e7cSGeert Uytterhoeven 226580947e7cSGeert Uytterhoeven u32 ppc_warn_emulated; 226680947e7cSGeert Uytterhoeven 226780947e7cSGeert Uytterhoeven void ppc_warn_emulated_print(const char *type) 226880947e7cSGeert Uytterhoeven { 226976462232SChristian Dietrich pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 227080947e7cSGeert Uytterhoeven type); 227180947e7cSGeert Uytterhoeven } 227280947e7cSGeert Uytterhoeven 227380947e7cSGeert Uytterhoeven static int __init ppc_warn_emulated_init(void) 227480947e7cSGeert Uytterhoeven { 2275860286cfSGreg Kroah-Hartman struct dentry *dir; 227680947e7cSGeert Uytterhoeven unsigned int i; 227780947e7cSGeert Uytterhoeven struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 227880947e7cSGeert Uytterhoeven 227980947e7cSGeert Uytterhoeven dir = debugfs_create_dir("emulated_instructions", 2280dbf77fedSAneesh Kumar K.V arch_debugfs_dir); 228180947e7cSGeert Uytterhoeven 2282860286cfSGreg Kroah-Hartman debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated); 228380947e7cSGeert Uytterhoeven 2284860286cfSGreg Kroah-Hartman for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) 2285860286cfSGreg Kroah-Hartman debugfs_create_u32(entries[i].name, 0644, dir, 228680947e7cSGeert Uytterhoeven (u32 *)&entries[i].val.counter); 228780947e7cSGeert Uytterhoeven 228880947e7cSGeert Uytterhoeven return 0; 228980947e7cSGeert Uytterhoeven } 229080947e7cSGeert Uytterhoeven 229180947e7cSGeert Uytterhoeven device_initcall(ppc_warn_emulated_init); 229280947e7cSGeert Uytterhoeven 229380947e7cSGeert Uytterhoeven #endif /* CONFIG_PPC_EMULATED_STATS */ 2294