114cf11afSPaul Mackerras /* 214cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3fe04b112SScott Wood * Copyright 2007-2010 Freescale Semiconductor, Inc. 414cf11afSPaul Mackerras * 514cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 614cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 714cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 814cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 914cf11afSPaul Mackerras * 1014cf11afSPaul Mackerras * Modified by Cort Dougan (cort@cs.nmt.edu) 1114cf11afSPaul Mackerras * and Paul Mackerras (paulus@samba.org) 1214cf11afSPaul Mackerras */ 1314cf11afSPaul Mackerras 1414cf11afSPaul Mackerras /* 1514cf11afSPaul Mackerras * This file handles the architecture-dependent parts of hardware exceptions 1614cf11afSPaul Mackerras */ 1714cf11afSPaul Mackerras 1814cf11afSPaul Mackerras #include <linux/errno.h> 1914cf11afSPaul Mackerras #include <linux/sched.h> 20b17b0153SIngo Molnar #include <linux/sched/debug.h> 2114cf11afSPaul Mackerras #include <linux/kernel.h> 2214cf11afSPaul Mackerras #include <linux/mm.h> 2314cf11afSPaul Mackerras #include <linux/stddef.h> 2414cf11afSPaul Mackerras #include <linux/unistd.h> 258dad3f92SPaul Mackerras #include <linux/ptrace.h> 2614cf11afSPaul Mackerras #include <linux/user.h> 2714cf11afSPaul Mackerras #include <linux/interrupt.h> 2814cf11afSPaul Mackerras #include <linux/init.h> 298a39b05fSPaul Gortmaker #include <linux/extable.h> 308a39b05fSPaul Gortmaker #include <linux/module.h> /* print_modules */ 318dad3f92SPaul Mackerras #include <linux/prctl.h> 3214cf11afSPaul Mackerras #include <linux/delay.h> 3314cf11afSPaul Mackerras #include <linux/kprobes.h> 34cc532915SMichael Ellerman #include <linux/kexec.h> 355474c120SMichael Hanselmann #include <linux/backlight.h> 3673c9ceabSJeremy Fitzhardinge #include <linux/bug.h> 371eeb66a1SChristoph Hellwig #include <linux/kdebug.h> 3876462232SChristian Dietrich #include <linux/ratelimit.h> 39ba12eedeSLi Zhong #include <linux/context_tracking.h> 4014cf11afSPaul Mackerras 4180947e7cSGeert Uytterhoeven #include <asm/emulated_ops.h> 4214cf11afSPaul Mackerras #include <asm/pgtable.h> 437c0f6ba6SLinus Torvalds #include <linux/uaccess.h> 447644d581SMichael Ellerman #include <asm/debugfs.h> 4514cf11afSPaul Mackerras #include <asm/io.h> 4686417780SPaul Mackerras #include <asm/machdep.h> 4786417780SPaul Mackerras #include <asm/rtas.h> 48f7f6f4feSDavid Gibson #include <asm/pmc.h> 4914cf11afSPaul Mackerras #include <asm/reg.h> 5014cf11afSPaul Mackerras #ifdef CONFIG_PMAC_BACKLIGHT 5114cf11afSPaul Mackerras #include <asm/backlight.h> 5214cf11afSPaul Mackerras #endif 53dc1c1ca3SStephen Rothwell #ifdef CONFIG_PPC64 5486417780SPaul Mackerras #include <asm/firmware.h> 55dc1c1ca3SStephen Rothwell #include <asm/processor.h> 566ce6c629SMichael Neuling #include <asm/tm.h> 57dc1c1ca3SStephen Rothwell #endif 58c0ce7d08SDavid Wilder #include <asm/kexec.h> 5916c57b36SKumar Gala #include <asm/ppc-opcode.h> 60cce1f106SShaohui Xie #include <asm/rio.h> 61ebaeb5aeSMahesh Salgaonkar #include <asm/fadump.h> 62ae3a197eSDavid Howells #include <asm/switch_to.h> 63f54db641SMichael Neuling #include <asm/tm.h> 64ae3a197eSDavid Howells #include <asm/debug.h> 6542f5b4caSDaniel Axtens #include <asm/asm-prototypes.h> 66fd7bacbcSMahesh Salgaonkar #include <asm/hmi.h> 674e0e3435SHongtao Jia #include <sysdev/fsl_pci.h> 686cc89badSNaveen N. Rao #include <asm/kprobes.h> 69dc1c1ca3SStephen Rothwell 70da665885SThiago Jung Bauermann #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 715be3492fSAnton Blanchard int (*__debugger)(struct pt_regs *regs) __read_mostly; 725be3492fSAnton Blanchard int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 735be3492fSAnton Blanchard int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 745be3492fSAnton Blanchard int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 755be3492fSAnton Blanchard int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 769422de3eSMichael Neuling int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 775be3492fSAnton Blanchard int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 7814cf11afSPaul Mackerras 7914cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger); 8014cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_ipi); 8114cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_bpt); 8214cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_sstep); 8314cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_iabr_match); 849422de3eSMichael Neuling EXPORT_SYMBOL(__debugger_break_match); 8514cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_fault_handler); 8614cf11afSPaul Mackerras #endif 8714cf11afSPaul Mackerras 888b3c34cfSMichael Neuling /* Transactional Memory trap debug */ 898b3c34cfSMichael Neuling #ifdef TM_DEBUG_SW 908b3c34cfSMichael Neuling #define TM_DEBUG(x...) printk(KERN_INFO x) 918b3c34cfSMichael Neuling #else 928b3c34cfSMichael Neuling #define TM_DEBUG(x...) do { } while(0) 938b3c34cfSMichael Neuling #endif 948b3c34cfSMichael Neuling 9514cf11afSPaul Mackerras /* 9614cf11afSPaul Mackerras * Trap & Exception support 9714cf11afSPaul Mackerras */ 9814cf11afSPaul Mackerras 996031d9d9Santon@samba.org #ifdef CONFIG_PMAC_BACKLIGHT 1006031d9d9Santon@samba.org static void pmac_backlight_unblank(void) 1016031d9d9Santon@samba.org { 1026031d9d9Santon@samba.org mutex_lock(&pmac_backlight_mutex); 1036031d9d9Santon@samba.org if (pmac_backlight) { 1046031d9d9Santon@samba.org struct backlight_properties *props; 1056031d9d9Santon@samba.org 1066031d9d9Santon@samba.org props = &pmac_backlight->props; 1076031d9d9Santon@samba.org props->brightness = props->max_brightness; 1086031d9d9Santon@samba.org props->power = FB_BLANK_UNBLANK; 1096031d9d9Santon@samba.org backlight_update_status(pmac_backlight); 1106031d9d9Santon@samba.org } 1116031d9d9Santon@samba.org mutex_unlock(&pmac_backlight_mutex); 1126031d9d9Santon@samba.org } 1136031d9d9Santon@samba.org #else 1146031d9d9Santon@samba.org static inline void pmac_backlight_unblank(void) { } 1156031d9d9Santon@samba.org #endif 1166031d9d9Santon@samba.org 117760ca4dcSAnton Blanchard static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 118760ca4dcSAnton Blanchard static int die_owner = -1; 119760ca4dcSAnton Blanchard static unsigned int die_nest_count; 120c0ce7d08SDavid Wilder static int die_counter; 121760ca4dcSAnton Blanchard 12203465f89SNicholas Piggin static unsigned long oops_begin(struct pt_regs *regs) 123760ca4dcSAnton Blanchard { 124760ca4dcSAnton Blanchard int cpu; 12534c2a14fSanton@samba.org unsigned long flags; 12614cf11afSPaul Mackerras 127293e4688Santon@samba.org oops_enter(); 128293e4688Santon@samba.org 129760ca4dcSAnton Blanchard /* racy, but better than risking deadlock. */ 130760ca4dcSAnton Blanchard raw_local_irq_save(flags); 131760ca4dcSAnton Blanchard cpu = smp_processor_id(); 132760ca4dcSAnton Blanchard if (!arch_spin_trylock(&die_lock)) { 133760ca4dcSAnton Blanchard if (cpu == die_owner) 134760ca4dcSAnton Blanchard /* nested oops. should stop eventually */; 135760ca4dcSAnton Blanchard else 136760ca4dcSAnton Blanchard arch_spin_lock(&die_lock); 137760ca4dcSAnton Blanchard } 138760ca4dcSAnton Blanchard die_nest_count++; 139760ca4dcSAnton Blanchard die_owner = cpu; 14014cf11afSPaul Mackerras console_verbose(); 14114cf11afSPaul Mackerras bust_spinlocks(1); 1426031d9d9Santon@samba.org if (machine_is(powermac)) 1436031d9d9Santon@samba.org pmac_backlight_unblank(); 144760ca4dcSAnton Blanchard return flags; 14534c2a14fSanton@samba.org } 14603465f89SNicholas Piggin NOKPROBE_SYMBOL(oops_begin); 1475474c120SMichael Hanselmann 14803465f89SNicholas Piggin static void oops_end(unsigned long flags, struct pt_regs *regs, 149760ca4dcSAnton Blanchard int signr) 150760ca4dcSAnton Blanchard { 15114cf11afSPaul Mackerras bust_spinlocks(0); 152373d4d09SRusty Russell add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 153760ca4dcSAnton Blanchard die_nest_count--; 15458154c8cSAnton Blanchard oops_exit(); 15558154c8cSAnton Blanchard printk("\n"); 1567458e8b2SNicholas Piggin if (!die_nest_count) { 157760ca4dcSAnton Blanchard /* Nest count reaches zero, release the lock. */ 1587458e8b2SNicholas Piggin die_owner = -1; 159760ca4dcSAnton Blanchard arch_spin_unlock(&die_lock); 1607458e8b2SNicholas Piggin } 161760ca4dcSAnton Blanchard raw_local_irq_restore(flags); 162cc532915SMichael Ellerman 163ebaeb5aeSMahesh Salgaonkar crash_fadump(regs, "die oops"); 164ebaeb5aeSMahesh Salgaonkar 165*4388c9b3SNicholas Piggin if (kexec_should_crash(current)) 166cc532915SMichael Ellerman crash_kexec(regs); 1679b00ac06SAnton Blanchard 168760ca4dcSAnton Blanchard if (!signr) 169760ca4dcSAnton Blanchard return; 170760ca4dcSAnton Blanchard 17158154c8cSAnton Blanchard /* 17258154c8cSAnton Blanchard * While our oops output is serialised by a spinlock, output 17358154c8cSAnton Blanchard * from panic() called below can race and corrupt it. If we 17458154c8cSAnton Blanchard * know we are going to panic, delay for 1 second so we have a 17558154c8cSAnton Blanchard * chance to get clean backtraces from all CPUs that are oopsing. 17658154c8cSAnton Blanchard */ 17758154c8cSAnton Blanchard if (in_interrupt() || panic_on_oops || !current->pid || 17858154c8cSAnton Blanchard is_global_init(current)) { 17958154c8cSAnton Blanchard mdelay(MSEC_PER_SEC); 18058154c8cSAnton Blanchard } 18158154c8cSAnton Blanchard 18214cf11afSPaul Mackerras if (in_interrupt()) 18314cf11afSPaul Mackerras panic("Fatal exception in interrupt"); 184cea6a4baSHorms if (panic_on_oops) 185012c437dSHorms panic("Fatal exception"); 186760ca4dcSAnton Blanchard do_exit(signr); 187760ca4dcSAnton Blanchard } 18803465f89SNicholas Piggin NOKPROBE_SYMBOL(oops_end); 189cea6a4baSHorms 19003465f89SNicholas Piggin static int __die(const char *str, struct pt_regs *regs, long err) 191760ca4dcSAnton Blanchard { 192760ca4dcSAnton Blanchard printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 1932e82ca3cSMichael Ellerman 1942e82ca3cSMichael Ellerman if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 1952e82ca3cSMichael Ellerman printk("LE "); 1962e82ca3cSMichael Ellerman else 1972e82ca3cSMichael Ellerman printk("BE "); 1982e82ca3cSMichael Ellerman 1991c56cd8eSMichael Ellerman if (IS_ENABLED(CONFIG_PREEMPT)) 20072c0d9eeSMichael Ellerman pr_cont("PREEMPT "); 2011c56cd8eSMichael Ellerman 2021c56cd8eSMichael Ellerman if (IS_ENABLED(CONFIG_SMP)) 20372c0d9eeSMichael Ellerman pr_cont("SMP NR_CPUS=%d ", NR_CPUS); 2041c56cd8eSMichael Ellerman 205e7df0d88SJoonsoo Kim if (debug_pagealloc_enabled()) 20672c0d9eeSMichael Ellerman pr_cont("DEBUG_PAGEALLOC "); 2071c56cd8eSMichael Ellerman 2081c56cd8eSMichael Ellerman if (IS_ENABLED(CONFIG_NUMA)) 20972c0d9eeSMichael Ellerman pr_cont("NUMA "); 2101c56cd8eSMichael Ellerman 21172c0d9eeSMichael Ellerman pr_cont("%s\n", ppc_md.name ? ppc_md.name : ""); 212760ca4dcSAnton Blanchard 213760ca4dcSAnton Blanchard if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 214760ca4dcSAnton Blanchard return 1; 215760ca4dcSAnton Blanchard 216760ca4dcSAnton Blanchard print_modules(); 217760ca4dcSAnton Blanchard show_regs(regs); 21814cf11afSPaul Mackerras 21914cf11afSPaul Mackerras return 0; 22014cf11afSPaul Mackerras } 22103465f89SNicholas Piggin NOKPROBE_SYMBOL(__die); 22214cf11afSPaul Mackerras 223760ca4dcSAnton Blanchard void die(const char *str, struct pt_regs *regs, long err) 224760ca4dcSAnton Blanchard { 2256f44b20eSNicholas Piggin unsigned long flags; 226760ca4dcSAnton Blanchard 2276f44b20eSNicholas Piggin if (debugger(regs)) 2286f44b20eSNicholas Piggin return; 2296f44b20eSNicholas Piggin 2306f44b20eSNicholas Piggin flags = oops_begin(regs); 231760ca4dcSAnton Blanchard if (__die(str, regs, err)) 232760ca4dcSAnton Blanchard err = 0; 233760ca4dcSAnton Blanchard oops_end(flags, regs, err); 234760ca4dcSAnton Blanchard } 23515770a13SNaveen N. Rao NOKPROBE_SYMBOL(die); 236760ca4dcSAnton Blanchard 23725baa35bSOleg Nesterov void user_single_step_siginfo(struct task_struct *tsk, 23825baa35bSOleg Nesterov struct pt_regs *regs, siginfo_t *info) 23925baa35bSOleg Nesterov { 24025baa35bSOleg Nesterov memset(info, 0, sizeof(*info)); 24125baa35bSOleg Nesterov info->si_signo = SIGTRAP; 24225baa35bSOleg Nesterov info->si_code = TRAP_TRACE; 24325baa35bSOleg Nesterov info->si_addr = (void __user *)regs->nip; 24425baa35bSOleg Nesterov } 24525baa35bSOleg Nesterov 24614cf11afSPaul Mackerras void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 24714cf11afSPaul Mackerras { 24814cf11afSPaul Mackerras siginfo_t info; 249d0c3d534SOlof Johansson const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 250d0c3d534SOlof Johansson "at %08lx nip %08lx lr %08lx code %x\n"; 251d0c3d534SOlof Johansson const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 252d0c3d534SOlof Johansson "at %016lx nip %016lx lr %016lx code %x\n"; 25314cf11afSPaul Mackerras 25414cf11afSPaul Mackerras if (!user_mode(regs)) { 255760ca4dcSAnton Blanchard die("Exception in kernel mode", regs, signr); 25614cf11afSPaul Mackerras return; 257760ca4dcSAnton Blanchard } 258760ca4dcSAnton Blanchard 259760ca4dcSAnton Blanchard if (show_unhandled_signals && unhandled_signal(current, signr)) { 26076462232SChristian Dietrich printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, 261d0c3d534SOlof Johansson current->comm, current->pid, signr, 262d0c3d534SOlof Johansson addr, regs->nip, regs->link, code); 26314cf11afSPaul Mackerras } 26414cf11afSPaul Mackerras 265a3512b2dSBenjamin Herrenschmidt if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 2669f2f79e3SBenjamin Herrenschmidt local_irq_enable(); 2679f2f79e3SBenjamin Herrenschmidt 26841ab5266SAnanth N Mavinakayanahalli current->thread.trap_nr = code; 26914cf11afSPaul Mackerras memset(&info, 0, sizeof(info)); 27014cf11afSPaul Mackerras info.si_signo = signr; 27114cf11afSPaul Mackerras info.si_code = code; 27214cf11afSPaul Mackerras info.si_addr = (void __user *) addr; 27314cf11afSPaul Mackerras force_sig_info(signr, &info, current); 27414cf11afSPaul Mackerras } 27514cf11afSPaul Mackerras 27614cf11afSPaul Mackerras void system_reset_exception(struct pt_regs *regs) 27714cf11afSPaul Mackerras { 2782b4f3ac5SNicholas Piggin /* 2792b4f3ac5SNicholas Piggin * Avoid crashes in case of nested NMI exceptions. Recoverability 2802b4f3ac5SNicholas Piggin * is determined by RI and in_nmi 2812b4f3ac5SNicholas Piggin */ 2822b4f3ac5SNicholas Piggin bool nested = in_nmi(); 2832b4f3ac5SNicholas Piggin if (!nested) 2842b4f3ac5SNicholas Piggin nmi_enter(); 2852b4f3ac5SNicholas Piggin 286ca41ad43SNicholas Piggin __this_cpu_inc(irq_stat.sreset_irqs); 287ca41ad43SNicholas Piggin 28814cf11afSPaul Mackerras /* See if any machine dependent calls */ 289c902be71SArnd Bergmann if (ppc_md.system_reset_exception) { 290c902be71SArnd Bergmann if (ppc_md.system_reset_exception(regs)) 291c4f3b52cSNicholas Piggin goto out; 292c902be71SArnd Bergmann } 29314cf11afSPaul Mackerras 294*4388c9b3SNicholas Piggin if (debugger(regs)) 295*4388c9b3SNicholas Piggin goto out; 296*4388c9b3SNicholas Piggin 297*4388c9b3SNicholas Piggin /* 298*4388c9b3SNicholas Piggin * A system reset is a request to dump, so we always send 299*4388c9b3SNicholas Piggin * it through the crashdump code (if fadump or kdump are 300*4388c9b3SNicholas Piggin * registered). 301*4388c9b3SNicholas Piggin */ 302*4388c9b3SNicholas Piggin crash_fadump(regs, "System Reset"); 303*4388c9b3SNicholas Piggin 304*4388c9b3SNicholas Piggin crash_kexec(regs); 305*4388c9b3SNicholas Piggin 306*4388c9b3SNicholas Piggin /* 307*4388c9b3SNicholas Piggin * We aren't the primary crash CPU. We need to send it 308*4388c9b3SNicholas Piggin * to a holding pattern to avoid it ending up in the panic 309*4388c9b3SNicholas Piggin * code. 310*4388c9b3SNicholas Piggin */ 311*4388c9b3SNicholas Piggin crash_kexec_secondary(regs); 312*4388c9b3SNicholas Piggin 313*4388c9b3SNicholas Piggin /* 314*4388c9b3SNicholas Piggin * No debugger or crash dump registered, print logs then 315*4388c9b3SNicholas Piggin * panic. 316*4388c9b3SNicholas Piggin */ 317*4388c9b3SNicholas Piggin __die("System Reset", regs, SIGABRT); 318*4388c9b3SNicholas Piggin 319*4388c9b3SNicholas Piggin mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 320*4388c9b3SNicholas Piggin add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 321*4388c9b3SNicholas Piggin nmi_panic(regs, "System Reset"); 32214cf11afSPaul Mackerras 323c4f3b52cSNicholas Piggin out: 324c4f3b52cSNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 325c4f3b52cSNicholas Piggin BUG_ON(get_paca()->in_nmi == 0); 326c4f3b52cSNicholas Piggin if (get_paca()->in_nmi > 1) 327*4388c9b3SNicholas Piggin nmi_panic(regs, "Unrecoverable nested System Reset"); 328c4f3b52cSNicholas Piggin #endif 32914cf11afSPaul Mackerras /* Must die if the interrupt is not recoverable */ 33014cf11afSPaul Mackerras if (!(regs->msr & MSR_RI)) 331*4388c9b3SNicholas Piggin nmi_panic(regs, "Unrecoverable System Reset"); 33214cf11afSPaul Mackerras 3332b4f3ac5SNicholas Piggin if (!nested) 3342b4f3ac5SNicholas Piggin nmi_exit(); 3352b4f3ac5SNicholas Piggin 33614cf11afSPaul Mackerras /* What should we do here? We could issue a shutdown or hard reset. */ 33714cf11afSPaul Mackerras } 3381e9b4507SMahesh Salgaonkar 33914cf11afSPaul Mackerras /* 34014cf11afSPaul Mackerras * I/O accesses can cause machine checks on powermacs. 34114cf11afSPaul Mackerras * Check if the NIP corresponds to the address of a sync 34214cf11afSPaul Mackerras * instruction for which there is an entry in the exception 34314cf11afSPaul Mackerras * table. 34414cf11afSPaul Mackerras * Note that the 601 only takes a machine check on TEA 34514cf11afSPaul Mackerras * (transfer error ack) signal assertion, and does not 34614cf11afSPaul Mackerras * set any of the top 16 bits of SRR1. 34714cf11afSPaul Mackerras * -- paulus. 34814cf11afSPaul Mackerras */ 34914cf11afSPaul Mackerras static inline int check_io_access(struct pt_regs *regs) 35014cf11afSPaul Mackerras { 35168a64357SBenjamin Herrenschmidt #ifdef CONFIG_PPC32 35214cf11afSPaul Mackerras unsigned long msr = regs->msr; 35314cf11afSPaul Mackerras const struct exception_table_entry *entry; 35414cf11afSPaul Mackerras unsigned int *nip = (unsigned int *)regs->nip; 35514cf11afSPaul Mackerras 35614cf11afSPaul Mackerras if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 35714cf11afSPaul Mackerras && (entry = search_exception_tables(regs->nip)) != NULL) { 35814cf11afSPaul Mackerras /* 35914cf11afSPaul Mackerras * Check that it's a sync instruction, or somewhere 36014cf11afSPaul Mackerras * in the twi; isync; nop sequence that inb/inw/inl uses. 36114cf11afSPaul Mackerras * As the address is in the exception table 36214cf11afSPaul Mackerras * we should be able to read the instr there. 36314cf11afSPaul Mackerras * For the debug message, we look at the preceding 36414cf11afSPaul Mackerras * load or store. 36514cf11afSPaul Mackerras */ 366ddc6cd0dSChristophe Leroy if (*nip == PPC_INST_NOP) 36714cf11afSPaul Mackerras nip -= 2; 368ddc6cd0dSChristophe Leroy else if (*nip == PPC_INST_ISYNC) 36914cf11afSPaul Mackerras --nip; 370ddc6cd0dSChristophe Leroy if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { 37114cf11afSPaul Mackerras unsigned int rb; 37214cf11afSPaul Mackerras 37314cf11afSPaul Mackerras --nip; 37414cf11afSPaul Mackerras rb = (*nip >> 11) & 0x1f; 37514cf11afSPaul Mackerras printk(KERN_DEBUG "%s bad port %lx at %p\n", 37614cf11afSPaul Mackerras (*nip & 0x100)? "OUT to": "IN from", 37714cf11afSPaul Mackerras regs->gpr[rb] - _IO_BASE, nip); 37814cf11afSPaul Mackerras regs->msr |= MSR_RI; 37961a92f70SNicholas Piggin regs->nip = extable_fixup(entry); 38014cf11afSPaul Mackerras return 1; 38114cf11afSPaul Mackerras } 38214cf11afSPaul Mackerras } 38368a64357SBenjamin Herrenschmidt #endif /* CONFIG_PPC32 */ 38414cf11afSPaul Mackerras return 0; 38514cf11afSPaul Mackerras } 38614cf11afSPaul Mackerras 387172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 38814cf11afSPaul Mackerras /* On 4xx, the reason for the machine check or program exception 38914cf11afSPaul Mackerras is in the ESR. */ 39014cf11afSPaul Mackerras #define get_reason(regs) ((regs)->dsisr) 39114cf11afSPaul Mackerras #define REASON_FP ESR_FP 39214cf11afSPaul Mackerras #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 39314cf11afSPaul Mackerras #define REASON_PRIVILEGED ESR_PPR 39414cf11afSPaul Mackerras #define REASON_TRAP ESR_PTR 39514cf11afSPaul Mackerras 39614cf11afSPaul Mackerras /* single-step stuff */ 39751ae8d4aSBharat Bhushan #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 39851ae8d4aSBharat Bhushan #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 39914cf11afSPaul Mackerras 40014cf11afSPaul Mackerras #else 40114cf11afSPaul Mackerras /* On non-4xx, the reason for the machine check or program 40214cf11afSPaul Mackerras exception is in the MSR. */ 40314cf11afSPaul Mackerras #define get_reason(regs) ((regs)->msr) 404d30a5a52SMichael Ellerman #define REASON_TM SRR1_PROGTM 405d30a5a52SMichael Ellerman #define REASON_FP SRR1_PROGFPE 406d30a5a52SMichael Ellerman #define REASON_ILLEGAL SRR1_PROGILL 407d30a5a52SMichael Ellerman #define REASON_PRIVILEGED SRR1_PROGPRIV 408d30a5a52SMichael Ellerman #define REASON_TRAP SRR1_PROGTRAP 40914cf11afSPaul Mackerras 41014cf11afSPaul Mackerras #define single_stepping(regs) ((regs)->msr & MSR_SE) 41114cf11afSPaul Mackerras #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 41214cf11afSPaul Mackerras #endif 41314cf11afSPaul Mackerras 4140d0935b3SMichael Ellerman #if defined(CONFIG_E500) 415fe04b112SScott Wood int machine_check_e500mc(struct pt_regs *regs) 416fe04b112SScott Wood { 417fe04b112SScott Wood unsigned long mcsr = mfspr(SPRN_MCSR); 418fe04b112SScott Wood unsigned long reason = mcsr; 419fe04b112SScott Wood int recoverable = 1; 420fe04b112SScott Wood 42182a9a480SScott Wood if (reason & MCSR_LD) { 422cce1f106SShaohui Xie recoverable = fsl_rio_mcheck_exception(regs); 423cce1f106SShaohui Xie if (recoverable == 1) 424cce1f106SShaohui Xie goto silent_out; 425cce1f106SShaohui Xie } 426cce1f106SShaohui Xie 427fe04b112SScott Wood printk("Machine check in kernel mode.\n"); 428fe04b112SScott Wood printk("Caused by (from MCSR=%lx): ", reason); 429fe04b112SScott Wood 430fe04b112SScott Wood if (reason & MCSR_MCP) 431fe04b112SScott Wood printk("Machine Check Signal\n"); 432fe04b112SScott Wood 433fe04b112SScott Wood if (reason & MCSR_ICPERR) { 434fe04b112SScott Wood printk("Instruction Cache Parity Error\n"); 435fe04b112SScott Wood 436fe04b112SScott Wood /* 437fe04b112SScott Wood * This is recoverable by invalidating the i-cache. 438fe04b112SScott Wood */ 439fe04b112SScott Wood mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 440fe04b112SScott Wood while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 441fe04b112SScott Wood ; 442fe04b112SScott Wood 443fe04b112SScott Wood /* 444fe04b112SScott Wood * This will generally be accompanied by an instruction 445fe04b112SScott Wood * fetch error report -- only treat MCSR_IF as fatal 446fe04b112SScott Wood * if it wasn't due to an L1 parity error. 447fe04b112SScott Wood */ 448fe04b112SScott Wood reason &= ~MCSR_IF; 449fe04b112SScott Wood } 450fe04b112SScott Wood 451fe04b112SScott Wood if (reason & MCSR_DCPERR_MC) { 452fe04b112SScott Wood printk("Data Cache Parity Error\n"); 45337caf9f2SKumar Gala 45437caf9f2SKumar Gala /* 45537caf9f2SKumar Gala * In write shadow mode we auto-recover from the error, but it 45637caf9f2SKumar Gala * may still get logged and cause a machine check. We should 45737caf9f2SKumar Gala * only treat the non-write shadow case as non-recoverable. 45837caf9f2SKumar Gala */ 45937caf9f2SKumar Gala if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 460fe04b112SScott Wood recoverable = 0; 461fe04b112SScott Wood } 462fe04b112SScott Wood 463fe04b112SScott Wood if (reason & MCSR_L2MMU_MHIT) { 464fe04b112SScott Wood printk("Hit on multiple TLB entries\n"); 465fe04b112SScott Wood recoverable = 0; 466fe04b112SScott Wood } 467fe04b112SScott Wood 468fe04b112SScott Wood if (reason & MCSR_NMI) 469fe04b112SScott Wood printk("Non-maskable interrupt\n"); 470fe04b112SScott Wood 471fe04b112SScott Wood if (reason & MCSR_IF) { 472fe04b112SScott Wood printk("Instruction Fetch Error Report\n"); 473fe04b112SScott Wood recoverable = 0; 474fe04b112SScott Wood } 475fe04b112SScott Wood 476fe04b112SScott Wood if (reason & MCSR_LD) { 477fe04b112SScott Wood printk("Load Error Report\n"); 478fe04b112SScott Wood recoverable = 0; 479fe04b112SScott Wood } 480fe04b112SScott Wood 481fe04b112SScott Wood if (reason & MCSR_ST) { 482fe04b112SScott Wood printk("Store Error Report\n"); 483fe04b112SScott Wood recoverable = 0; 484fe04b112SScott Wood } 485fe04b112SScott Wood 486fe04b112SScott Wood if (reason & MCSR_LDG) { 487fe04b112SScott Wood printk("Guarded Load Error Report\n"); 488fe04b112SScott Wood recoverable = 0; 489fe04b112SScott Wood } 490fe04b112SScott Wood 491fe04b112SScott Wood if (reason & MCSR_TLBSYNC) 492fe04b112SScott Wood printk("Simultaneous tlbsync operations\n"); 493fe04b112SScott Wood 494fe04b112SScott Wood if (reason & MCSR_BSL2_ERR) { 495fe04b112SScott Wood printk("Level 2 Cache Error\n"); 496fe04b112SScott Wood recoverable = 0; 497fe04b112SScott Wood } 498fe04b112SScott Wood 499fe04b112SScott Wood if (reason & MCSR_MAV) { 500fe04b112SScott Wood u64 addr; 501fe04b112SScott Wood 502fe04b112SScott Wood addr = mfspr(SPRN_MCAR); 503fe04b112SScott Wood addr |= (u64)mfspr(SPRN_MCARU) << 32; 504fe04b112SScott Wood 505fe04b112SScott Wood printk("Machine Check %s Address: %#llx\n", 506fe04b112SScott Wood reason & MCSR_MEA ? "Effective" : "Physical", addr); 507fe04b112SScott Wood } 508fe04b112SScott Wood 509cce1f106SShaohui Xie silent_out: 510fe04b112SScott Wood mtspr(SPRN_MCSR, mcsr); 511fe04b112SScott Wood return mfspr(SPRN_MCSR) == 0 && recoverable; 512fe04b112SScott Wood } 513fe04b112SScott Wood 51447c0bd1aSBenjamin Herrenschmidt int machine_check_e500(struct pt_regs *regs) 51547c0bd1aSBenjamin Herrenschmidt { 51642bff234SMichael Ellerman unsigned long reason = mfspr(SPRN_MCSR); 51747c0bd1aSBenjamin Herrenschmidt 518cce1f106SShaohui Xie if (reason & MCSR_BUS_RBERR) { 519cce1f106SShaohui Xie if (fsl_rio_mcheck_exception(regs)) 520cce1f106SShaohui Xie return 1; 5214e0e3435SHongtao Jia if (fsl_pci_mcheck_exception(regs)) 5224e0e3435SHongtao Jia return 1; 523cce1f106SShaohui Xie } 524cce1f106SShaohui Xie 52514cf11afSPaul Mackerras printk("Machine check in kernel mode.\n"); 52614cf11afSPaul Mackerras printk("Caused by (from MCSR=%lx): ", reason); 52714cf11afSPaul Mackerras 52814cf11afSPaul Mackerras if (reason & MCSR_MCP) 52914cf11afSPaul Mackerras printk("Machine Check Signal\n"); 53014cf11afSPaul Mackerras if (reason & MCSR_ICPERR) 53114cf11afSPaul Mackerras printk("Instruction Cache Parity Error\n"); 53214cf11afSPaul Mackerras if (reason & MCSR_DCP_PERR) 53314cf11afSPaul Mackerras printk("Data Cache Push Parity Error\n"); 53414cf11afSPaul Mackerras if (reason & MCSR_DCPERR) 53514cf11afSPaul Mackerras printk("Data Cache Parity Error\n"); 53614cf11afSPaul Mackerras if (reason & MCSR_BUS_IAERR) 53714cf11afSPaul Mackerras printk("Bus - Instruction Address Error\n"); 53814cf11afSPaul Mackerras if (reason & MCSR_BUS_RAERR) 53914cf11afSPaul Mackerras printk("Bus - Read Address Error\n"); 54014cf11afSPaul Mackerras if (reason & MCSR_BUS_WAERR) 54114cf11afSPaul Mackerras printk("Bus - Write Address Error\n"); 54214cf11afSPaul Mackerras if (reason & MCSR_BUS_IBERR) 54314cf11afSPaul Mackerras printk("Bus - Instruction Data Error\n"); 54414cf11afSPaul Mackerras if (reason & MCSR_BUS_RBERR) 54514cf11afSPaul Mackerras printk("Bus - Read Data Bus Error\n"); 54614cf11afSPaul Mackerras if (reason & MCSR_BUS_WBERR) 547c1528339SWladislav Wiebe printk("Bus - Write Data Bus Error\n"); 54814cf11afSPaul Mackerras if (reason & MCSR_BUS_IPERR) 54914cf11afSPaul Mackerras printk("Bus - Instruction Parity Error\n"); 55014cf11afSPaul Mackerras if (reason & MCSR_BUS_RPERR) 55114cf11afSPaul Mackerras printk("Bus - Read Parity Error\n"); 55247c0bd1aSBenjamin Herrenschmidt 55347c0bd1aSBenjamin Herrenschmidt return 0; 55447c0bd1aSBenjamin Herrenschmidt } 5554490c06bSKumar Gala 5564490c06bSKumar Gala int machine_check_generic(struct pt_regs *regs) 5574490c06bSKumar Gala { 5584490c06bSKumar Gala return 0; 5594490c06bSKumar Gala } 56014cf11afSPaul Mackerras #elif defined(CONFIG_E200) 56147c0bd1aSBenjamin Herrenschmidt int machine_check_e200(struct pt_regs *regs) 56247c0bd1aSBenjamin Herrenschmidt { 56342bff234SMichael Ellerman unsigned long reason = mfspr(SPRN_MCSR); 56447c0bd1aSBenjamin Herrenschmidt 56514cf11afSPaul Mackerras printk("Machine check in kernel mode.\n"); 56614cf11afSPaul Mackerras printk("Caused by (from MCSR=%lx): ", reason); 56714cf11afSPaul Mackerras 56814cf11afSPaul Mackerras if (reason & MCSR_MCP) 56914cf11afSPaul Mackerras printk("Machine Check Signal\n"); 57014cf11afSPaul Mackerras if (reason & MCSR_CP_PERR) 57114cf11afSPaul Mackerras printk("Cache Push Parity Error\n"); 57214cf11afSPaul Mackerras if (reason & MCSR_CPERR) 57314cf11afSPaul Mackerras printk("Cache Parity Error\n"); 57414cf11afSPaul Mackerras if (reason & MCSR_EXCP_ERR) 57514cf11afSPaul Mackerras printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 57614cf11afSPaul Mackerras if (reason & MCSR_BUS_IRERR) 57714cf11afSPaul Mackerras printk("Bus - Read Bus Error on instruction fetch\n"); 57814cf11afSPaul Mackerras if (reason & MCSR_BUS_DRERR) 57914cf11afSPaul Mackerras printk("Bus - Read Bus Error on data load\n"); 58014cf11afSPaul Mackerras if (reason & MCSR_BUS_WRERR) 58114cf11afSPaul Mackerras printk("Bus - Write Bus Error on buffered store or cache line push\n"); 58247c0bd1aSBenjamin Herrenschmidt 58347c0bd1aSBenjamin Herrenschmidt return 0; 58447c0bd1aSBenjamin Herrenschmidt } 5857f3f819eSMichael Ellerman #elif defined(CONFIG_PPC32) 58647c0bd1aSBenjamin Herrenschmidt int machine_check_generic(struct pt_regs *regs) 58747c0bd1aSBenjamin Herrenschmidt { 58842bff234SMichael Ellerman unsigned long reason = regs->msr; 58947c0bd1aSBenjamin Herrenschmidt 59014cf11afSPaul Mackerras printk("Machine check in kernel mode.\n"); 59114cf11afSPaul Mackerras printk("Caused by (from SRR1=%lx): ", reason); 59214cf11afSPaul Mackerras switch (reason & 0x601F0000) { 59314cf11afSPaul Mackerras case 0x80000: 59414cf11afSPaul Mackerras printk("Machine check signal\n"); 59514cf11afSPaul Mackerras break; 59614cf11afSPaul Mackerras case 0: /* for 601 */ 59714cf11afSPaul Mackerras case 0x40000: 59814cf11afSPaul Mackerras case 0x140000: /* 7450 MSS error and TEA */ 59914cf11afSPaul Mackerras printk("Transfer error ack signal\n"); 60014cf11afSPaul Mackerras break; 60114cf11afSPaul Mackerras case 0x20000: 60214cf11afSPaul Mackerras printk("Data parity error signal\n"); 60314cf11afSPaul Mackerras break; 60414cf11afSPaul Mackerras case 0x10000: 60514cf11afSPaul Mackerras printk("Address parity error signal\n"); 60614cf11afSPaul Mackerras break; 60714cf11afSPaul Mackerras case 0x20000000: 60814cf11afSPaul Mackerras printk("L1 Data Cache error\n"); 60914cf11afSPaul Mackerras break; 61014cf11afSPaul Mackerras case 0x40000000: 61114cf11afSPaul Mackerras printk("L1 Instruction Cache error\n"); 61214cf11afSPaul Mackerras break; 61314cf11afSPaul Mackerras case 0x00100000: 61414cf11afSPaul Mackerras printk("L2 data cache parity error\n"); 61514cf11afSPaul Mackerras break; 61614cf11afSPaul Mackerras default: 61714cf11afSPaul Mackerras printk("Unknown values in msr\n"); 61814cf11afSPaul Mackerras } 61975918a4bSOlof Johansson return 0; 62075918a4bSOlof Johansson } 62147c0bd1aSBenjamin Herrenschmidt #endif /* everything else */ 62275918a4bSOlof Johansson 62375918a4bSOlof Johansson void machine_check_exception(struct pt_regs *regs) 62475918a4bSOlof Johansson { 625ba12eedeSLi Zhong enum ctx_state prev_state = exception_enter(); 62675918a4bSOlof Johansson int recover = 0; 62775918a4bSOlof Johansson 628f886f0f6SNicholas Piggin /* 64s accounts the mce in machine_check_early when in HVMODE */ 629f886f0f6SNicholas Piggin if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE)) 63069111bacSChristoph Lameter __this_cpu_inc(irq_stat.mce_exceptions); 63189713ed1SAnton Blanchard 632d93b0ac0SMahesh Salgaonkar add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 633d93b0ac0SMahesh Salgaonkar 63447c0bd1aSBenjamin Herrenschmidt /* See if any machine dependent calls. In theory, we would want 63547c0bd1aSBenjamin Herrenschmidt * to call the CPU first, and call the ppc_md. one if the CPU 63647c0bd1aSBenjamin Herrenschmidt * one returns a positive number. However there is existing code 63747c0bd1aSBenjamin Herrenschmidt * that assumes the board gets a first chance, so let's keep it 63847c0bd1aSBenjamin Herrenschmidt * that way for now and fix things later. --BenH. 63947c0bd1aSBenjamin Herrenschmidt */ 64075918a4bSOlof Johansson if (ppc_md.machine_check_exception) 64175918a4bSOlof Johansson recover = ppc_md.machine_check_exception(regs); 64247c0bd1aSBenjamin Herrenschmidt else if (cur_cpu_spec->machine_check) 64347c0bd1aSBenjamin Herrenschmidt recover = cur_cpu_spec->machine_check(regs); 64475918a4bSOlof Johansson 64547c0bd1aSBenjamin Herrenschmidt if (recover > 0) 646ba12eedeSLi Zhong goto bail; 64775918a4bSOlof Johansson 648a443506bSAnton Blanchard if (debugger_fault_handler(regs)) 649ba12eedeSLi Zhong goto bail; 65075918a4bSOlof Johansson 65175918a4bSOlof Johansson if (check_io_access(regs)) 652ba12eedeSLi Zhong goto bail; 65375918a4bSOlof Johansson 6548dad3f92SPaul Mackerras die("Machine check", regs, SIGBUS); 65514cf11afSPaul Mackerras 65614cf11afSPaul Mackerras /* Must die if the interrupt is not recoverable */ 65714cf11afSPaul Mackerras if (!(regs->msr & MSR_RI)) 65814cf11afSPaul Mackerras panic("Unrecoverable Machine check"); 659ba12eedeSLi Zhong 660ba12eedeSLi Zhong bail: 661ba12eedeSLi Zhong exception_exit(prev_state); 66214cf11afSPaul Mackerras } 66314cf11afSPaul Mackerras 66414cf11afSPaul Mackerras void SMIException(struct pt_regs *regs) 66514cf11afSPaul Mackerras { 66614cf11afSPaul Mackerras die("System Management Interrupt", regs, SIGABRT); 66714cf11afSPaul Mackerras } 66814cf11afSPaul Mackerras 6690869b6fdSMahesh Salgaonkar void handle_hmi_exception(struct pt_regs *regs) 6700869b6fdSMahesh Salgaonkar { 6710869b6fdSMahesh Salgaonkar struct pt_regs *old_regs; 6720869b6fdSMahesh Salgaonkar 6730869b6fdSMahesh Salgaonkar old_regs = set_irq_regs(regs); 6740869b6fdSMahesh Salgaonkar irq_enter(); 6750869b6fdSMahesh Salgaonkar 6760869b6fdSMahesh Salgaonkar if (ppc_md.handle_hmi_exception) 6770869b6fdSMahesh Salgaonkar ppc_md.handle_hmi_exception(regs); 6780869b6fdSMahesh Salgaonkar 6790869b6fdSMahesh Salgaonkar irq_exit(); 6800869b6fdSMahesh Salgaonkar set_irq_regs(old_regs); 6810869b6fdSMahesh Salgaonkar } 6820869b6fdSMahesh Salgaonkar 683dc1c1ca3SStephen Rothwell void unknown_exception(struct pt_regs *regs) 68414cf11afSPaul Mackerras { 685ba12eedeSLi Zhong enum ctx_state prev_state = exception_enter(); 686ba12eedeSLi Zhong 68714cf11afSPaul Mackerras printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 68814cf11afSPaul Mackerras regs->nip, regs->msr, regs->trap); 68914cf11afSPaul Mackerras 69014cf11afSPaul Mackerras _exception(SIGTRAP, regs, 0, 0); 691ba12eedeSLi Zhong 692ba12eedeSLi Zhong exception_exit(prev_state); 69314cf11afSPaul Mackerras } 69414cf11afSPaul Mackerras 695dc1c1ca3SStephen Rothwell void instruction_breakpoint_exception(struct pt_regs *regs) 69614cf11afSPaul Mackerras { 697ba12eedeSLi Zhong enum ctx_state prev_state = exception_enter(); 698ba12eedeSLi Zhong 69914cf11afSPaul Mackerras if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 70014cf11afSPaul Mackerras 5, SIGTRAP) == NOTIFY_STOP) 701ba12eedeSLi Zhong goto bail; 70214cf11afSPaul Mackerras if (debugger_iabr_match(regs)) 703ba12eedeSLi Zhong goto bail; 70414cf11afSPaul Mackerras _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 705ba12eedeSLi Zhong 706ba12eedeSLi Zhong bail: 707ba12eedeSLi Zhong exception_exit(prev_state); 70814cf11afSPaul Mackerras } 70914cf11afSPaul Mackerras 71014cf11afSPaul Mackerras void RunModeException(struct pt_regs *regs) 71114cf11afSPaul Mackerras { 71214cf11afSPaul Mackerras _exception(SIGTRAP, regs, 0, 0); 71314cf11afSPaul Mackerras } 71414cf11afSPaul Mackerras 71503465f89SNicholas Piggin void single_step_exception(struct pt_regs *regs) 71614cf11afSPaul Mackerras { 717ba12eedeSLi Zhong enum ctx_state prev_state = exception_enter(); 718ba12eedeSLi Zhong 7192538c2d0SK.Prasad clear_single_step(regs); 72014cf11afSPaul Mackerras 7216cc89badSNaveen N. Rao if (kprobe_post_handler(regs)) 7226cc89badSNaveen N. Rao return; 7236cc89badSNaveen N. Rao 72414cf11afSPaul Mackerras if (notify_die(DIE_SSTEP, "single_step", regs, 5, 72514cf11afSPaul Mackerras 5, SIGTRAP) == NOTIFY_STOP) 726ba12eedeSLi Zhong goto bail; 72714cf11afSPaul Mackerras if (debugger_sstep(regs)) 728ba12eedeSLi Zhong goto bail; 72914cf11afSPaul Mackerras 73014cf11afSPaul Mackerras _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 731ba12eedeSLi Zhong 732ba12eedeSLi Zhong bail: 733ba12eedeSLi Zhong exception_exit(prev_state); 73414cf11afSPaul Mackerras } 73503465f89SNicholas Piggin NOKPROBE_SYMBOL(single_step_exception); 73614cf11afSPaul Mackerras 73714cf11afSPaul Mackerras /* 73814cf11afSPaul Mackerras * After we have successfully emulated an instruction, we have to 73914cf11afSPaul Mackerras * check if the instruction was being single-stepped, and if so, 74014cf11afSPaul Mackerras * pretend we got a single-step exception. This was pointed out 74114cf11afSPaul Mackerras * by Kumar Gala. -- paulus 74214cf11afSPaul Mackerras */ 7438dad3f92SPaul Mackerras static void emulate_single_step(struct pt_regs *regs) 74414cf11afSPaul Mackerras { 7452538c2d0SK.Prasad if (single_stepping(regs)) 7462538c2d0SK.Prasad single_step_exception(regs); 74714cf11afSPaul Mackerras } 74814cf11afSPaul Mackerras 7495fad293bSKumar Gala static inline int __parse_fpscr(unsigned long fpscr) 750dc1c1ca3SStephen Rothwell { 7515fad293bSKumar Gala int ret = 0; 752dc1c1ca3SStephen Rothwell 753dc1c1ca3SStephen Rothwell /* Invalid operation */ 754dc1c1ca3SStephen Rothwell if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 7555fad293bSKumar Gala ret = FPE_FLTINV; 756dc1c1ca3SStephen Rothwell 757dc1c1ca3SStephen Rothwell /* Overflow */ 758dc1c1ca3SStephen Rothwell else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 7595fad293bSKumar Gala ret = FPE_FLTOVF; 760dc1c1ca3SStephen Rothwell 761dc1c1ca3SStephen Rothwell /* Underflow */ 762dc1c1ca3SStephen Rothwell else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 7635fad293bSKumar Gala ret = FPE_FLTUND; 764dc1c1ca3SStephen Rothwell 765dc1c1ca3SStephen Rothwell /* Divide by zero */ 766dc1c1ca3SStephen Rothwell else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 7675fad293bSKumar Gala ret = FPE_FLTDIV; 768dc1c1ca3SStephen Rothwell 769dc1c1ca3SStephen Rothwell /* Inexact result */ 770dc1c1ca3SStephen Rothwell else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 7715fad293bSKumar Gala ret = FPE_FLTRES; 7725fad293bSKumar Gala 7735fad293bSKumar Gala return ret; 7745fad293bSKumar Gala } 7755fad293bSKumar Gala 7765fad293bSKumar Gala static void parse_fpe(struct pt_regs *regs) 7775fad293bSKumar Gala { 7785fad293bSKumar Gala int code = 0; 7795fad293bSKumar Gala 7805fad293bSKumar Gala flush_fp_to_thread(current); 7815fad293bSKumar Gala 782de79f7b9SPaul Mackerras code = __parse_fpscr(current->thread.fp_state.fpscr); 783dc1c1ca3SStephen Rothwell 784dc1c1ca3SStephen Rothwell _exception(SIGFPE, regs, code, regs->nip); 785dc1c1ca3SStephen Rothwell } 786dc1c1ca3SStephen Rothwell 787dc1c1ca3SStephen Rothwell /* 788dc1c1ca3SStephen Rothwell * Illegal instruction emulation support. Originally written to 78914cf11afSPaul Mackerras * provide the PVR to user applications using the mfspr rd, PVR. 79014cf11afSPaul Mackerras * Return non-zero if we can't emulate, or -EFAULT if the associated 79114cf11afSPaul Mackerras * memory access caused an access fault. Return zero on success. 79214cf11afSPaul Mackerras * 79314cf11afSPaul Mackerras * There are a couple of ways to do this, either "decode" the instruction 79414cf11afSPaul Mackerras * or directly match lots of bits. In this case, matching lots of 79514cf11afSPaul Mackerras * bits is faster and easier. 79686417780SPaul Mackerras * 79714cf11afSPaul Mackerras */ 79814cf11afSPaul Mackerras static int emulate_string_inst(struct pt_regs *regs, u32 instword) 79914cf11afSPaul Mackerras { 80014cf11afSPaul Mackerras u8 rT = (instword >> 21) & 0x1f; 80114cf11afSPaul Mackerras u8 rA = (instword >> 16) & 0x1f; 80214cf11afSPaul Mackerras u8 NB_RB = (instword >> 11) & 0x1f; 80314cf11afSPaul Mackerras u32 num_bytes; 80414cf11afSPaul Mackerras unsigned long EA; 80514cf11afSPaul Mackerras int pos = 0; 80614cf11afSPaul Mackerras 80714cf11afSPaul Mackerras /* Early out if we are an invalid form of lswx */ 80816c57b36SKumar Gala if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 80914cf11afSPaul Mackerras if ((rT == rA) || (rT == NB_RB)) 81014cf11afSPaul Mackerras return -EINVAL; 81114cf11afSPaul Mackerras 81214cf11afSPaul Mackerras EA = (rA == 0) ? 0 : regs->gpr[rA]; 81314cf11afSPaul Mackerras 81416c57b36SKumar Gala switch (instword & PPC_INST_STRING_MASK) { 81516c57b36SKumar Gala case PPC_INST_LSWX: 81616c57b36SKumar Gala case PPC_INST_STSWX: 81714cf11afSPaul Mackerras EA += NB_RB; 81814cf11afSPaul Mackerras num_bytes = regs->xer & 0x7f; 81914cf11afSPaul Mackerras break; 82016c57b36SKumar Gala case PPC_INST_LSWI: 82116c57b36SKumar Gala case PPC_INST_STSWI: 82214cf11afSPaul Mackerras num_bytes = (NB_RB == 0) ? 32 : NB_RB; 82314cf11afSPaul Mackerras break; 82414cf11afSPaul Mackerras default: 82514cf11afSPaul Mackerras return -EINVAL; 82614cf11afSPaul Mackerras } 82714cf11afSPaul Mackerras 82814cf11afSPaul Mackerras while (num_bytes != 0) 82914cf11afSPaul Mackerras { 83014cf11afSPaul Mackerras u8 val; 83114cf11afSPaul Mackerras u32 shift = 8 * (3 - (pos & 0x3)); 83214cf11afSPaul Mackerras 83380aa0fb4SJames Yang /* if process is 32-bit, clear upper 32 bits of EA */ 83480aa0fb4SJames Yang if ((regs->msr & MSR_64BIT) == 0) 83580aa0fb4SJames Yang EA &= 0xFFFFFFFF; 83680aa0fb4SJames Yang 83716c57b36SKumar Gala switch ((instword & PPC_INST_STRING_MASK)) { 83816c57b36SKumar Gala case PPC_INST_LSWX: 83916c57b36SKumar Gala case PPC_INST_LSWI: 84014cf11afSPaul Mackerras if (get_user(val, (u8 __user *)EA)) 84114cf11afSPaul Mackerras return -EFAULT; 84214cf11afSPaul Mackerras /* first time updating this reg, 84314cf11afSPaul Mackerras * zero it out */ 84414cf11afSPaul Mackerras if (pos == 0) 84514cf11afSPaul Mackerras regs->gpr[rT] = 0; 84614cf11afSPaul Mackerras regs->gpr[rT] |= val << shift; 84714cf11afSPaul Mackerras break; 84816c57b36SKumar Gala case PPC_INST_STSWI: 84916c57b36SKumar Gala case PPC_INST_STSWX: 85014cf11afSPaul Mackerras val = regs->gpr[rT] >> shift; 85114cf11afSPaul Mackerras if (put_user(val, (u8 __user *)EA)) 85214cf11afSPaul Mackerras return -EFAULT; 85314cf11afSPaul Mackerras break; 85414cf11afSPaul Mackerras } 85514cf11afSPaul Mackerras /* move EA to next address */ 85614cf11afSPaul Mackerras EA += 1; 85714cf11afSPaul Mackerras num_bytes--; 85814cf11afSPaul Mackerras 85914cf11afSPaul Mackerras /* manage our position within the register */ 86014cf11afSPaul Mackerras if (++pos == 4) { 86114cf11afSPaul Mackerras pos = 0; 86214cf11afSPaul Mackerras if (++rT == 32) 86314cf11afSPaul Mackerras rT = 0; 86414cf11afSPaul Mackerras } 86514cf11afSPaul Mackerras } 86614cf11afSPaul Mackerras 86714cf11afSPaul Mackerras return 0; 86814cf11afSPaul Mackerras } 86914cf11afSPaul Mackerras 870c3412dcbSWill Schmidt static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 871c3412dcbSWill Schmidt { 872c3412dcbSWill Schmidt u32 ra,rs; 873c3412dcbSWill Schmidt unsigned long tmp; 874c3412dcbSWill Schmidt 875c3412dcbSWill Schmidt ra = (instword >> 16) & 0x1f; 876c3412dcbSWill Schmidt rs = (instword >> 21) & 0x1f; 877c3412dcbSWill Schmidt 878c3412dcbSWill Schmidt tmp = regs->gpr[rs]; 879c3412dcbSWill Schmidt tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 880c3412dcbSWill Schmidt tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 881c3412dcbSWill Schmidt tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 882c3412dcbSWill Schmidt regs->gpr[ra] = tmp; 883c3412dcbSWill Schmidt 884c3412dcbSWill Schmidt return 0; 885c3412dcbSWill Schmidt } 886c3412dcbSWill Schmidt 887c1469f13SKumar Gala static int emulate_isel(struct pt_regs *regs, u32 instword) 888c1469f13SKumar Gala { 889c1469f13SKumar Gala u8 rT = (instword >> 21) & 0x1f; 890c1469f13SKumar Gala u8 rA = (instword >> 16) & 0x1f; 891c1469f13SKumar Gala u8 rB = (instword >> 11) & 0x1f; 892c1469f13SKumar Gala u8 BC = (instword >> 6) & 0x1f; 893c1469f13SKumar Gala u8 bit; 894c1469f13SKumar Gala unsigned long tmp; 895c1469f13SKumar Gala 896c1469f13SKumar Gala tmp = (rA == 0) ? 0 : regs->gpr[rA]; 897c1469f13SKumar Gala bit = (regs->ccr >> (31 - BC)) & 0x1; 898c1469f13SKumar Gala 899c1469f13SKumar Gala regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 900c1469f13SKumar Gala 901c1469f13SKumar Gala return 0; 902c1469f13SKumar Gala } 903c1469f13SKumar Gala 9046ce6c629SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 9056ce6c629SMichael Neuling static inline bool tm_abort_check(struct pt_regs *regs, int cause) 9066ce6c629SMichael Neuling { 9076ce6c629SMichael Neuling /* If we're emulating a load/store in an active transaction, we cannot 9086ce6c629SMichael Neuling * emulate it as the kernel operates in transaction suspended context. 9096ce6c629SMichael Neuling * We need to abort the transaction. This creates a persistent TM 9106ce6c629SMichael Neuling * abort so tell the user what caused it with a new code. 9116ce6c629SMichael Neuling */ 9126ce6c629SMichael Neuling if (MSR_TM_TRANSACTIONAL(regs->msr)) { 9136ce6c629SMichael Neuling tm_enable(); 9146ce6c629SMichael Neuling tm_abort(cause); 9156ce6c629SMichael Neuling return true; 9166ce6c629SMichael Neuling } 9176ce6c629SMichael Neuling return false; 9186ce6c629SMichael Neuling } 9196ce6c629SMichael Neuling #else 9206ce6c629SMichael Neuling static inline bool tm_abort_check(struct pt_regs *regs, int reason) 9216ce6c629SMichael Neuling { 9226ce6c629SMichael Neuling return false; 9236ce6c629SMichael Neuling } 9246ce6c629SMichael Neuling #endif 9256ce6c629SMichael Neuling 92614cf11afSPaul Mackerras static int emulate_instruction(struct pt_regs *regs) 92714cf11afSPaul Mackerras { 92814cf11afSPaul Mackerras u32 instword; 92914cf11afSPaul Mackerras u32 rd; 93014cf11afSPaul Mackerras 9314288e343SAnton Blanchard if (!user_mode(regs)) 93214cf11afSPaul Mackerras return -EINVAL; 93314cf11afSPaul Mackerras CHECK_FULL_REGS(regs); 93414cf11afSPaul Mackerras 93514cf11afSPaul Mackerras if (get_user(instword, (u32 __user *)(regs->nip))) 93614cf11afSPaul Mackerras return -EFAULT; 93714cf11afSPaul Mackerras 93814cf11afSPaul Mackerras /* Emulate the mfspr rD, PVR. */ 93916c57b36SKumar Gala if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 940eecff81dSAnton Blanchard PPC_WARN_EMULATED(mfpvr, regs); 94114cf11afSPaul Mackerras rd = (instword >> 21) & 0x1f; 94214cf11afSPaul Mackerras regs->gpr[rd] = mfspr(SPRN_PVR); 94314cf11afSPaul Mackerras return 0; 94414cf11afSPaul Mackerras } 94514cf11afSPaul Mackerras 94614cf11afSPaul Mackerras /* Emulating the dcba insn is just a no-op. */ 94780947e7cSGeert Uytterhoeven if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 948eecff81dSAnton Blanchard PPC_WARN_EMULATED(dcba, regs); 94914cf11afSPaul Mackerras return 0; 95080947e7cSGeert Uytterhoeven } 95114cf11afSPaul Mackerras 95214cf11afSPaul Mackerras /* Emulate the mcrxr insn. */ 95316c57b36SKumar Gala if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 95486417780SPaul Mackerras int shift = (instword >> 21) & 0x1c; 95514cf11afSPaul Mackerras unsigned long msk = 0xf0000000UL >> shift; 95614cf11afSPaul Mackerras 957eecff81dSAnton Blanchard PPC_WARN_EMULATED(mcrxr, regs); 95814cf11afSPaul Mackerras regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 95914cf11afSPaul Mackerras regs->xer &= ~0xf0000000UL; 96014cf11afSPaul Mackerras return 0; 96114cf11afSPaul Mackerras } 96214cf11afSPaul Mackerras 96314cf11afSPaul Mackerras /* Emulate load/store string insn. */ 96480947e7cSGeert Uytterhoeven if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 9656ce6c629SMichael Neuling if (tm_abort_check(regs, 9666ce6c629SMichael Neuling TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 9676ce6c629SMichael Neuling return -EINVAL; 968eecff81dSAnton Blanchard PPC_WARN_EMULATED(string, regs); 96914cf11afSPaul Mackerras return emulate_string_inst(regs, instword); 97080947e7cSGeert Uytterhoeven } 97114cf11afSPaul Mackerras 972c3412dcbSWill Schmidt /* Emulate the popcntb (Population Count Bytes) instruction. */ 97316c57b36SKumar Gala if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 974eecff81dSAnton Blanchard PPC_WARN_EMULATED(popcntb, regs); 975c3412dcbSWill Schmidt return emulate_popcntb_inst(regs, instword); 976c3412dcbSWill Schmidt } 977c3412dcbSWill Schmidt 978c1469f13SKumar Gala /* Emulate isel (Integer Select) instruction */ 97916c57b36SKumar Gala if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 980eecff81dSAnton Blanchard PPC_WARN_EMULATED(isel, regs); 981c1469f13SKumar Gala return emulate_isel(regs, instword); 982c1469f13SKumar Gala } 983c1469f13SKumar Gala 9849863c28aSJames Yang /* Emulate sync instruction variants */ 9859863c28aSJames Yang if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 9869863c28aSJames Yang PPC_WARN_EMULATED(sync, regs); 9879863c28aSJames Yang asm volatile("sync"); 9889863c28aSJames Yang return 0; 9899863c28aSJames Yang } 9909863c28aSJames Yang 991efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64 992efcac658SAlexey Kardashevskiy /* Emulate the mfspr rD, DSCR. */ 99373d2fb75SAnton Blanchard if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 99473d2fb75SAnton Blanchard PPC_INST_MFSPR_DSCR_USER) || 99573d2fb75SAnton Blanchard ((instword & PPC_INST_MFSPR_DSCR_MASK) == 99673d2fb75SAnton Blanchard PPC_INST_MFSPR_DSCR)) && 997efcac658SAlexey Kardashevskiy cpu_has_feature(CPU_FTR_DSCR)) { 998efcac658SAlexey Kardashevskiy PPC_WARN_EMULATED(mfdscr, regs); 999efcac658SAlexey Kardashevskiy rd = (instword >> 21) & 0x1f; 1000efcac658SAlexey Kardashevskiy regs->gpr[rd] = mfspr(SPRN_DSCR); 1001efcac658SAlexey Kardashevskiy return 0; 1002efcac658SAlexey Kardashevskiy } 1003efcac658SAlexey Kardashevskiy /* Emulate the mtspr DSCR, rD. */ 100473d2fb75SAnton Blanchard if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 100573d2fb75SAnton Blanchard PPC_INST_MTSPR_DSCR_USER) || 100673d2fb75SAnton Blanchard ((instword & PPC_INST_MTSPR_DSCR_MASK) == 100773d2fb75SAnton Blanchard PPC_INST_MTSPR_DSCR)) && 1008efcac658SAlexey Kardashevskiy cpu_has_feature(CPU_FTR_DSCR)) { 1009efcac658SAlexey Kardashevskiy PPC_WARN_EMULATED(mtdscr, regs); 1010efcac658SAlexey Kardashevskiy rd = (instword >> 21) & 0x1f; 101100ca0de0SAnton Blanchard current->thread.dscr = regs->gpr[rd]; 1012efcac658SAlexey Kardashevskiy current->thread.dscr_inherit = 1; 101300ca0de0SAnton Blanchard mtspr(SPRN_DSCR, current->thread.dscr); 1014efcac658SAlexey Kardashevskiy return 0; 1015efcac658SAlexey Kardashevskiy } 1016efcac658SAlexey Kardashevskiy #endif 1017efcac658SAlexey Kardashevskiy 101814cf11afSPaul Mackerras return -EINVAL; 101914cf11afSPaul Mackerras } 102014cf11afSPaul Mackerras 102173c9ceabSJeremy Fitzhardinge int is_valid_bugaddr(unsigned long addr) 102214cf11afSPaul Mackerras { 102373c9ceabSJeremy Fitzhardinge return is_kernel_addr(addr); 102414cf11afSPaul Mackerras } 102514cf11afSPaul Mackerras 10263a3b5aa6SKevin Hao #ifdef CONFIG_MATH_EMULATION 10273a3b5aa6SKevin Hao static int emulate_math(struct pt_regs *regs) 10283a3b5aa6SKevin Hao { 10293a3b5aa6SKevin Hao int ret; 10303a3b5aa6SKevin Hao extern int do_mathemu(struct pt_regs *regs); 10313a3b5aa6SKevin Hao 10323a3b5aa6SKevin Hao ret = do_mathemu(regs); 10333a3b5aa6SKevin Hao if (ret >= 0) 10343a3b5aa6SKevin Hao PPC_WARN_EMULATED(math, regs); 10353a3b5aa6SKevin Hao 10363a3b5aa6SKevin Hao switch (ret) { 10373a3b5aa6SKevin Hao case 0: 10383a3b5aa6SKevin Hao emulate_single_step(regs); 10393a3b5aa6SKevin Hao return 0; 10403a3b5aa6SKevin Hao case 1: { 10413a3b5aa6SKevin Hao int code = 0; 1042de79f7b9SPaul Mackerras code = __parse_fpscr(current->thread.fp_state.fpscr); 10433a3b5aa6SKevin Hao _exception(SIGFPE, regs, code, regs->nip); 10443a3b5aa6SKevin Hao return 0; 10453a3b5aa6SKevin Hao } 10463a3b5aa6SKevin Hao case -EFAULT: 10473a3b5aa6SKevin Hao _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 10483a3b5aa6SKevin Hao return 0; 10493a3b5aa6SKevin Hao } 10503a3b5aa6SKevin Hao 10513a3b5aa6SKevin Hao return -1; 10523a3b5aa6SKevin Hao } 10533a3b5aa6SKevin Hao #else 10543a3b5aa6SKevin Hao static inline int emulate_math(struct pt_regs *regs) { return -1; } 10553a3b5aa6SKevin Hao #endif 10563a3b5aa6SKevin Hao 105703465f89SNicholas Piggin void program_check_exception(struct pt_regs *regs) 105814cf11afSPaul Mackerras { 1059ba12eedeSLi Zhong enum ctx_state prev_state = exception_enter(); 106014cf11afSPaul Mackerras unsigned int reason = get_reason(regs); 106114cf11afSPaul Mackerras 1062aa42c69cSKim Phillips /* We can now get here via a FP Unavailable exception if the core 106304903a30SKumar Gala * has no FPU, in that case the reason flags will be 0 */ 106414cf11afSPaul Mackerras 106514cf11afSPaul Mackerras if (reason & REASON_FP) { 106614cf11afSPaul Mackerras /* IEEE FP exception */ 1067dc1c1ca3SStephen Rothwell parse_fpe(regs); 1068ba12eedeSLi Zhong goto bail; 10698dad3f92SPaul Mackerras } 10708dad3f92SPaul Mackerras if (reason & REASON_TRAP) { 1071a4c3f909SBalbir Singh unsigned long bugaddr; 1072ba797b28SJason Wessel /* Debugger is first in line to stop recursive faults in 1073ba797b28SJason Wessel * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1074ba797b28SJason Wessel if (debugger_bpt(regs)) 1075ba12eedeSLi Zhong goto bail; 1076ba797b28SJason Wessel 10776cc89badSNaveen N. Rao if (kprobe_handler(regs)) 10786cc89badSNaveen N. Rao goto bail; 10796cc89badSNaveen N. Rao 108014cf11afSPaul Mackerras /* trap exception */ 1081dc1c1ca3SStephen Rothwell if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1082dc1c1ca3SStephen Rothwell == NOTIFY_STOP) 1083ba12eedeSLi Zhong goto bail; 108473c9ceabSJeremy Fitzhardinge 1085a4c3f909SBalbir Singh bugaddr = regs->nip; 1086a4c3f909SBalbir Singh /* 1087a4c3f909SBalbir Singh * Fixup bugaddr for BUG_ON() in real mode 1088a4c3f909SBalbir Singh */ 1089a4c3f909SBalbir Singh if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1090a4c3f909SBalbir Singh bugaddr += PAGE_OFFSET; 1091a4c3f909SBalbir Singh 109273c9ceabSJeremy Fitzhardinge if (!(regs->msr & MSR_PR) && /* not user-mode */ 1093a4c3f909SBalbir Singh report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 109414cf11afSPaul Mackerras regs->nip += 4; 1095ba12eedeSLi Zhong goto bail; 109614cf11afSPaul Mackerras } 10978dad3f92SPaul Mackerras _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1098ba12eedeSLi Zhong goto bail; 10998dad3f92SPaul Mackerras } 1100bc2a9408SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1101bc2a9408SMichael Neuling if (reason & REASON_TM) { 1102bc2a9408SMichael Neuling /* This is a TM "Bad Thing Exception" program check. 1103bc2a9408SMichael Neuling * This occurs when: 1104bc2a9408SMichael Neuling * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1105bc2a9408SMichael Neuling * transition in TM states. 1106bc2a9408SMichael Neuling * - A trechkpt is attempted when transactional. 1107bc2a9408SMichael Neuling * - A treclaim is attempted when non transactional. 1108bc2a9408SMichael Neuling * - A tend is illegally attempted. 1109bc2a9408SMichael Neuling * - writing a TM SPR when transactional. 1110bc2a9408SMichael Neuling */ 1111bc2a9408SMichael Neuling if (!user_mode(regs) && 1112bc2a9408SMichael Neuling report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 1113bc2a9408SMichael Neuling regs->nip += 4; 1114ba12eedeSLi Zhong goto bail; 1115bc2a9408SMichael Neuling } 1116bc2a9408SMichael Neuling /* If usermode caused this, it's done something illegal and 1117bc2a9408SMichael Neuling * gets a SIGILL slap on the wrist. We call it an illegal 1118bc2a9408SMichael Neuling * operand to distinguish from the instruction just being bad 1119bc2a9408SMichael Neuling * (e.g. executing a 'tend' on a CPU without TM!); it's an 1120bc2a9408SMichael Neuling * illegal /placement/ of a valid instruction. 1121bc2a9408SMichael Neuling */ 1122bc2a9408SMichael Neuling if (user_mode(regs)) { 1123bc2a9408SMichael Neuling _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1124ba12eedeSLi Zhong goto bail; 1125bc2a9408SMichael Neuling } else { 1126bc2a9408SMichael Neuling printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1127bc2a9408SMichael Neuling "at %lx (msr 0x%x)\n", regs->nip, reason); 1128bc2a9408SMichael Neuling die("Unrecoverable exception", regs, SIGABRT); 1129bc2a9408SMichael Neuling } 1130bc2a9408SMichael Neuling } 1131bc2a9408SMichael Neuling #endif 11328dad3f92SPaul Mackerras 1133b3f6a459SMichael Ellerman /* 1134b3f6a459SMichael Ellerman * If we took the program check in the kernel skip down to sending a 1135b3f6a459SMichael Ellerman * SIGILL. The subsequent cases all relate to emulating instructions 1136b3f6a459SMichael Ellerman * which we should only do for userspace. We also do not want to enable 1137b3f6a459SMichael Ellerman * interrupts for kernel faults because that might lead to further 1138b3f6a459SMichael Ellerman * faults, and loose the context of the original exception. 1139b3f6a459SMichael Ellerman */ 1140b3f6a459SMichael Ellerman if (!user_mode(regs)) 1141b3f6a459SMichael Ellerman goto sigill; 1142b3f6a459SMichael Ellerman 1143a3512b2dSBenjamin Herrenschmidt /* We restore the interrupt state now */ 1144a3512b2dSBenjamin Herrenschmidt if (!arch_irq_disabled_regs(regs)) 1145cd8a5673SPaul Mackerras local_irq_enable(); 1146cd8a5673SPaul Mackerras 114704903a30SKumar Gala /* (reason & REASON_ILLEGAL) would be the obvious thing here, 114804903a30SKumar Gala * but there seems to be a hardware bug on the 405GP (RevD) 114904903a30SKumar Gala * that means ESR is sometimes set incorrectly - either to 115004903a30SKumar Gala * ESR_DST (!?) or 0. In the process of chasing this with the 115104903a30SKumar Gala * hardware people - not sure if it can happen on any illegal 115204903a30SKumar Gala * instruction or only on FP instructions, whether there is a 11534e63f8edSBenjamin Herrenschmidt * pattern to occurrences etc. -dgibson 31/Mar/2003 11544e63f8edSBenjamin Herrenschmidt */ 11553a3b5aa6SKevin Hao if (!emulate_math(regs)) 1156ba12eedeSLi Zhong goto bail; 115704903a30SKumar Gala 11588dad3f92SPaul Mackerras /* Try to emulate it if we should. */ 11598dad3f92SPaul Mackerras if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 116014cf11afSPaul Mackerras switch (emulate_instruction(regs)) { 116114cf11afSPaul Mackerras case 0: 116214cf11afSPaul Mackerras regs->nip += 4; 116314cf11afSPaul Mackerras emulate_single_step(regs); 1164ba12eedeSLi Zhong goto bail; 116514cf11afSPaul Mackerras case -EFAULT: 116614cf11afSPaul Mackerras _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1167ba12eedeSLi Zhong goto bail; 11688dad3f92SPaul Mackerras } 11698dad3f92SPaul Mackerras } 11708dad3f92SPaul Mackerras 1171b3f6a459SMichael Ellerman sigill: 117214cf11afSPaul Mackerras if (reason & REASON_PRIVILEGED) 117314cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 117414cf11afSPaul Mackerras else 117514cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1176ba12eedeSLi Zhong 1177ba12eedeSLi Zhong bail: 1178ba12eedeSLi Zhong exception_exit(prev_state); 117914cf11afSPaul Mackerras } 118003465f89SNicholas Piggin NOKPROBE_SYMBOL(program_check_exception); 118114cf11afSPaul Mackerras 1182bf593907SPaul Mackerras /* 1183bf593907SPaul Mackerras * This occurs when running in hypervisor mode on POWER6 or later 1184bf593907SPaul Mackerras * and an illegal instruction is encountered. 1185bf593907SPaul Mackerras */ 118603465f89SNicholas Piggin void emulation_assist_interrupt(struct pt_regs *regs) 1187bf593907SPaul Mackerras { 1188bf593907SPaul Mackerras regs->msr |= REASON_ILLEGAL; 1189bf593907SPaul Mackerras program_check_exception(regs); 1190bf593907SPaul Mackerras } 119103465f89SNicholas Piggin NOKPROBE_SYMBOL(emulation_assist_interrupt); 1192bf593907SPaul Mackerras 1193dc1c1ca3SStephen Rothwell void alignment_exception(struct pt_regs *regs) 119414cf11afSPaul Mackerras { 1195ba12eedeSLi Zhong enum ctx_state prev_state = exception_enter(); 11964393c4f6SBenjamin Herrenschmidt int sig, code, fixed = 0; 119714cf11afSPaul Mackerras 1198a3512b2dSBenjamin Herrenschmidt /* We restore the interrupt state now */ 1199a3512b2dSBenjamin Herrenschmidt if (!arch_irq_disabled_regs(regs)) 1200a3512b2dSBenjamin Herrenschmidt local_irq_enable(); 1201a3512b2dSBenjamin Herrenschmidt 12026ce6c629SMichael Neuling if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 12036ce6c629SMichael Neuling goto bail; 12046ce6c629SMichael Neuling 1205e9370ae1SPaul Mackerras /* we don't implement logging of alignment exceptions */ 1206e9370ae1SPaul Mackerras if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 120714cf11afSPaul Mackerras fixed = fix_alignment(regs); 120814cf11afSPaul Mackerras 120914cf11afSPaul Mackerras if (fixed == 1) { 121014cf11afSPaul Mackerras regs->nip += 4; /* skip over emulated instruction */ 121114cf11afSPaul Mackerras emulate_single_step(regs); 1212ba12eedeSLi Zhong goto bail; 121314cf11afSPaul Mackerras } 121414cf11afSPaul Mackerras 121514cf11afSPaul Mackerras /* Operand address was bad */ 121614cf11afSPaul Mackerras if (fixed == -EFAULT) { 12174393c4f6SBenjamin Herrenschmidt sig = SIGSEGV; 12184393c4f6SBenjamin Herrenschmidt code = SEGV_ACCERR; 12194393c4f6SBenjamin Herrenschmidt } else { 12204393c4f6SBenjamin Herrenschmidt sig = SIGBUS; 12214393c4f6SBenjamin Herrenschmidt code = BUS_ADRALN; 122214cf11afSPaul Mackerras } 12234393c4f6SBenjamin Herrenschmidt if (user_mode(regs)) 12244393c4f6SBenjamin Herrenschmidt _exception(sig, regs, code, regs->dar); 12254393c4f6SBenjamin Herrenschmidt else 12264393c4f6SBenjamin Herrenschmidt bad_page_fault(regs, regs->dar, sig); 1227ba12eedeSLi Zhong 1228ba12eedeSLi Zhong bail: 1229ba12eedeSLi Zhong exception_exit(prev_state); 123014cf11afSPaul Mackerras } 123114cf11afSPaul Mackerras 1232f0f558b1SPaul Mackerras void slb_miss_bad_addr(struct pt_regs *regs) 1233f0f558b1SPaul Mackerras { 1234f0f558b1SPaul Mackerras enum ctx_state prev_state = exception_enter(); 1235f0f558b1SPaul Mackerras 1236f0f558b1SPaul Mackerras if (user_mode(regs)) 1237f0f558b1SPaul Mackerras _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar); 1238f0f558b1SPaul Mackerras else 1239f0f558b1SPaul Mackerras bad_page_fault(regs, regs->dar, SIGSEGV); 1240f0f558b1SPaul Mackerras 1241f0f558b1SPaul Mackerras exception_exit(prev_state); 1242f0f558b1SPaul Mackerras } 1243f0f558b1SPaul Mackerras 124414cf11afSPaul Mackerras void StackOverflow(struct pt_regs *regs) 124514cf11afSPaul Mackerras { 124614cf11afSPaul Mackerras printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 124714cf11afSPaul Mackerras current, regs->gpr[1]); 124814cf11afSPaul Mackerras debugger(regs); 124914cf11afSPaul Mackerras show_regs(regs); 125014cf11afSPaul Mackerras panic("kernel stack overflow"); 125114cf11afSPaul Mackerras } 125214cf11afSPaul Mackerras 125314cf11afSPaul Mackerras void nonrecoverable_exception(struct pt_regs *regs) 125414cf11afSPaul Mackerras { 125514cf11afSPaul Mackerras printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 125614cf11afSPaul Mackerras regs->nip, regs->msr); 125714cf11afSPaul Mackerras debugger(regs); 125814cf11afSPaul Mackerras die("nonrecoverable exception", regs, SIGKILL); 125914cf11afSPaul Mackerras } 126014cf11afSPaul Mackerras 1261dc1c1ca3SStephen Rothwell void kernel_fp_unavailable_exception(struct pt_regs *regs) 1262dc1c1ca3SStephen Rothwell { 1263ba12eedeSLi Zhong enum ctx_state prev_state = exception_enter(); 1264ba12eedeSLi Zhong 1265dc1c1ca3SStephen Rothwell printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1266dc1c1ca3SStephen Rothwell "%lx at %lx\n", regs->trap, regs->nip); 1267dc1c1ca3SStephen Rothwell die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1268ba12eedeSLi Zhong 1269ba12eedeSLi Zhong exception_exit(prev_state); 1270dc1c1ca3SStephen Rothwell } 1271dc1c1ca3SStephen Rothwell 1272dc1c1ca3SStephen Rothwell void altivec_unavailable_exception(struct pt_regs *regs) 1273dc1c1ca3SStephen Rothwell { 1274ba12eedeSLi Zhong enum ctx_state prev_state = exception_enter(); 1275ba12eedeSLi Zhong 1276dc1c1ca3SStephen Rothwell if (user_mode(regs)) { 1277dc1c1ca3SStephen Rothwell /* A user program has executed an altivec instruction, 1278dc1c1ca3SStephen Rothwell but this kernel doesn't support altivec. */ 1279dc1c1ca3SStephen Rothwell _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1280ba12eedeSLi Zhong goto bail; 1281dc1c1ca3SStephen Rothwell } 12826c4841c2SAnton Blanchard 1283dc1c1ca3SStephen Rothwell printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1284dc1c1ca3SStephen Rothwell "%lx at %lx\n", regs->trap, regs->nip); 1285dc1c1ca3SStephen Rothwell die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1286ba12eedeSLi Zhong 1287ba12eedeSLi Zhong bail: 1288ba12eedeSLi Zhong exception_exit(prev_state); 1289dc1c1ca3SStephen Rothwell } 1290dc1c1ca3SStephen Rothwell 1291ce48b210SMichael Neuling void vsx_unavailable_exception(struct pt_regs *regs) 1292ce48b210SMichael Neuling { 1293ce48b210SMichael Neuling if (user_mode(regs)) { 1294ce48b210SMichael Neuling /* A user program has executed an vsx instruction, 1295ce48b210SMichael Neuling but this kernel doesn't support vsx. */ 1296ce48b210SMichael Neuling _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1297ce48b210SMichael Neuling return; 1298ce48b210SMichael Neuling } 1299ce48b210SMichael Neuling 1300ce48b210SMichael Neuling printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1301ce48b210SMichael Neuling "%lx at %lx\n", regs->trap, regs->nip); 1302ce48b210SMichael Neuling die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1303ce48b210SMichael Neuling } 1304ce48b210SMichael Neuling 13052517617eSMichael Neuling #ifdef CONFIG_PPC64 1306172f7aaaSCyril Bur static void tm_unavailable(struct pt_regs *regs) 1307172f7aaaSCyril Bur { 13085d176f75SCyril Bur #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 13095d176f75SCyril Bur if (user_mode(regs)) { 13105d176f75SCyril Bur current->thread.load_tm++; 13115d176f75SCyril Bur regs->msr |= MSR_TM; 13125d176f75SCyril Bur tm_enable(); 13135d176f75SCyril Bur tm_restore_sprs(¤t->thread); 13145d176f75SCyril Bur return; 13155d176f75SCyril Bur } 13165d176f75SCyril Bur #endif 1317172f7aaaSCyril Bur pr_emerg("Unrecoverable TM Unavailable Exception " 1318172f7aaaSCyril Bur "%lx at %lx\n", regs->trap, regs->nip); 1319172f7aaaSCyril Bur die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1320172f7aaaSCyril Bur } 1321172f7aaaSCyril Bur 1322021424a1SMichael Ellerman void facility_unavailable_exception(struct pt_regs *regs) 1323d0c0c9a1SMichael Neuling { 1324021424a1SMichael Ellerman static char *facility_strings[] = { 13252517617eSMichael Neuling [FSCR_FP_LG] = "FPU", 13262517617eSMichael Neuling [FSCR_VECVSX_LG] = "VMX/VSX", 13272517617eSMichael Neuling [FSCR_DSCR_LG] = "DSCR", 13282517617eSMichael Neuling [FSCR_PM_LG] = "PMU SPRs", 13292517617eSMichael Neuling [FSCR_BHRB_LG] = "BHRB", 13302517617eSMichael Neuling [FSCR_TM_LG] = "TM", 13312517617eSMichael Neuling [FSCR_EBB_LG] = "EBB", 13322517617eSMichael Neuling [FSCR_TAR_LG] = "TAR", 1333794464f4SNicholas Piggin [FSCR_MSGP_LG] = "MSGP", 13349b7ff0c6SNicholas Piggin [FSCR_SCV_LG] = "SCV", 1335021424a1SMichael Ellerman }; 13362517617eSMichael Neuling char *facility = "unknown"; 1337021424a1SMichael Ellerman u64 value; 1338c952c1c4SAnshuman Khandual u32 instword, rd; 13392517617eSMichael Neuling u8 status; 13402517617eSMichael Neuling bool hv; 1341021424a1SMichael Ellerman 13422517617eSMichael Neuling hv = (regs->trap == 0xf80); 13432517617eSMichael Neuling if (hv) 1344b14b6260SMichael Ellerman value = mfspr(SPRN_HFSCR); 13452517617eSMichael Neuling else 13462517617eSMichael Neuling value = mfspr(SPRN_FSCR); 13472517617eSMichael Neuling 13482517617eSMichael Neuling status = value >> 56; 13492517617eSMichael Neuling if (status == FSCR_DSCR_LG) { 1350c952c1c4SAnshuman Khandual /* 1351c952c1c4SAnshuman Khandual * User is accessing the DSCR register using the problem 1352c952c1c4SAnshuman Khandual * state only SPR number (0x03) either through a mfspr or 1353c952c1c4SAnshuman Khandual * a mtspr instruction. If it is a write attempt through 1354c952c1c4SAnshuman Khandual * a mtspr, then we set the inherit bit. This also allows 1355c952c1c4SAnshuman Khandual * the user to write or read the register directly in the 1356c952c1c4SAnshuman Khandual * future by setting via the FSCR DSCR bit. But in case it 1357c952c1c4SAnshuman Khandual * is a read DSCR attempt through a mfspr instruction, we 1358c952c1c4SAnshuman Khandual * just emulate the instruction instead. This code path will 1359c952c1c4SAnshuman Khandual * always emulate all the mfspr instructions till the user 1360c952c1c4SAnshuman Khandual * has attempted at least one mtspr instruction. This way it 1361c952c1c4SAnshuman Khandual * preserves the same behaviour when the user is accessing 1362c952c1c4SAnshuman Khandual * the DSCR through privilege level only SPR number (0x11) 1363c952c1c4SAnshuman Khandual * which is emulated through illegal instruction exception. 1364c952c1c4SAnshuman Khandual * We always leave HFSCR DSCR set. 13652517617eSMichael Neuling */ 1366c952c1c4SAnshuman Khandual if (get_user(instword, (u32 __user *)(regs->nip))) { 1367c952c1c4SAnshuman Khandual pr_err("Failed to fetch the user instruction\n"); 1368c952c1c4SAnshuman Khandual return; 1369c952c1c4SAnshuman Khandual } 1370c952c1c4SAnshuman Khandual 1371c952c1c4SAnshuman Khandual /* Write into DSCR (mtspr 0x03, RS) */ 1372c952c1c4SAnshuman Khandual if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1373c952c1c4SAnshuman Khandual == PPC_INST_MTSPR_DSCR_USER) { 1374c952c1c4SAnshuman Khandual rd = (instword >> 21) & 0x1f; 1375c952c1c4SAnshuman Khandual current->thread.dscr = regs->gpr[rd]; 13762517617eSMichael Neuling current->thread.dscr_inherit = 1; 1377b57bd2deSMichael Neuling current->thread.fscr |= FSCR_DSCR; 1378b57bd2deSMichael Neuling mtspr(SPRN_FSCR, current->thread.fscr); 1379c952c1c4SAnshuman Khandual } 1380c952c1c4SAnshuman Khandual 1381c952c1c4SAnshuman Khandual /* Read from DSCR (mfspr RT, 0x03) */ 1382c952c1c4SAnshuman Khandual if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1383c952c1c4SAnshuman Khandual == PPC_INST_MFSPR_DSCR_USER) { 1384c952c1c4SAnshuman Khandual if (emulate_instruction(regs)) { 1385c952c1c4SAnshuman Khandual pr_err("DSCR based mfspr emulation failed\n"); 1386c952c1c4SAnshuman Khandual return; 1387c952c1c4SAnshuman Khandual } 1388c952c1c4SAnshuman Khandual regs->nip += 4; 1389c952c1c4SAnshuman Khandual emulate_single_step(regs); 1390c952c1c4SAnshuman Khandual } 13912517617eSMichael Neuling return; 1392b14b6260SMichael Ellerman } 1393b14b6260SMichael Ellerman 1394172f7aaaSCyril Bur if (status == FSCR_TM_LG) { 1395172f7aaaSCyril Bur /* 1396172f7aaaSCyril Bur * If we're here then the hardware is TM aware because it 1397172f7aaaSCyril Bur * generated an exception with FSRM_TM set. 1398172f7aaaSCyril Bur * 1399172f7aaaSCyril Bur * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1400172f7aaaSCyril Bur * told us not to do TM, or the kernel is not built with TM 1401172f7aaaSCyril Bur * support. 1402172f7aaaSCyril Bur * 1403172f7aaaSCyril Bur * If both of those things are true, then userspace can spam the 1404172f7aaaSCyril Bur * console by triggering the printk() below just by continually 1405172f7aaaSCyril Bur * doing tbegin (or any TM instruction). So in that case just 1406172f7aaaSCyril Bur * send the process a SIGILL immediately. 1407172f7aaaSCyril Bur */ 1408172f7aaaSCyril Bur if (!cpu_has_feature(CPU_FTR_TM)) 1409172f7aaaSCyril Bur goto out; 1410172f7aaaSCyril Bur 1411172f7aaaSCyril Bur tm_unavailable(regs); 1412172f7aaaSCyril Bur return; 1413172f7aaaSCyril Bur } 1414172f7aaaSCyril Bur 141593c2ec0fSBalbir Singh if ((hv || status >= 2) && 141693c2ec0fSBalbir Singh (status < ARRAY_SIZE(facility_strings)) && 14172517617eSMichael Neuling facility_strings[status]) 14182517617eSMichael Neuling facility = facility_strings[status]; 1419021424a1SMichael Ellerman 1420d0c0c9a1SMichael Neuling /* We restore the interrupt state now */ 1421d0c0c9a1SMichael Neuling if (!arch_irq_disabled_regs(regs)) 1422d0c0c9a1SMichael Neuling local_irq_enable(); 1423d0c0c9a1SMichael Neuling 142493c2ec0fSBalbir Singh pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 142593c2ec0fSBalbir Singh hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1426d0c0c9a1SMichael Neuling 1427172f7aaaSCyril Bur out: 1428d0c0c9a1SMichael Neuling if (user_mode(regs)) { 1429d0c0c9a1SMichael Neuling _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1430d0c0c9a1SMichael Neuling return; 1431d0c0c9a1SMichael Neuling } 1432d0c0c9a1SMichael Neuling 1433021424a1SMichael Ellerman die("Unexpected facility unavailable exception", regs, SIGABRT); 1434d0c0c9a1SMichael Neuling } 14352517617eSMichael Neuling #endif 1436d0c0c9a1SMichael Neuling 1437f54db641SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1438f54db641SMichael Neuling 1439f54db641SMichael Neuling void fp_unavailable_tm(struct pt_regs *regs) 1440f54db641SMichael Neuling { 1441f54db641SMichael Neuling /* Note: This does not handle any kind of FP laziness. */ 1442f54db641SMichael Neuling 1443f54db641SMichael Neuling TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1444f54db641SMichael Neuling regs->nip, regs->msr); 1445f54db641SMichael Neuling 1446f54db641SMichael Neuling /* We can only have got here if the task started using FP after 1447f54db641SMichael Neuling * beginning the transaction. So, the transactional regs are just a 1448f54db641SMichael Neuling * copy of the checkpointed ones. But, we still need to recheckpoint 1449f54db641SMichael Neuling * as we're enabling FP for the process; it will return, abort the 1450f54db641SMichael Neuling * transaction, and probably retry but now with FP enabled. So the 1451f54db641SMichael Neuling * checkpointed FP registers need to be loaded. 1452f54db641SMichael Neuling */ 1453d31626f7SPaul Mackerras tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1454f54db641SMichael Neuling /* Reclaim didn't save out any FPRs to transact_fprs. */ 1455f54db641SMichael Neuling 1456f54db641SMichael Neuling /* Enable FP for the task: */ 1457f54db641SMichael Neuling regs->msr |= (MSR_FP | current->thread.fpexc_mode); 1458f54db641SMichael Neuling 1459f54db641SMichael Neuling /* This loads and recheckpoints the FP registers from 1460f54db641SMichael Neuling * thread.fpr[]. They will remain in registers after the 1461f54db641SMichael Neuling * checkpoint so we don't need to reload them after. 14623ac8ff1cSPaul Mackerras * If VMX is in use, the VRs now hold checkpointed values, 14633ac8ff1cSPaul Mackerras * so we don't want to load the VRs from the thread_struct. 1464f54db641SMichael Neuling */ 14653ac8ff1cSPaul Mackerras tm_recheckpoint(¤t->thread, MSR_FP); 14663ac8ff1cSPaul Mackerras 14673ac8ff1cSPaul Mackerras /* If VMX is in use, get the transactional values back */ 14683ac8ff1cSPaul Mackerras if (regs->msr & MSR_VEC) { 1469dc310669SCyril Bur msr_check_and_set(MSR_VEC); 1470dc310669SCyril Bur load_vr_state(¤t->thread.vr_state); 14713ac8ff1cSPaul Mackerras /* At this point all the VSX state is loaded, so enable it */ 14723ac8ff1cSPaul Mackerras regs->msr |= MSR_VSX; 14733ac8ff1cSPaul Mackerras } 1474f54db641SMichael Neuling } 1475f54db641SMichael Neuling 1476f54db641SMichael Neuling void altivec_unavailable_tm(struct pt_regs *regs) 1477f54db641SMichael Neuling { 1478f54db641SMichael Neuling /* See the comments in fp_unavailable_tm(). This function operates 1479f54db641SMichael Neuling * the same way. 1480f54db641SMichael Neuling */ 1481f54db641SMichael Neuling 1482f54db641SMichael Neuling TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1483f54db641SMichael Neuling "MSR=%lx\n", 1484f54db641SMichael Neuling regs->nip, regs->msr); 1485d31626f7SPaul Mackerras tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1486f54db641SMichael Neuling regs->msr |= MSR_VEC; 14873ac8ff1cSPaul Mackerras tm_recheckpoint(¤t->thread, MSR_VEC); 1488f54db641SMichael Neuling current->thread.used_vr = 1; 1489f54db641SMichael Neuling 14903ac8ff1cSPaul Mackerras if (regs->msr & MSR_FP) { 1491dc310669SCyril Bur msr_check_and_set(MSR_FP); 1492dc310669SCyril Bur load_fp_state(¤t->thread.fp_state); 14933ac8ff1cSPaul Mackerras regs->msr |= MSR_VSX; 14943ac8ff1cSPaul Mackerras } 14953ac8ff1cSPaul Mackerras } 14963ac8ff1cSPaul Mackerras 1497f54db641SMichael Neuling void vsx_unavailable_tm(struct pt_regs *regs) 1498f54db641SMichael Neuling { 14993ac8ff1cSPaul Mackerras unsigned long orig_msr = regs->msr; 15003ac8ff1cSPaul Mackerras 1501f54db641SMichael Neuling /* See the comments in fp_unavailable_tm(). This works similarly, 1502f54db641SMichael Neuling * though we're loading both FP and VEC registers in here. 1503f54db641SMichael Neuling * 1504f54db641SMichael Neuling * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1505f54db641SMichael Neuling * regs. Either way, set MSR_VSX. 1506f54db641SMichael Neuling */ 1507f54db641SMichael Neuling 1508f54db641SMichael Neuling TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1509f54db641SMichael Neuling "MSR=%lx\n", 1510f54db641SMichael Neuling regs->nip, regs->msr); 1511f54db641SMichael Neuling 15123ac8ff1cSPaul Mackerras current->thread.used_vsr = 1; 15133ac8ff1cSPaul Mackerras 15143ac8ff1cSPaul Mackerras /* If FP and VMX are already loaded, we have all the state we need */ 15153ac8ff1cSPaul Mackerras if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) { 15163ac8ff1cSPaul Mackerras regs->msr |= MSR_VSX; 15173ac8ff1cSPaul Mackerras return; 15183ac8ff1cSPaul Mackerras } 15193ac8ff1cSPaul Mackerras 1520f54db641SMichael Neuling /* This reclaims FP and/or VR regs if they're already enabled */ 1521d31626f7SPaul Mackerras tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1522f54db641SMichael Neuling 1523f54db641SMichael Neuling regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | 1524f54db641SMichael Neuling MSR_VSX; 15253ac8ff1cSPaul Mackerras 15263ac8ff1cSPaul Mackerras /* This loads & recheckpoints FP and VRs; but we have 15273ac8ff1cSPaul Mackerras * to be sure not to overwrite previously-valid state. 15283ac8ff1cSPaul Mackerras */ 15293ac8ff1cSPaul Mackerras tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr); 15303ac8ff1cSPaul Mackerras 1531dc310669SCyril Bur msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC)); 1532dc310669SCyril Bur 15333ac8ff1cSPaul Mackerras if (orig_msr & MSR_FP) 1534dc310669SCyril Bur load_fp_state(¤t->thread.fp_state); 15353ac8ff1cSPaul Mackerras if (orig_msr & MSR_VEC) 1536dc310669SCyril Bur load_vr_state(¤t->thread.vr_state); 1537f54db641SMichael Neuling } 1538f54db641SMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1539f54db641SMichael Neuling 1540dc1c1ca3SStephen Rothwell void performance_monitor_exception(struct pt_regs *regs) 1541dc1c1ca3SStephen Rothwell { 154269111bacSChristoph Lameter __this_cpu_inc(irq_stat.pmu_irqs); 154389713ed1SAnton Blanchard 1544dc1c1ca3SStephen Rothwell perf_irq(regs); 1545dc1c1ca3SStephen Rothwell } 1546dc1c1ca3SStephen Rothwell 1547172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 15483bffb652SDave Kleikamp static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 15493bffb652SDave Kleikamp { 15503bffb652SDave Kleikamp int changed = 0; 15513bffb652SDave Kleikamp /* 15523bffb652SDave Kleikamp * Determine the cause of the debug event, clear the 15533bffb652SDave Kleikamp * event flags and send a trap to the handler. Torez 15543bffb652SDave Kleikamp */ 15553bffb652SDave Kleikamp if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 15563bffb652SDave Kleikamp dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 15573bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 155851ae8d4aSBharat Bhushan current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 15593bffb652SDave Kleikamp #endif 15603bffb652SDave Kleikamp do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, 15613bffb652SDave Kleikamp 5); 15623bffb652SDave Kleikamp changed |= 0x01; 15633bffb652SDave Kleikamp } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 15643bffb652SDave Kleikamp dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 15653bffb652SDave Kleikamp do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, 15663bffb652SDave Kleikamp 6); 15673bffb652SDave Kleikamp changed |= 0x01; 15683bffb652SDave Kleikamp } else if (debug_status & DBSR_IAC1) { 156951ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 15703bffb652SDave Kleikamp dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 15713bffb652SDave Kleikamp do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, 15723bffb652SDave Kleikamp 1); 15733bffb652SDave Kleikamp changed |= 0x01; 15743bffb652SDave Kleikamp } else if (debug_status & DBSR_IAC2) { 157551ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 15763bffb652SDave Kleikamp do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, 15773bffb652SDave Kleikamp 2); 15783bffb652SDave Kleikamp changed |= 0x01; 15793bffb652SDave Kleikamp } else if (debug_status & DBSR_IAC3) { 158051ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 15813bffb652SDave Kleikamp dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 15823bffb652SDave Kleikamp do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, 15833bffb652SDave Kleikamp 3); 15843bffb652SDave Kleikamp changed |= 0x01; 15853bffb652SDave Kleikamp } else if (debug_status & DBSR_IAC4) { 158651ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 15873bffb652SDave Kleikamp do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, 15883bffb652SDave Kleikamp 4); 15893bffb652SDave Kleikamp changed |= 0x01; 15903bffb652SDave Kleikamp } 15913bffb652SDave Kleikamp /* 15923bffb652SDave Kleikamp * At the point this routine was called, the MSR(DE) was turned off. 15933bffb652SDave Kleikamp * Check all other debug flags and see if that bit needs to be turned 15943bffb652SDave Kleikamp * back on or not. 15953bffb652SDave Kleikamp */ 159651ae8d4aSBharat Bhushan if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 159751ae8d4aSBharat Bhushan current->thread.debug.dbcr1)) 15983bffb652SDave Kleikamp regs->msr |= MSR_DE; 15993bffb652SDave Kleikamp else 16003bffb652SDave Kleikamp /* Make sure the IDM flag is off */ 160151ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IDM; 16023bffb652SDave Kleikamp 16033bffb652SDave Kleikamp if (changed & 0x01) 160451ae8d4aSBharat Bhushan mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 16053bffb652SDave Kleikamp } 160614cf11afSPaul Mackerras 160703465f89SNicholas Piggin void DebugException(struct pt_regs *regs, unsigned long debug_status) 160814cf11afSPaul Mackerras { 160951ae8d4aSBharat Bhushan current->thread.debug.dbsr = debug_status; 16103bffb652SDave Kleikamp 1611ec097c84SRoland McGrath /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1612ec097c84SRoland McGrath * on server, it stops on the target of the branch. In order to simulate 1613ec097c84SRoland McGrath * the server behaviour, we thus restart right away with a single step 1614ec097c84SRoland McGrath * instead of stopping here when hitting a BT 1615ec097c84SRoland McGrath */ 1616ec097c84SRoland McGrath if (debug_status & DBSR_BT) { 1617ec097c84SRoland McGrath regs->msr &= ~MSR_DE; 1618ec097c84SRoland McGrath 1619ec097c84SRoland McGrath /* Disable BT */ 1620ec097c84SRoland McGrath mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1621ec097c84SRoland McGrath /* Clear the BT event */ 1622ec097c84SRoland McGrath mtspr(SPRN_DBSR, DBSR_BT); 1623ec097c84SRoland McGrath 1624ec097c84SRoland McGrath /* Do the single step trick only when coming from userspace */ 1625ec097c84SRoland McGrath if (user_mode(regs)) { 162651ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_BT; 162751ae8d4aSBharat Bhushan current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1628ec097c84SRoland McGrath regs->msr |= MSR_DE; 1629ec097c84SRoland McGrath return; 1630ec097c84SRoland McGrath } 1631ec097c84SRoland McGrath 16326cc89badSNaveen N. Rao if (kprobe_post_handler(regs)) 16336cc89badSNaveen N. Rao return; 16346cc89badSNaveen N. Rao 1635ec097c84SRoland McGrath if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1636ec097c84SRoland McGrath 5, SIGTRAP) == NOTIFY_STOP) { 1637ec097c84SRoland McGrath return; 1638ec097c84SRoland McGrath } 1639ec097c84SRoland McGrath if (debugger_sstep(regs)) 1640ec097c84SRoland McGrath return; 1641ec097c84SRoland McGrath } else if (debug_status & DBSR_IC) { /* Instruction complete */ 164214cf11afSPaul Mackerras regs->msr &= ~MSR_DE; 1643f8279621SKumar Gala 164414cf11afSPaul Mackerras /* Disable instruction completion */ 164514cf11afSPaul Mackerras mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 164614cf11afSPaul Mackerras /* Clear the instruction completion event */ 164714cf11afSPaul Mackerras mtspr(SPRN_DBSR, DBSR_IC); 1648f8279621SKumar Gala 16496cc89badSNaveen N. Rao if (kprobe_post_handler(regs)) 16506cc89badSNaveen N. Rao return; 16516cc89badSNaveen N. Rao 1652f8279621SKumar Gala if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1653f8279621SKumar Gala 5, SIGTRAP) == NOTIFY_STOP) { 165414cf11afSPaul Mackerras return; 165514cf11afSPaul Mackerras } 1656f8279621SKumar Gala 1657f8279621SKumar Gala if (debugger_sstep(regs)) 1658f8279621SKumar Gala return; 1659f8279621SKumar Gala 16603bffb652SDave Kleikamp if (user_mode(regs)) { 166151ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IC; 166251ae8d4aSBharat Bhushan if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 166351ae8d4aSBharat Bhushan current->thread.debug.dbcr1)) 16643bffb652SDave Kleikamp regs->msr |= MSR_DE; 16653bffb652SDave Kleikamp else 16663bffb652SDave Kleikamp /* Make sure the IDM bit is off */ 166751ae8d4aSBharat Bhushan current->thread.debug.dbcr0 &= ~DBCR0_IDM; 16683bffb652SDave Kleikamp } 1669f8279621SKumar Gala 1670f8279621SKumar Gala _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 16713bffb652SDave Kleikamp } else 16723bffb652SDave Kleikamp handle_debug(regs, debug_status); 167314cf11afSPaul Mackerras } 167403465f89SNicholas Piggin NOKPROBE_SYMBOL(DebugException); 1675172ae2e7SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 167614cf11afSPaul Mackerras 167714cf11afSPaul Mackerras #if !defined(CONFIG_TAU_INT) 167814cf11afSPaul Mackerras void TAUException(struct pt_regs *regs) 167914cf11afSPaul Mackerras { 168014cf11afSPaul Mackerras printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 168114cf11afSPaul Mackerras regs->nip, regs->msr, regs->trap, print_tainted()); 168214cf11afSPaul Mackerras } 168314cf11afSPaul Mackerras #endif /* CONFIG_INT_TAU */ 168414cf11afSPaul Mackerras 168514cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 1686dc1c1ca3SStephen Rothwell void altivec_assist_exception(struct pt_regs *regs) 168714cf11afSPaul Mackerras { 168814cf11afSPaul Mackerras int err; 168914cf11afSPaul Mackerras 169014cf11afSPaul Mackerras if (!user_mode(regs)) { 169114cf11afSPaul Mackerras printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 169214cf11afSPaul Mackerras " at %lx\n", regs->nip); 16938dad3f92SPaul Mackerras die("Kernel VMX/Altivec assist exception", regs, SIGILL); 169414cf11afSPaul Mackerras } 169514cf11afSPaul Mackerras 1696dc1c1ca3SStephen Rothwell flush_altivec_to_thread(current); 1697dc1c1ca3SStephen Rothwell 1698eecff81dSAnton Blanchard PPC_WARN_EMULATED(altivec, regs); 169914cf11afSPaul Mackerras err = emulate_altivec(regs); 170014cf11afSPaul Mackerras if (err == 0) { 170114cf11afSPaul Mackerras regs->nip += 4; /* skip emulated instruction */ 170214cf11afSPaul Mackerras emulate_single_step(regs); 170314cf11afSPaul Mackerras return; 170414cf11afSPaul Mackerras } 170514cf11afSPaul Mackerras 170614cf11afSPaul Mackerras if (err == -EFAULT) { 170714cf11afSPaul Mackerras /* got an error reading the instruction */ 170814cf11afSPaul Mackerras _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 170914cf11afSPaul Mackerras } else { 171014cf11afSPaul Mackerras /* didn't recognize the instruction */ 171114cf11afSPaul Mackerras /* XXX quick hack for now: set the non-Java bit in the VSCR */ 171276462232SChristian Dietrich printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 171314cf11afSPaul Mackerras "in %s at %lx\n", current->comm, regs->nip); 1714de79f7b9SPaul Mackerras current->thread.vr_state.vscr.u[3] |= 0x10000; 171514cf11afSPaul Mackerras } 171614cf11afSPaul Mackerras } 171714cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 171814cf11afSPaul Mackerras 171914cf11afSPaul Mackerras #ifdef CONFIG_FSL_BOOKE 172014cf11afSPaul Mackerras void CacheLockingException(struct pt_regs *regs, unsigned long address, 172114cf11afSPaul Mackerras unsigned long error_code) 172214cf11afSPaul Mackerras { 172314cf11afSPaul Mackerras /* We treat cache locking instructions from the user 172414cf11afSPaul Mackerras * as priv ops, in the future we could try to do 172514cf11afSPaul Mackerras * something smarter 172614cf11afSPaul Mackerras */ 172714cf11afSPaul Mackerras if (error_code & (ESR_DLK|ESR_ILK)) 172814cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 172914cf11afSPaul Mackerras return; 173014cf11afSPaul Mackerras } 173114cf11afSPaul Mackerras #endif /* CONFIG_FSL_BOOKE */ 173214cf11afSPaul Mackerras 173314cf11afSPaul Mackerras #ifdef CONFIG_SPE 173414cf11afSPaul Mackerras void SPEFloatingPointException(struct pt_regs *regs) 173514cf11afSPaul Mackerras { 17366a800f36SLiu Yu extern int do_spe_mathemu(struct pt_regs *regs); 173714cf11afSPaul Mackerras unsigned long spefscr; 173814cf11afSPaul Mackerras int fpexc_mode; 173914cf11afSPaul Mackerras int code = 0; 17406a800f36SLiu Yu int err; 17416a800f36SLiu Yu 1742685659eeSyu liu flush_spe_to_thread(current); 174314cf11afSPaul Mackerras 174414cf11afSPaul Mackerras spefscr = current->thread.spefscr; 174514cf11afSPaul Mackerras fpexc_mode = current->thread.fpexc_mode; 174614cf11afSPaul Mackerras 174714cf11afSPaul Mackerras if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 174814cf11afSPaul Mackerras code = FPE_FLTOVF; 174914cf11afSPaul Mackerras } 175014cf11afSPaul Mackerras else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 175114cf11afSPaul Mackerras code = FPE_FLTUND; 175214cf11afSPaul Mackerras } 175314cf11afSPaul Mackerras else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 175414cf11afSPaul Mackerras code = FPE_FLTDIV; 175514cf11afSPaul Mackerras else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 175614cf11afSPaul Mackerras code = FPE_FLTINV; 175714cf11afSPaul Mackerras } 175814cf11afSPaul Mackerras else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 175914cf11afSPaul Mackerras code = FPE_FLTRES; 176014cf11afSPaul Mackerras 17616a800f36SLiu Yu err = do_spe_mathemu(regs); 17626a800f36SLiu Yu if (err == 0) { 17636a800f36SLiu Yu regs->nip += 4; /* skip emulated instruction */ 17646a800f36SLiu Yu emulate_single_step(regs); 176514cf11afSPaul Mackerras return; 176614cf11afSPaul Mackerras } 17676a800f36SLiu Yu 17686a800f36SLiu Yu if (err == -EFAULT) { 17696a800f36SLiu Yu /* got an error reading the instruction */ 17706a800f36SLiu Yu _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 17716a800f36SLiu Yu } else if (err == -EINVAL) { 17726a800f36SLiu Yu /* didn't recognize the instruction */ 17736a800f36SLiu Yu printk(KERN_ERR "unrecognized spe instruction " 17746a800f36SLiu Yu "in %s at %lx\n", current->comm, regs->nip); 17756a800f36SLiu Yu } else { 17766a800f36SLiu Yu _exception(SIGFPE, regs, code, regs->nip); 17776a800f36SLiu Yu } 17786a800f36SLiu Yu 17796a800f36SLiu Yu return; 17806a800f36SLiu Yu } 17816a800f36SLiu Yu 17826a800f36SLiu Yu void SPEFloatingPointRoundException(struct pt_regs *regs) 17836a800f36SLiu Yu { 17846a800f36SLiu Yu extern int speround_handler(struct pt_regs *regs); 17856a800f36SLiu Yu int err; 17866a800f36SLiu Yu 17876a800f36SLiu Yu preempt_disable(); 17886a800f36SLiu Yu if (regs->msr & MSR_SPE) 17896a800f36SLiu Yu giveup_spe(current); 17906a800f36SLiu Yu preempt_enable(); 17916a800f36SLiu Yu 17926a800f36SLiu Yu regs->nip -= 4; 17936a800f36SLiu Yu err = speround_handler(regs); 17946a800f36SLiu Yu if (err == 0) { 17956a800f36SLiu Yu regs->nip += 4; /* skip emulated instruction */ 17966a800f36SLiu Yu emulate_single_step(regs); 17976a800f36SLiu Yu return; 17986a800f36SLiu Yu } 17996a800f36SLiu Yu 18006a800f36SLiu Yu if (err == -EFAULT) { 18016a800f36SLiu Yu /* got an error reading the instruction */ 18026a800f36SLiu Yu _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 18036a800f36SLiu Yu } else if (err == -EINVAL) { 18046a800f36SLiu Yu /* didn't recognize the instruction */ 18056a800f36SLiu Yu printk(KERN_ERR "unrecognized spe instruction " 18066a800f36SLiu Yu "in %s at %lx\n", current->comm, regs->nip); 18076a800f36SLiu Yu } else { 18086a800f36SLiu Yu _exception(SIGFPE, regs, 0, regs->nip); 18096a800f36SLiu Yu return; 18106a800f36SLiu Yu } 18116a800f36SLiu Yu } 181214cf11afSPaul Mackerras #endif 181314cf11afSPaul Mackerras 1814dc1c1ca3SStephen Rothwell /* 1815dc1c1ca3SStephen Rothwell * We enter here if we get an unrecoverable exception, that is, one 1816dc1c1ca3SStephen Rothwell * that happened at a point where the RI (recoverable interrupt) bit 1817dc1c1ca3SStephen Rothwell * in the MSR is 0. This indicates that SRR0/1 are live, and that 1818dc1c1ca3SStephen Rothwell * we therefore lost state by taking this exception. 1819dc1c1ca3SStephen Rothwell */ 1820dc1c1ca3SStephen Rothwell void unrecoverable_exception(struct pt_regs *regs) 1821dc1c1ca3SStephen Rothwell { 1822dc1c1ca3SStephen Rothwell printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 1823dc1c1ca3SStephen Rothwell regs->trap, regs->nip); 1824dc1c1ca3SStephen Rothwell die("Unrecoverable exception", regs, SIGABRT); 1825dc1c1ca3SStephen Rothwell } 182615770a13SNaveen N. Rao NOKPROBE_SYMBOL(unrecoverable_exception); 1827dc1c1ca3SStephen Rothwell 18281e18c17aSJason Gunthorpe #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 182914cf11afSPaul Mackerras /* 183014cf11afSPaul Mackerras * Default handler for a Watchdog exception, 183114cf11afSPaul Mackerras * spins until a reboot occurs 183214cf11afSPaul Mackerras */ 183314cf11afSPaul Mackerras void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 183414cf11afSPaul Mackerras { 183514cf11afSPaul Mackerras /* Generic WatchdogHandler, implement your own */ 183614cf11afSPaul Mackerras mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 183714cf11afSPaul Mackerras return; 183814cf11afSPaul Mackerras } 183914cf11afSPaul Mackerras 184014cf11afSPaul Mackerras void WatchdogException(struct pt_regs *regs) 184114cf11afSPaul Mackerras { 184214cf11afSPaul Mackerras printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 184314cf11afSPaul Mackerras WatchdogHandler(regs); 184414cf11afSPaul Mackerras } 184514cf11afSPaul Mackerras #endif 1846dc1c1ca3SStephen Rothwell 1847dc1c1ca3SStephen Rothwell /* 1848dc1c1ca3SStephen Rothwell * We enter here if we discover during exception entry that we are 1849dc1c1ca3SStephen Rothwell * running in supervisor mode with a userspace value in the stack pointer. 1850dc1c1ca3SStephen Rothwell */ 1851dc1c1ca3SStephen Rothwell void kernel_bad_stack(struct pt_regs *regs) 1852dc1c1ca3SStephen Rothwell { 1853dc1c1ca3SStephen Rothwell printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 1854dc1c1ca3SStephen Rothwell regs->gpr[1], regs->nip); 1855dc1c1ca3SStephen Rothwell die("Bad kernel stack pointer", regs, SIGABRT); 1856dc1c1ca3SStephen Rothwell } 185715770a13SNaveen N. Rao NOKPROBE_SYMBOL(kernel_bad_stack); 185814cf11afSPaul Mackerras 185914cf11afSPaul Mackerras void __init trap_init(void) 186014cf11afSPaul Mackerras { 186114cf11afSPaul Mackerras } 186280947e7cSGeert Uytterhoeven 186380947e7cSGeert Uytterhoeven 186480947e7cSGeert Uytterhoeven #ifdef CONFIG_PPC_EMULATED_STATS 186580947e7cSGeert Uytterhoeven 186680947e7cSGeert Uytterhoeven #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 186780947e7cSGeert Uytterhoeven 186880947e7cSGeert Uytterhoeven struct ppc_emulated ppc_emulated = { 186980947e7cSGeert Uytterhoeven #ifdef CONFIG_ALTIVEC 187080947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(altivec), 187180947e7cSGeert Uytterhoeven #endif 187280947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(dcba), 187380947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(dcbz), 187480947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(fp_pair), 187580947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(isel), 187680947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(mcrxr), 187780947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(mfpvr), 187880947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(multiple), 187980947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(popcntb), 188080947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(spe), 188180947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(string), 1882a3821b2aSScott Wood WARN_EMULATED_SETUP(sync), 188380947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(unaligned), 188480947e7cSGeert Uytterhoeven #ifdef CONFIG_MATH_EMULATION 188580947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(math), 188680947e7cSGeert Uytterhoeven #endif 188780947e7cSGeert Uytterhoeven #ifdef CONFIG_VSX 188880947e7cSGeert Uytterhoeven WARN_EMULATED_SETUP(vsx), 188980947e7cSGeert Uytterhoeven #endif 1890efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64 1891efcac658SAlexey Kardashevskiy WARN_EMULATED_SETUP(mfdscr), 1892efcac658SAlexey Kardashevskiy WARN_EMULATED_SETUP(mtdscr), 1893f83319d7SAnton Blanchard WARN_EMULATED_SETUP(lq_stq), 1894efcac658SAlexey Kardashevskiy #endif 189580947e7cSGeert Uytterhoeven }; 189680947e7cSGeert Uytterhoeven 189780947e7cSGeert Uytterhoeven u32 ppc_warn_emulated; 189880947e7cSGeert Uytterhoeven 189980947e7cSGeert Uytterhoeven void ppc_warn_emulated_print(const char *type) 190080947e7cSGeert Uytterhoeven { 190176462232SChristian Dietrich pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 190280947e7cSGeert Uytterhoeven type); 190380947e7cSGeert Uytterhoeven } 190480947e7cSGeert Uytterhoeven 190580947e7cSGeert Uytterhoeven static int __init ppc_warn_emulated_init(void) 190680947e7cSGeert Uytterhoeven { 190780947e7cSGeert Uytterhoeven struct dentry *dir, *d; 190880947e7cSGeert Uytterhoeven unsigned int i; 190980947e7cSGeert Uytterhoeven struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 191080947e7cSGeert Uytterhoeven 191180947e7cSGeert Uytterhoeven if (!powerpc_debugfs_root) 191280947e7cSGeert Uytterhoeven return -ENODEV; 191380947e7cSGeert Uytterhoeven 191480947e7cSGeert Uytterhoeven dir = debugfs_create_dir("emulated_instructions", 191580947e7cSGeert Uytterhoeven powerpc_debugfs_root); 191680947e7cSGeert Uytterhoeven if (!dir) 191780947e7cSGeert Uytterhoeven return -ENOMEM; 191880947e7cSGeert Uytterhoeven 191980947e7cSGeert Uytterhoeven d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, 192080947e7cSGeert Uytterhoeven &ppc_warn_emulated); 192180947e7cSGeert Uytterhoeven if (!d) 192280947e7cSGeert Uytterhoeven goto fail; 192380947e7cSGeert Uytterhoeven 192480947e7cSGeert Uytterhoeven for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 192580947e7cSGeert Uytterhoeven d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, 192680947e7cSGeert Uytterhoeven (u32 *)&entries[i].val.counter); 192780947e7cSGeert Uytterhoeven if (!d) 192880947e7cSGeert Uytterhoeven goto fail; 192980947e7cSGeert Uytterhoeven } 193080947e7cSGeert Uytterhoeven 193180947e7cSGeert Uytterhoeven return 0; 193280947e7cSGeert Uytterhoeven 193380947e7cSGeert Uytterhoeven fail: 193480947e7cSGeert Uytterhoeven debugfs_remove_recursive(dir); 193580947e7cSGeert Uytterhoeven return -ENOMEM; 193680947e7cSGeert Uytterhoeven } 193780947e7cSGeert Uytterhoeven 193880947e7cSGeert Uytterhoeven device_initcall(ppc_warn_emulated_init); 193980947e7cSGeert Uytterhoeven 194080947e7cSGeert Uytterhoeven #endif /* CONFIG_PPC_EMULATED_STATS */ 1941