1*14cf11afSPaul Mackerras /* 2*14cf11afSPaul Mackerras * arch/powerpc/kernel/traps.c 3*14cf11afSPaul Mackerras * 4*14cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5*14cf11afSPaul Mackerras * 6*14cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 7*14cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 8*14cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 9*14cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 10*14cf11afSPaul Mackerras * 11*14cf11afSPaul Mackerras * Modified by Cort Dougan (cort@cs.nmt.edu) 12*14cf11afSPaul Mackerras * and Paul Mackerras (paulus@samba.org) 13*14cf11afSPaul Mackerras */ 14*14cf11afSPaul Mackerras 15*14cf11afSPaul Mackerras /* 16*14cf11afSPaul Mackerras * This file handles the architecture-dependent parts of hardware exceptions 17*14cf11afSPaul Mackerras */ 18*14cf11afSPaul Mackerras 19*14cf11afSPaul Mackerras #include <linux/config.h> 20*14cf11afSPaul Mackerras #include <linux/errno.h> 21*14cf11afSPaul Mackerras #include <linux/sched.h> 22*14cf11afSPaul Mackerras #include <linux/kernel.h> 23*14cf11afSPaul Mackerras #include <linux/mm.h> 24*14cf11afSPaul Mackerras #include <linux/stddef.h> 25*14cf11afSPaul Mackerras #include <linux/unistd.h> 26*14cf11afSPaul Mackerras #include <linux/ptrace.h> 27*14cf11afSPaul Mackerras #include <linux/slab.h> 28*14cf11afSPaul Mackerras #include <linux/user.h> 29*14cf11afSPaul Mackerras #include <linux/a.out.h> 30*14cf11afSPaul Mackerras #include <linux/interrupt.h> 31*14cf11afSPaul Mackerras #include <linux/config.h> 32*14cf11afSPaul Mackerras #include <linux/init.h> 33*14cf11afSPaul Mackerras #include <linux/module.h> 34*14cf11afSPaul Mackerras #include <linux/prctl.h> 35*14cf11afSPaul Mackerras #include <linux/delay.h> 36*14cf11afSPaul Mackerras #include <linux/kprobes.h> 37*14cf11afSPaul Mackerras #include <asm/kdebug.h> 38*14cf11afSPaul Mackerras 39*14cf11afSPaul Mackerras #include <asm/pgtable.h> 40*14cf11afSPaul Mackerras #include <asm/uaccess.h> 41*14cf11afSPaul Mackerras #include <asm/system.h> 42*14cf11afSPaul Mackerras #include <asm/io.h> 43*14cf11afSPaul Mackerras #include <asm/reg.h> 44*14cf11afSPaul Mackerras #include <asm/xmon.h> 45*14cf11afSPaul Mackerras #ifdef CONFIG_PMAC_BACKLIGHT 46*14cf11afSPaul Mackerras #include <asm/backlight.h> 47*14cf11afSPaul Mackerras #endif 48*14cf11afSPaul Mackerras #include <asm/perfmon.h> 49*14cf11afSPaul Mackerras 50*14cf11afSPaul Mackerras #ifdef CONFIG_DEBUGGER 51*14cf11afSPaul Mackerras int (*__debugger)(struct pt_regs *regs); 52*14cf11afSPaul Mackerras int (*__debugger_ipi)(struct pt_regs *regs); 53*14cf11afSPaul Mackerras int (*__debugger_bpt)(struct pt_regs *regs); 54*14cf11afSPaul Mackerras int (*__debugger_sstep)(struct pt_regs *regs); 55*14cf11afSPaul Mackerras int (*__debugger_iabr_match)(struct pt_regs *regs); 56*14cf11afSPaul Mackerras int (*__debugger_dabr_match)(struct pt_regs *regs); 57*14cf11afSPaul Mackerras int (*__debugger_fault_handler)(struct pt_regs *regs); 58*14cf11afSPaul Mackerras 59*14cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger); 60*14cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_ipi); 61*14cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_bpt); 62*14cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_sstep); 63*14cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_iabr_match); 64*14cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_dabr_match); 65*14cf11afSPaul Mackerras EXPORT_SYMBOL(__debugger_fault_handler); 66*14cf11afSPaul Mackerras #endif 67*14cf11afSPaul Mackerras 68*14cf11afSPaul Mackerras struct notifier_block *powerpc_die_chain; 69*14cf11afSPaul Mackerras static DEFINE_SPINLOCK(die_notifier_lock); 70*14cf11afSPaul Mackerras 71*14cf11afSPaul Mackerras int register_die_notifier(struct notifier_block *nb) 72*14cf11afSPaul Mackerras { 73*14cf11afSPaul Mackerras int err = 0; 74*14cf11afSPaul Mackerras unsigned long flags; 75*14cf11afSPaul Mackerras 76*14cf11afSPaul Mackerras spin_lock_irqsave(&die_notifier_lock, flags); 77*14cf11afSPaul Mackerras err = notifier_chain_register(&powerpc_die_chain, nb); 78*14cf11afSPaul Mackerras spin_unlock_irqrestore(&die_notifier_lock, flags); 79*14cf11afSPaul Mackerras return err; 80*14cf11afSPaul Mackerras } 81*14cf11afSPaul Mackerras 82*14cf11afSPaul Mackerras /* 83*14cf11afSPaul Mackerras * Trap & Exception support 84*14cf11afSPaul Mackerras */ 85*14cf11afSPaul Mackerras 86*14cf11afSPaul Mackerras static DEFINE_SPINLOCK(die_lock); 87*14cf11afSPaul Mackerras 88*14cf11afSPaul Mackerras int die(const char *str, struct pt_regs *regs, long err) 89*14cf11afSPaul Mackerras { 90*14cf11afSPaul Mackerras static int die_counter; 91*14cf11afSPaul Mackerras int nl = 0; 92*14cf11afSPaul Mackerras 93*14cf11afSPaul Mackerras if (debugger(regs)) 94*14cf11afSPaul Mackerras return 1; 95*14cf11afSPaul Mackerras 96*14cf11afSPaul Mackerras console_verbose(); 97*14cf11afSPaul Mackerras spin_lock_irq(&die_lock); 98*14cf11afSPaul Mackerras bust_spinlocks(1); 99*14cf11afSPaul Mackerras #ifdef CONFIG_PMAC_BACKLIGHT 100*14cf11afSPaul Mackerras if (_machine == _MACH_Pmac) { 101*14cf11afSPaul Mackerras set_backlight_enable(1); 102*14cf11afSPaul Mackerras set_backlight_level(BACKLIGHT_MAX); 103*14cf11afSPaul Mackerras } 104*14cf11afSPaul Mackerras #endif 105*14cf11afSPaul Mackerras printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 106*14cf11afSPaul Mackerras #ifdef CONFIG_PREEMPT 107*14cf11afSPaul Mackerras printk("PREEMPT "); 108*14cf11afSPaul Mackerras nl = 1; 109*14cf11afSPaul Mackerras #endif 110*14cf11afSPaul Mackerras #ifdef CONFIG_SMP 111*14cf11afSPaul Mackerras printk("SMP NR_CPUS=%d ", NR_CPUS); 112*14cf11afSPaul Mackerras nl = 1; 113*14cf11afSPaul Mackerras #endif 114*14cf11afSPaul Mackerras #ifdef CONFIG_DEBUG_PAGEALLOC 115*14cf11afSPaul Mackerras printk("DEBUG_PAGEALLOC "); 116*14cf11afSPaul Mackerras nl = 1; 117*14cf11afSPaul Mackerras #endif 118*14cf11afSPaul Mackerras #ifdef CONFIG_NUMA 119*14cf11afSPaul Mackerras printk("NUMA "); 120*14cf11afSPaul Mackerras nl = 1; 121*14cf11afSPaul Mackerras #endif 122*14cf11afSPaul Mackerras #ifdef CONFIG_PPC64 123*14cf11afSPaul Mackerras switch (systemcfg->platform) { 124*14cf11afSPaul Mackerras case PLATFORM_PSERIES: 125*14cf11afSPaul Mackerras printk("PSERIES "); 126*14cf11afSPaul Mackerras nl = 1; 127*14cf11afSPaul Mackerras break; 128*14cf11afSPaul Mackerras case PLATFORM_PSERIES_LPAR: 129*14cf11afSPaul Mackerras printk("PSERIES LPAR "); 130*14cf11afSPaul Mackerras nl = 1; 131*14cf11afSPaul Mackerras break; 132*14cf11afSPaul Mackerras case PLATFORM_ISERIES_LPAR: 133*14cf11afSPaul Mackerras printk("ISERIES LPAR "); 134*14cf11afSPaul Mackerras nl = 1; 135*14cf11afSPaul Mackerras break; 136*14cf11afSPaul Mackerras case PLATFORM_POWERMAC: 137*14cf11afSPaul Mackerras printk("POWERMAC "); 138*14cf11afSPaul Mackerras nl = 1; 139*14cf11afSPaul Mackerras break; 140*14cf11afSPaul Mackerras case PLATFORM_BPA: 141*14cf11afSPaul Mackerras printk("BPA "); 142*14cf11afSPaul Mackerras nl = 1; 143*14cf11afSPaul Mackerras break; 144*14cf11afSPaul Mackerras } 145*14cf11afSPaul Mackerras #endif 146*14cf11afSPaul Mackerras if (nl) 147*14cf11afSPaul Mackerras printk("\n"); 148*14cf11afSPaul Mackerras print_modules(); 149*14cf11afSPaul Mackerras show_regs(regs); 150*14cf11afSPaul Mackerras bust_spinlocks(0); 151*14cf11afSPaul Mackerras spin_unlock_irq(&die_lock); 152*14cf11afSPaul Mackerras 153*14cf11afSPaul Mackerras if (in_interrupt()) 154*14cf11afSPaul Mackerras panic("Fatal exception in interrupt"); 155*14cf11afSPaul Mackerras 156*14cf11afSPaul Mackerras if (panic_on_oops) { 157*14cf11afSPaul Mackerras panic("Fatal exception"); 158*14cf11afSPaul Mackerras } 159*14cf11afSPaul Mackerras do_exit(err); 160*14cf11afSPaul Mackerras 161*14cf11afSPaul Mackerras return 0; 162*14cf11afSPaul Mackerras } 163*14cf11afSPaul Mackerras 164*14cf11afSPaul Mackerras void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 165*14cf11afSPaul Mackerras { 166*14cf11afSPaul Mackerras siginfo_t info; 167*14cf11afSPaul Mackerras 168*14cf11afSPaul Mackerras if (!user_mode(regs)) { 169*14cf11afSPaul Mackerras if (die("Exception in kernel mode", regs, signr)) 170*14cf11afSPaul Mackerras return; 171*14cf11afSPaul Mackerras } 172*14cf11afSPaul Mackerras 173*14cf11afSPaul Mackerras memset(&info, 0, sizeof(info)); 174*14cf11afSPaul Mackerras info.si_signo = signr; 175*14cf11afSPaul Mackerras info.si_code = code; 176*14cf11afSPaul Mackerras info.si_addr = (void __user *) addr; 177*14cf11afSPaul Mackerras force_sig_info(signr, &info, current); 178*14cf11afSPaul Mackerras 179*14cf11afSPaul Mackerras /* 180*14cf11afSPaul Mackerras * Init gets no signals that it doesn't have a handler for. 181*14cf11afSPaul Mackerras * That's all very well, but if it has caused a synchronous 182*14cf11afSPaul Mackerras * exception and we ignore the resulting signal, it will just 183*14cf11afSPaul Mackerras * generate the same exception over and over again and we get 184*14cf11afSPaul Mackerras * nowhere. Better to kill it and let the kernel panic. 185*14cf11afSPaul Mackerras */ 186*14cf11afSPaul Mackerras if (current->pid == 1) { 187*14cf11afSPaul Mackerras __sighandler_t handler; 188*14cf11afSPaul Mackerras 189*14cf11afSPaul Mackerras spin_lock_irq(¤t->sighand->siglock); 190*14cf11afSPaul Mackerras handler = current->sighand->action[signr-1].sa.sa_handler; 191*14cf11afSPaul Mackerras spin_unlock_irq(¤t->sighand->siglock); 192*14cf11afSPaul Mackerras if (handler == SIG_DFL) { 193*14cf11afSPaul Mackerras /* init has generated a synchronous exception 194*14cf11afSPaul Mackerras and it doesn't have a handler for the signal */ 195*14cf11afSPaul Mackerras printk(KERN_CRIT "init has generated signal %d " 196*14cf11afSPaul Mackerras "but has no handler for it\n", signr); 197*14cf11afSPaul Mackerras do_exit(signr); 198*14cf11afSPaul Mackerras } 199*14cf11afSPaul Mackerras } 200*14cf11afSPaul Mackerras } 201*14cf11afSPaul Mackerras 202*14cf11afSPaul Mackerras #ifdef CONFIG_PPC64 203*14cf11afSPaul Mackerras void system_reset_exception(struct pt_regs *regs) 204*14cf11afSPaul Mackerras { 205*14cf11afSPaul Mackerras /* See if any machine dependent calls */ 206*14cf11afSPaul Mackerras if (ppc_md.system_reset_exception) 207*14cf11afSPaul Mackerras ppc_md.system_reset_exception(regs); 208*14cf11afSPaul Mackerras 209*14cf11afSPaul Mackerras die("System Reset", regs, SIGABRT); 210*14cf11afSPaul Mackerras 211*14cf11afSPaul Mackerras /* Must die if the interrupt is not recoverable */ 212*14cf11afSPaul Mackerras if (!(regs->msr & MSR_RI)) 213*14cf11afSPaul Mackerras panic("Unrecoverable System Reset"); 214*14cf11afSPaul Mackerras 215*14cf11afSPaul Mackerras /* What should we do here? We could issue a shutdown or hard reset. */ 216*14cf11afSPaul Mackerras } 217*14cf11afSPaul Mackerras #endif 218*14cf11afSPaul Mackerras 219*14cf11afSPaul Mackerras /* 220*14cf11afSPaul Mackerras * I/O accesses can cause machine checks on powermacs. 221*14cf11afSPaul Mackerras * Check if the NIP corresponds to the address of a sync 222*14cf11afSPaul Mackerras * instruction for which there is an entry in the exception 223*14cf11afSPaul Mackerras * table. 224*14cf11afSPaul Mackerras * Note that the 601 only takes a machine check on TEA 225*14cf11afSPaul Mackerras * (transfer error ack) signal assertion, and does not 226*14cf11afSPaul Mackerras * set any of the top 16 bits of SRR1. 227*14cf11afSPaul Mackerras * -- paulus. 228*14cf11afSPaul Mackerras */ 229*14cf11afSPaul Mackerras static inline int check_io_access(struct pt_regs *regs) 230*14cf11afSPaul Mackerras { 231*14cf11afSPaul Mackerras #ifdef CONFIG_PPC_PMAC 232*14cf11afSPaul Mackerras unsigned long msr = regs->msr; 233*14cf11afSPaul Mackerras const struct exception_table_entry *entry; 234*14cf11afSPaul Mackerras unsigned int *nip = (unsigned int *)regs->nip; 235*14cf11afSPaul Mackerras 236*14cf11afSPaul Mackerras if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 237*14cf11afSPaul Mackerras && (entry = search_exception_tables(regs->nip)) != NULL) { 238*14cf11afSPaul Mackerras /* 239*14cf11afSPaul Mackerras * Check that it's a sync instruction, or somewhere 240*14cf11afSPaul Mackerras * in the twi; isync; nop sequence that inb/inw/inl uses. 241*14cf11afSPaul Mackerras * As the address is in the exception table 242*14cf11afSPaul Mackerras * we should be able to read the instr there. 243*14cf11afSPaul Mackerras * For the debug message, we look at the preceding 244*14cf11afSPaul Mackerras * load or store. 245*14cf11afSPaul Mackerras */ 246*14cf11afSPaul Mackerras if (*nip == 0x60000000) /* nop */ 247*14cf11afSPaul Mackerras nip -= 2; 248*14cf11afSPaul Mackerras else if (*nip == 0x4c00012c) /* isync */ 249*14cf11afSPaul Mackerras --nip; 250*14cf11afSPaul Mackerras if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { 251*14cf11afSPaul Mackerras /* sync or twi */ 252*14cf11afSPaul Mackerras unsigned int rb; 253*14cf11afSPaul Mackerras 254*14cf11afSPaul Mackerras --nip; 255*14cf11afSPaul Mackerras rb = (*nip >> 11) & 0x1f; 256*14cf11afSPaul Mackerras printk(KERN_DEBUG "%s bad port %lx at %p\n", 257*14cf11afSPaul Mackerras (*nip & 0x100)? "OUT to": "IN from", 258*14cf11afSPaul Mackerras regs->gpr[rb] - _IO_BASE, nip); 259*14cf11afSPaul Mackerras regs->msr |= MSR_RI; 260*14cf11afSPaul Mackerras regs->nip = entry->fixup; 261*14cf11afSPaul Mackerras return 1; 262*14cf11afSPaul Mackerras } 263*14cf11afSPaul Mackerras } 264*14cf11afSPaul Mackerras #endif /* CONFIG_PPC_PMAC */ 265*14cf11afSPaul Mackerras return 0; 266*14cf11afSPaul Mackerras } 267*14cf11afSPaul Mackerras 268*14cf11afSPaul Mackerras #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 269*14cf11afSPaul Mackerras /* On 4xx, the reason for the machine check or program exception 270*14cf11afSPaul Mackerras is in the ESR. */ 271*14cf11afSPaul Mackerras #define get_reason(regs) ((regs)->dsisr) 272*14cf11afSPaul Mackerras #ifndef CONFIG_FSL_BOOKE 273*14cf11afSPaul Mackerras #define get_mc_reason(regs) ((regs)->dsisr) 274*14cf11afSPaul Mackerras #else 275*14cf11afSPaul Mackerras #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) 276*14cf11afSPaul Mackerras #endif 277*14cf11afSPaul Mackerras #define REASON_FP ESR_FP 278*14cf11afSPaul Mackerras #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 279*14cf11afSPaul Mackerras #define REASON_PRIVILEGED ESR_PPR 280*14cf11afSPaul Mackerras #define REASON_TRAP ESR_PTR 281*14cf11afSPaul Mackerras 282*14cf11afSPaul Mackerras /* single-step stuff */ 283*14cf11afSPaul Mackerras #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) 284*14cf11afSPaul Mackerras #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) 285*14cf11afSPaul Mackerras 286*14cf11afSPaul Mackerras #else 287*14cf11afSPaul Mackerras /* On non-4xx, the reason for the machine check or program 288*14cf11afSPaul Mackerras exception is in the MSR. */ 289*14cf11afSPaul Mackerras #define get_reason(regs) ((regs)->msr) 290*14cf11afSPaul Mackerras #define get_mc_reason(regs) ((regs)->msr) 291*14cf11afSPaul Mackerras #define REASON_FP 0x100000 292*14cf11afSPaul Mackerras #define REASON_ILLEGAL 0x80000 293*14cf11afSPaul Mackerras #define REASON_PRIVILEGED 0x40000 294*14cf11afSPaul Mackerras #define REASON_TRAP 0x20000 295*14cf11afSPaul Mackerras 296*14cf11afSPaul Mackerras #define single_stepping(regs) ((regs)->msr & MSR_SE) 297*14cf11afSPaul Mackerras #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 298*14cf11afSPaul Mackerras #endif 299*14cf11afSPaul Mackerras 300*14cf11afSPaul Mackerras /* 301*14cf11afSPaul Mackerras * This is "fall-back" implementation for configurations 302*14cf11afSPaul Mackerras * which don't provide platform-specific machine check info 303*14cf11afSPaul Mackerras */ 304*14cf11afSPaul Mackerras void __attribute__ ((weak)) 305*14cf11afSPaul Mackerras platform_machine_check(struct pt_regs *regs) 306*14cf11afSPaul Mackerras { 307*14cf11afSPaul Mackerras } 308*14cf11afSPaul Mackerras 309*14cf11afSPaul Mackerras void MachineCheckException(struct pt_regs *regs) 310*14cf11afSPaul Mackerras { 311*14cf11afSPaul Mackerras #ifdef CONFIG_PPC64 312*14cf11afSPaul Mackerras int recover = 0; 313*14cf11afSPaul Mackerras 314*14cf11afSPaul Mackerras /* See if any machine dependent calls */ 315*14cf11afSPaul Mackerras if (ppc_md.machine_check_exception) 316*14cf11afSPaul Mackerras recover = ppc_md.machine_check_exception(regs); 317*14cf11afSPaul Mackerras 318*14cf11afSPaul Mackerras if (recover) 319*14cf11afSPaul Mackerras return; 320*14cf11afSPaul Mackerras #else 321*14cf11afSPaul Mackerras unsigned long reason = get_mc_reason(regs); 322*14cf11afSPaul Mackerras 323*14cf11afSPaul Mackerras if (user_mode(regs)) { 324*14cf11afSPaul Mackerras regs->msr |= MSR_RI; 325*14cf11afSPaul Mackerras _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); 326*14cf11afSPaul Mackerras return; 327*14cf11afSPaul Mackerras } 328*14cf11afSPaul Mackerras 329*14cf11afSPaul Mackerras #if defined(CONFIG_8xx) && defined(CONFIG_PCI) 330*14cf11afSPaul Mackerras /* the qspan pci read routines can cause machine checks -- Cort */ 331*14cf11afSPaul Mackerras bad_page_fault(regs, regs->dar, SIGBUS); 332*14cf11afSPaul Mackerras return; 333*14cf11afSPaul Mackerras #endif 334*14cf11afSPaul Mackerras 335*14cf11afSPaul Mackerras if (debugger_fault_handler(regs)) { 336*14cf11afSPaul Mackerras regs->msr |= MSR_RI; 337*14cf11afSPaul Mackerras return; 338*14cf11afSPaul Mackerras } 339*14cf11afSPaul Mackerras 340*14cf11afSPaul Mackerras if (check_io_access(regs)) 341*14cf11afSPaul Mackerras return; 342*14cf11afSPaul Mackerras 343*14cf11afSPaul Mackerras #if defined(CONFIG_4xx) && !defined(CONFIG_440A) 344*14cf11afSPaul Mackerras if (reason & ESR_IMCP) { 345*14cf11afSPaul Mackerras printk("Instruction"); 346*14cf11afSPaul Mackerras mtspr(SPRN_ESR, reason & ~ESR_IMCP); 347*14cf11afSPaul Mackerras } else 348*14cf11afSPaul Mackerras printk("Data"); 349*14cf11afSPaul Mackerras printk(" machine check in kernel mode.\n"); 350*14cf11afSPaul Mackerras #elif defined(CONFIG_440A) 351*14cf11afSPaul Mackerras printk("Machine check in kernel mode.\n"); 352*14cf11afSPaul Mackerras if (reason & ESR_IMCP){ 353*14cf11afSPaul Mackerras printk("Instruction Synchronous Machine Check exception\n"); 354*14cf11afSPaul Mackerras mtspr(SPRN_ESR, reason & ~ESR_IMCP); 355*14cf11afSPaul Mackerras } 356*14cf11afSPaul Mackerras else { 357*14cf11afSPaul Mackerras u32 mcsr = mfspr(SPRN_MCSR); 358*14cf11afSPaul Mackerras if (mcsr & MCSR_IB) 359*14cf11afSPaul Mackerras printk("Instruction Read PLB Error\n"); 360*14cf11afSPaul Mackerras if (mcsr & MCSR_DRB) 361*14cf11afSPaul Mackerras printk("Data Read PLB Error\n"); 362*14cf11afSPaul Mackerras if (mcsr & MCSR_DWB) 363*14cf11afSPaul Mackerras printk("Data Write PLB Error\n"); 364*14cf11afSPaul Mackerras if (mcsr & MCSR_TLBP) 365*14cf11afSPaul Mackerras printk("TLB Parity Error\n"); 366*14cf11afSPaul Mackerras if (mcsr & MCSR_ICP){ 367*14cf11afSPaul Mackerras flush_instruction_cache(); 368*14cf11afSPaul Mackerras printk("I-Cache Parity Error\n"); 369*14cf11afSPaul Mackerras } 370*14cf11afSPaul Mackerras if (mcsr & MCSR_DCSP) 371*14cf11afSPaul Mackerras printk("D-Cache Search Parity Error\n"); 372*14cf11afSPaul Mackerras if (mcsr & MCSR_DCFP) 373*14cf11afSPaul Mackerras printk("D-Cache Flush Parity Error\n"); 374*14cf11afSPaul Mackerras if (mcsr & MCSR_IMPE) 375*14cf11afSPaul Mackerras printk("Machine Check exception is imprecise\n"); 376*14cf11afSPaul Mackerras 377*14cf11afSPaul Mackerras /* Clear MCSR */ 378*14cf11afSPaul Mackerras mtspr(SPRN_MCSR, mcsr); 379*14cf11afSPaul Mackerras } 380*14cf11afSPaul Mackerras #elif defined (CONFIG_E500) 381*14cf11afSPaul Mackerras printk("Machine check in kernel mode.\n"); 382*14cf11afSPaul Mackerras printk("Caused by (from MCSR=%lx): ", reason); 383*14cf11afSPaul Mackerras 384*14cf11afSPaul Mackerras if (reason & MCSR_MCP) 385*14cf11afSPaul Mackerras printk("Machine Check Signal\n"); 386*14cf11afSPaul Mackerras if (reason & MCSR_ICPERR) 387*14cf11afSPaul Mackerras printk("Instruction Cache Parity Error\n"); 388*14cf11afSPaul Mackerras if (reason & MCSR_DCP_PERR) 389*14cf11afSPaul Mackerras printk("Data Cache Push Parity Error\n"); 390*14cf11afSPaul Mackerras if (reason & MCSR_DCPERR) 391*14cf11afSPaul Mackerras printk("Data Cache Parity Error\n"); 392*14cf11afSPaul Mackerras if (reason & MCSR_GL_CI) 393*14cf11afSPaul Mackerras printk("Guarded Load or Cache-Inhibited stwcx.\n"); 394*14cf11afSPaul Mackerras if (reason & MCSR_BUS_IAERR) 395*14cf11afSPaul Mackerras printk("Bus - Instruction Address Error\n"); 396*14cf11afSPaul Mackerras if (reason & MCSR_BUS_RAERR) 397*14cf11afSPaul Mackerras printk("Bus - Read Address Error\n"); 398*14cf11afSPaul Mackerras if (reason & MCSR_BUS_WAERR) 399*14cf11afSPaul Mackerras printk("Bus - Write Address Error\n"); 400*14cf11afSPaul Mackerras if (reason & MCSR_BUS_IBERR) 401*14cf11afSPaul Mackerras printk("Bus - Instruction Data Error\n"); 402*14cf11afSPaul Mackerras if (reason & MCSR_BUS_RBERR) 403*14cf11afSPaul Mackerras printk("Bus - Read Data Bus Error\n"); 404*14cf11afSPaul Mackerras if (reason & MCSR_BUS_WBERR) 405*14cf11afSPaul Mackerras printk("Bus - Read Data Bus Error\n"); 406*14cf11afSPaul Mackerras if (reason & MCSR_BUS_IPERR) 407*14cf11afSPaul Mackerras printk("Bus - Instruction Parity Error\n"); 408*14cf11afSPaul Mackerras if (reason & MCSR_BUS_RPERR) 409*14cf11afSPaul Mackerras printk("Bus - Read Parity Error\n"); 410*14cf11afSPaul Mackerras #elif defined (CONFIG_E200) 411*14cf11afSPaul Mackerras printk("Machine check in kernel mode.\n"); 412*14cf11afSPaul Mackerras printk("Caused by (from MCSR=%lx): ", reason); 413*14cf11afSPaul Mackerras 414*14cf11afSPaul Mackerras if (reason & MCSR_MCP) 415*14cf11afSPaul Mackerras printk("Machine Check Signal\n"); 416*14cf11afSPaul Mackerras if (reason & MCSR_CP_PERR) 417*14cf11afSPaul Mackerras printk("Cache Push Parity Error\n"); 418*14cf11afSPaul Mackerras if (reason & MCSR_CPERR) 419*14cf11afSPaul Mackerras printk("Cache Parity Error\n"); 420*14cf11afSPaul Mackerras if (reason & MCSR_EXCP_ERR) 421*14cf11afSPaul Mackerras printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 422*14cf11afSPaul Mackerras if (reason & MCSR_BUS_IRERR) 423*14cf11afSPaul Mackerras printk("Bus - Read Bus Error on instruction fetch\n"); 424*14cf11afSPaul Mackerras if (reason & MCSR_BUS_DRERR) 425*14cf11afSPaul Mackerras printk("Bus - Read Bus Error on data load\n"); 426*14cf11afSPaul Mackerras if (reason & MCSR_BUS_WRERR) 427*14cf11afSPaul Mackerras printk("Bus - Write Bus Error on buffered store or cache line push\n"); 428*14cf11afSPaul Mackerras #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */ 429*14cf11afSPaul Mackerras printk("Machine check in kernel mode.\n"); 430*14cf11afSPaul Mackerras printk("Caused by (from SRR1=%lx): ", reason); 431*14cf11afSPaul Mackerras switch (reason & 0x601F0000) { 432*14cf11afSPaul Mackerras case 0x80000: 433*14cf11afSPaul Mackerras printk("Machine check signal\n"); 434*14cf11afSPaul Mackerras break; 435*14cf11afSPaul Mackerras case 0: /* for 601 */ 436*14cf11afSPaul Mackerras case 0x40000: 437*14cf11afSPaul Mackerras case 0x140000: /* 7450 MSS error and TEA */ 438*14cf11afSPaul Mackerras printk("Transfer error ack signal\n"); 439*14cf11afSPaul Mackerras break; 440*14cf11afSPaul Mackerras case 0x20000: 441*14cf11afSPaul Mackerras printk("Data parity error signal\n"); 442*14cf11afSPaul Mackerras break; 443*14cf11afSPaul Mackerras case 0x10000: 444*14cf11afSPaul Mackerras printk("Address parity error signal\n"); 445*14cf11afSPaul Mackerras break; 446*14cf11afSPaul Mackerras case 0x20000000: 447*14cf11afSPaul Mackerras printk("L1 Data Cache error\n"); 448*14cf11afSPaul Mackerras break; 449*14cf11afSPaul Mackerras case 0x40000000: 450*14cf11afSPaul Mackerras printk("L1 Instruction Cache error\n"); 451*14cf11afSPaul Mackerras break; 452*14cf11afSPaul Mackerras case 0x00100000: 453*14cf11afSPaul Mackerras printk("L2 data cache parity error\n"); 454*14cf11afSPaul Mackerras break; 455*14cf11afSPaul Mackerras default: 456*14cf11afSPaul Mackerras printk("Unknown values in msr\n"); 457*14cf11afSPaul Mackerras } 458*14cf11afSPaul Mackerras #endif /* CONFIG_4xx */ 459*14cf11afSPaul Mackerras 460*14cf11afSPaul Mackerras /* 461*14cf11afSPaul Mackerras * Optional platform-provided routine to print out 462*14cf11afSPaul Mackerras * additional info, e.g. bus error registers. 463*14cf11afSPaul Mackerras */ 464*14cf11afSPaul Mackerras platform_machine_check(regs); 465*14cf11afSPaul Mackerras #endif /* CONFIG_PPC64 */ 466*14cf11afSPaul Mackerras 467*14cf11afSPaul Mackerras if (debugger_fault_handler(regs)) 468*14cf11afSPaul Mackerras return; 469*14cf11afSPaul Mackerras die("Machine check", regs, SIGBUS); 470*14cf11afSPaul Mackerras 471*14cf11afSPaul Mackerras /* Must die if the interrupt is not recoverable */ 472*14cf11afSPaul Mackerras if (!(regs->msr & MSR_RI)) 473*14cf11afSPaul Mackerras panic("Unrecoverable Machine check"); 474*14cf11afSPaul Mackerras } 475*14cf11afSPaul Mackerras 476*14cf11afSPaul Mackerras void SMIException(struct pt_regs *regs) 477*14cf11afSPaul Mackerras { 478*14cf11afSPaul Mackerras die("System Management Interrupt", regs, SIGABRT); 479*14cf11afSPaul Mackerras } 480*14cf11afSPaul Mackerras 481*14cf11afSPaul Mackerras void UnknownException(struct pt_regs *regs) 482*14cf11afSPaul Mackerras { 483*14cf11afSPaul Mackerras printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 484*14cf11afSPaul Mackerras regs->nip, regs->msr, regs->trap); 485*14cf11afSPaul Mackerras 486*14cf11afSPaul Mackerras _exception(SIGTRAP, regs, 0, 0); 487*14cf11afSPaul Mackerras } 488*14cf11afSPaul Mackerras 489*14cf11afSPaul Mackerras void InstructionBreakpoint(struct pt_regs *regs) 490*14cf11afSPaul Mackerras { 491*14cf11afSPaul Mackerras if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 492*14cf11afSPaul Mackerras 5, SIGTRAP) == NOTIFY_STOP) 493*14cf11afSPaul Mackerras return; 494*14cf11afSPaul Mackerras if (debugger_iabr_match(regs)) 495*14cf11afSPaul Mackerras return; 496*14cf11afSPaul Mackerras _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 497*14cf11afSPaul Mackerras } 498*14cf11afSPaul Mackerras 499*14cf11afSPaul Mackerras void RunModeException(struct pt_regs *regs) 500*14cf11afSPaul Mackerras { 501*14cf11afSPaul Mackerras _exception(SIGTRAP, regs, 0, 0); 502*14cf11afSPaul Mackerras } 503*14cf11afSPaul Mackerras 504*14cf11afSPaul Mackerras void SingleStepException(struct pt_regs *regs) 505*14cf11afSPaul Mackerras { 506*14cf11afSPaul Mackerras regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ 507*14cf11afSPaul Mackerras 508*14cf11afSPaul Mackerras if (notify_die(DIE_SSTEP, "single_step", regs, 5, 509*14cf11afSPaul Mackerras 5, SIGTRAP) == NOTIFY_STOP) 510*14cf11afSPaul Mackerras return; 511*14cf11afSPaul Mackerras if (debugger_sstep(regs)) 512*14cf11afSPaul Mackerras return; 513*14cf11afSPaul Mackerras 514*14cf11afSPaul Mackerras _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 515*14cf11afSPaul Mackerras } 516*14cf11afSPaul Mackerras 517*14cf11afSPaul Mackerras /* 518*14cf11afSPaul Mackerras * After we have successfully emulated an instruction, we have to 519*14cf11afSPaul Mackerras * check if the instruction was being single-stepped, and if so, 520*14cf11afSPaul Mackerras * pretend we got a single-step exception. This was pointed out 521*14cf11afSPaul Mackerras * by Kumar Gala. -- paulus 522*14cf11afSPaul Mackerras */ 523*14cf11afSPaul Mackerras static void emulate_single_step(struct pt_regs *regs) 524*14cf11afSPaul Mackerras { 525*14cf11afSPaul Mackerras if (single_stepping(regs)) { 526*14cf11afSPaul Mackerras clear_single_step(regs); 527*14cf11afSPaul Mackerras _exception(SIGTRAP, regs, TRAP_TRACE, 0); 528*14cf11afSPaul Mackerras } 529*14cf11afSPaul Mackerras } 530*14cf11afSPaul Mackerras 531*14cf11afSPaul Mackerras /* Illegal instruction emulation support. Originally written to 532*14cf11afSPaul Mackerras * provide the PVR to user applications using the mfspr rd, PVR. 533*14cf11afSPaul Mackerras * Return non-zero if we can't emulate, or -EFAULT if the associated 534*14cf11afSPaul Mackerras * memory access caused an access fault. Return zero on success. 535*14cf11afSPaul Mackerras * 536*14cf11afSPaul Mackerras * There are a couple of ways to do this, either "decode" the instruction 537*14cf11afSPaul Mackerras * or directly match lots of bits. In this case, matching lots of 538*14cf11afSPaul Mackerras * bits is faster and easier. 539*14cf11afSPaul Mackerras * 540*14cf11afSPaul Mackerras */ 541*14cf11afSPaul Mackerras #define INST_MFSPR_PVR 0x7c1f42a6 542*14cf11afSPaul Mackerras #define INST_MFSPR_PVR_MASK 0xfc1fffff 543*14cf11afSPaul Mackerras 544*14cf11afSPaul Mackerras #define INST_DCBA 0x7c0005ec 545*14cf11afSPaul Mackerras #define INST_DCBA_MASK 0x7c0007fe 546*14cf11afSPaul Mackerras 547*14cf11afSPaul Mackerras #define INST_MCRXR 0x7c000400 548*14cf11afSPaul Mackerras #define INST_MCRXR_MASK 0x7c0007fe 549*14cf11afSPaul Mackerras 550*14cf11afSPaul Mackerras #define INST_STRING 0x7c00042a 551*14cf11afSPaul Mackerras #define INST_STRING_MASK 0x7c0007fe 552*14cf11afSPaul Mackerras #define INST_STRING_GEN_MASK 0x7c00067e 553*14cf11afSPaul Mackerras #define INST_LSWI 0x7c0004aa 554*14cf11afSPaul Mackerras #define INST_LSWX 0x7c00042a 555*14cf11afSPaul Mackerras #define INST_STSWI 0x7c0005aa 556*14cf11afSPaul Mackerras #define INST_STSWX 0x7c00052a 557*14cf11afSPaul Mackerras 558*14cf11afSPaul Mackerras static int emulate_string_inst(struct pt_regs *regs, u32 instword) 559*14cf11afSPaul Mackerras { 560*14cf11afSPaul Mackerras u8 rT = (instword >> 21) & 0x1f; 561*14cf11afSPaul Mackerras u8 rA = (instword >> 16) & 0x1f; 562*14cf11afSPaul Mackerras u8 NB_RB = (instword >> 11) & 0x1f; 563*14cf11afSPaul Mackerras u32 num_bytes; 564*14cf11afSPaul Mackerras unsigned long EA; 565*14cf11afSPaul Mackerras int pos = 0; 566*14cf11afSPaul Mackerras 567*14cf11afSPaul Mackerras /* Early out if we are an invalid form of lswx */ 568*14cf11afSPaul Mackerras if ((instword & INST_STRING_MASK) == INST_LSWX) 569*14cf11afSPaul Mackerras if ((rT == rA) || (rT == NB_RB)) 570*14cf11afSPaul Mackerras return -EINVAL; 571*14cf11afSPaul Mackerras 572*14cf11afSPaul Mackerras EA = (rA == 0) ? 0 : regs->gpr[rA]; 573*14cf11afSPaul Mackerras 574*14cf11afSPaul Mackerras switch (instword & INST_STRING_MASK) { 575*14cf11afSPaul Mackerras case INST_LSWX: 576*14cf11afSPaul Mackerras case INST_STSWX: 577*14cf11afSPaul Mackerras EA += NB_RB; 578*14cf11afSPaul Mackerras num_bytes = regs->xer & 0x7f; 579*14cf11afSPaul Mackerras break; 580*14cf11afSPaul Mackerras case INST_LSWI: 581*14cf11afSPaul Mackerras case INST_STSWI: 582*14cf11afSPaul Mackerras num_bytes = (NB_RB == 0) ? 32 : NB_RB; 583*14cf11afSPaul Mackerras break; 584*14cf11afSPaul Mackerras default: 585*14cf11afSPaul Mackerras return -EINVAL; 586*14cf11afSPaul Mackerras } 587*14cf11afSPaul Mackerras 588*14cf11afSPaul Mackerras while (num_bytes != 0) 589*14cf11afSPaul Mackerras { 590*14cf11afSPaul Mackerras u8 val; 591*14cf11afSPaul Mackerras u32 shift = 8 * (3 - (pos & 0x3)); 592*14cf11afSPaul Mackerras 593*14cf11afSPaul Mackerras switch ((instword & INST_STRING_MASK)) { 594*14cf11afSPaul Mackerras case INST_LSWX: 595*14cf11afSPaul Mackerras case INST_LSWI: 596*14cf11afSPaul Mackerras if (get_user(val, (u8 __user *)EA)) 597*14cf11afSPaul Mackerras return -EFAULT; 598*14cf11afSPaul Mackerras /* first time updating this reg, 599*14cf11afSPaul Mackerras * zero it out */ 600*14cf11afSPaul Mackerras if (pos == 0) 601*14cf11afSPaul Mackerras regs->gpr[rT] = 0; 602*14cf11afSPaul Mackerras regs->gpr[rT] |= val << shift; 603*14cf11afSPaul Mackerras break; 604*14cf11afSPaul Mackerras case INST_STSWI: 605*14cf11afSPaul Mackerras case INST_STSWX: 606*14cf11afSPaul Mackerras val = regs->gpr[rT] >> shift; 607*14cf11afSPaul Mackerras if (put_user(val, (u8 __user *)EA)) 608*14cf11afSPaul Mackerras return -EFAULT; 609*14cf11afSPaul Mackerras break; 610*14cf11afSPaul Mackerras } 611*14cf11afSPaul Mackerras /* move EA to next address */ 612*14cf11afSPaul Mackerras EA += 1; 613*14cf11afSPaul Mackerras num_bytes--; 614*14cf11afSPaul Mackerras 615*14cf11afSPaul Mackerras /* manage our position within the register */ 616*14cf11afSPaul Mackerras if (++pos == 4) { 617*14cf11afSPaul Mackerras pos = 0; 618*14cf11afSPaul Mackerras if (++rT == 32) 619*14cf11afSPaul Mackerras rT = 0; 620*14cf11afSPaul Mackerras } 621*14cf11afSPaul Mackerras } 622*14cf11afSPaul Mackerras 623*14cf11afSPaul Mackerras return 0; 624*14cf11afSPaul Mackerras } 625*14cf11afSPaul Mackerras 626*14cf11afSPaul Mackerras static int emulate_instruction(struct pt_regs *regs) 627*14cf11afSPaul Mackerras { 628*14cf11afSPaul Mackerras u32 instword; 629*14cf11afSPaul Mackerras u32 rd; 630*14cf11afSPaul Mackerras 631*14cf11afSPaul Mackerras if (!user_mode(regs)) 632*14cf11afSPaul Mackerras return -EINVAL; 633*14cf11afSPaul Mackerras CHECK_FULL_REGS(regs); 634*14cf11afSPaul Mackerras 635*14cf11afSPaul Mackerras if (get_user(instword, (u32 __user *)(regs->nip))) 636*14cf11afSPaul Mackerras return -EFAULT; 637*14cf11afSPaul Mackerras 638*14cf11afSPaul Mackerras /* Emulate the mfspr rD, PVR. */ 639*14cf11afSPaul Mackerras if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { 640*14cf11afSPaul Mackerras rd = (instword >> 21) & 0x1f; 641*14cf11afSPaul Mackerras regs->gpr[rd] = mfspr(SPRN_PVR); 642*14cf11afSPaul Mackerras return 0; 643*14cf11afSPaul Mackerras } 644*14cf11afSPaul Mackerras 645*14cf11afSPaul Mackerras /* Emulating the dcba insn is just a no-op. */ 646*14cf11afSPaul Mackerras if ((instword & INST_DCBA_MASK) == INST_DCBA) 647*14cf11afSPaul Mackerras return 0; 648*14cf11afSPaul Mackerras 649*14cf11afSPaul Mackerras /* Emulate the mcrxr insn. */ 650*14cf11afSPaul Mackerras if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { 651*14cf11afSPaul Mackerras int shift = (instword >> 21) & 0x1c; 652*14cf11afSPaul Mackerras unsigned long msk = 0xf0000000UL >> shift; 653*14cf11afSPaul Mackerras 654*14cf11afSPaul Mackerras regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 655*14cf11afSPaul Mackerras regs->xer &= ~0xf0000000UL; 656*14cf11afSPaul Mackerras return 0; 657*14cf11afSPaul Mackerras } 658*14cf11afSPaul Mackerras 659*14cf11afSPaul Mackerras /* Emulate load/store string insn. */ 660*14cf11afSPaul Mackerras if ((instword & INST_STRING_GEN_MASK) == INST_STRING) 661*14cf11afSPaul Mackerras return emulate_string_inst(regs, instword); 662*14cf11afSPaul Mackerras 663*14cf11afSPaul Mackerras return -EINVAL; 664*14cf11afSPaul Mackerras } 665*14cf11afSPaul Mackerras 666*14cf11afSPaul Mackerras /* 667*14cf11afSPaul Mackerras * Look through the list of trap instructions that are used for BUG(), 668*14cf11afSPaul Mackerras * BUG_ON() and WARN_ON() and see if we hit one. At this point we know 669*14cf11afSPaul Mackerras * that the exception was caused by a trap instruction of some kind. 670*14cf11afSPaul Mackerras * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0 671*14cf11afSPaul Mackerras * otherwise. 672*14cf11afSPaul Mackerras */ 673*14cf11afSPaul Mackerras extern struct bug_entry __start___bug_table[], __stop___bug_table[]; 674*14cf11afSPaul Mackerras 675*14cf11afSPaul Mackerras #ifndef CONFIG_MODULES 676*14cf11afSPaul Mackerras #define module_find_bug(x) NULL 677*14cf11afSPaul Mackerras #endif 678*14cf11afSPaul Mackerras 679*14cf11afSPaul Mackerras struct bug_entry *find_bug(unsigned long bugaddr) 680*14cf11afSPaul Mackerras { 681*14cf11afSPaul Mackerras struct bug_entry *bug; 682*14cf11afSPaul Mackerras 683*14cf11afSPaul Mackerras for (bug = __start___bug_table; bug < __stop___bug_table; ++bug) 684*14cf11afSPaul Mackerras if (bugaddr == bug->bug_addr) 685*14cf11afSPaul Mackerras return bug; 686*14cf11afSPaul Mackerras return module_find_bug(bugaddr); 687*14cf11afSPaul Mackerras } 688*14cf11afSPaul Mackerras 689*14cf11afSPaul Mackerras int check_bug_trap(struct pt_regs *regs) 690*14cf11afSPaul Mackerras { 691*14cf11afSPaul Mackerras struct bug_entry *bug; 692*14cf11afSPaul Mackerras unsigned long addr; 693*14cf11afSPaul Mackerras 694*14cf11afSPaul Mackerras if (regs->msr & MSR_PR) 695*14cf11afSPaul Mackerras return 0; /* not in kernel */ 696*14cf11afSPaul Mackerras addr = regs->nip; /* address of trap instruction */ 697*14cf11afSPaul Mackerras if (addr < PAGE_OFFSET) 698*14cf11afSPaul Mackerras return 0; 699*14cf11afSPaul Mackerras bug = find_bug(regs->nip); 700*14cf11afSPaul Mackerras if (bug == NULL) 701*14cf11afSPaul Mackerras return 0; 702*14cf11afSPaul Mackerras if (bug->line & BUG_WARNING_TRAP) { 703*14cf11afSPaul Mackerras /* this is a WARN_ON rather than BUG/BUG_ON */ 704*14cf11afSPaul Mackerras #ifdef CONFIG_XMON 705*14cf11afSPaul Mackerras xmon_printf(KERN_ERR "Badness in %s at %s:%d\n", 706*14cf11afSPaul Mackerras bug->function, bug->file, 707*14cf11afSPaul Mackerras bug->line & ~BUG_WARNING_TRAP); 708*14cf11afSPaul Mackerras #endif /* CONFIG_XMON */ 709*14cf11afSPaul Mackerras printk(KERN_ERR "Badness in %s at %s:%d\n", 710*14cf11afSPaul Mackerras bug->function, bug->file, 711*14cf11afSPaul Mackerras bug->line & ~BUG_WARNING_TRAP); 712*14cf11afSPaul Mackerras dump_stack(); 713*14cf11afSPaul Mackerras return 1; 714*14cf11afSPaul Mackerras } 715*14cf11afSPaul Mackerras #ifdef CONFIG_XMON 716*14cf11afSPaul Mackerras xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%d!\n", 717*14cf11afSPaul Mackerras bug->function, bug->file, bug->line); 718*14cf11afSPaul Mackerras xmon(regs); 719*14cf11afSPaul Mackerras #endif /* CONFIG_XMON */ 720*14cf11afSPaul Mackerras printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n", 721*14cf11afSPaul Mackerras bug->function, bug->file, bug->line); 722*14cf11afSPaul Mackerras 723*14cf11afSPaul Mackerras return 0; 724*14cf11afSPaul Mackerras } 725*14cf11afSPaul Mackerras 726*14cf11afSPaul Mackerras void ProgramCheckException(struct pt_regs *regs) 727*14cf11afSPaul Mackerras { 728*14cf11afSPaul Mackerras unsigned int reason = get_reason(regs); 729*14cf11afSPaul Mackerras extern int do_mathemu(struct pt_regs *regs); 730*14cf11afSPaul Mackerras 731*14cf11afSPaul Mackerras #ifdef CONFIG_MATH_EMULATION 732*14cf11afSPaul Mackerras /* (reason & REASON_ILLEGAL) would be the obvious thing here, 733*14cf11afSPaul Mackerras * but there seems to be a hardware bug on the 405GP (RevD) 734*14cf11afSPaul Mackerras * that means ESR is sometimes set incorrectly - either to 735*14cf11afSPaul Mackerras * ESR_DST (!?) or 0. In the process of chasing this with the 736*14cf11afSPaul Mackerras * hardware people - not sure if it can happen on any illegal 737*14cf11afSPaul Mackerras * instruction or only on FP instructions, whether there is a 738*14cf11afSPaul Mackerras * pattern to occurences etc. -dgibson 31/Mar/2003 */ 739*14cf11afSPaul Mackerras if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) { 740*14cf11afSPaul Mackerras emulate_single_step(regs); 741*14cf11afSPaul Mackerras return; 742*14cf11afSPaul Mackerras } 743*14cf11afSPaul Mackerras #endif /* CONFIG_MATH_EMULATION */ 744*14cf11afSPaul Mackerras 745*14cf11afSPaul Mackerras if (reason & REASON_FP) { 746*14cf11afSPaul Mackerras /* IEEE FP exception */ 747*14cf11afSPaul Mackerras int code = 0; 748*14cf11afSPaul Mackerras u32 fpscr; 749*14cf11afSPaul Mackerras 750*14cf11afSPaul Mackerras /* We must make sure the FP state is consistent with 751*14cf11afSPaul Mackerras * our MSR_FP in regs 752*14cf11afSPaul Mackerras */ 753*14cf11afSPaul Mackerras preempt_disable(); 754*14cf11afSPaul Mackerras if (regs->msr & MSR_FP) 755*14cf11afSPaul Mackerras giveup_fpu(current); 756*14cf11afSPaul Mackerras preempt_enable(); 757*14cf11afSPaul Mackerras 758*14cf11afSPaul Mackerras fpscr = current->thread.fpscr; 759*14cf11afSPaul Mackerras fpscr &= fpscr << 22; /* mask summary bits with enables */ 760*14cf11afSPaul Mackerras if (fpscr & FPSCR_VX) 761*14cf11afSPaul Mackerras code = FPE_FLTINV; 762*14cf11afSPaul Mackerras else if (fpscr & FPSCR_OX) 763*14cf11afSPaul Mackerras code = FPE_FLTOVF; 764*14cf11afSPaul Mackerras else if (fpscr & FPSCR_UX) 765*14cf11afSPaul Mackerras code = FPE_FLTUND; 766*14cf11afSPaul Mackerras else if (fpscr & FPSCR_ZX) 767*14cf11afSPaul Mackerras code = FPE_FLTDIV; 768*14cf11afSPaul Mackerras else if (fpscr & FPSCR_XX) 769*14cf11afSPaul Mackerras code = FPE_FLTRES; 770*14cf11afSPaul Mackerras _exception(SIGFPE, regs, code, regs->nip); 771*14cf11afSPaul Mackerras return; 772*14cf11afSPaul Mackerras } 773*14cf11afSPaul Mackerras 774*14cf11afSPaul Mackerras if (reason & REASON_TRAP) { 775*14cf11afSPaul Mackerras /* trap exception */ 776*14cf11afSPaul Mackerras if (debugger_bpt(regs)) 777*14cf11afSPaul Mackerras return; 778*14cf11afSPaul Mackerras if (check_bug_trap(regs)) { 779*14cf11afSPaul Mackerras regs->nip += 4; 780*14cf11afSPaul Mackerras return; 781*14cf11afSPaul Mackerras } 782*14cf11afSPaul Mackerras _exception(SIGTRAP, regs, TRAP_BRKPT, 0); 783*14cf11afSPaul Mackerras return; 784*14cf11afSPaul Mackerras } 785*14cf11afSPaul Mackerras 786*14cf11afSPaul Mackerras /* Try to emulate it if we should. */ 787*14cf11afSPaul Mackerras if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 788*14cf11afSPaul Mackerras switch (emulate_instruction(regs)) { 789*14cf11afSPaul Mackerras case 0: 790*14cf11afSPaul Mackerras regs->nip += 4; 791*14cf11afSPaul Mackerras emulate_single_step(regs); 792*14cf11afSPaul Mackerras return; 793*14cf11afSPaul Mackerras case -EFAULT: 794*14cf11afSPaul Mackerras _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 795*14cf11afSPaul Mackerras return; 796*14cf11afSPaul Mackerras } 797*14cf11afSPaul Mackerras } 798*14cf11afSPaul Mackerras 799*14cf11afSPaul Mackerras if (reason & REASON_PRIVILEGED) 800*14cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 801*14cf11afSPaul Mackerras else 802*14cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 803*14cf11afSPaul Mackerras } 804*14cf11afSPaul Mackerras 805*14cf11afSPaul Mackerras void AlignmentException(struct pt_regs *regs) 806*14cf11afSPaul Mackerras { 807*14cf11afSPaul Mackerras int fixed; 808*14cf11afSPaul Mackerras 809*14cf11afSPaul Mackerras fixed = fix_alignment(regs); 810*14cf11afSPaul Mackerras 811*14cf11afSPaul Mackerras if (fixed == 1) { 812*14cf11afSPaul Mackerras regs->nip += 4; /* skip over emulated instruction */ 813*14cf11afSPaul Mackerras emulate_single_step(regs); 814*14cf11afSPaul Mackerras return; 815*14cf11afSPaul Mackerras } 816*14cf11afSPaul Mackerras 817*14cf11afSPaul Mackerras /* Operand address was bad */ 818*14cf11afSPaul Mackerras if (fixed == -EFAULT) { 819*14cf11afSPaul Mackerras if (user_mode(regs)) 820*14cf11afSPaul Mackerras _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar); 821*14cf11afSPaul Mackerras else 822*14cf11afSPaul Mackerras /* Search exception table */ 823*14cf11afSPaul Mackerras bad_page_fault(regs, regs->dar, SIGSEGV); 824*14cf11afSPaul Mackerras return; 825*14cf11afSPaul Mackerras } 826*14cf11afSPaul Mackerras _exception(SIGBUS, regs, BUS_ADRALN, regs->dar); 827*14cf11afSPaul Mackerras } 828*14cf11afSPaul Mackerras 829*14cf11afSPaul Mackerras void StackOverflow(struct pt_regs *regs) 830*14cf11afSPaul Mackerras { 831*14cf11afSPaul Mackerras printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 832*14cf11afSPaul Mackerras current, regs->gpr[1]); 833*14cf11afSPaul Mackerras debugger(regs); 834*14cf11afSPaul Mackerras show_regs(regs); 835*14cf11afSPaul Mackerras panic("kernel stack overflow"); 836*14cf11afSPaul Mackerras } 837*14cf11afSPaul Mackerras 838*14cf11afSPaul Mackerras void nonrecoverable_exception(struct pt_regs *regs) 839*14cf11afSPaul Mackerras { 840*14cf11afSPaul Mackerras printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 841*14cf11afSPaul Mackerras regs->nip, regs->msr); 842*14cf11afSPaul Mackerras debugger(regs); 843*14cf11afSPaul Mackerras die("nonrecoverable exception", regs, SIGKILL); 844*14cf11afSPaul Mackerras } 845*14cf11afSPaul Mackerras 846*14cf11afSPaul Mackerras void trace_syscall(struct pt_regs *regs) 847*14cf11afSPaul Mackerras { 848*14cf11afSPaul Mackerras printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", 849*14cf11afSPaul Mackerras current, current->pid, regs->nip, regs->link, regs->gpr[0], 850*14cf11afSPaul Mackerras regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); 851*14cf11afSPaul Mackerras } 852*14cf11afSPaul Mackerras 853*14cf11afSPaul Mackerras #ifdef CONFIG_8xx 854*14cf11afSPaul Mackerras void SoftwareEmulation(struct pt_regs *regs) 855*14cf11afSPaul Mackerras { 856*14cf11afSPaul Mackerras extern int do_mathemu(struct pt_regs *); 857*14cf11afSPaul Mackerras extern int Soft_emulate_8xx(struct pt_regs *); 858*14cf11afSPaul Mackerras int errcode; 859*14cf11afSPaul Mackerras 860*14cf11afSPaul Mackerras CHECK_FULL_REGS(regs); 861*14cf11afSPaul Mackerras 862*14cf11afSPaul Mackerras if (!user_mode(regs)) { 863*14cf11afSPaul Mackerras debugger(regs); 864*14cf11afSPaul Mackerras die("Kernel Mode Software FPU Emulation", regs, SIGFPE); 865*14cf11afSPaul Mackerras } 866*14cf11afSPaul Mackerras 867*14cf11afSPaul Mackerras #ifdef CONFIG_MATH_EMULATION 868*14cf11afSPaul Mackerras errcode = do_mathemu(regs); 869*14cf11afSPaul Mackerras #else 870*14cf11afSPaul Mackerras errcode = Soft_emulate_8xx(regs); 871*14cf11afSPaul Mackerras #endif 872*14cf11afSPaul Mackerras if (errcode) { 873*14cf11afSPaul Mackerras if (errcode > 0) 874*14cf11afSPaul Mackerras _exception(SIGFPE, regs, 0, 0); 875*14cf11afSPaul Mackerras else if (errcode == -EFAULT) 876*14cf11afSPaul Mackerras _exception(SIGSEGV, regs, 0, 0); 877*14cf11afSPaul Mackerras else 878*14cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 879*14cf11afSPaul Mackerras } else 880*14cf11afSPaul Mackerras emulate_single_step(regs); 881*14cf11afSPaul Mackerras } 882*14cf11afSPaul Mackerras #endif /* CONFIG_8xx */ 883*14cf11afSPaul Mackerras 884*14cf11afSPaul Mackerras #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) 885*14cf11afSPaul Mackerras 886*14cf11afSPaul Mackerras void DebugException(struct pt_regs *regs, unsigned long debug_status) 887*14cf11afSPaul Mackerras { 888*14cf11afSPaul Mackerras if (debug_status & DBSR_IC) { /* instruction completion */ 889*14cf11afSPaul Mackerras regs->msr &= ~MSR_DE; 890*14cf11afSPaul Mackerras if (user_mode(regs)) { 891*14cf11afSPaul Mackerras current->thread.dbcr0 &= ~DBCR0_IC; 892*14cf11afSPaul Mackerras } else { 893*14cf11afSPaul Mackerras /* Disable instruction completion */ 894*14cf11afSPaul Mackerras mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 895*14cf11afSPaul Mackerras /* Clear the instruction completion event */ 896*14cf11afSPaul Mackerras mtspr(SPRN_DBSR, DBSR_IC); 897*14cf11afSPaul Mackerras if (debugger_sstep(regs)) 898*14cf11afSPaul Mackerras return; 899*14cf11afSPaul Mackerras } 900*14cf11afSPaul Mackerras _exception(SIGTRAP, regs, TRAP_TRACE, 0); 901*14cf11afSPaul Mackerras } 902*14cf11afSPaul Mackerras } 903*14cf11afSPaul Mackerras #endif /* CONFIG_4xx || CONFIG_BOOKE */ 904*14cf11afSPaul Mackerras 905*14cf11afSPaul Mackerras #if !defined(CONFIG_TAU_INT) 906*14cf11afSPaul Mackerras void TAUException(struct pt_regs *regs) 907*14cf11afSPaul Mackerras { 908*14cf11afSPaul Mackerras printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 909*14cf11afSPaul Mackerras regs->nip, regs->msr, regs->trap, print_tainted()); 910*14cf11afSPaul Mackerras } 911*14cf11afSPaul Mackerras #endif /* CONFIG_INT_TAU */ 912*14cf11afSPaul Mackerras 913*14cf11afSPaul Mackerras void AltivecUnavailException(struct pt_regs *regs) 914*14cf11afSPaul Mackerras { 915*14cf11afSPaul Mackerras static int kernel_altivec_count; 916*14cf11afSPaul Mackerras 917*14cf11afSPaul Mackerras #ifndef CONFIG_ALTIVEC 918*14cf11afSPaul Mackerras if (user_mode(regs)) { 919*14cf11afSPaul Mackerras /* A user program has executed an altivec instruction, 920*14cf11afSPaul Mackerras but this kernel doesn't support altivec. */ 921*14cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 922*14cf11afSPaul Mackerras return; 923*14cf11afSPaul Mackerras } 924*14cf11afSPaul Mackerras #endif 925*14cf11afSPaul Mackerras /* The kernel has executed an altivec instruction without 926*14cf11afSPaul Mackerras first enabling altivec. Whinge but let it do it. */ 927*14cf11afSPaul Mackerras if (++kernel_altivec_count < 10) 928*14cf11afSPaul Mackerras printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n", 929*14cf11afSPaul Mackerras current, regs->nip); 930*14cf11afSPaul Mackerras regs->msr |= MSR_VEC; 931*14cf11afSPaul Mackerras } 932*14cf11afSPaul Mackerras 933*14cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 934*14cf11afSPaul Mackerras void AltivecAssistException(struct pt_regs *regs) 935*14cf11afSPaul Mackerras { 936*14cf11afSPaul Mackerras int err; 937*14cf11afSPaul Mackerras 938*14cf11afSPaul Mackerras preempt_disable(); 939*14cf11afSPaul Mackerras if (regs->msr & MSR_VEC) 940*14cf11afSPaul Mackerras giveup_altivec(current); 941*14cf11afSPaul Mackerras preempt_enable(); 942*14cf11afSPaul Mackerras if (!user_mode(regs)) { 943*14cf11afSPaul Mackerras printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 944*14cf11afSPaul Mackerras " at %lx\n", regs->nip); 945*14cf11afSPaul Mackerras die("Kernel Altivec assist exception", regs, SIGILL); 946*14cf11afSPaul Mackerras } 947*14cf11afSPaul Mackerras 948*14cf11afSPaul Mackerras err = emulate_altivec(regs); 949*14cf11afSPaul Mackerras if (err == 0) { 950*14cf11afSPaul Mackerras regs->nip += 4; /* skip emulated instruction */ 951*14cf11afSPaul Mackerras emulate_single_step(regs); 952*14cf11afSPaul Mackerras return; 953*14cf11afSPaul Mackerras } 954*14cf11afSPaul Mackerras 955*14cf11afSPaul Mackerras if (err == -EFAULT) { 956*14cf11afSPaul Mackerras /* got an error reading the instruction */ 957*14cf11afSPaul Mackerras _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 958*14cf11afSPaul Mackerras } else { 959*14cf11afSPaul Mackerras /* didn't recognize the instruction */ 960*14cf11afSPaul Mackerras /* XXX quick hack for now: set the non-Java bit in the VSCR */ 961*14cf11afSPaul Mackerras if (printk_ratelimit()) 962*14cf11afSPaul Mackerras printk(KERN_ERR "Unrecognized altivec instruction " 963*14cf11afSPaul Mackerras "in %s at %lx\n", current->comm, regs->nip); 964*14cf11afSPaul Mackerras current->thread.vscr.u[3] |= 0x10000; 965*14cf11afSPaul Mackerras } 966*14cf11afSPaul Mackerras } 967*14cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 968*14cf11afSPaul Mackerras 969*14cf11afSPaul Mackerras #ifdef CONFIG_E500 970*14cf11afSPaul Mackerras void PerformanceMonitorException(struct pt_regs *regs) 971*14cf11afSPaul Mackerras { 972*14cf11afSPaul Mackerras perf_irq(regs); 973*14cf11afSPaul Mackerras } 974*14cf11afSPaul Mackerras #endif 975*14cf11afSPaul Mackerras 976*14cf11afSPaul Mackerras #ifdef CONFIG_FSL_BOOKE 977*14cf11afSPaul Mackerras void CacheLockingException(struct pt_regs *regs, unsigned long address, 978*14cf11afSPaul Mackerras unsigned long error_code) 979*14cf11afSPaul Mackerras { 980*14cf11afSPaul Mackerras /* We treat cache locking instructions from the user 981*14cf11afSPaul Mackerras * as priv ops, in the future we could try to do 982*14cf11afSPaul Mackerras * something smarter 983*14cf11afSPaul Mackerras */ 984*14cf11afSPaul Mackerras if (error_code & (ESR_DLK|ESR_ILK)) 985*14cf11afSPaul Mackerras _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 986*14cf11afSPaul Mackerras return; 987*14cf11afSPaul Mackerras } 988*14cf11afSPaul Mackerras #endif /* CONFIG_FSL_BOOKE */ 989*14cf11afSPaul Mackerras 990*14cf11afSPaul Mackerras #ifdef CONFIG_SPE 991*14cf11afSPaul Mackerras void SPEFloatingPointException(struct pt_regs *regs) 992*14cf11afSPaul Mackerras { 993*14cf11afSPaul Mackerras unsigned long spefscr; 994*14cf11afSPaul Mackerras int fpexc_mode; 995*14cf11afSPaul Mackerras int code = 0; 996*14cf11afSPaul Mackerras 997*14cf11afSPaul Mackerras spefscr = current->thread.spefscr; 998*14cf11afSPaul Mackerras fpexc_mode = current->thread.fpexc_mode; 999*14cf11afSPaul Mackerras 1000*14cf11afSPaul Mackerras /* Hardware does not neccessarily set sticky 1001*14cf11afSPaul Mackerras * underflow/overflow/invalid flags */ 1002*14cf11afSPaul Mackerras if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1003*14cf11afSPaul Mackerras code = FPE_FLTOVF; 1004*14cf11afSPaul Mackerras spefscr |= SPEFSCR_FOVFS; 1005*14cf11afSPaul Mackerras } 1006*14cf11afSPaul Mackerras else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1007*14cf11afSPaul Mackerras code = FPE_FLTUND; 1008*14cf11afSPaul Mackerras spefscr |= SPEFSCR_FUNFS; 1009*14cf11afSPaul Mackerras } 1010*14cf11afSPaul Mackerras else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1011*14cf11afSPaul Mackerras code = FPE_FLTDIV; 1012*14cf11afSPaul Mackerras else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1013*14cf11afSPaul Mackerras code = FPE_FLTINV; 1014*14cf11afSPaul Mackerras spefscr |= SPEFSCR_FINVS; 1015*14cf11afSPaul Mackerras } 1016*14cf11afSPaul Mackerras else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1017*14cf11afSPaul Mackerras code = FPE_FLTRES; 1018*14cf11afSPaul Mackerras 1019*14cf11afSPaul Mackerras current->thread.spefscr = spefscr; 1020*14cf11afSPaul Mackerras 1021*14cf11afSPaul Mackerras _exception(SIGFPE, regs, code, regs->nip); 1022*14cf11afSPaul Mackerras return; 1023*14cf11afSPaul Mackerras } 1024*14cf11afSPaul Mackerras #endif 1025*14cf11afSPaul Mackerras 1026*14cf11afSPaul Mackerras #ifdef CONFIG_BOOKE_WDT 1027*14cf11afSPaul Mackerras /* 1028*14cf11afSPaul Mackerras * Default handler for a Watchdog exception, 1029*14cf11afSPaul Mackerras * spins until a reboot occurs 1030*14cf11afSPaul Mackerras */ 1031*14cf11afSPaul Mackerras void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 1032*14cf11afSPaul Mackerras { 1033*14cf11afSPaul Mackerras /* Generic WatchdogHandler, implement your own */ 1034*14cf11afSPaul Mackerras mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 1035*14cf11afSPaul Mackerras return; 1036*14cf11afSPaul Mackerras } 1037*14cf11afSPaul Mackerras 1038*14cf11afSPaul Mackerras void WatchdogException(struct pt_regs *regs) 1039*14cf11afSPaul Mackerras { 1040*14cf11afSPaul Mackerras printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 1041*14cf11afSPaul Mackerras WatchdogHandler(regs); 1042*14cf11afSPaul Mackerras } 1043*14cf11afSPaul Mackerras #endif 1044*14cf11afSPaul Mackerras 1045*14cf11afSPaul Mackerras void __init trap_init(void) 1046*14cf11afSPaul Mackerras { 1047*14cf11afSPaul Mackerras } 1048