1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/device.h> 3 #include <linux/cpu.h> 4 #include <linux/smp.h> 5 #include <linux/percpu.h> 6 #include <linux/init.h> 7 #include <linux/sched.h> 8 #include <linux/sysfs.h> 9 #include <linux/export.h> 10 #include <linux/nodemask.h> 11 #include <linux/cpumask.h> 12 #include <linux/notifier.h> 13 #include <linux/of.h> 14 15 #include <asm/current.h> 16 #include <asm/processor.h> 17 #include <asm/cputable.h> 18 #include <asm/hvcall.h> 19 #include <asm/machdep.h> 20 #include <asm/smp.h> 21 #include <asm/time.h> 22 #include <asm/pmc.h> 23 #include <asm/firmware.h> 24 #include <asm/idle.h> 25 #include <asm/svm.h> 26 27 #include "cacheinfo.h" 28 #include "setup.h" 29 30 #ifdef CONFIG_PPC64 31 #include <asm/paca.h> 32 #include <asm/lppaca.h> 33 #endif 34 35 static DEFINE_PER_CPU(struct cpu, cpu_devices); 36 37 #ifdef CONFIG_PPC64 38 39 /* 40 * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle: 41 * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in 42 * 2014: 43 * 44 * "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean 45 * up the kernel code." 46 * 47 * powerpc-utils stopped using it as of 1.3.8. At some point in the future this 48 * code should be removed. 49 */ 50 51 static ssize_t store_smt_snooze_delay(struct device *dev, 52 struct device_attribute *attr, 53 const char *buf, 54 size_t count) 55 { 56 pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n", 57 current->comm, current->pid); 58 return count; 59 } 60 61 static ssize_t show_smt_snooze_delay(struct device *dev, 62 struct device_attribute *attr, 63 char *buf) 64 { 65 pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n", 66 current->comm, current->pid); 67 return sysfs_emit(buf, "100\n"); 68 } 69 70 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay, 71 store_smt_snooze_delay); 72 73 static int __init setup_smt_snooze_delay(char *str) 74 { 75 if (!cpu_has_feature(CPU_FTR_SMT)) 76 return 1; 77 78 pr_warn("smt-snooze-delay command line option has no effect\n"); 79 return 1; 80 } 81 __setup("smt-snooze-delay=", setup_smt_snooze_delay); 82 83 #endif /* CONFIG_PPC64 */ 84 85 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \ 86 static void read_##NAME(void *val) \ 87 { \ 88 *(unsigned long *)val = mfspr(ADDRESS); \ 89 } \ 90 static void write_##NAME(void *val) \ 91 { \ 92 EXTRA; \ 93 mtspr(ADDRESS, *(unsigned long *)val); \ 94 } 95 96 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \ 97 static ssize_t show_##NAME(struct device *dev, \ 98 struct device_attribute *attr, \ 99 char *buf) \ 100 { \ 101 struct cpu *cpu = container_of(dev, struct cpu, dev); \ 102 unsigned long val; \ 103 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \ 104 return sysfs_emit(buf, "%lx\n", val); \ 105 } \ 106 static ssize_t __used \ 107 store_##NAME(struct device *dev, struct device_attribute *attr, \ 108 const char *buf, size_t count) \ 109 { \ 110 struct cpu *cpu = container_of(dev, struct cpu, dev); \ 111 unsigned long val; \ 112 int ret = sscanf(buf, "%lx", &val); \ 113 if (ret != 1) \ 114 return -EINVAL; \ 115 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \ 116 return count; \ 117 } 118 119 #define SYSFS_PMCSETUP(NAME, ADDRESS) \ 120 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \ 121 __SYSFS_SPRSETUP_SHOW_STORE(NAME) 122 #define SYSFS_SPRSETUP(NAME, ADDRESS) \ 123 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \ 124 __SYSFS_SPRSETUP_SHOW_STORE(NAME) 125 126 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \ 127 __SYSFS_SPRSETUP_SHOW_STORE(NAME) 128 129 #ifdef CONFIG_PPC64 130 131 /* 132 * This is the system wide DSCR register default value. Any 133 * change to this default value through the sysfs interface 134 * will update all per cpu DSCR default values across the 135 * system stored in their respective PACA structures. 136 */ 137 static unsigned long dscr_default; 138 139 /** 140 * read_dscr() - Fetch the cpu specific DSCR default 141 * @val: Returned cpu specific DSCR default value 142 * 143 * This function returns the per cpu DSCR default value 144 * for any cpu which is contained in its PACA structure. 145 */ 146 static void read_dscr(void *val) 147 { 148 *(unsigned long *)val = get_paca()->dscr_default; 149 } 150 151 152 /** 153 * write_dscr() - Update the cpu specific DSCR default 154 * @val: New cpu specific DSCR default value to update 155 * 156 * This function updates the per cpu DSCR default value 157 * for any cpu which is contained in its PACA structure. 158 */ 159 static void write_dscr(void *val) 160 { 161 get_paca()->dscr_default = *(unsigned long *)val; 162 if (!current->thread.dscr_inherit) { 163 current->thread.dscr = *(unsigned long *)val; 164 mtspr(SPRN_DSCR, *(unsigned long *)val); 165 } 166 } 167 168 SYSFS_SPRSETUP_SHOW_STORE(dscr); 169 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr); 170 171 static void add_write_permission_dev_attr(struct device_attribute *attr) 172 { 173 attr->attr.mode |= 0200; 174 } 175 176 /** 177 * show_dscr_default() - Fetch the system wide DSCR default 178 * @dev: Device structure 179 * @attr: Device attribute structure 180 * @buf: Interface buffer 181 * 182 * This function returns the system wide DSCR default value. 183 */ 184 static ssize_t show_dscr_default(struct device *dev, 185 struct device_attribute *attr, char *buf) 186 { 187 return sysfs_emit(buf, "%lx\n", dscr_default); 188 } 189 190 /** 191 * store_dscr_default() - Update the system wide DSCR default 192 * @dev: Device structure 193 * @attr: Device attribute structure 194 * @buf: Interface buffer 195 * @count: Size of the update 196 * 197 * This function updates the system wide DSCR default value. 198 */ 199 static ssize_t __used store_dscr_default(struct device *dev, 200 struct device_attribute *attr, const char *buf, 201 size_t count) 202 { 203 unsigned long val; 204 int ret = 0; 205 206 ret = sscanf(buf, "%lx", &val); 207 if (ret != 1) 208 return -EINVAL; 209 dscr_default = val; 210 211 on_each_cpu(write_dscr, &val, 1); 212 213 return count; 214 } 215 216 static DEVICE_ATTR(dscr_default, 0600, 217 show_dscr_default, store_dscr_default); 218 219 static void __init sysfs_create_dscr_default(void) 220 { 221 if (cpu_has_feature(CPU_FTR_DSCR)) { 222 struct device *dev_root; 223 int cpu; 224 225 dscr_default = spr_default_dscr; 226 for_each_possible_cpu(cpu) 227 paca_ptrs[cpu]->dscr_default = dscr_default; 228 229 dev_root = bus_get_dev_root(&cpu_subsys); 230 if (dev_root) { 231 device_create_file(dev_root, &dev_attr_dscr_default); 232 put_device(dev_root); 233 } 234 } 235 } 236 #endif /* CONFIG_PPC64 */ 237 238 #ifdef CONFIG_PPC_E500 239 #define MAX_BIT 63 240 241 static u64 pw20_wt; 242 static u64 altivec_idle_wt; 243 244 static unsigned int get_idle_ticks_bit(u64 ns) 245 { 246 u64 cycle; 247 248 if (ns >= 10000) 249 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec; 250 else 251 cycle = div_u64(ns * tb_ticks_per_usec, 1000); 252 253 if (!cycle) 254 return 0; 255 256 return ilog2(cycle); 257 } 258 259 static void do_show_pwrmgtcr0(void *val) 260 { 261 u32 *value = val; 262 263 *value = mfspr(SPRN_PWRMGTCR0); 264 } 265 266 static ssize_t show_pw20_state(struct device *dev, 267 struct device_attribute *attr, char *buf) 268 { 269 u32 value; 270 unsigned int cpu = dev->id; 271 272 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 273 274 value &= PWRMGTCR0_PW20_WAIT; 275 276 return sysfs_emit(buf, "%u\n", value ? 1 : 0); 277 } 278 279 static void do_store_pw20_state(void *val) 280 { 281 u32 *value = val; 282 u32 pw20_state; 283 284 pw20_state = mfspr(SPRN_PWRMGTCR0); 285 286 if (*value) 287 pw20_state |= PWRMGTCR0_PW20_WAIT; 288 else 289 pw20_state &= ~PWRMGTCR0_PW20_WAIT; 290 291 mtspr(SPRN_PWRMGTCR0, pw20_state); 292 } 293 294 static ssize_t store_pw20_state(struct device *dev, 295 struct device_attribute *attr, 296 const char *buf, size_t count) 297 { 298 u32 value; 299 unsigned int cpu = dev->id; 300 301 if (kstrtou32(buf, 0, &value)) 302 return -EINVAL; 303 304 if (value > 1) 305 return -EINVAL; 306 307 smp_call_function_single(cpu, do_store_pw20_state, &value, 1); 308 309 return count; 310 } 311 312 static ssize_t show_pw20_wait_time(struct device *dev, 313 struct device_attribute *attr, char *buf) 314 { 315 u32 value; 316 u64 tb_cycle = 1; 317 u64 time; 318 319 unsigned int cpu = dev->id; 320 321 if (!pw20_wt) { 322 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 323 value = (value & PWRMGTCR0_PW20_ENT) >> 324 PWRMGTCR0_PW20_ENT_SHIFT; 325 326 tb_cycle = (tb_cycle << (MAX_BIT - value + 1)); 327 /* convert ms to ns */ 328 if (tb_ticks_per_usec > 1000) { 329 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000); 330 } else { 331 u32 rem_us; 332 333 time = div_u64_rem(tb_cycle, tb_ticks_per_usec, 334 &rem_us); 335 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec; 336 } 337 } else { 338 time = pw20_wt; 339 } 340 341 return sysfs_emit(buf, "%llu\n", time > 0 ? time : 0); 342 } 343 344 static void set_pw20_wait_entry_bit(void *val) 345 { 346 u32 *value = val; 347 u32 pw20_idle; 348 349 pw20_idle = mfspr(SPRN_PWRMGTCR0); 350 351 /* Set Automatic PW20 Core Idle Count */ 352 /* clear count */ 353 pw20_idle &= ~PWRMGTCR0_PW20_ENT; 354 355 /* set count */ 356 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT); 357 358 mtspr(SPRN_PWRMGTCR0, pw20_idle); 359 } 360 361 static ssize_t store_pw20_wait_time(struct device *dev, 362 struct device_attribute *attr, 363 const char *buf, size_t count) 364 { 365 u32 entry_bit; 366 u64 value; 367 368 unsigned int cpu = dev->id; 369 370 if (kstrtou64(buf, 0, &value)) 371 return -EINVAL; 372 373 if (!value) 374 return -EINVAL; 375 376 entry_bit = get_idle_ticks_bit(value); 377 if (entry_bit > MAX_BIT) 378 return -EINVAL; 379 380 pw20_wt = value; 381 382 smp_call_function_single(cpu, set_pw20_wait_entry_bit, 383 &entry_bit, 1); 384 385 return count; 386 } 387 388 static ssize_t show_altivec_idle(struct device *dev, 389 struct device_attribute *attr, char *buf) 390 { 391 u32 value; 392 unsigned int cpu = dev->id; 393 394 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 395 396 value &= PWRMGTCR0_AV_IDLE_PD_EN; 397 398 return sysfs_emit(buf, "%u\n", value ? 1 : 0); 399 } 400 401 static void do_store_altivec_idle(void *val) 402 { 403 u32 *value = val; 404 u32 altivec_idle; 405 406 altivec_idle = mfspr(SPRN_PWRMGTCR0); 407 408 if (*value) 409 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN; 410 else 411 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN; 412 413 mtspr(SPRN_PWRMGTCR0, altivec_idle); 414 } 415 416 static ssize_t store_altivec_idle(struct device *dev, 417 struct device_attribute *attr, 418 const char *buf, size_t count) 419 { 420 u32 value; 421 unsigned int cpu = dev->id; 422 423 if (kstrtou32(buf, 0, &value)) 424 return -EINVAL; 425 426 if (value > 1) 427 return -EINVAL; 428 429 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1); 430 431 return count; 432 } 433 434 static ssize_t show_altivec_idle_wait_time(struct device *dev, 435 struct device_attribute *attr, char *buf) 436 { 437 u32 value; 438 u64 tb_cycle = 1; 439 u64 time; 440 441 unsigned int cpu = dev->id; 442 443 if (!altivec_idle_wt) { 444 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 445 value = (value & PWRMGTCR0_AV_IDLE_CNT) >> 446 PWRMGTCR0_AV_IDLE_CNT_SHIFT; 447 448 tb_cycle = (tb_cycle << (MAX_BIT - value + 1)); 449 /* convert ms to ns */ 450 if (tb_ticks_per_usec > 1000) { 451 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000); 452 } else { 453 u32 rem_us; 454 455 time = div_u64_rem(tb_cycle, tb_ticks_per_usec, 456 &rem_us); 457 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec; 458 } 459 } else { 460 time = altivec_idle_wt; 461 } 462 463 return sysfs_emit(buf, "%llu\n", time > 0 ? time : 0); 464 } 465 466 static void set_altivec_idle_wait_entry_bit(void *val) 467 { 468 u32 *value = val; 469 u32 altivec_idle; 470 471 altivec_idle = mfspr(SPRN_PWRMGTCR0); 472 473 /* Set Automatic AltiVec Idle Count */ 474 /* clear count */ 475 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT; 476 477 /* set count */ 478 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT); 479 480 mtspr(SPRN_PWRMGTCR0, altivec_idle); 481 } 482 483 static ssize_t store_altivec_idle_wait_time(struct device *dev, 484 struct device_attribute *attr, 485 const char *buf, size_t count) 486 { 487 u32 entry_bit; 488 u64 value; 489 490 unsigned int cpu = dev->id; 491 492 if (kstrtou64(buf, 0, &value)) 493 return -EINVAL; 494 495 if (!value) 496 return -EINVAL; 497 498 entry_bit = get_idle_ticks_bit(value); 499 if (entry_bit > MAX_BIT) 500 return -EINVAL; 501 502 altivec_idle_wt = value; 503 504 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit, 505 &entry_bit, 1); 506 507 return count; 508 } 509 510 /* 511 * Enable/Disable interface: 512 * 0, disable. 1, enable. 513 */ 514 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state); 515 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle); 516 517 /* 518 * Set wait time interface:(Nanosecond) 519 * Example: Base on TBfreq is 41MHZ. 520 * 1~48(ns): TB[63] 521 * 49~97(ns): TB[62] 522 * 98~195(ns): TB[61] 523 * 196~390(ns): TB[60] 524 * 391~780(ns): TB[59] 525 * 781~1560(ns): TB[58] 526 * ... 527 */ 528 static DEVICE_ATTR(pw20_wait_time, 0600, 529 show_pw20_wait_time, 530 store_pw20_wait_time); 531 static DEVICE_ATTR(altivec_idle_wait_time, 0600, 532 show_altivec_idle_wait_time, 533 store_altivec_idle_wait_time); 534 #endif 535 536 /* 537 * Enabling PMCs will slow partition context switch times so we only do 538 * it the first time we write to the PMCs. 539 */ 540 541 static DEFINE_PER_CPU(char, pmcs_enabled); 542 543 void ppc_enable_pmcs(void) 544 { 545 ppc_set_pmu_inuse(1); 546 547 /* Only need to enable them once */ 548 if (__this_cpu_read(pmcs_enabled)) 549 return; 550 551 __this_cpu_write(pmcs_enabled, 1); 552 553 if (ppc_md.enable_pmcs) 554 ppc_md.enable_pmcs(); 555 } 556 EXPORT_SYMBOL(ppc_enable_pmcs); 557 558 559 560 /* Let's define all possible registers, we'll only hook up the ones 561 * that are implemented on the current processor 562 */ 563 564 #ifdef CONFIG_PMU_SYSFS 565 #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32) 566 #define HAS_PPC_PMC_CLASSIC 1 567 #define HAS_PPC_PMC_IBM 1 568 #endif 569 570 #ifdef CONFIG_PPC64 571 #define HAS_PPC_PMC_PA6T 1 572 #define HAS_PPC_PMC56 1 573 #endif 574 575 #ifdef CONFIG_PPC_BOOK3S_32 576 #define HAS_PPC_PMC_G4 1 577 #endif 578 #endif /* CONFIG_PMU_SYSFS */ 579 580 #if defined(CONFIG_PPC64) && defined(CONFIG_DEBUG_MISC) 581 #define HAS_PPC_PA6T 582 #endif 583 /* 584 * SPRs which are not related to PMU. 585 */ 586 #ifdef CONFIG_PPC64 587 SYSFS_SPRSETUP(purr, SPRN_PURR); 588 SYSFS_SPRSETUP(spurr, SPRN_SPURR); 589 SYSFS_SPRSETUP(pir, SPRN_PIR); 590 SYSFS_SPRSETUP(tscr, SPRN_TSCR); 591 592 /* 593 Lets only enable read for phyp resources and 594 enable write when needed with a separate function. 595 Lets be conservative and default to pseries. 596 */ 597 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL); 598 static DEVICE_ATTR(purr, 0400, show_purr, store_purr); 599 static DEVICE_ATTR(pir, 0400, show_pir, NULL); 600 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr); 601 #endif /* CONFIG_PPC64 */ 602 603 #ifdef HAS_PPC_PMC_CLASSIC 604 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0); 605 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1); 606 SYSFS_PMCSETUP(pmc1, SPRN_PMC1); 607 SYSFS_PMCSETUP(pmc2, SPRN_PMC2); 608 SYSFS_PMCSETUP(pmc3, SPRN_PMC3); 609 SYSFS_PMCSETUP(pmc4, SPRN_PMC4); 610 SYSFS_PMCSETUP(pmc5, SPRN_PMC5); 611 SYSFS_PMCSETUP(pmc6, SPRN_PMC6); 612 #endif 613 614 #ifdef HAS_PPC_PMC_G4 615 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2); 616 #endif 617 618 #ifdef HAS_PPC_PMC56 619 SYSFS_PMCSETUP(pmc7, SPRN_PMC7); 620 SYSFS_PMCSETUP(pmc8, SPRN_PMC8); 621 622 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA); 623 SYSFS_PMCSETUP(mmcr3, SPRN_MMCR3); 624 625 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra); 626 static DEVICE_ATTR(mmcr3, 0600, show_mmcr3, store_mmcr3); 627 #endif /* HAS_PPC_PMC56 */ 628 629 630 631 632 #ifdef HAS_PPC_PMC_PA6T 633 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0); 634 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1); 635 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2); 636 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3); 637 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4); 638 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5); 639 #endif 640 641 #ifdef HAS_PPC_PA6T 642 SYSFS_SPRSETUP(hid0, SPRN_HID0); 643 SYSFS_SPRSETUP(hid1, SPRN_HID1); 644 SYSFS_SPRSETUP(hid4, SPRN_HID4); 645 SYSFS_SPRSETUP(hid5, SPRN_HID5); 646 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0); 647 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1); 648 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2); 649 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3); 650 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4); 651 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5); 652 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6); 653 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7); 654 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8); 655 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9); 656 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT); 657 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR); 658 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR); 659 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR); 660 SYSFS_SPRSETUP(der, SPRN_PA6T_DER); 661 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER); 662 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER); 663 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER); 664 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER); 665 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR); 666 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0); 667 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1); 668 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2); 669 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3); 670 #endif /* HAS_PPC_PA6T */ 671 672 #ifdef HAS_PPC_PMC_IBM 673 static struct device_attribute ibm_common_attrs[] = { 674 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 675 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 676 }; 677 #endif /* HAS_PPC_PMC_IBM */ 678 679 #ifdef HAS_PPC_PMC_G4 680 static struct device_attribute g4_common_attrs[] = { 681 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 682 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 683 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2), 684 }; 685 #endif /* HAS_PPC_PMC_G4 */ 686 687 #ifdef HAS_PPC_PMC_CLASSIC 688 static struct device_attribute classic_pmc_attrs[] = { 689 __ATTR(pmc1, 0600, show_pmc1, store_pmc1), 690 __ATTR(pmc2, 0600, show_pmc2, store_pmc2), 691 __ATTR(pmc3, 0600, show_pmc3, store_pmc3), 692 __ATTR(pmc4, 0600, show_pmc4, store_pmc4), 693 __ATTR(pmc5, 0600, show_pmc5, store_pmc5), 694 __ATTR(pmc6, 0600, show_pmc6, store_pmc6), 695 #ifdef HAS_PPC_PMC56 696 __ATTR(pmc7, 0600, show_pmc7, store_pmc7), 697 __ATTR(pmc8, 0600, show_pmc8, store_pmc8), 698 #endif 699 }; 700 #endif 701 702 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T) 703 static struct device_attribute pa6t_attrs[] = { 704 #ifdef HAS_PPC_PMC_PA6T 705 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 706 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 707 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0), 708 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1), 709 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2), 710 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3), 711 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4), 712 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5), 713 #endif 714 #ifdef HAS_PPC_PA6T 715 __ATTR(hid0, 0600, show_hid0, store_hid0), 716 __ATTR(hid1, 0600, show_hid1, store_hid1), 717 __ATTR(hid4, 0600, show_hid4, store_hid4), 718 __ATTR(hid5, 0600, show_hid5, store_hid5), 719 __ATTR(ima0, 0600, show_ima0, store_ima0), 720 __ATTR(ima1, 0600, show_ima1, store_ima1), 721 __ATTR(ima2, 0600, show_ima2, store_ima2), 722 __ATTR(ima3, 0600, show_ima3, store_ima3), 723 __ATTR(ima4, 0600, show_ima4, store_ima4), 724 __ATTR(ima5, 0600, show_ima5, store_ima5), 725 __ATTR(ima6, 0600, show_ima6, store_ima6), 726 __ATTR(ima7, 0600, show_ima7, store_ima7), 727 __ATTR(ima8, 0600, show_ima8, store_ima8), 728 __ATTR(ima9, 0600, show_ima9, store_ima9), 729 __ATTR(imaat, 0600, show_imaat, store_imaat), 730 __ATTR(btcr, 0600, show_btcr, store_btcr), 731 __ATTR(pccr, 0600, show_pccr, store_pccr), 732 __ATTR(rpccr, 0600, show_rpccr, store_rpccr), 733 __ATTR(der, 0600, show_der, store_der), 734 __ATTR(mer, 0600, show_mer, store_mer), 735 __ATTR(ber, 0600, show_ber, store_ber), 736 __ATTR(ier, 0600, show_ier, store_ier), 737 __ATTR(sier, 0600, show_sier, store_sier), 738 __ATTR(siar, 0600, show_siar, store_siar), 739 __ATTR(tsr0, 0600, show_tsr0, store_tsr0), 740 __ATTR(tsr1, 0600, show_tsr1, store_tsr1), 741 __ATTR(tsr2, 0600, show_tsr2, store_tsr2), 742 __ATTR(tsr3, 0600, show_tsr3, store_tsr3), 743 #endif /* HAS_PPC_PA6T */ 744 }; 745 #endif 746 747 #ifdef CONFIG_PPC_SVM 748 static ssize_t show_svm(struct device *dev, struct device_attribute *attr, char *buf) 749 { 750 return sysfs_emit(buf, "%u\n", is_secure_guest()); 751 } 752 static DEVICE_ATTR(svm, 0444, show_svm, NULL); 753 754 static void __init create_svm_file(void) 755 { 756 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 757 758 if (dev_root) { 759 device_create_file(dev_root, &dev_attr_svm); 760 put_device(dev_root); 761 } 762 } 763 #else 764 static void __init create_svm_file(void) 765 { 766 } 767 #endif /* CONFIG_PPC_SVM */ 768 769 #ifdef CONFIG_PPC_PSERIES 770 static void read_idle_purr(void *val) 771 { 772 u64 *ret = val; 773 774 *ret = read_this_idle_purr(); 775 } 776 777 static ssize_t idle_purr_show(struct device *dev, 778 struct device_attribute *attr, char *buf) 779 { 780 struct cpu *cpu = container_of(dev, struct cpu, dev); 781 u64 val; 782 783 smp_call_function_single(cpu->dev.id, read_idle_purr, &val, 1); 784 return sysfs_emit(buf, "%llx\n", val); 785 } 786 static DEVICE_ATTR(idle_purr, 0400, idle_purr_show, NULL); 787 788 static void create_idle_purr_file(struct device *s) 789 { 790 if (firmware_has_feature(FW_FEATURE_LPAR)) 791 device_create_file(s, &dev_attr_idle_purr); 792 } 793 794 static void remove_idle_purr_file(struct device *s) 795 { 796 if (firmware_has_feature(FW_FEATURE_LPAR)) 797 device_remove_file(s, &dev_attr_idle_purr); 798 } 799 800 static void read_idle_spurr(void *val) 801 { 802 u64 *ret = val; 803 804 *ret = read_this_idle_spurr(); 805 } 806 807 static ssize_t idle_spurr_show(struct device *dev, 808 struct device_attribute *attr, char *buf) 809 { 810 struct cpu *cpu = container_of(dev, struct cpu, dev); 811 u64 val; 812 813 smp_call_function_single(cpu->dev.id, read_idle_spurr, &val, 1); 814 return sysfs_emit(buf, "%llx\n", val); 815 } 816 static DEVICE_ATTR(idle_spurr, 0400, idle_spurr_show, NULL); 817 818 static void create_idle_spurr_file(struct device *s) 819 { 820 if (firmware_has_feature(FW_FEATURE_LPAR)) 821 device_create_file(s, &dev_attr_idle_spurr); 822 } 823 824 static void remove_idle_spurr_file(struct device *s) 825 { 826 if (firmware_has_feature(FW_FEATURE_LPAR)) 827 device_remove_file(s, &dev_attr_idle_spurr); 828 } 829 830 #else /* CONFIG_PPC_PSERIES */ 831 #define create_idle_purr_file(s) 832 #define remove_idle_purr_file(s) 833 #define create_idle_spurr_file(s) 834 #define remove_idle_spurr_file(s) 835 #endif /* CONFIG_PPC_PSERIES */ 836 837 static int register_cpu_online(unsigned int cpu) 838 { 839 struct cpu *c = &per_cpu(cpu_devices, cpu); 840 struct device *s = &c->dev; 841 struct device_attribute *attrs, *pmc_attrs; 842 int i, nattrs; 843 844 /* For cpus present at boot a reference was already grabbed in register_cpu() */ 845 if (!s->of_node) 846 s->of_node = of_get_cpu_node(cpu, NULL); 847 848 #ifdef CONFIG_PPC64 849 if (cpu_has_feature(CPU_FTR_SMT)) 850 device_create_file(s, &dev_attr_smt_snooze_delay); 851 #endif 852 853 /* PMC stuff */ 854 switch (cur_cpu_spec->pmc_type) { 855 #ifdef HAS_PPC_PMC_IBM 856 case PPC_PMC_IBM: 857 attrs = ibm_common_attrs; 858 nattrs = ARRAY_SIZE(ibm_common_attrs); 859 pmc_attrs = classic_pmc_attrs; 860 break; 861 #endif /* HAS_PPC_PMC_IBM */ 862 #ifdef HAS_PPC_PMC_G4 863 case PPC_PMC_G4: 864 attrs = g4_common_attrs; 865 nattrs = ARRAY_SIZE(g4_common_attrs); 866 pmc_attrs = classic_pmc_attrs; 867 break; 868 #endif /* HAS_PPC_PMC_G4 */ 869 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T) 870 case PPC_PMC_PA6T: 871 /* PA Semi starts counting at PMC0 */ 872 attrs = pa6t_attrs; 873 nattrs = ARRAY_SIZE(pa6t_attrs); 874 pmc_attrs = NULL; 875 break; 876 #endif 877 default: 878 attrs = NULL; 879 nattrs = 0; 880 pmc_attrs = NULL; 881 } 882 883 for (i = 0; i < nattrs; i++) 884 device_create_file(s, &attrs[i]); 885 886 if (pmc_attrs) 887 for (i = 0; i < cur_cpu_spec->num_pmcs; i++) 888 device_create_file(s, &pmc_attrs[i]); 889 890 #ifdef CONFIG_PPC64 891 #ifdef CONFIG_PMU_SYSFS 892 if (cpu_has_feature(CPU_FTR_MMCRA)) 893 device_create_file(s, &dev_attr_mmcra); 894 895 if (cpu_has_feature(CPU_FTR_ARCH_31)) 896 device_create_file(s, &dev_attr_mmcr3); 897 #endif /* CONFIG_PMU_SYSFS */ 898 899 if (cpu_has_feature(CPU_FTR_PURR)) { 900 if (!firmware_has_feature(FW_FEATURE_LPAR)) 901 add_write_permission_dev_attr(&dev_attr_purr); 902 device_create_file(s, &dev_attr_purr); 903 create_idle_purr_file(s); 904 } 905 906 if (cpu_has_feature(CPU_FTR_SPURR)) { 907 device_create_file(s, &dev_attr_spurr); 908 create_idle_spurr_file(s); 909 } 910 911 if (cpu_has_feature(CPU_FTR_DSCR)) 912 device_create_file(s, &dev_attr_dscr); 913 914 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2)) 915 device_create_file(s, &dev_attr_pir); 916 917 if (cpu_has_feature(CPU_FTR_ARCH_206) && 918 !firmware_has_feature(FW_FEATURE_LPAR)) 919 device_create_file(s, &dev_attr_tscr); 920 #endif /* CONFIG_PPC64 */ 921 922 #ifdef CONFIG_PPC_E500 923 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 924 device_create_file(s, &dev_attr_pw20_state); 925 device_create_file(s, &dev_attr_pw20_wait_time); 926 927 device_create_file(s, &dev_attr_altivec_idle); 928 device_create_file(s, &dev_attr_altivec_idle_wait_time); 929 } 930 #endif 931 cacheinfo_cpu_online(cpu); 932 return 0; 933 } 934 935 #ifdef CONFIG_HOTPLUG_CPU 936 static int unregister_cpu_online(unsigned int cpu) 937 { 938 struct cpu *c = &per_cpu(cpu_devices, cpu); 939 struct device *s = &c->dev; 940 struct device_attribute *attrs, *pmc_attrs; 941 int i, nattrs; 942 943 if (WARN_RATELIMIT(!c->hotpluggable, "cpu %d can't be offlined\n", cpu)) 944 return -EBUSY; 945 946 #ifdef CONFIG_PPC64 947 if (cpu_has_feature(CPU_FTR_SMT)) 948 device_remove_file(s, &dev_attr_smt_snooze_delay); 949 #endif 950 951 /* PMC stuff */ 952 switch (cur_cpu_spec->pmc_type) { 953 #ifdef HAS_PPC_PMC_IBM 954 case PPC_PMC_IBM: 955 attrs = ibm_common_attrs; 956 nattrs = ARRAY_SIZE(ibm_common_attrs); 957 pmc_attrs = classic_pmc_attrs; 958 break; 959 #endif /* HAS_PPC_PMC_IBM */ 960 #ifdef HAS_PPC_PMC_G4 961 case PPC_PMC_G4: 962 attrs = g4_common_attrs; 963 nattrs = ARRAY_SIZE(g4_common_attrs); 964 pmc_attrs = classic_pmc_attrs; 965 break; 966 #endif /* HAS_PPC_PMC_G4 */ 967 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T) 968 case PPC_PMC_PA6T: 969 /* PA Semi starts counting at PMC0 */ 970 attrs = pa6t_attrs; 971 nattrs = ARRAY_SIZE(pa6t_attrs); 972 pmc_attrs = NULL; 973 break; 974 #endif 975 default: 976 attrs = NULL; 977 nattrs = 0; 978 pmc_attrs = NULL; 979 } 980 981 for (i = 0; i < nattrs; i++) 982 device_remove_file(s, &attrs[i]); 983 984 if (pmc_attrs) 985 for (i = 0; i < cur_cpu_spec->num_pmcs; i++) 986 device_remove_file(s, &pmc_attrs[i]); 987 988 #ifdef CONFIG_PPC64 989 #ifdef CONFIG_PMU_SYSFS 990 if (cpu_has_feature(CPU_FTR_MMCRA)) 991 device_remove_file(s, &dev_attr_mmcra); 992 993 if (cpu_has_feature(CPU_FTR_ARCH_31)) 994 device_remove_file(s, &dev_attr_mmcr3); 995 #endif /* CONFIG_PMU_SYSFS */ 996 997 if (cpu_has_feature(CPU_FTR_PURR)) { 998 device_remove_file(s, &dev_attr_purr); 999 remove_idle_purr_file(s); 1000 } 1001 1002 if (cpu_has_feature(CPU_FTR_SPURR)) { 1003 device_remove_file(s, &dev_attr_spurr); 1004 remove_idle_spurr_file(s); 1005 } 1006 1007 if (cpu_has_feature(CPU_FTR_DSCR)) 1008 device_remove_file(s, &dev_attr_dscr); 1009 1010 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2)) 1011 device_remove_file(s, &dev_attr_pir); 1012 1013 if (cpu_has_feature(CPU_FTR_ARCH_206) && 1014 !firmware_has_feature(FW_FEATURE_LPAR)) 1015 device_remove_file(s, &dev_attr_tscr); 1016 #endif /* CONFIG_PPC64 */ 1017 1018 #ifdef CONFIG_PPC_E500 1019 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 1020 device_remove_file(s, &dev_attr_pw20_state); 1021 device_remove_file(s, &dev_attr_pw20_wait_time); 1022 1023 device_remove_file(s, &dev_attr_altivec_idle); 1024 device_remove_file(s, &dev_attr_altivec_idle_wait_time); 1025 } 1026 #endif 1027 cacheinfo_cpu_offline(cpu); 1028 of_node_put(s->of_node); 1029 s->of_node = NULL; 1030 return 0; 1031 } 1032 #else /* !CONFIG_HOTPLUG_CPU */ 1033 #define unregister_cpu_online NULL 1034 #endif 1035 1036 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE 1037 ssize_t arch_cpu_probe(const char *buf, size_t count) 1038 { 1039 if (ppc_md.cpu_probe) 1040 return ppc_md.cpu_probe(buf, count); 1041 1042 return -EINVAL; 1043 } 1044 1045 ssize_t arch_cpu_release(const char *buf, size_t count) 1046 { 1047 if (ppc_md.cpu_release) 1048 return ppc_md.cpu_release(buf, count); 1049 1050 return -EINVAL; 1051 } 1052 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ 1053 1054 static DEFINE_MUTEX(cpu_mutex); 1055 1056 int cpu_add_dev_attr(struct device_attribute *attr) 1057 { 1058 int cpu; 1059 1060 mutex_lock(&cpu_mutex); 1061 1062 for_each_possible_cpu(cpu) { 1063 device_create_file(get_cpu_device(cpu), attr); 1064 } 1065 1066 mutex_unlock(&cpu_mutex); 1067 return 0; 1068 } 1069 EXPORT_SYMBOL_GPL(cpu_add_dev_attr); 1070 1071 int cpu_add_dev_attr_group(struct attribute_group *attrs) 1072 { 1073 int cpu; 1074 struct device *dev; 1075 int ret; 1076 1077 mutex_lock(&cpu_mutex); 1078 1079 for_each_possible_cpu(cpu) { 1080 dev = get_cpu_device(cpu); 1081 ret = sysfs_create_group(&dev->kobj, attrs); 1082 WARN_ON(ret != 0); 1083 } 1084 1085 mutex_unlock(&cpu_mutex); 1086 return 0; 1087 } 1088 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group); 1089 1090 1091 void cpu_remove_dev_attr(struct device_attribute *attr) 1092 { 1093 int cpu; 1094 1095 mutex_lock(&cpu_mutex); 1096 1097 for_each_possible_cpu(cpu) { 1098 device_remove_file(get_cpu_device(cpu), attr); 1099 } 1100 1101 mutex_unlock(&cpu_mutex); 1102 } 1103 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr); 1104 1105 void cpu_remove_dev_attr_group(struct attribute_group *attrs) 1106 { 1107 int cpu; 1108 struct device *dev; 1109 1110 mutex_lock(&cpu_mutex); 1111 1112 for_each_possible_cpu(cpu) { 1113 dev = get_cpu_device(cpu); 1114 sysfs_remove_group(&dev->kobj, attrs); 1115 } 1116 1117 mutex_unlock(&cpu_mutex); 1118 } 1119 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group); 1120 1121 1122 /* NUMA stuff */ 1123 1124 #ifdef CONFIG_NUMA 1125 int sysfs_add_device_to_node(struct device *dev, int nid) 1126 { 1127 struct node *node = node_devices[nid]; 1128 return sysfs_create_link(&node->dev.kobj, &dev->kobj, 1129 kobject_name(&dev->kobj)); 1130 } 1131 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node); 1132 1133 void sysfs_remove_device_from_node(struct device *dev, int nid) 1134 { 1135 struct node *node = node_devices[nid]; 1136 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj)); 1137 } 1138 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node); 1139 #endif 1140 1141 /* Only valid if CPU is present. */ 1142 static ssize_t show_physical_id(struct device *dev, 1143 struct device_attribute *attr, char *buf) 1144 { 1145 struct cpu *cpu = container_of(dev, struct cpu, dev); 1146 1147 return sysfs_emit(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id)); 1148 } 1149 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL); 1150 1151 static int __init topology_init(void) 1152 { 1153 int cpu, r; 1154 1155 for_each_possible_cpu(cpu) { 1156 struct cpu *c = &per_cpu(cpu_devices, cpu); 1157 1158 #ifdef CONFIG_HOTPLUG_CPU 1159 /* 1160 * For now, we just see if the system supports making 1161 * the RTAS calls for CPU hotplug. But, there may be a 1162 * more comprehensive way to do this for an individual 1163 * CPU. For instance, the boot cpu might never be valid 1164 * for hotplugging. 1165 */ 1166 if (smp_ops && smp_ops->cpu_offline_self) 1167 c->hotpluggable = 1; 1168 #endif 1169 1170 if (cpu_online(cpu) || c->hotpluggable) { 1171 register_cpu(c, cpu); 1172 1173 device_create_file(&c->dev, &dev_attr_physical_id); 1174 } 1175 } 1176 r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online", 1177 register_cpu_online, unregister_cpu_online); 1178 WARN_ON(r < 0); 1179 #ifdef CONFIG_PPC64 1180 sysfs_create_dscr_default(); 1181 #endif /* CONFIG_PPC64 */ 1182 1183 create_svm_file(); 1184 1185 return 0; 1186 } 1187 subsys_initcall(topology_init); 1188