1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * SMP support for ppc. 4 * 5 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great 6 * deal of code from the sparc and intel versions. 7 * 8 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> 9 * 10 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and 11 * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com 12 */ 13 14 #undef DEBUG 15 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/sched/mm.h> 19 #include <linux/sched/task_stack.h> 20 #include <linux/sched/topology.h> 21 #include <linux/smp.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/init.h> 25 #include <linux/spinlock.h> 26 #include <linux/cache.h> 27 #include <linux/err.h> 28 #include <linux/device.h> 29 #include <linux/cpu.h> 30 #include <linux/notifier.h> 31 #include <linux/topology.h> 32 #include <linux/profile.h> 33 #include <linux/processor.h> 34 #include <linux/random.h> 35 #include <linux/stackprotector.h> 36 #include <linux/pgtable.h> 37 #include <linux/clockchips.h> 38 #include <linux/kexec.h> 39 40 #include <asm/ptrace.h> 41 #include <linux/atomic.h> 42 #include <asm/irq.h> 43 #include <asm/hw_irq.h> 44 #include <asm/kvm_ppc.h> 45 #include <asm/dbell.h> 46 #include <asm/page.h> 47 #include <asm/smp.h> 48 #include <asm/time.h> 49 #include <asm/machdep.h> 50 #include <asm/mmu_context.h> 51 #include <asm/cputhreads.h> 52 #include <asm/cputable.h> 53 #include <asm/mpic.h> 54 #include <asm/vdso_datapage.h> 55 #ifdef CONFIG_PPC64 56 #include <asm/paca.h> 57 #endif 58 #include <asm/vdso.h> 59 #include <asm/debug.h> 60 #include <asm/cpu_has_feature.h> 61 #include <asm/ftrace.h> 62 #include <asm/kup.h> 63 #include <asm/fadump.h> 64 #include <asm/systemcfg.h> 65 66 #include <trace/events/ipi.h> 67 68 #ifdef DEBUG 69 #include <asm/udbg.h> 70 #define DBG(fmt...) udbg_printf(fmt) 71 #else 72 #define DBG(fmt...) 73 #endif 74 75 #ifdef CONFIG_HOTPLUG_CPU 76 /* State of each CPU during hotplug phases */ 77 static DEFINE_PER_CPU(int, cpu_state) = { 0 }; 78 #endif 79 80 struct task_struct *secondary_current; 81 bool has_big_cores __ro_after_init; 82 bool coregroup_enabled __ro_after_init; 83 bool thread_group_shares_l2 __ro_after_init; 84 bool thread_group_shares_l3 __ro_after_init; 85 86 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 87 DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map); 88 DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map); 89 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 90 static DEFINE_PER_CPU(cpumask_var_t, cpu_coregroup_map); 91 92 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 93 EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 95 EXPORT_SYMBOL_GPL(has_big_cores); 96 97 #define MAX_THREAD_LIST_SIZE 8 98 #define THREAD_GROUP_SHARE_L1 1 99 #define THREAD_GROUP_SHARE_L2_L3 2 100 struct thread_groups { 101 unsigned int property; 102 unsigned int nr_groups; 103 unsigned int threads_per_group; 104 unsigned int thread_list[MAX_THREAD_LIST_SIZE]; 105 }; 106 107 /* Maximum number of properties that groups of threads within a core can share */ 108 #define MAX_THREAD_GROUP_PROPERTIES 2 109 110 struct thread_groups_list { 111 unsigned int nr_properties; 112 struct thread_groups property_tgs[MAX_THREAD_GROUP_PROPERTIES]; 113 }; 114 115 static struct thread_groups_list tgl[NR_CPUS] __initdata; 116 /* 117 * On big-cores system, thread_group_l1_cache_map for each CPU corresponds to 118 * the set its siblings that share the L1-cache. 119 */ 120 DEFINE_PER_CPU(cpumask_var_t, thread_group_l1_cache_map); 121 122 /* 123 * On some big-cores system, thread_group_l2_cache_map for each CPU 124 * corresponds to the set its siblings within the core that share the 125 * L2-cache. 126 */ 127 DEFINE_PER_CPU(cpumask_var_t, thread_group_l2_cache_map); 128 129 /* 130 * On P10, thread_group_l3_cache_map for each CPU is equal to the 131 * thread_group_l2_cache_map 132 */ 133 DEFINE_PER_CPU(cpumask_var_t, thread_group_l3_cache_map); 134 135 /* SMP operations for this machine */ 136 struct smp_ops_t *smp_ops; 137 138 /* Can't be static due to PowerMac hackery */ 139 volatile unsigned int cpu_callin_map[NR_CPUS]; 140 141 int smt_enabled_at_boot = 1; 142 143 /* 144 * Returns 1 if the specified cpu should be brought up during boot. 145 * Used to inhibit booting threads if they've been disabled or 146 * limited on the command line 147 */ 148 int smp_generic_cpu_bootable(unsigned int nr) 149 { 150 /* Special case - we inhibit secondary thread startup 151 * during boot if the user requests it. 152 */ 153 if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) { 154 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0) 155 return 0; 156 if (smt_enabled_at_boot 157 && cpu_thread_in_core(nr) >= smt_enabled_at_boot) 158 return 0; 159 } 160 161 return 1; 162 } 163 164 165 #ifdef CONFIG_PPC64 166 int smp_generic_kick_cpu(int nr) 167 { 168 if (nr < 0 || nr >= nr_cpu_ids) 169 return -EINVAL; 170 171 /* 172 * The processor is currently spinning, waiting for the 173 * cpu_start field to become non-zero After we set cpu_start, 174 * the processor will continue on to secondary_start 175 */ 176 if (!paca_ptrs[nr]->cpu_start) { 177 paca_ptrs[nr]->cpu_start = 1; 178 smp_mb(); 179 return 0; 180 } 181 182 #ifdef CONFIG_HOTPLUG_CPU 183 /* 184 * Ok it's not there, so it might be soft-unplugged, let's 185 * try to bring it back 186 */ 187 generic_set_cpu_up(nr); 188 smp_wmb(); 189 smp_send_reschedule(nr); 190 #endif /* CONFIG_HOTPLUG_CPU */ 191 192 return 0; 193 } 194 #endif /* CONFIG_PPC64 */ 195 196 static irqreturn_t call_function_action(int irq, void *data) 197 { 198 generic_smp_call_function_interrupt(); 199 return IRQ_HANDLED; 200 } 201 202 static irqreturn_t reschedule_action(int irq, void *data) 203 { 204 scheduler_ipi(); 205 return IRQ_HANDLED; 206 } 207 208 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 209 static irqreturn_t tick_broadcast_ipi_action(int irq, void *data) 210 { 211 timer_broadcast_interrupt(); 212 return IRQ_HANDLED; 213 } 214 #endif 215 216 #ifdef CONFIG_NMI_IPI 217 static irqreturn_t nmi_ipi_action(int irq, void *data) 218 { 219 smp_handle_nmi_ipi(get_irq_regs()); 220 return IRQ_HANDLED; 221 } 222 #endif 223 224 static irq_handler_t smp_ipi_action[] = { 225 [PPC_MSG_CALL_FUNCTION] = call_function_action, 226 [PPC_MSG_RESCHEDULE] = reschedule_action, 227 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 228 [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action, 229 #endif 230 #ifdef CONFIG_NMI_IPI 231 [PPC_MSG_NMI_IPI] = nmi_ipi_action, 232 #endif 233 }; 234 235 /* 236 * The NMI IPI is a fallback and not truly non-maskable. It is simpler 237 * than going through the call function infrastructure, and strongly 238 * serialized, so it is more appropriate for debugging. 239 */ 240 const char *smp_ipi_name[] = { 241 [PPC_MSG_CALL_FUNCTION] = "ipi call function", 242 [PPC_MSG_RESCHEDULE] = "ipi reschedule", 243 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 244 [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast", 245 #endif 246 #ifdef CONFIG_NMI_IPI 247 [PPC_MSG_NMI_IPI] = "nmi ipi", 248 #endif 249 }; 250 251 /* optional function to request ipi, for controllers with >= 4 ipis */ 252 int smp_request_message_ipi(int virq, int msg) 253 { 254 int err; 255 256 if (msg < 0 || msg > PPC_MSG_NMI_IPI) 257 return -EINVAL; 258 #ifndef CONFIG_NMI_IPI 259 if (msg == PPC_MSG_NMI_IPI) 260 return 1; 261 #endif 262 263 err = request_irq(virq, smp_ipi_action[msg], 264 IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND, 265 smp_ipi_name[msg], NULL); 266 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", 267 virq, smp_ipi_name[msg], err); 268 269 return err; 270 } 271 272 #ifdef CONFIG_PPC_SMP_MUXED_IPI 273 struct cpu_messages { 274 long messages; /* current messages */ 275 }; 276 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message); 277 278 void smp_muxed_ipi_set_message(int cpu, int msg) 279 { 280 struct cpu_messages *info = &per_cpu(ipi_message, cpu); 281 char *message = (char *)&info->messages; 282 283 /* 284 * Order previous accesses before accesses in the IPI handler. 285 */ 286 smp_mb(); 287 WRITE_ONCE(message[msg], 1); 288 } 289 290 void smp_muxed_ipi_message_pass(int cpu, int msg) 291 { 292 if (!smp_ops->cause_ipi) 293 return; 294 295 smp_muxed_ipi_set_message(cpu, msg); 296 297 /* 298 * cause_ipi functions are required to include a full barrier 299 * before doing whatever causes the IPI. 300 */ 301 smp_ops->cause_ipi(cpu); 302 } 303 304 #ifdef __BIG_ENDIAN__ 305 #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A))) 306 #else 307 #define IPI_MESSAGE(A) (1uL << (8 * (A))) 308 #endif 309 310 irqreturn_t smp_ipi_demux(void) 311 { 312 mb(); /* order any irq clear */ 313 314 return smp_ipi_demux_relaxed(); 315 } 316 317 /* sync-free variant. Callers should ensure synchronization */ 318 irqreturn_t smp_ipi_demux_relaxed(void) 319 { 320 struct cpu_messages *info; 321 unsigned long all; 322 323 info = this_cpu_ptr(&ipi_message); 324 do { 325 all = xchg(&info->messages, 0); 326 #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) 327 /* 328 * Must check for PPC_MSG_RM_HOST_ACTION messages 329 * before PPC_MSG_CALL_FUNCTION messages because when 330 * a VM is destroyed, we call kick_all_cpus_sync() 331 * to ensure that any pending PPC_MSG_RM_HOST_ACTION 332 * messages have completed before we free any VCPUs. 333 */ 334 if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION)) 335 kvmppc_xics_ipi_action(); 336 #endif 337 if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION)) 338 generic_smp_call_function_interrupt(); 339 if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE)) 340 scheduler_ipi(); 341 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 342 if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST)) 343 timer_broadcast_interrupt(); 344 #endif 345 #ifdef CONFIG_NMI_IPI 346 if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI)) 347 nmi_ipi_action(0, NULL); 348 #endif 349 } while (READ_ONCE(info->messages)); 350 351 return IRQ_HANDLED; 352 } 353 #endif /* CONFIG_PPC_SMP_MUXED_IPI */ 354 355 static inline void do_message_pass(int cpu, int msg) 356 { 357 if (smp_ops->message_pass) 358 smp_ops->message_pass(cpu, msg); 359 #ifdef CONFIG_PPC_SMP_MUXED_IPI 360 else 361 smp_muxed_ipi_message_pass(cpu, msg); 362 #endif 363 } 364 365 void arch_smp_send_reschedule(int cpu) 366 { 367 if (likely(smp_ops)) 368 do_message_pass(cpu, PPC_MSG_RESCHEDULE); 369 } 370 EXPORT_SYMBOL_GPL(arch_smp_send_reschedule); 371 372 void arch_send_call_function_single_ipi(int cpu) 373 { 374 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); 375 } 376 377 void arch_send_call_function_ipi_mask(const struct cpumask *mask) 378 { 379 unsigned int cpu; 380 381 for_each_cpu(cpu, mask) 382 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); 383 } 384 385 #ifdef CONFIG_NMI_IPI 386 387 /* 388 * "NMI IPI" system. 389 * 390 * NMI IPIs may not be recoverable, so should not be used as ongoing part of 391 * a running system. They can be used for crash, debug, halt/reboot, etc. 392 * 393 * The IPI call waits with interrupts disabled until all targets enter the 394 * NMI handler, then returns. Subsequent IPIs can be issued before targets 395 * have returned from their handlers, so there is no guarantee about 396 * concurrency or re-entrancy. 397 * 398 * A new NMI can be issued before all targets exit the handler. 399 * 400 * The IPI call may time out without all targets entering the NMI handler. 401 * In that case, there is some logic to recover (and ignore subsequent 402 * NMI interrupts that may eventually be raised), but the platform interrupt 403 * handler may not be able to distinguish this from other exception causes, 404 * which may cause a crash. 405 */ 406 407 static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0); 408 static struct cpumask nmi_ipi_pending_mask; 409 static bool nmi_ipi_busy = false; 410 static void (*nmi_ipi_function)(struct pt_regs *) = NULL; 411 412 noinstr static void nmi_ipi_lock_start(unsigned long *flags) 413 { 414 raw_local_irq_save(*flags); 415 hard_irq_disable(); 416 while (raw_atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) { 417 raw_local_irq_restore(*flags); 418 spin_until_cond(raw_atomic_read(&__nmi_ipi_lock) == 0); 419 raw_local_irq_save(*flags); 420 hard_irq_disable(); 421 } 422 } 423 424 noinstr static void nmi_ipi_lock(void) 425 { 426 while (raw_atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) 427 spin_until_cond(raw_atomic_read(&__nmi_ipi_lock) == 0); 428 } 429 430 noinstr static void nmi_ipi_unlock(void) 431 { 432 smp_mb(); 433 WARN_ON(raw_atomic_read(&__nmi_ipi_lock) != 1); 434 raw_atomic_set(&__nmi_ipi_lock, 0); 435 } 436 437 noinstr static void nmi_ipi_unlock_end(unsigned long *flags) 438 { 439 nmi_ipi_unlock(); 440 raw_local_irq_restore(*flags); 441 } 442 443 /* 444 * Platform NMI handler calls this to ack 445 */ 446 noinstr int smp_handle_nmi_ipi(struct pt_regs *regs) 447 { 448 void (*fn)(struct pt_regs *) = NULL; 449 unsigned long flags; 450 int me = raw_smp_processor_id(); 451 int ret = 0; 452 453 /* 454 * Unexpected NMIs are possible here because the interrupt may not 455 * be able to distinguish NMI IPIs from other types of NMIs, or 456 * because the caller may have timed out. 457 */ 458 nmi_ipi_lock_start(&flags); 459 if (cpumask_test_cpu(me, &nmi_ipi_pending_mask)) { 460 cpumask_clear_cpu(me, &nmi_ipi_pending_mask); 461 fn = READ_ONCE(nmi_ipi_function); 462 WARN_ON_ONCE(!fn); 463 ret = 1; 464 } 465 nmi_ipi_unlock_end(&flags); 466 467 if (fn) 468 fn(regs); 469 470 return ret; 471 } 472 473 static void do_smp_send_nmi_ipi(int cpu, bool safe) 474 { 475 if (!safe && smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu)) 476 return; 477 478 if (cpu >= 0) { 479 do_message_pass(cpu, PPC_MSG_NMI_IPI); 480 } else { 481 int c; 482 483 for_each_online_cpu(c) { 484 if (c == raw_smp_processor_id()) 485 continue; 486 do_message_pass(c, PPC_MSG_NMI_IPI); 487 } 488 } 489 } 490 491 /* 492 * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS. 493 * - fn is the target callback function. 494 * - delay_us > 0 is the delay before giving up waiting for targets to 495 * begin executing the handler, == 0 specifies indefinite delay. 496 */ 497 static int __smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), 498 u64 delay_us, bool safe) 499 { 500 unsigned long flags; 501 int me = raw_smp_processor_id(); 502 int ret = 1; 503 504 BUG_ON(cpu == me); 505 BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS); 506 507 if (unlikely(!smp_ops)) 508 return 0; 509 510 nmi_ipi_lock_start(&flags); 511 while (nmi_ipi_busy) { 512 nmi_ipi_unlock_end(&flags); 513 spin_until_cond(!nmi_ipi_busy); 514 nmi_ipi_lock_start(&flags); 515 } 516 nmi_ipi_busy = true; 517 nmi_ipi_function = fn; 518 519 WARN_ON_ONCE(!cpumask_empty(&nmi_ipi_pending_mask)); 520 521 if (cpu < 0) { 522 /* ALL_OTHERS */ 523 cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask); 524 cpumask_clear_cpu(me, &nmi_ipi_pending_mask); 525 } else { 526 cpumask_set_cpu(cpu, &nmi_ipi_pending_mask); 527 } 528 529 nmi_ipi_unlock(); 530 531 /* Interrupts remain hard disabled */ 532 533 do_smp_send_nmi_ipi(cpu, safe); 534 535 nmi_ipi_lock(); 536 /* nmi_ipi_busy is set here, so unlock/lock is okay */ 537 while (!cpumask_empty(&nmi_ipi_pending_mask)) { 538 nmi_ipi_unlock(); 539 udelay(1); 540 nmi_ipi_lock(); 541 if (delay_us) { 542 delay_us--; 543 if (!delay_us) 544 break; 545 } 546 } 547 548 if (!cpumask_empty(&nmi_ipi_pending_mask)) { 549 /* Timeout waiting for CPUs to call smp_handle_nmi_ipi */ 550 ret = 0; 551 cpumask_clear(&nmi_ipi_pending_mask); 552 } 553 554 nmi_ipi_function = NULL; 555 nmi_ipi_busy = false; 556 557 nmi_ipi_unlock_end(&flags); 558 559 return ret; 560 } 561 562 int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) 563 { 564 return __smp_send_nmi_ipi(cpu, fn, delay_us, false); 565 } 566 567 int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) 568 { 569 return __smp_send_nmi_ipi(cpu, fn, delay_us, true); 570 } 571 #endif /* CONFIG_NMI_IPI */ 572 573 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 574 void tick_broadcast(const struct cpumask *mask) 575 { 576 unsigned int cpu; 577 578 for_each_cpu(cpu, mask) 579 do_message_pass(cpu, PPC_MSG_TICK_BROADCAST); 580 } 581 #endif 582 583 #ifdef CONFIG_DEBUGGER 584 static void debugger_ipi_callback(struct pt_regs *regs) 585 { 586 debugger_ipi(regs); 587 } 588 589 void smp_send_debugger_break(void) 590 { 591 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000); 592 } 593 #endif 594 595 #ifdef CONFIG_CRASH_DUMP 596 void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) 597 { 598 int cpu; 599 600 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000); 601 if (kdump_in_progress() && crash_wake_offline) { 602 for_each_present_cpu(cpu) { 603 if (cpu_online(cpu)) 604 continue; 605 /* 606 * crash_ipi_callback will wait for 607 * all cpus, including offline CPUs. 608 * We don't care about nmi_ipi_function. 609 * Offline cpus will jump straight into 610 * crash_ipi_callback, we can skip the 611 * entire NMI dance and waiting for 612 * cpus to clear pending mask, etc. 613 */ 614 do_smp_send_nmi_ipi(cpu, false); 615 } 616 } 617 } 618 #endif 619 620 void crash_smp_send_stop(void) 621 { 622 static bool stopped = false; 623 624 /* 625 * In case of fadump, register data for all CPUs is captured by f/w 626 * on ibm,os-term rtas call. Skip IPI callbacks to other CPUs before 627 * this rtas call to avoid tricky post processing of those CPUs' 628 * backtraces. 629 */ 630 if (should_fadump_crash()) 631 return; 632 633 if (stopped) 634 return; 635 636 stopped = true; 637 638 #ifdef CONFIG_CRASH_DUMP 639 if (kexec_crash_image) { 640 crash_kexec_prepare(); 641 return; 642 } 643 #endif 644 645 smp_send_stop(); 646 } 647 648 #ifdef CONFIG_NMI_IPI 649 static void nmi_stop_this_cpu(struct pt_regs *regs) 650 { 651 /* 652 * IRQs are already hard disabled by the smp_handle_nmi_ipi. 653 */ 654 set_cpu_online(smp_processor_id(), false); 655 656 spin_begin(); 657 while (1) 658 spin_cpu_relax(); 659 } 660 661 void smp_send_stop(void) 662 { 663 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000); 664 } 665 666 #else /* CONFIG_NMI_IPI */ 667 668 static void stop_this_cpu(void *dummy) 669 { 670 hard_irq_disable(); 671 672 /* 673 * Offlining CPUs in stop_this_cpu can result in scheduler warnings, 674 * (see commit de6e5d38417e), but printk_safe_flush_on_panic() wants 675 * to know other CPUs are offline before it breaks locks to flush 676 * printk buffers, in case we panic()ed while holding the lock. 677 */ 678 set_cpu_online(smp_processor_id(), false); 679 680 spin_begin(); 681 while (1) 682 spin_cpu_relax(); 683 } 684 685 void smp_send_stop(void) 686 { 687 static bool stopped = false; 688 689 /* 690 * Prevent waiting on csd lock from a previous smp_send_stop. 691 * This is racy, but in general callers try to do the right 692 * thing and only fire off one smp_send_stop (e.g., see 693 * kernel/panic.c) 694 */ 695 if (stopped) 696 return; 697 698 stopped = true; 699 700 smp_call_function(stop_this_cpu, NULL, 0); 701 } 702 #endif /* CONFIG_NMI_IPI */ 703 704 static struct task_struct *current_set[NR_CPUS]; 705 706 static void smp_store_cpu_info(int id) 707 { 708 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); 709 #ifdef CONFIG_PPC_E500 710 per_cpu(next_tlbcam_idx, id) 711 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; 712 #endif 713 } 714 715 /* 716 * Relationships between CPUs are maintained in a set of per-cpu cpumasks so 717 * rather than just passing around the cpumask we pass around a function that 718 * returns the that cpumask for the given CPU. 719 */ 720 static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int)) 721 { 722 cpumask_set_cpu(i, get_cpumask(j)); 723 cpumask_set_cpu(j, get_cpumask(i)); 724 } 725 726 #ifdef CONFIG_HOTPLUG_CPU 727 static void set_cpus_unrelated(int i, int j, 728 struct cpumask *(*get_cpumask)(int)) 729 { 730 cpumask_clear_cpu(i, get_cpumask(j)); 731 cpumask_clear_cpu(j, get_cpumask(i)); 732 } 733 #endif 734 735 /* 736 * Extends set_cpus_related. Instead of setting one CPU at a time in 737 * dstmask, set srcmask at oneshot. dstmask should be super set of srcmask. 738 */ 739 static void or_cpumasks_related(int i, int j, struct cpumask *(*srcmask)(int), 740 struct cpumask *(*dstmask)(int)) 741 { 742 struct cpumask *mask; 743 int k; 744 745 mask = srcmask(j); 746 for_each_cpu(k, srcmask(i)) 747 cpumask_or(dstmask(k), dstmask(k), mask); 748 749 if (i == j) 750 return; 751 752 mask = srcmask(i); 753 for_each_cpu(k, srcmask(j)) 754 cpumask_or(dstmask(k), dstmask(k), mask); 755 } 756 757 /* 758 * parse_thread_groups: Parses the "ibm,thread-groups" device tree 759 * property for the CPU device node @dn and stores 760 * the parsed output in the thread_groups_list 761 * structure @tglp. 762 * 763 * @dn: The device node of the CPU device. 764 * @tglp: Pointer to a thread group list structure into which the parsed 765 * output of "ibm,thread-groups" is stored. 766 * 767 * ibm,thread-groups[0..N-1] array defines which group of threads in 768 * the CPU-device node can be grouped together based on the property. 769 * 770 * This array can represent thread groupings for multiple properties. 771 * 772 * ibm,thread-groups[i + 0] tells us the property based on which the 773 * threads are being grouped together. If this value is 1, it implies 774 * that the threads in the same group share L1, translation cache. If 775 * the value is 2, it implies that the threads in the same group share 776 * the same L2 cache. 777 * 778 * ibm,thread-groups[i+1] tells us how many such thread groups exist for the 779 * property ibm,thread-groups[i] 780 * 781 * ibm,thread-groups[i+2] tells us the number of threads in each such 782 * group. 783 * Suppose k = (ibm,thread-groups[i+1] * ibm,thread-groups[i+2]), then, 784 * 785 * ibm,thread-groups[i+3..i+k+2] (is the list of threads identified by 786 * "ibm,ppc-interrupt-server#s" arranged as per their membership in 787 * the grouping. 788 * 789 * Example: 790 * If "ibm,thread-groups" = [1,2,4,8,10,12,14,9,11,13,15,2,2,4,8,10,12,14,9,11,13,15] 791 * This can be decomposed up into two consecutive arrays: 792 * a) [1,2,4,8,10,12,14,9,11,13,15] 793 * b) [2,2,4,8,10,12,14,9,11,13,15] 794 * 795 * where in, 796 * 797 * a) provides information of Property "1" being shared by "2" groups, 798 * each with "4" threads each. The "ibm,ppc-interrupt-server#s" of 799 * the first group is {8,10,12,14} and the 800 * "ibm,ppc-interrupt-server#s" of the second group is 801 * {9,11,13,15}. Property "1" is indicative of the thread in the 802 * group sharing L1 cache, translation cache and Instruction Data 803 * flow. 804 * 805 * b) provides information of Property "2" being shared by "2" groups, 806 * each group with "4" threads. The "ibm,ppc-interrupt-server#s" of 807 * the first group is {8,10,12,14} and the 808 * "ibm,ppc-interrupt-server#s" of the second group is 809 * {9,11,13,15}. Property "2" indicates that the threads in each 810 * group share the L2-cache. 811 * 812 * Returns 0 on success, -EINVAL if the property does not exist, 813 * -ENODATA if property does not have a value, and -EOVERFLOW if the 814 * property data isn't large enough. 815 */ 816 static int parse_thread_groups(struct device_node *dn, 817 struct thread_groups_list *tglp) 818 { 819 unsigned int property_idx = 0; 820 u32 *thread_group_array; 821 size_t total_threads; 822 int ret = 0, count; 823 u32 *thread_list; 824 int i = 0; 825 826 count = of_property_count_u32_elems(dn, "ibm,thread-groups"); 827 thread_group_array = kcalloc(count, sizeof(u32), GFP_KERNEL); 828 if (!thread_group_array) 829 return -ENOMEM; 830 ret = of_property_read_u32_array(dn, "ibm,thread-groups", 831 thread_group_array, count); 832 if (ret) 833 goto out_free; 834 835 while (i < count && property_idx < MAX_THREAD_GROUP_PROPERTIES) { 836 int j; 837 struct thread_groups *tg = &tglp->property_tgs[property_idx++]; 838 839 tg->property = thread_group_array[i]; 840 tg->nr_groups = thread_group_array[i + 1]; 841 tg->threads_per_group = thread_group_array[i + 2]; 842 total_threads = tg->nr_groups * tg->threads_per_group; 843 844 thread_list = &thread_group_array[i + 3]; 845 846 for (j = 0; j < total_threads; j++) 847 tg->thread_list[j] = thread_list[j]; 848 i = i + 3 + total_threads; 849 } 850 851 tglp->nr_properties = property_idx; 852 853 out_free: 854 kfree(thread_group_array); 855 return ret; 856 } 857 858 /* 859 * get_cpu_thread_group_start : Searches the thread group in tg->thread_list 860 * that @cpu belongs to. 861 * 862 * @cpu : The logical CPU whose thread group is being searched. 863 * @tg : The thread-group structure of the CPU node which @cpu belongs 864 * to. 865 * 866 * Returns the index to tg->thread_list that points to the start 867 * of the thread_group that @cpu belongs to. 868 * 869 * Returns -1 if cpu doesn't belong to any of the groups pointed to by 870 * tg->thread_list. 871 */ 872 static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg) 873 { 874 int hw_cpu_id = get_hard_smp_processor_id(cpu); 875 int i, j; 876 877 for (i = 0; i < tg->nr_groups; i++) { 878 int group_start = i * tg->threads_per_group; 879 880 for (j = 0; j < tg->threads_per_group; j++) { 881 int idx = group_start + j; 882 883 if (tg->thread_list[idx] == hw_cpu_id) 884 return group_start; 885 } 886 } 887 888 return -1; 889 } 890 891 static struct thread_groups *__init get_thread_groups(int cpu, 892 int group_property, 893 int *err) 894 { 895 struct device_node *dn = of_get_cpu_node(cpu, NULL); 896 struct thread_groups_list *cpu_tgl = &tgl[cpu]; 897 struct thread_groups *tg = NULL; 898 int i; 899 *err = 0; 900 901 if (!dn) { 902 *err = -ENODATA; 903 return NULL; 904 } 905 906 if (!cpu_tgl->nr_properties) { 907 *err = parse_thread_groups(dn, cpu_tgl); 908 if (*err) 909 goto out; 910 } 911 912 for (i = 0; i < cpu_tgl->nr_properties; i++) { 913 if (cpu_tgl->property_tgs[i].property == group_property) { 914 tg = &cpu_tgl->property_tgs[i]; 915 break; 916 } 917 } 918 919 if (!tg) 920 *err = -EINVAL; 921 out: 922 of_node_put(dn); 923 return tg; 924 } 925 926 static int __init update_mask_from_threadgroup(cpumask_var_t *mask, struct thread_groups *tg, 927 int cpu, int cpu_group_start) 928 { 929 int first_thread = cpu_first_thread_sibling(cpu); 930 int i; 931 932 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cpu)); 933 934 for (i = first_thread; i < first_thread + threads_per_core; i++) { 935 int i_group_start = get_cpu_thread_group_start(i, tg); 936 937 if (unlikely(i_group_start == -1)) { 938 WARN_ON_ONCE(1); 939 return -ENODATA; 940 } 941 942 if (i_group_start == cpu_group_start) 943 cpumask_set_cpu(i, *mask); 944 } 945 946 return 0; 947 } 948 949 static int __init init_thread_group_cache_map(int cpu, int cache_property) 950 951 { 952 int cpu_group_start = -1, err = 0; 953 struct thread_groups *tg = NULL; 954 cpumask_var_t *mask = NULL; 955 956 if (cache_property != THREAD_GROUP_SHARE_L1 && 957 cache_property != THREAD_GROUP_SHARE_L2_L3) 958 return -EINVAL; 959 960 tg = get_thread_groups(cpu, cache_property, &err); 961 962 if (!tg) 963 return err; 964 965 cpu_group_start = get_cpu_thread_group_start(cpu, tg); 966 967 if (unlikely(cpu_group_start == -1)) { 968 WARN_ON_ONCE(1); 969 return -ENODATA; 970 } 971 972 if (cache_property == THREAD_GROUP_SHARE_L1) { 973 mask = &per_cpu(thread_group_l1_cache_map, cpu); 974 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start); 975 } 976 else if (cache_property == THREAD_GROUP_SHARE_L2_L3) { 977 mask = &per_cpu(thread_group_l2_cache_map, cpu); 978 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start); 979 mask = &per_cpu(thread_group_l3_cache_map, cpu); 980 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start); 981 } 982 983 984 return 0; 985 } 986 987 static bool shared_caches __ro_after_init; 988 989 #ifdef CONFIG_SCHED_SMT 990 /* cpumask of CPUs with asymmetric SMT dependency */ 991 static int powerpc_smt_flags(void) 992 { 993 int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_LLC; 994 995 if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { 996 printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); 997 flags |= SD_ASYM_PACKING; 998 } 999 return flags; 1000 } 1001 #endif 1002 1003 /* 1004 * On shared processor LPARs scheduled on a big core (which has two or more 1005 * independent thread groups per core), prefer lower numbered CPUs, so 1006 * that workload consolidates to lesser number of cores. 1007 */ 1008 static __ro_after_init DEFINE_STATIC_KEY_FALSE(splpar_asym_pack); 1009 1010 /* 1011 * P9 has a slightly odd architecture where pairs of cores share an L2 cache. 1012 * This topology makes it *much* cheaper to migrate tasks between adjacent cores 1013 * since the migrated task remains cache hot. We want to take advantage of this 1014 * at the scheduler level so an extra topology level is required. 1015 */ 1016 static int powerpc_shared_cache_flags(void) 1017 { 1018 if (static_branch_unlikely(&splpar_asym_pack)) 1019 return SD_SHARE_LLC | SD_ASYM_PACKING; 1020 1021 return SD_SHARE_LLC; 1022 } 1023 1024 static int powerpc_shared_proc_flags(void) 1025 { 1026 if (static_branch_unlikely(&splpar_asym_pack)) 1027 return SD_ASYM_PACKING; 1028 1029 return 0; 1030 } 1031 1032 /* 1033 * We can't just pass cpu_l2_cache_mask() directly because 1034 * returns a non-const pointer and the compiler barfs on that. 1035 */ 1036 static const struct cpumask *tl_cache_mask(struct sched_domain_topology_level *tl, int cpu) 1037 { 1038 return per_cpu(cpu_l2_cache_map, cpu); 1039 } 1040 1041 #ifdef CONFIG_SCHED_SMT 1042 static const struct cpumask *tl_smallcore_smt_mask(struct sched_domain_topology_level *tl, int cpu) 1043 { 1044 return cpu_smallcore_mask(cpu); 1045 } 1046 #endif 1047 1048 struct cpumask *cpu_coregroup_mask(int cpu) 1049 { 1050 return per_cpu(cpu_coregroup_map, cpu); 1051 } 1052 1053 static bool has_coregroup_support(void) 1054 { 1055 /* Coregroup identification not available on shared systems */ 1056 if (is_shared_processor()) 1057 return 0; 1058 1059 return coregroup_enabled; 1060 } 1061 1062 static int __init init_big_cores(void) 1063 { 1064 int cpu; 1065 1066 for_each_possible_cpu(cpu) { 1067 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L1); 1068 1069 if (err) 1070 return err; 1071 1072 zalloc_cpumask_var_node(&per_cpu(cpu_smallcore_map, cpu), 1073 GFP_KERNEL, 1074 cpu_to_node(cpu)); 1075 } 1076 1077 has_big_cores = true; 1078 1079 for_each_possible_cpu(cpu) { 1080 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L2_L3); 1081 1082 if (err) 1083 return err; 1084 } 1085 1086 thread_group_shares_l2 = true; 1087 thread_group_shares_l3 = true; 1088 pr_debug("L2/L3 cache only shared by the threads in the small core\n"); 1089 1090 return 0; 1091 } 1092 1093 /* 1094 * die_mask and die_id are only available on systems which support 1095 * multiple coregroups within a same package. On all other systems, die_mask 1096 * would be same as package mask and die_id would be set to -1. 1097 */ 1098 const struct cpumask *cpu_die_mask(int cpu) 1099 { 1100 if (has_coregroup_support()) 1101 return per_cpu(cpu_coregroup_map, cpu); 1102 else 1103 return cpu_node_mask(cpu); 1104 } 1105 EXPORT_SYMBOL_GPL(cpu_die_mask); 1106 1107 int cpu_die_id(int cpu) 1108 { 1109 if (has_coregroup_support()) 1110 return cpu_to_coregroup_id(cpu); 1111 else 1112 return -1; 1113 } 1114 EXPORT_SYMBOL_GPL(cpu_die_id); 1115 1116 void __init smp_prepare_cpus(unsigned int max_cpus) 1117 { 1118 unsigned int cpu, num_threads; 1119 1120 DBG("smp_prepare_cpus\n"); 1121 1122 /* 1123 * setup_cpu may need to be called on the boot cpu. We haven't 1124 * spun any cpus up but lets be paranoid. 1125 */ 1126 BUG_ON(boot_cpuid != smp_processor_id()); 1127 1128 /* Fixup boot cpu */ 1129 smp_store_cpu_info(boot_cpuid); 1130 cpu_callin_map[boot_cpuid] = 1; 1131 1132 for_each_possible_cpu(cpu) { 1133 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), 1134 GFP_KERNEL, cpu_to_node(cpu)); 1135 zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu), 1136 GFP_KERNEL, cpu_to_node(cpu)); 1137 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), 1138 GFP_KERNEL, cpu_to_node(cpu)); 1139 if (has_coregroup_support()) 1140 zalloc_cpumask_var_node(&per_cpu(cpu_coregroup_map, cpu), 1141 GFP_KERNEL, cpu_to_node(cpu)); 1142 1143 #ifdef CONFIG_NUMA 1144 /* 1145 * numa_node_id() works after this. 1146 */ 1147 if (cpu_present(cpu)) { 1148 set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]); 1149 set_cpu_numa_mem(cpu, 1150 local_memory_node(numa_cpu_lookup_table[cpu])); 1151 } 1152 #endif 1153 } 1154 1155 /* Init the cpumasks so the boot CPU is related to itself */ 1156 cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid)); 1157 cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid)); 1158 cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid)); 1159 1160 if (has_coregroup_support()) 1161 cpumask_set_cpu(boot_cpuid, cpu_coregroup_mask(boot_cpuid)); 1162 1163 init_big_cores(); 1164 if (has_big_cores) { 1165 cpumask_set_cpu(boot_cpuid, 1166 cpu_smallcore_mask(boot_cpuid)); 1167 } 1168 1169 if (cpu_to_chip_id(boot_cpuid) != -1) { 1170 int idx = DIV_ROUND_UP(num_possible_cpus(), threads_per_core); 1171 1172 /* 1173 * All threads of a core will all belong to the same core, 1174 * chip_id_lookup_table will have one entry per core. 1175 * Assumption: if boot_cpuid doesn't have a chip-id, then no 1176 * other CPUs, will also not have chip-id. 1177 */ 1178 chip_id_lookup_table = kzalloc_objs(int, idx); 1179 if (chip_id_lookup_table) 1180 memset(chip_id_lookup_table, -1, sizeof(int) * idx); 1181 } 1182 1183 if (smp_ops && smp_ops->probe) 1184 smp_ops->probe(); 1185 1186 // Initalise the generic SMT topology support 1187 num_threads = 1; 1188 if (smt_enabled_at_boot) 1189 num_threads = smt_enabled_at_boot; 1190 cpu_smt_set_num_threads(num_threads, threads_per_core); 1191 } 1192 1193 void __init smp_prepare_boot_cpu(void) 1194 { 1195 BUG_ON(smp_processor_id() != boot_cpuid); 1196 #ifdef CONFIG_PPC64 1197 paca_ptrs[boot_cpuid]->__current = current; 1198 #endif 1199 set_numa_node(numa_cpu_lookup_table[boot_cpuid]); 1200 current_set[boot_cpuid] = current; 1201 } 1202 1203 #ifdef CONFIG_HOTPLUG_CPU 1204 1205 int generic_cpu_disable(void) 1206 { 1207 unsigned int cpu = smp_processor_id(); 1208 1209 if (cpu == boot_cpuid) 1210 return -EBUSY; 1211 1212 set_cpu_online(cpu, false); 1213 #ifdef CONFIG_PPC64_PROC_SYSTEMCFG 1214 systemcfg->processorCount--; 1215 #endif 1216 /* Update affinity of all IRQs previously aimed at this CPU */ 1217 irq_migrate_all_off_this_cpu(); 1218 1219 /* 1220 * Depending on the details of the interrupt controller, it's possible 1221 * that one of the interrupts we just migrated away from this CPU is 1222 * actually already pending on this CPU. If we leave it in that state 1223 * the interrupt will never be EOI'ed, and will never fire again. So 1224 * temporarily enable interrupts here, to allow any pending interrupt to 1225 * be received (and EOI'ed), before we take this CPU offline. 1226 */ 1227 local_irq_enable(); 1228 mdelay(1); 1229 local_irq_disable(); 1230 1231 return 0; 1232 } 1233 1234 void generic_cpu_die(unsigned int cpu) 1235 { 1236 int i; 1237 1238 for (i = 0; i < 100; i++) { 1239 smp_rmb(); 1240 if (is_cpu_dead(cpu)) 1241 return; 1242 msleep(100); 1243 } 1244 printk(KERN_ERR "CPU%d didn't die...\n", cpu); 1245 } 1246 1247 void generic_set_cpu_dead(unsigned int cpu) 1248 { 1249 per_cpu(cpu_state, cpu) = CPU_DEAD; 1250 } 1251 1252 /* 1253 * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise 1254 * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), 1255 * which makes the delay in generic_cpu_die() not happen. 1256 */ 1257 void generic_set_cpu_up(unsigned int cpu) 1258 { 1259 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 1260 } 1261 1262 int generic_check_cpu_restart(unsigned int cpu) 1263 { 1264 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; 1265 } 1266 1267 int is_cpu_dead(unsigned int cpu) 1268 { 1269 return per_cpu(cpu_state, cpu) == CPU_DEAD; 1270 } 1271 1272 static bool secondaries_inhibited(void) 1273 { 1274 return kvm_hv_mode_active(); 1275 } 1276 1277 #else /* HOTPLUG_CPU */ 1278 1279 #define secondaries_inhibited() 0 1280 1281 #endif 1282 1283 static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle) 1284 { 1285 #ifdef CONFIG_PPC64 1286 paca_ptrs[cpu]->__current = idle; 1287 paca_ptrs[cpu]->kstack = (unsigned long)task_stack_page(idle) + 1288 THREAD_SIZE - STACK_FRAME_MIN_SIZE; 1289 #endif 1290 task_thread_info(idle)->cpu = cpu; 1291 secondary_current = current_set[cpu] = idle; 1292 } 1293 1294 int __cpu_up(unsigned int cpu, struct task_struct *tidle) 1295 { 1296 const unsigned long boot_spin_ms = 5 * MSEC_PER_SEC; 1297 const bool booting = system_state < SYSTEM_RUNNING; 1298 const unsigned long hp_spin_ms = 1; 1299 unsigned long deadline; 1300 int rc; 1301 const unsigned long spin_wait_ms = booting ? boot_spin_ms : hp_spin_ms; 1302 1303 /* 1304 * Don't allow secondary threads to come online if inhibited 1305 */ 1306 if (threads_per_core > 1 && secondaries_inhibited() && 1307 cpu_thread_in_subcore(cpu)) 1308 return -EBUSY; 1309 1310 if (smp_ops == NULL || 1311 (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) 1312 return -EINVAL; 1313 1314 cpu_idle_thread_init(cpu, tidle); 1315 1316 /* 1317 * The platform might need to allocate resources prior to bringing 1318 * up the CPU 1319 */ 1320 if (smp_ops->prepare_cpu) { 1321 rc = smp_ops->prepare_cpu(cpu); 1322 if (rc) 1323 return rc; 1324 } 1325 1326 /* Make sure callin-map entry is 0 (can be leftover a CPU 1327 * hotplug 1328 */ 1329 cpu_callin_map[cpu] = 0; 1330 1331 /* The information for processor bringup must 1332 * be written out to main store before we release 1333 * the processor. 1334 */ 1335 smp_mb(); 1336 1337 /* wake up cpus */ 1338 DBG("smp: kicking cpu %d\n", cpu); 1339 rc = smp_ops->kick_cpu(cpu); 1340 if (rc) { 1341 pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc); 1342 return rc; 1343 } 1344 1345 /* 1346 * At boot time, simply spin on the callin word until the 1347 * deadline passes. 1348 * 1349 * At run time, spin for an optimistic amount of time to avoid 1350 * sleeping in the common case. 1351 */ 1352 deadline = jiffies + msecs_to_jiffies(spin_wait_ms); 1353 spin_until_cond(cpu_callin_map[cpu] || time_is_before_jiffies(deadline)); 1354 1355 if (!cpu_callin_map[cpu] && system_state >= SYSTEM_RUNNING) { 1356 const unsigned long sleep_interval_us = 10 * USEC_PER_MSEC; 1357 const unsigned long sleep_wait_ms = 100 * MSEC_PER_SEC; 1358 1359 deadline = jiffies + msecs_to_jiffies(sleep_wait_ms); 1360 while (!cpu_callin_map[cpu] && time_is_after_jiffies(deadline)) 1361 fsleep(sleep_interval_us); 1362 } 1363 1364 if (!cpu_callin_map[cpu]) { 1365 printk(KERN_ERR "Processor %u is stuck.\n", cpu); 1366 return -ENOENT; 1367 } 1368 1369 DBG("Processor %u found.\n", cpu); 1370 1371 if (smp_ops->give_timebase) 1372 smp_ops->give_timebase(); 1373 1374 /* Wait until cpu puts itself in the online & active maps */ 1375 spin_until_cond(cpu_online(cpu)); 1376 1377 return 0; 1378 } 1379 1380 /* Return the value of the reg property corresponding to the given 1381 * logical cpu. 1382 */ 1383 int cpu_to_core_id(int cpu) 1384 { 1385 struct device_node *np; 1386 int id = -1; 1387 1388 np = of_get_cpu_node(cpu, NULL); 1389 if (!np) 1390 goto out; 1391 1392 id = of_get_cpu_hwid(np, 0); 1393 out: 1394 of_node_put(np); 1395 return id; 1396 } 1397 EXPORT_SYMBOL_GPL(cpu_to_core_id); 1398 1399 /* Helper routines for cpu to core mapping */ 1400 int cpu_core_index_of_thread(int cpu) 1401 { 1402 return cpu >> threads_shift; 1403 } 1404 EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); 1405 1406 int cpu_first_thread_of_core(int core) 1407 { 1408 return core << threads_shift; 1409 } 1410 EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); 1411 1412 /* Must be called when no change can occur to cpu_present_mask, 1413 * i.e. during cpu online or offline. 1414 */ 1415 static struct device_node *cpu_to_l2cache(int cpu) 1416 { 1417 struct device_node *np; 1418 struct device_node *cache; 1419 1420 if (!cpu_present(cpu)) 1421 return NULL; 1422 1423 np = of_get_cpu_node(cpu, NULL); 1424 if (np == NULL) 1425 return NULL; 1426 1427 cache = of_find_next_cache_node(np); 1428 1429 of_node_put(np); 1430 1431 return cache; 1432 } 1433 1434 static bool update_mask_by_l2(int cpu, cpumask_var_t *mask) 1435 { 1436 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask; 1437 struct device_node *l2_cache, *np; 1438 int i; 1439 1440 if (has_big_cores) 1441 submask_fn = cpu_smallcore_mask; 1442 1443 /* 1444 * If the threads in a thread-group share L2 cache, then the 1445 * L2-mask can be obtained from thread_group_l2_cache_map. 1446 */ 1447 if (thread_group_shares_l2) { 1448 cpumask_set_cpu(cpu, cpu_l2_cache_mask(cpu)); 1449 1450 for_each_cpu(i, per_cpu(thread_group_l2_cache_map, cpu)) { 1451 if (cpu_online(i)) 1452 set_cpus_related(i, cpu, cpu_l2_cache_mask); 1453 } 1454 1455 /* Verify that L1-cache siblings are a subset of L2 cache-siblings */ 1456 if (!cpumask_equal(submask_fn(cpu), cpu_l2_cache_mask(cpu)) && 1457 !cpumask_subset(submask_fn(cpu), cpu_l2_cache_mask(cpu))) { 1458 pr_warn_once("CPU %d : Inconsistent L1 and L2 cache siblings\n", 1459 cpu); 1460 } 1461 1462 return true; 1463 } 1464 1465 l2_cache = cpu_to_l2cache(cpu); 1466 if (!l2_cache || !*mask) { 1467 /* Assume only core siblings share cache with this CPU */ 1468 for_each_cpu(i, cpu_sibling_mask(cpu)) 1469 set_cpus_related(cpu, i, cpu_l2_cache_mask); 1470 1471 return false; 1472 } 1473 1474 cpumask_and(*mask, cpu_online_mask, cpu_node_mask(cpu)); 1475 1476 /* Update l2-cache mask with all the CPUs that are part of submask */ 1477 or_cpumasks_related(cpu, cpu, submask_fn, cpu_l2_cache_mask); 1478 1479 /* Skip all CPUs already part of current CPU l2-cache mask */ 1480 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(cpu)); 1481 1482 for_each_cpu(i, *mask) { 1483 /* 1484 * when updating the marks the current CPU has not been marked 1485 * online, but we need to update the cache masks 1486 */ 1487 np = cpu_to_l2cache(i); 1488 1489 /* Skip all CPUs already part of current CPU l2-cache */ 1490 if (np == l2_cache) { 1491 or_cpumasks_related(cpu, i, submask_fn, cpu_l2_cache_mask); 1492 cpumask_andnot(*mask, *mask, submask_fn(i)); 1493 } else { 1494 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(i)); 1495 } 1496 1497 of_node_put(np); 1498 } 1499 of_node_put(l2_cache); 1500 1501 return true; 1502 } 1503 1504 #ifdef CONFIG_HOTPLUG_CPU 1505 static void remove_cpu_from_masks(int cpu) 1506 { 1507 struct cpumask *(*mask_fn)(int) = cpu_sibling_mask; 1508 int i; 1509 1510 unmap_cpu_from_node(cpu); 1511 1512 if (shared_caches) 1513 mask_fn = cpu_l2_cache_mask; 1514 1515 for_each_cpu(i, mask_fn(cpu)) { 1516 set_cpus_unrelated(cpu, i, cpu_l2_cache_mask); 1517 set_cpus_unrelated(cpu, i, cpu_sibling_mask); 1518 if (has_big_cores) 1519 set_cpus_unrelated(cpu, i, cpu_smallcore_mask); 1520 } 1521 1522 for_each_cpu(i, cpu_core_mask(cpu)) 1523 set_cpus_unrelated(cpu, i, cpu_core_mask); 1524 1525 if (has_coregroup_support()) { 1526 for_each_cpu(i, cpu_coregroup_mask(cpu)) 1527 set_cpus_unrelated(cpu, i, cpu_coregroup_mask); 1528 } 1529 } 1530 #endif 1531 1532 static inline void add_cpu_to_smallcore_masks(int cpu) 1533 { 1534 int i; 1535 1536 if (!has_big_cores) 1537 return; 1538 1539 cpumask_set_cpu(cpu, cpu_smallcore_mask(cpu)); 1540 1541 for_each_cpu(i, per_cpu(thread_group_l1_cache_map, cpu)) { 1542 if (cpu_online(i)) 1543 set_cpus_related(i, cpu, cpu_smallcore_mask); 1544 } 1545 } 1546 1547 static void update_coregroup_mask(int cpu, cpumask_var_t *mask) 1548 { 1549 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask; 1550 int coregroup_id = cpu_to_coregroup_id(cpu); 1551 int i; 1552 1553 if (shared_caches) 1554 submask_fn = cpu_l2_cache_mask; 1555 1556 if (!*mask) { 1557 /* Assume only siblings are part of this CPU's coregroup */ 1558 for_each_cpu(i, submask_fn(cpu)) 1559 set_cpus_related(cpu, i, cpu_coregroup_mask); 1560 1561 return; 1562 } 1563 1564 cpumask_and(*mask, cpu_online_mask, cpu_node_mask(cpu)); 1565 1566 /* Update coregroup mask with all the CPUs that are part of submask */ 1567 or_cpumasks_related(cpu, cpu, submask_fn, cpu_coregroup_mask); 1568 1569 /* Skip all CPUs already part of coregroup mask */ 1570 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(cpu)); 1571 1572 for_each_cpu(i, *mask) { 1573 /* Skip all CPUs not part of this coregroup */ 1574 if (coregroup_id == cpu_to_coregroup_id(i)) { 1575 or_cpumasks_related(cpu, i, submask_fn, cpu_coregroup_mask); 1576 cpumask_andnot(*mask, *mask, submask_fn(i)); 1577 } else { 1578 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(i)); 1579 } 1580 } 1581 } 1582 1583 static void add_cpu_to_masks(int cpu) 1584 { 1585 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask; 1586 int first_thread = cpu_first_thread_sibling(cpu); 1587 cpumask_var_t mask; 1588 int chip_id = -1; 1589 bool ret; 1590 int i; 1591 1592 /* 1593 * This CPU will not be in the online mask yet so we need to manually 1594 * add it to its own thread sibling mask. 1595 */ 1596 map_cpu_to_node(cpu, cpu_to_node(cpu)); 1597 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 1598 cpumask_set_cpu(cpu, cpu_core_mask(cpu)); 1599 1600 for (i = first_thread; i < first_thread + threads_per_core; i++) 1601 if (cpu_online(i)) 1602 set_cpus_related(i, cpu, cpu_sibling_mask); 1603 1604 add_cpu_to_smallcore_masks(cpu); 1605 1606 /* In CPU-hotplug path, hence use GFP_ATOMIC */ 1607 ret = alloc_cpumask_var_node(&mask, GFP_ATOMIC, cpu_to_node(cpu)); 1608 update_mask_by_l2(cpu, &mask); 1609 1610 if (has_coregroup_support()) 1611 update_coregroup_mask(cpu, &mask); 1612 1613 if (chip_id_lookup_table && ret) 1614 chip_id = cpu_to_chip_id(cpu); 1615 1616 if (shared_caches) 1617 submask_fn = cpu_l2_cache_mask; 1618 1619 /* Update core_mask with all the CPUs that are part of submask */ 1620 or_cpumasks_related(cpu, cpu, submask_fn, cpu_core_mask); 1621 1622 /* Skip all CPUs already part of current CPU core mask */ 1623 cpumask_andnot(mask, cpu_online_mask, cpu_core_mask(cpu)); 1624 1625 /* If chip_id is -1; limit the cpu_core_mask to within PKG */ 1626 if (chip_id == -1) 1627 cpumask_and(mask, mask, cpu_node_mask(cpu)); 1628 1629 for_each_cpu(i, mask) { 1630 if (chip_id == cpu_to_chip_id(i)) { 1631 or_cpumasks_related(cpu, i, submask_fn, cpu_core_mask); 1632 cpumask_andnot(mask, mask, submask_fn(i)); 1633 } else { 1634 cpumask_andnot(mask, mask, cpu_core_mask(i)); 1635 } 1636 } 1637 1638 free_cpumask_var(mask); 1639 } 1640 1641 /* Activate a secondary processor. */ 1642 __no_stack_protector 1643 void start_secondary(void *unused) 1644 { 1645 unsigned int cpu = raw_smp_processor_id(); 1646 1647 /* PPC64 calls setup_kup() in early_setup_secondary() */ 1648 if (IS_ENABLED(CONFIG_PPC32)) 1649 setup_kup(); 1650 1651 mmgrab_lazy_tlb(&init_mm); 1652 current->active_mm = &init_mm; 1653 VM_WARN_ON(cpumask_test_cpu(smp_processor_id(), mm_cpumask(&init_mm))); 1654 cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); 1655 inc_mm_active_cpus(&init_mm); 1656 1657 smp_store_cpu_info(cpu); 1658 set_dec(tb_ticks_per_jiffy); 1659 rcutree_report_cpu_starting(cpu); 1660 cpu_callin_map[cpu] = 1; 1661 1662 if (smp_ops->setup_cpu) 1663 smp_ops->setup_cpu(cpu); 1664 if (smp_ops->take_timebase) 1665 smp_ops->take_timebase(); 1666 1667 secondary_cpu_time_init(); 1668 1669 #ifdef CONFIG_PPC64_PROC_SYSTEMCFG 1670 if (system_state == SYSTEM_RUNNING) 1671 systemcfg->processorCount++; 1672 #endif 1673 1674 #ifdef CONFIG_PPC64 1675 vdso_getcpu_init(); 1676 #endif 1677 set_numa_node(numa_cpu_lookup_table[cpu]); 1678 set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu])); 1679 1680 /* Update topology CPU masks */ 1681 add_cpu_to_masks(cpu); 1682 1683 /* 1684 * Check for any shared caches. Note that this must be done on a 1685 * per-core basis because one core in the pair might be disabled. 1686 */ 1687 if (!shared_caches) { 1688 struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask; 1689 struct cpumask *mask = cpu_l2_cache_mask(cpu); 1690 1691 if (has_big_cores) 1692 sibling_mask = cpu_smallcore_mask; 1693 1694 if (cpumask_weight(mask) > cpumask_weight(sibling_mask(cpu))) 1695 shared_caches = true; 1696 } 1697 1698 smp_wmb(); 1699 notify_cpu_starting(cpu); 1700 set_cpu_online(cpu, true); 1701 1702 boot_init_stack_canary(); 1703 1704 local_irq_enable(); 1705 1706 /* We can enable ftrace for secondary cpus now */ 1707 this_cpu_enable_ftrace(); 1708 1709 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 1710 1711 BUG(); 1712 } 1713 1714 static struct sched_domain_topology_level powerpc_topology[6]; 1715 1716 static void __init build_sched_topology(void) 1717 { 1718 int i = 0; 1719 1720 if (is_shared_processor() && has_big_cores) 1721 static_branch_enable(&splpar_asym_pack); 1722 1723 #ifdef CONFIG_SCHED_SMT 1724 if (has_big_cores) { 1725 pr_info("Big cores detected but using small core scheduling\n"); 1726 powerpc_topology[i++] = 1727 SDTL_INIT(tl_smallcore_smt_mask, powerpc_smt_flags, SMT); 1728 } else { 1729 powerpc_topology[i++] = SDTL_INIT(tl_smt_mask, powerpc_smt_flags, SMT); 1730 } 1731 #endif 1732 if (shared_caches) { 1733 powerpc_topology[i++] = 1734 SDTL_INIT(tl_cache_mask, powerpc_shared_cache_flags, CACHE); 1735 } 1736 1737 if (has_coregroup_support()) { 1738 powerpc_topology[i++] = 1739 SDTL_INIT(tl_mc_mask, powerpc_shared_proc_flags, MC); 1740 } 1741 1742 powerpc_topology[i++] = SDTL_INIT(tl_pkg_mask, powerpc_shared_proc_flags, PKG); 1743 1744 /* There must be one trailing NULL entry left. */ 1745 BUG_ON(i >= ARRAY_SIZE(powerpc_topology) - 1); 1746 1747 set_sched_topology(powerpc_topology); 1748 } 1749 1750 void __init smp_cpus_done(unsigned int max_cpus) 1751 { 1752 /* 1753 * We are running pinned to the boot CPU, see rest_init(). 1754 */ 1755 if (smp_ops && smp_ops->setup_cpu) 1756 smp_ops->setup_cpu(boot_cpuid); 1757 1758 if (smp_ops && smp_ops->bringup_done) 1759 smp_ops->bringup_done(); 1760 1761 dump_numa_cpu_topology(); 1762 build_sched_topology(); 1763 } 1764 1765 /* 1766 * For asym packing, by default lower numbered CPU has higher priority. 1767 * On shared processors, pack to lower numbered core. However avoid moving 1768 * between thread_groups within the same core. 1769 */ 1770 int arch_asym_cpu_priority(int cpu) 1771 { 1772 if (static_branch_unlikely(&splpar_asym_pack)) 1773 return -cpu / threads_per_core; 1774 1775 return -cpu; 1776 } 1777 1778 #ifdef CONFIG_HOTPLUG_CPU 1779 int __cpu_disable(void) 1780 { 1781 int cpu = smp_processor_id(); 1782 int err; 1783 1784 if (!smp_ops->cpu_disable) 1785 return -ENOSYS; 1786 1787 this_cpu_disable_ftrace(); 1788 1789 err = smp_ops->cpu_disable(); 1790 if (err) 1791 return err; 1792 1793 /* Update sibling maps */ 1794 remove_cpu_from_masks(cpu); 1795 1796 return 0; 1797 } 1798 1799 void __cpu_die(unsigned int cpu) 1800 { 1801 /* 1802 * This could perhaps be a generic call in idlea_task_dead(), but 1803 * that requires testing from all archs, so first put it here to 1804 */ 1805 VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu, mm_cpumask(&init_mm))); 1806 dec_mm_active_cpus(&init_mm); 1807 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); 1808 1809 if (smp_ops->cpu_die) 1810 smp_ops->cpu_die(cpu); 1811 } 1812 1813 void __noreturn arch_cpu_idle_dead(void) 1814 { 1815 /* 1816 * Disable on the down path. This will be re-enabled by 1817 * start_secondary() via start_secondary_resume() below 1818 */ 1819 this_cpu_disable_ftrace(); 1820 1821 if (smp_ops->cpu_offline_self) 1822 smp_ops->cpu_offline_self(); 1823 1824 /* If we return, we re-enter start_secondary */ 1825 start_secondary_resume(); 1826 } 1827 1828 #endif 1829