1 /* 2 * SMP support for ppc. 3 * 4 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great 5 * deal of code from the sparc and intel versions. 6 * 7 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> 8 * 9 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and 10 * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * as published by the Free Software Foundation; either version 15 * 2 of the License, or (at your option) any later version. 16 */ 17 18 #undef DEBUG 19 20 #include <linux/kernel.h> 21 #include <linux/export.h> 22 #include <linux/sched/mm.h> 23 #include <linux/sched/task_stack.h> 24 #include <linux/sched/topology.h> 25 #include <linux/smp.h> 26 #include <linux/interrupt.h> 27 #include <linux/delay.h> 28 #include <linux/init.h> 29 #include <linux/spinlock.h> 30 #include <linux/cache.h> 31 #include <linux/err.h> 32 #include <linux/device.h> 33 #include <linux/cpu.h> 34 #include <linux/notifier.h> 35 #include <linux/topology.h> 36 #include <linux/profile.h> 37 #include <linux/processor.h> 38 #include <linux/random.h> 39 #include <linux/stackprotector.h> 40 41 #include <asm/ptrace.h> 42 #include <linux/atomic.h> 43 #include <asm/irq.h> 44 #include <asm/hw_irq.h> 45 #include <asm/kvm_ppc.h> 46 #include <asm/dbell.h> 47 #include <asm/page.h> 48 #include <asm/pgtable.h> 49 #include <asm/prom.h> 50 #include <asm/smp.h> 51 #include <asm/time.h> 52 #include <asm/machdep.h> 53 #include <asm/cputhreads.h> 54 #include <asm/cputable.h> 55 #include <asm/mpic.h> 56 #include <asm/vdso_datapage.h> 57 #ifdef CONFIG_PPC64 58 #include <asm/paca.h> 59 #endif 60 #include <asm/vdso.h> 61 #include <asm/debug.h> 62 #include <asm/kexec.h> 63 #include <asm/asm-prototypes.h> 64 #include <asm/cpu_has_feature.h> 65 #include <asm/ftrace.h> 66 67 #ifdef DEBUG 68 #include <asm/udbg.h> 69 #define DBG(fmt...) udbg_printf(fmt) 70 #else 71 #define DBG(fmt...) 72 #endif 73 74 #ifdef CONFIG_HOTPLUG_CPU 75 /* State of each CPU during hotplug phases */ 76 static DEFINE_PER_CPU(int, cpu_state) = { 0 }; 77 #endif 78 79 struct task_struct *secondary_current; 80 bool has_big_cores; 81 82 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 83 DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map); 84 DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map); 85 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 86 87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 88 EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map); 89 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 90 EXPORT_SYMBOL_GPL(has_big_cores); 91 92 #define MAX_THREAD_LIST_SIZE 8 93 #define THREAD_GROUP_SHARE_L1 1 94 struct thread_groups { 95 unsigned int property; 96 unsigned int nr_groups; 97 unsigned int threads_per_group; 98 unsigned int thread_list[MAX_THREAD_LIST_SIZE]; 99 }; 100 101 /* 102 * On big-cores system, cpu_l1_cache_map for each CPU corresponds to 103 * the set its siblings that share the L1-cache. 104 */ 105 DEFINE_PER_CPU(cpumask_var_t, cpu_l1_cache_map); 106 107 /* SMP operations for this machine */ 108 struct smp_ops_t *smp_ops; 109 110 /* Can't be static due to PowerMac hackery */ 111 volatile unsigned int cpu_callin_map[NR_CPUS]; 112 113 int smt_enabled_at_boot = 1; 114 115 /* 116 * Returns 1 if the specified cpu should be brought up during boot. 117 * Used to inhibit booting threads if they've been disabled or 118 * limited on the command line 119 */ 120 int smp_generic_cpu_bootable(unsigned int nr) 121 { 122 /* Special case - we inhibit secondary thread startup 123 * during boot if the user requests it. 124 */ 125 if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) { 126 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0) 127 return 0; 128 if (smt_enabled_at_boot 129 && cpu_thread_in_core(nr) >= smt_enabled_at_boot) 130 return 0; 131 } 132 133 return 1; 134 } 135 136 137 #ifdef CONFIG_PPC64 138 int smp_generic_kick_cpu(int nr) 139 { 140 if (nr < 0 || nr >= nr_cpu_ids) 141 return -EINVAL; 142 143 /* 144 * The processor is currently spinning, waiting for the 145 * cpu_start field to become non-zero After we set cpu_start, 146 * the processor will continue on to secondary_start 147 */ 148 if (!paca_ptrs[nr]->cpu_start) { 149 paca_ptrs[nr]->cpu_start = 1; 150 smp_mb(); 151 return 0; 152 } 153 154 #ifdef CONFIG_HOTPLUG_CPU 155 /* 156 * Ok it's not there, so it might be soft-unplugged, let's 157 * try to bring it back 158 */ 159 generic_set_cpu_up(nr); 160 smp_wmb(); 161 smp_send_reschedule(nr); 162 #endif /* CONFIG_HOTPLUG_CPU */ 163 164 return 0; 165 } 166 #endif /* CONFIG_PPC64 */ 167 168 static irqreturn_t call_function_action(int irq, void *data) 169 { 170 generic_smp_call_function_interrupt(); 171 return IRQ_HANDLED; 172 } 173 174 static irqreturn_t reschedule_action(int irq, void *data) 175 { 176 scheduler_ipi(); 177 return IRQ_HANDLED; 178 } 179 180 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 181 static irqreturn_t tick_broadcast_ipi_action(int irq, void *data) 182 { 183 timer_broadcast_interrupt(); 184 return IRQ_HANDLED; 185 } 186 #endif 187 188 #ifdef CONFIG_NMI_IPI 189 static irqreturn_t nmi_ipi_action(int irq, void *data) 190 { 191 smp_handle_nmi_ipi(get_irq_regs()); 192 return IRQ_HANDLED; 193 } 194 #endif 195 196 static irq_handler_t smp_ipi_action[] = { 197 [PPC_MSG_CALL_FUNCTION] = call_function_action, 198 [PPC_MSG_RESCHEDULE] = reschedule_action, 199 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 200 [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action, 201 #endif 202 #ifdef CONFIG_NMI_IPI 203 [PPC_MSG_NMI_IPI] = nmi_ipi_action, 204 #endif 205 }; 206 207 /* 208 * The NMI IPI is a fallback and not truly non-maskable. It is simpler 209 * than going through the call function infrastructure, and strongly 210 * serialized, so it is more appropriate for debugging. 211 */ 212 const char *smp_ipi_name[] = { 213 [PPC_MSG_CALL_FUNCTION] = "ipi call function", 214 [PPC_MSG_RESCHEDULE] = "ipi reschedule", 215 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 216 [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast", 217 #endif 218 #ifdef CONFIG_NMI_IPI 219 [PPC_MSG_NMI_IPI] = "nmi ipi", 220 #endif 221 }; 222 223 /* optional function to request ipi, for controllers with >= 4 ipis */ 224 int smp_request_message_ipi(int virq, int msg) 225 { 226 int err; 227 228 if (msg < 0 || msg > PPC_MSG_NMI_IPI) 229 return -EINVAL; 230 #ifndef CONFIG_NMI_IPI 231 if (msg == PPC_MSG_NMI_IPI) 232 return 1; 233 #endif 234 235 err = request_irq(virq, smp_ipi_action[msg], 236 IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND, 237 smp_ipi_name[msg], NULL); 238 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", 239 virq, smp_ipi_name[msg], err); 240 241 return err; 242 } 243 244 #ifdef CONFIG_PPC_SMP_MUXED_IPI 245 struct cpu_messages { 246 long messages; /* current messages */ 247 }; 248 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message); 249 250 void smp_muxed_ipi_set_message(int cpu, int msg) 251 { 252 struct cpu_messages *info = &per_cpu(ipi_message, cpu); 253 char *message = (char *)&info->messages; 254 255 /* 256 * Order previous accesses before accesses in the IPI handler. 257 */ 258 smp_mb(); 259 message[msg] = 1; 260 } 261 262 void smp_muxed_ipi_message_pass(int cpu, int msg) 263 { 264 smp_muxed_ipi_set_message(cpu, msg); 265 266 /* 267 * cause_ipi functions are required to include a full barrier 268 * before doing whatever causes the IPI. 269 */ 270 smp_ops->cause_ipi(cpu); 271 } 272 273 #ifdef __BIG_ENDIAN__ 274 #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A))) 275 #else 276 #define IPI_MESSAGE(A) (1uL << (8 * (A))) 277 #endif 278 279 irqreturn_t smp_ipi_demux(void) 280 { 281 mb(); /* order any irq clear */ 282 283 return smp_ipi_demux_relaxed(); 284 } 285 286 /* sync-free variant. Callers should ensure synchronization */ 287 irqreturn_t smp_ipi_demux_relaxed(void) 288 { 289 struct cpu_messages *info; 290 unsigned long all; 291 292 info = this_cpu_ptr(&ipi_message); 293 do { 294 all = xchg(&info->messages, 0); 295 #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) 296 /* 297 * Must check for PPC_MSG_RM_HOST_ACTION messages 298 * before PPC_MSG_CALL_FUNCTION messages because when 299 * a VM is destroyed, we call kick_all_cpus_sync() 300 * to ensure that any pending PPC_MSG_RM_HOST_ACTION 301 * messages have completed before we free any VCPUs. 302 */ 303 if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION)) 304 kvmppc_xics_ipi_action(); 305 #endif 306 if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION)) 307 generic_smp_call_function_interrupt(); 308 if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE)) 309 scheduler_ipi(); 310 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 311 if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST)) 312 timer_broadcast_interrupt(); 313 #endif 314 #ifdef CONFIG_NMI_IPI 315 if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI)) 316 nmi_ipi_action(0, NULL); 317 #endif 318 } while (info->messages); 319 320 return IRQ_HANDLED; 321 } 322 #endif /* CONFIG_PPC_SMP_MUXED_IPI */ 323 324 static inline void do_message_pass(int cpu, int msg) 325 { 326 if (smp_ops->message_pass) 327 smp_ops->message_pass(cpu, msg); 328 #ifdef CONFIG_PPC_SMP_MUXED_IPI 329 else 330 smp_muxed_ipi_message_pass(cpu, msg); 331 #endif 332 } 333 334 void smp_send_reschedule(int cpu) 335 { 336 if (likely(smp_ops)) 337 do_message_pass(cpu, PPC_MSG_RESCHEDULE); 338 } 339 EXPORT_SYMBOL_GPL(smp_send_reschedule); 340 341 void arch_send_call_function_single_ipi(int cpu) 342 { 343 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); 344 } 345 346 void arch_send_call_function_ipi_mask(const struct cpumask *mask) 347 { 348 unsigned int cpu; 349 350 for_each_cpu(cpu, mask) 351 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); 352 } 353 354 #ifdef CONFIG_NMI_IPI 355 356 /* 357 * "NMI IPI" system. 358 * 359 * NMI IPIs may not be recoverable, so should not be used as ongoing part of 360 * a running system. They can be used for crash, debug, halt/reboot, etc. 361 * 362 * The IPI call waits with interrupts disabled until all targets enter the 363 * NMI handler, then returns. Subsequent IPIs can be issued before targets 364 * have returned from their handlers, so there is no guarantee about 365 * concurrency or re-entrancy. 366 * 367 * A new NMI can be issued before all targets exit the handler. 368 * 369 * The IPI call may time out without all targets entering the NMI handler. 370 * In that case, there is some logic to recover (and ignore subsequent 371 * NMI interrupts that may eventually be raised), but the platform interrupt 372 * handler may not be able to distinguish this from other exception causes, 373 * which may cause a crash. 374 */ 375 376 static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0); 377 static struct cpumask nmi_ipi_pending_mask; 378 static bool nmi_ipi_busy = false; 379 static void (*nmi_ipi_function)(struct pt_regs *) = NULL; 380 381 static void nmi_ipi_lock_start(unsigned long *flags) 382 { 383 raw_local_irq_save(*flags); 384 hard_irq_disable(); 385 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) { 386 raw_local_irq_restore(*flags); 387 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0); 388 raw_local_irq_save(*flags); 389 hard_irq_disable(); 390 } 391 } 392 393 static void nmi_ipi_lock(void) 394 { 395 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) 396 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0); 397 } 398 399 static void nmi_ipi_unlock(void) 400 { 401 smp_mb(); 402 WARN_ON(atomic_read(&__nmi_ipi_lock) != 1); 403 atomic_set(&__nmi_ipi_lock, 0); 404 } 405 406 static void nmi_ipi_unlock_end(unsigned long *flags) 407 { 408 nmi_ipi_unlock(); 409 raw_local_irq_restore(*flags); 410 } 411 412 /* 413 * Platform NMI handler calls this to ack 414 */ 415 int smp_handle_nmi_ipi(struct pt_regs *regs) 416 { 417 void (*fn)(struct pt_regs *) = NULL; 418 unsigned long flags; 419 int me = raw_smp_processor_id(); 420 int ret = 0; 421 422 /* 423 * Unexpected NMIs are possible here because the interrupt may not 424 * be able to distinguish NMI IPIs from other types of NMIs, or 425 * because the caller may have timed out. 426 */ 427 nmi_ipi_lock_start(&flags); 428 if (cpumask_test_cpu(me, &nmi_ipi_pending_mask)) { 429 cpumask_clear_cpu(me, &nmi_ipi_pending_mask); 430 fn = READ_ONCE(nmi_ipi_function); 431 WARN_ON_ONCE(!fn); 432 ret = 1; 433 } 434 nmi_ipi_unlock_end(&flags); 435 436 if (fn) 437 fn(regs); 438 439 return ret; 440 } 441 442 static void do_smp_send_nmi_ipi(int cpu, bool safe) 443 { 444 if (!safe && smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu)) 445 return; 446 447 if (cpu >= 0) { 448 do_message_pass(cpu, PPC_MSG_NMI_IPI); 449 } else { 450 int c; 451 452 for_each_online_cpu(c) { 453 if (c == raw_smp_processor_id()) 454 continue; 455 do_message_pass(c, PPC_MSG_NMI_IPI); 456 } 457 } 458 } 459 460 /* 461 * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS. 462 * - fn is the target callback function. 463 * - delay_us > 0 is the delay before giving up waiting for targets to 464 * begin executing the handler, == 0 specifies indefinite delay. 465 */ 466 static int __smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), 467 u64 delay_us, bool safe) 468 { 469 unsigned long flags; 470 int me = raw_smp_processor_id(); 471 int ret = 1; 472 473 BUG_ON(cpu == me); 474 BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS); 475 476 if (unlikely(!smp_ops)) 477 return 0; 478 479 nmi_ipi_lock_start(&flags); 480 while (nmi_ipi_busy) { 481 nmi_ipi_unlock_end(&flags); 482 spin_until_cond(!nmi_ipi_busy); 483 nmi_ipi_lock_start(&flags); 484 } 485 nmi_ipi_busy = true; 486 nmi_ipi_function = fn; 487 488 WARN_ON_ONCE(!cpumask_empty(&nmi_ipi_pending_mask)); 489 490 if (cpu < 0) { 491 /* ALL_OTHERS */ 492 cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask); 493 cpumask_clear_cpu(me, &nmi_ipi_pending_mask); 494 } else { 495 cpumask_set_cpu(cpu, &nmi_ipi_pending_mask); 496 } 497 498 nmi_ipi_unlock(); 499 500 /* Interrupts remain hard disabled */ 501 502 do_smp_send_nmi_ipi(cpu, safe); 503 504 nmi_ipi_lock(); 505 /* nmi_ipi_busy is set here, so unlock/lock is okay */ 506 while (!cpumask_empty(&nmi_ipi_pending_mask)) { 507 nmi_ipi_unlock(); 508 udelay(1); 509 nmi_ipi_lock(); 510 if (delay_us) { 511 delay_us--; 512 if (!delay_us) 513 break; 514 } 515 } 516 517 if (!cpumask_empty(&nmi_ipi_pending_mask)) { 518 /* Timeout waiting for CPUs to call smp_handle_nmi_ipi */ 519 ret = 0; 520 cpumask_clear(&nmi_ipi_pending_mask); 521 } 522 523 nmi_ipi_function = NULL; 524 nmi_ipi_busy = false; 525 526 nmi_ipi_unlock_end(&flags); 527 528 return ret; 529 } 530 531 int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) 532 { 533 return __smp_send_nmi_ipi(cpu, fn, delay_us, false); 534 } 535 536 int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) 537 { 538 return __smp_send_nmi_ipi(cpu, fn, delay_us, true); 539 } 540 #endif /* CONFIG_NMI_IPI */ 541 542 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 543 void tick_broadcast(const struct cpumask *mask) 544 { 545 unsigned int cpu; 546 547 for_each_cpu(cpu, mask) 548 do_message_pass(cpu, PPC_MSG_TICK_BROADCAST); 549 } 550 #endif 551 552 #ifdef CONFIG_DEBUGGER 553 void debugger_ipi_callback(struct pt_regs *regs) 554 { 555 debugger_ipi(regs); 556 } 557 558 void smp_send_debugger_break(void) 559 { 560 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000); 561 } 562 #endif 563 564 #ifdef CONFIG_KEXEC_CORE 565 void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) 566 { 567 int cpu; 568 569 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000); 570 if (kdump_in_progress() && crash_wake_offline) { 571 for_each_present_cpu(cpu) { 572 if (cpu_online(cpu)) 573 continue; 574 /* 575 * crash_ipi_callback will wait for 576 * all cpus, including offline CPUs. 577 * We don't care about nmi_ipi_function. 578 * Offline cpus will jump straight into 579 * crash_ipi_callback, we can skip the 580 * entire NMI dance and waiting for 581 * cpus to clear pending mask, etc. 582 */ 583 do_smp_send_nmi_ipi(cpu, false); 584 } 585 } 586 } 587 #endif 588 589 #ifdef CONFIG_NMI_IPI 590 static void nmi_stop_this_cpu(struct pt_regs *regs) 591 { 592 /* 593 * IRQs are already hard disabled by the smp_handle_nmi_ipi. 594 */ 595 spin_begin(); 596 while (1) 597 spin_cpu_relax(); 598 } 599 600 void smp_send_stop(void) 601 { 602 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000); 603 } 604 605 #else /* CONFIG_NMI_IPI */ 606 607 static void stop_this_cpu(void *dummy) 608 { 609 hard_irq_disable(); 610 spin_begin(); 611 while (1) 612 spin_cpu_relax(); 613 } 614 615 void smp_send_stop(void) 616 { 617 static bool stopped = false; 618 619 /* 620 * Prevent waiting on csd lock from a previous smp_send_stop. 621 * This is racy, but in general callers try to do the right 622 * thing and only fire off one smp_send_stop (e.g., see 623 * kernel/panic.c) 624 */ 625 if (stopped) 626 return; 627 628 stopped = true; 629 630 smp_call_function(stop_this_cpu, NULL, 0); 631 } 632 #endif /* CONFIG_NMI_IPI */ 633 634 struct task_struct *current_set[NR_CPUS]; 635 636 static void smp_store_cpu_info(int id) 637 { 638 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); 639 #ifdef CONFIG_PPC_FSL_BOOK3E 640 per_cpu(next_tlbcam_idx, id) 641 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; 642 #endif 643 } 644 645 /* 646 * Relationships between CPUs are maintained in a set of per-cpu cpumasks so 647 * rather than just passing around the cpumask we pass around a function that 648 * returns the that cpumask for the given CPU. 649 */ 650 static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int)) 651 { 652 cpumask_set_cpu(i, get_cpumask(j)); 653 cpumask_set_cpu(j, get_cpumask(i)); 654 } 655 656 #ifdef CONFIG_HOTPLUG_CPU 657 static void set_cpus_unrelated(int i, int j, 658 struct cpumask *(*get_cpumask)(int)) 659 { 660 cpumask_clear_cpu(i, get_cpumask(j)); 661 cpumask_clear_cpu(j, get_cpumask(i)); 662 } 663 #endif 664 665 /* 666 * parse_thread_groups: Parses the "ibm,thread-groups" device tree 667 * property for the CPU device node @dn and stores 668 * the parsed output in the thread_groups 669 * structure @tg if the ibm,thread-groups[0] 670 * matches @property. 671 * 672 * @dn: The device node of the CPU device. 673 * @tg: Pointer to a thread group structure into which the parsed 674 * output of "ibm,thread-groups" is stored. 675 * @property: The property of the thread-group that the caller is 676 * interested in. 677 * 678 * ibm,thread-groups[0..N-1] array defines which group of threads in 679 * the CPU-device node can be grouped together based on the property. 680 * 681 * ibm,thread-groups[0] tells us the property based on which the 682 * threads are being grouped together. If this value is 1, it implies 683 * that the threads in the same group share L1, translation cache. 684 * 685 * ibm,thread-groups[1] tells us how many such thread groups exist. 686 * 687 * ibm,thread-groups[2] tells us the number of threads in each such 688 * group. 689 * 690 * ibm,thread-groups[3..N-1] is the list of threads identified by 691 * "ibm,ppc-interrupt-server#s" arranged as per their membership in 692 * the grouping. 693 * 694 * Example: If ibm,thread-groups = [1,2,4,5,6,7,8,9,10,11,12] it 695 * implies that there are 2 groups of 4 threads each, where each group 696 * of threads share L1, translation cache. 697 * 698 * The "ibm,ppc-interrupt-server#s" of the first group is {5,6,7,8} 699 * and the "ibm,ppc-interrupt-server#s" of the second group is {9, 10, 700 * 11, 12} structure 701 * 702 * Returns 0 on success, -EINVAL if the property does not exist, 703 * -ENODATA if property does not have a value, and -EOVERFLOW if the 704 * property data isn't large enough. 705 */ 706 static int parse_thread_groups(struct device_node *dn, 707 struct thread_groups *tg, 708 unsigned int property) 709 { 710 int i; 711 u32 thread_group_array[3 + MAX_THREAD_LIST_SIZE]; 712 u32 *thread_list; 713 size_t total_threads; 714 int ret; 715 716 ret = of_property_read_u32_array(dn, "ibm,thread-groups", 717 thread_group_array, 3); 718 if (ret) 719 return ret; 720 721 tg->property = thread_group_array[0]; 722 tg->nr_groups = thread_group_array[1]; 723 tg->threads_per_group = thread_group_array[2]; 724 if (tg->property != property || 725 tg->nr_groups < 1 || 726 tg->threads_per_group < 1) 727 return -ENODATA; 728 729 total_threads = tg->nr_groups * tg->threads_per_group; 730 731 ret = of_property_read_u32_array(dn, "ibm,thread-groups", 732 thread_group_array, 733 3 + total_threads); 734 if (ret) 735 return ret; 736 737 thread_list = &thread_group_array[3]; 738 739 for (i = 0 ; i < total_threads; i++) 740 tg->thread_list[i] = thread_list[i]; 741 742 return 0; 743 } 744 745 /* 746 * get_cpu_thread_group_start : Searches the thread group in tg->thread_list 747 * that @cpu belongs to. 748 * 749 * @cpu : The logical CPU whose thread group is being searched. 750 * @tg : The thread-group structure of the CPU node which @cpu belongs 751 * to. 752 * 753 * Returns the index to tg->thread_list that points to the the start 754 * of the thread_group that @cpu belongs to. 755 * 756 * Returns -1 if cpu doesn't belong to any of the groups pointed to by 757 * tg->thread_list. 758 */ 759 static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg) 760 { 761 int hw_cpu_id = get_hard_smp_processor_id(cpu); 762 int i, j; 763 764 for (i = 0; i < tg->nr_groups; i++) { 765 int group_start = i * tg->threads_per_group; 766 767 for (j = 0; j < tg->threads_per_group; j++) { 768 int idx = group_start + j; 769 770 if (tg->thread_list[idx] == hw_cpu_id) 771 return group_start; 772 } 773 } 774 775 return -1; 776 } 777 778 static int init_cpu_l1_cache_map(int cpu) 779 780 { 781 struct device_node *dn = of_get_cpu_node(cpu, NULL); 782 struct thread_groups tg = {.property = 0, 783 .nr_groups = 0, 784 .threads_per_group = 0}; 785 int first_thread = cpu_first_thread_sibling(cpu); 786 int i, cpu_group_start = -1, err = 0; 787 788 if (!dn) 789 return -ENODATA; 790 791 err = parse_thread_groups(dn, &tg, THREAD_GROUP_SHARE_L1); 792 if (err) 793 goto out; 794 795 zalloc_cpumask_var_node(&per_cpu(cpu_l1_cache_map, cpu), 796 GFP_KERNEL, 797 cpu_to_node(cpu)); 798 799 cpu_group_start = get_cpu_thread_group_start(cpu, &tg); 800 801 if (unlikely(cpu_group_start == -1)) { 802 WARN_ON_ONCE(1); 803 err = -ENODATA; 804 goto out; 805 } 806 807 for (i = first_thread; i < first_thread + threads_per_core; i++) { 808 int i_group_start = get_cpu_thread_group_start(i, &tg); 809 810 if (unlikely(i_group_start == -1)) { 811 WARN_ON_ONCE(1); 812 err = -ENODATA; 813 goto out; 814 } 815 816 if (i_group_start == cpu_group_start) 817 cpumask_set_cpu(i, per_cpu(cpu_l1_cache_map, cpu)); 818 } 819 820 out: 821 of_node_put(dn); 822 return err; 823 } 824 825 static int init_big_cores(void) 826 { 827 int cpu; 828 829 for_each_possible_cpu(cpu) { 830 int err = init_cpu_l1_cache_map(cpu); 831 832 if (err) 833 return err; 834 835 zalloc_cpumask_var_node(&per_cpu(cpu_smallcore_map, cpu), 836 GFP_KERNEL, 837 cpu_to_node(cpu)); 838 } 839 840 has_big_cores = true; 841 return 0; 842 } 843 844 void __init smp_prepare_cpus(unsigned int max_cpus) 845 { 846 unsigned int cpu; 847 848 DBG("smp_prepare_cpus\n"); 849 850 /* 851 * setup_cpu may need to be called on the boot cpu. We havent 852 * spun any cpus up but lets be paranoid. 853 */ 854 BUG_ON(boot_cpuid != smp_processor_id()); 855 856 /* Fixup boot cpu */ 857 smp_store_cpu_info(boot_cpuid); 858 cpu_callin_map[boot_cpuid] = 1; 859 860 for_each_possible_cpu(cpu) { 861 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), 862 GFP_KERNEL, cpu_to_node(cpu)); 863 zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu), 864 GFP_KERNEL, cpu_to_node(cpu)); 865 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), 866 GFP_KERNEL, cpu_to_node(cpu)); 867 /* 868 * numa_node_id() works after this. 869 */ 870 if (cpu_present(cpu)) { 871 set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]); 872 set_cpu_numa_mem(cpu, 873 local_memory_node(numa_cpu_lookup_table[cpu])); 874 } 875 } 876 877 /* Init the cpumasks so the boot CPU is related to itself */ 878 cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid)); 879 cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid)); 880 cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid)); 881 882 init_big_cores(); 883 if (has_big_cores) { 884 cpumask_set_cpu(boot_cpuid, 885 cpu_smallcore_mask(boot_cpuid)); 886 } 887 888 if (smp_ops && smp_ops->probe) 889 smp_ops->probe(); 890 } 891 892 void smp_prepare_boot_cpu(void) 893 { 894 BUG_ON(smp_processor_id() != boot_cpuid); 895 #ifdef CONFIG_PPC64 896 paca_ptrs[boot_cpuid]->__current = current; 897 #endif 898 set_numa_node(numa_cpu_lookup_table[boot_cpuid]); 899 current_set[boot_cpuid] = current; 900 } 901 902 #ifdef CONFIG_HOTPLUG_CPU 903 904 int generic_cpu_disable(void) 905 { 906 unsigned int cpu = smp_processor_id(); 907 908 if (cpu == boot_cpuid) 909 return -EBUSY; 910 911 set_cpu_online(cpu, false); 912 #ifdef CONFIG_PPC64 913 vdso_data->processorCount--; 914 #endif 915 /* Update affinity of all IRQs previously aimed at this CPU */ 916 irq_migrate_all_off_this_cpu(); 917 918 /* 919 * Depending on the details of the interrupt controller, it's possible 920 * that one of the interrupts we just migrated away from this CPU is 921 * actually already pending on this CPU. If we leave it in that state 922 * the interrupt will never be EOI'ed, and will never fire again. So 923 * temporarily enable interrupts here, to allow any pending interrupt to 924 * be received (and EOI'ed), before we take this CPU offline. 925 */ 926 local_irq_enable(); 927 mdelay(1); 928 local_irq_disable(); 929 930 return 0; 931 } 932 933 void generic_cpu_die(unsigned int cpu) 934 { 935 int i; 936 937 for (i = 0; i < 100; i++) { 938 smp_rmb(); 939 if (is_cpu_dead(cpu)) 940 return; 941 msleep(100); 942 } 943 printk(KERN_ERR "CPU%d didn't die...\n", cpu); 944 } 945 946 void generic_set_cpu_dead(unsigned int cpu) 947 { 948 per_cpu(cpu_state, cpu) = CPU_DEAD; 949 } 950 951 /* 952 * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise 953 * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), 954 * which makes the delay in generic_cpu_die() not happen. 955 */ 956 void generic_set_cpu_up(unsigned int cpu) 957 { 958 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 959 } 960 961 int generic_check_cpu_restart(unsigned int cpu) 962 { 963 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; 964 } 965 966 int is_cpu_dead(unsigned int cpu) 967 { 968 return per_cpu(cpu_state, cpu) == CPU_DEAD; 969 } 970 971 static bool secondaries_inhibited(void) 972 { 973 return kvm_hv_mode_active(); 974 } 975 976 #else /* HOTPLUG_CPU */ 977 978 #define secondaries_inhibited() 0 979 980 #endif 981 982 static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle) 983 { 984 #ifdef CONFIG_PPC64 985 paca_ptrs[cpu]->__current = idle; 986 paca_ptrs[cpu]->kstack = (unsigned long)task_stack_page(idle) + 987 THREAD_SIZE - STACK_FRAME_OVERHEAD; 988 #endif 989 idle->cpu = cpu; 990 secondary_current = current_set[cpu] = idle; 991 } 992 993 int __cpu_up(unsigned int cpu, struct task_struct *tidle) 994 { 995 int rc, c; 996 997 /* 998 * Don't allow secondary threads to come online if inhibited 999 */ 1000 if (threads_per_core > 1 && secondaries_inhibited() && 1001 cpu_thread_in_subcore(cpu)) 1002 return -EBUSY; 1003 1004 if (smp_ops == NULL || 1005 (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) 1006 return -EINVAL; 1007 1008 cpu_idle_thread_init(cpu, tidle); 1009 1010 /* 1011 * The platform might need to allocate resources prior to bringing 1012 * up the CPU 1013 */ 1014 if (smp_ops->prepare_cpu) { 1015 rc = smp_ops->prepare_cpu(cpu); 1016 if (rc) 1017 return rc; 1018 } 1019 1020 /* Make sure callin-map entry is 0 (can be leftover a CPU 1021 * hotplug 1022 */ 1023 cpu_callin_map[cpu] = 0; 1024 1025 /* The information for processor bringup must 1026 * be written out to main store before we release 1027 * the processor. 1028 */ 1029 smp_mb(); 1030 1031 /* wake up cpus */ 1032 DBG("smp: kicking cpu %d\n", cpu); 1033 rc = smp_ops->kick_cpu(cpu); 1034 if (rc) { 1035 pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc); 1036 return rc; 1037 } 1038 1039 /* 1040 * wait to see if the cpu made a callin (is actually up). 1041 * use this value that I found through experimentation. 1042 * -- Cort 1043 */ 1044 if (system_state < SYSTEM_RUNNING) 1045 for (c = 50000; c && !cpu_callin_map[cpu]; c--) 1046 udelay(100); 1047 #ifdef CONFIG_HOTPLUG_CPU 1048 else 1049 /* 1050 * CPUs can take much longer to come up in the 1051 * hotplug case. Wait five seconds. 1052 */ 1053 for (c = 5000; c && !cpu_callin_map[cpu]; c--) 1054 msleep(1); 1055 #endif 1056 1057 if (!cpu_callin_map[cpu]) { 1058 printk(KERN_ERR "Processor %u is stuck.\n", cpu); 1059 return -ENOENT; 1060 } 1061 1062 DBG("Processor %u found.\n", cpu); 1063 1064 if (smp_ops->give_timebase) 1065 smp_ops->give_timebase(); 1066 1067 /* Wait until cpu puts itself in the online & active maps */ 1068 spin_until_cond(cpu_online(cpu)); 1069 1070 return 0; 1071 } 1072 1073 /* Return the value of the reg property corresponding to the given 1074 * logical cpu. 1075 */ 1076 int cpu_to_core_id(int cpu) 1077 { 1078 struct device_node *np; 1079 const __be32 *reg; 1080 int id = -1; 1081 1082 np = of_get_cpu_node(cpu, NULL); 1083 if (!np) 1084 goto out; 1085 1086 reg = of_get_property(np, "reg", NULL); 1087 if (!reg) 1088 goto out; 1089 1090 id = be32_to_cpup(reg); 1091 out: 1092 of_node_put(np); 1093 return id; 1094 } 1095 EXPORT_SYMBOL_GPL(cpu_to_core_id); 1096 1097 /* Helper routines for cpu to core mapping */ 1098 int cpu_core_index_of_thread(int cpu) 1099 { 1100 return cpu >> threads_shift; 1101 } 1102 EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); 1103 1104 int cpu_first_thread_of_core(int core) 1105 { 1106 return core << threads_shift; 1107 } 1108 EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); 1109 1110 /* Must be called when no change can occur to cpu_present_mask, 1111 * i.e. during cpu online or offline. 1112 */ 1113 static struct device_node *cpu_to_l2cache(int cpu) 1114 { 1115 struct device_node *np; 1116 struct device_node *cache; 1117 1118 if (!cpu_present(cpu)) 1119 return NULL; 1120 1121 np = of_get_cpu_node(cpu, NULL); 1122 if (np == NULL) 1123 return NULL; 1124 1125 cache = of_find_next_cache_node(np); 1126 1127 of_node_put(np); 1128 1129 return cache; 1130 } 1131 1132 static bool update_mask_by_l2(int cpu, struct cpumask *(*mask_fn)(int)) 1133 { 1134 struct device_node *l2_cache, *np; 1135 int i; 1136 1137 l2_cache = cpu_to_l2cache(cpu); 1138 if (!l2_cache) 1139 return false; 1140 1141 for_each_cpu(i, cpu_online_mask) { 1142 /* 1143 * when updating the marks the current CPU has not been marked 1144 * online, but we need to update the cache masks 1145 */ 1146 np = cpu_to_l2cache(i); 1147 if (!np) 1148 continue; 1149 1150 if (np == l2_cache) 1151 set_cpus_related(cpu, i, mask_fn); 1152 1153 of_node_put(np); 1154 } 1155 of_node_put(l2_cache); 1156 1157 return true; 1158 } 1159 1160 #ifdef CONFIG_HOTPLUG_CPU 1161 static void remove_cpu_from_masks(int cpu) 1162 { 1163 int i; 1164 1165 /* NB: cpu_core_mask is a superset of the others */ 1166 for_each_cpu(i, cpu_core_mask(cpu)) { 1167 set_cpus_unrelated(cpu, i, cpu_core_mask); 1168 set_cpus_unrelated(cpu, i, cpu_l2_cache_mask); 1169 set_cpus_unrelated(cpu, i, cpu_sibling_mask); 1170 if (has_big_cores) 1171 set_cpus_unrelated(cpu, i, cpu_smallcore_mask); 1172 } 1173 } 1174 #endif 1175 1176 static inline void add_cpu_to_smallcore_masks(int cpu) 1177 { 1178 struct cpumask *this_l1_cache_map = per_cpu(cpu_l1_cache_map, cpu); 1179 int i, first_thread = cpu_first_thread_sibling(cpu); 1180 1181 if (!has_big_cores) 1182 return; 1183 1184 cpumask_set_cpu(cpu, cpu_smallcore_mask(cpu)); 1185 1186 for (i = first_thread; i < first_thread + threads_per_core; i++) { 1187 if (cpu_online(i) && cpumask_test_cpu(i, this_l1_cache_map)) 1188 set_cpus_related(i, cpu, cpu_smallcore_mask); 1189 } 1190 } 1191 1192 static void add_cpu_to_masks(int cpu) 1193 { 1194 int first_thread = cpu_first_thread_sibling(cpu); 1195 int chipid = cpu_to_chip_id(cpu); 1196 int i; 1197 1198 /* 1199 * This CPU will not be in the online mask yet so we need to manually 1200 * add it to it's own thread sibling mask. 1201 */ 1202 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 1203 1204 for (i = first_thread; i < first_thread + threads_per_core; i++) 1205 if (cpu_online(i)) 1206 set_cpus_related(i, cpu, cpu_sibling_mask); 1207 1208 add_cpu_to_smallcore_masks(cpu); 1209 /* 1210 * Copy the thread sibling mask into the cache sibling mask 1211 * and mark any CPUs that share an L2 with this CPU. 1212 */ 1213 for_each_cpu(i, cpu_sibling_mask(cpu)) 1214 set_cpus_related(cpu, i, cpu_l2_cache_mask); 1215 update_mask_by_l2(cpu, cpu_l2_cache_mask); 1216 1217 /* 1218 * Copy the cache sibling mask into core sibling mask and mark 1219 * any CPUs on the same chip as this CPU. 1220 */ 1221 for_each_cpu(i, cpu_l2_cache_mask(cpu)) 1222 set_cpus_related(cpu, i, cpu_core_mask); 1223 1224 if (chipid == -1) 1225 return; 1226 1227 for_each_cpu(i, cpu_online_mask) 1228 if (cpu_to_chip_id(i) == chipid) 1229 set_cpus_related(cpu, i, cpu_core_mask); 1230 } 1231 1232 static bool shared_caches; 1233 1234 /* Activate a secondary processor. */ 1235 void start_secondary(void *unused) 1236 { 1237 unsigned int cpu = smp_processor_id(); 1238 struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask; 1239 1240 mmgrab(&init_mm); 1241 current->active_mm = &init_mm; 1242 1243 smp_store_cpu_info(cpu); 1244 set_dec(tb_ticks_per_jiffy); 1245 preempt_disable(); 1246 cpu_callin_map[cpu] = 1; 1247 1248 if (smp_ops->setup_cpu) 1249 smp_ops->setup_cpu(cpu); 1250 if (smp_ops->take_timebase) 1251 smp_ops->take_timebase(); 1252 1253 secondary_cpu_time_init(); 1254 1255 #ifdef CONFIG_PPC64 1256 if (system_state == SYSTEM_RUNNING) 1257 vdso_data->processorCount++; 1258 1259 vdso_getcpu_init(); 1260 #endif 1261 /* Update topology CPU masks */ 1262 add_cpu_to_masks(cpu); 1263 1264 if (has_big_cores) 1265 sibling_mask = cpu_smallcore_mask; 1266 /* 1267 * Check for any shared caches. Note that this must be done on a 1268 * per-core basis because one core in the pair might be disabled. 1269 */ 1270 if (!cpumask_equal(cpu_l2_cache_mask(cpu), sibling_mask(cpu))) 1271 shared_caches = true; 1272 1273 set_numa_node(numa_cpu_lookup_table[cpu]); 1274 set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu])); 1275 1276 smp_wmb(); 1277 notify_cpu_starting(cpu); 1278 set_cpu_online(cpu, true); 1279 1280 boot_init_stack_canary(); 1281 1282 local_irq_enable(); 1283 1284 /* We can enable ftrace for secondary cpus now */ 1285 this_cpu_enable_ftrace(); 1286 1287 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 1288 1289 BUG(); 1290 } 1291 1292 int setup_profiling_timer(unsigned int multiplier) 1293 { 1294 return 0; 1295 } 1296 1297 #ifdef CONFIG_SCHED_SMT 1298 /* cpumask of CPUs with asymetric SMT dependancy */ 1299 static int powerpc_smt_flags(void) 1300 { 1301 int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; 1302 1303 if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { 1304 printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); 1305 flags |= SD_ASYM_PACKING; 1306 } 1307 return flags; 1308 } 1309 #endif 1310 1311 static struct sched_domain_topology_level powerpc_topology[] = { 1312 #ifdef CONFIG_SCHED_SMT 1313 { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, 1314 #endif 1315 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 1316 { NULL, }, 1317 }; 1318 1319 /* 1320 * P9 has a slightly odd architecture where pairs of cores share an L2 cache. 1321 * This topology makes it *much* cheaper to migrate tasks between adjacent cores 1322 * since the migrated task remains cache hot. We want to take advantage of this 1323 * at the scheduler level so an extra topology level is required. 1324 */ 1325 static int powerpc_shared_cache_flags(void) 1326 { 1327 return SD_SHARE_PKG_RESOURCES; 1328 } 1329 1330 /* 1331 * We can't just pass cpu_l2_cache_mask() directly because 1332 * returns a non-const pointer and the compiler barfs on that. 1333 */ 1334 static const struct cpumask *shared_cache_mask(int cpu) 1335 { 1336 return cpu_l2_cache_mask(cpu); 1337 } 1338 1339 #ifdef CONFIG_SCHED_SMT 1340 static const struct cpumask *smallcore_smt_mask(int cpu) 1341 { 1342 return cpu_smallcore_mask(cpu); 1343 } 1344 #endif 1345 1346 static struct sched_domain_topology_level power9_topology[] = { 1347 #ifdef CONFIG_SCHED_SMT 1348 { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, 1349 #endif 1350 { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, 1351 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 1352 { NULL, }, 1353 }; 1354 1355 void __init smp_cpus_done(unsigned int max_cpus) 1356 { 1357 /* 1358 * We are running pinned to the boot CPU, see rest_init(). 1359 */ 1360 if (smp_ops && smp_ops->setup_cpu) 1361 smp_ops->setup_cpu(boot_cpuid); 1362 1363 if (smp_ops && smp_ops->bringup_done) 1364 smp_ops->bringup_done(); 1365 1366 /* 1367 * On a shared LPAR, associativity needs to be requested. 1368 * Hence, get numa topology before dumping cpu topology 1369 */ 1370 shared_proc_topology_init(); 1371 dump_numa_cpu_topology(); 1372 1373 #ifdef CONFIG_SCHED_SMT 1374 if (has_big_cores) { 1375 pr_info("Using small cores at SMT level\n"); 1376 power9_topology[0].mask = smallcore_smt_mask; 1377 powerpc_topology[0].mask = smallcore_smt_mask; 1378 } 1379 #endif 1380 /* 1381 * If any CPU detects that it's sharing a cache with another CPU then 1382 * use the deeper topology that is aware of this sharing. 1383 */ 1384 if (shared_caches) { 1385 pr_info("Using shared cache scheduler topology\n"); 1386 set_sched_topology(power9_topology); 1387 } else { 1388 pr_info("Using standard scheduler topology\n"); 1389 set_sched_topology(powerpc_topology); 1390 } 1391 } 1392 1393 #ifdef CONFIG_HOTPLUG_CPU 1394 int __cpu_disable(void) 1395 { 1396 int cpu = smp_processor_id(); 1397 int err; 1398 1399 if (!smp_ops->cpu_disable) 1400 return -ENOSYS; 1401 1402 this_cpu_disable_ftrace(); 1403 1404 err = smp_ops->cpu_disable(); 1405 if (err) 1406 return err; 1407 1408 /* Update sibling maps */ 1409 remove_cpu_from_masks(cpu); 1410 1411 return 0; 1412 } 1413 1414 void __cpu_die(unsigned int cpu) 1415 { 1416 if (smp_ops->cpu_die) 1417 smp_ops->cpu_die(cpu); 1418 } 1419 1420 void cpu_die(void) 1421 { 1422 /* 1423 * Disable on the down path. This will be re-enabled by 1424 * start_secondary() via start_secondary_resume() below 1425 */ 1426 this_cpu_disable_ftrace(); 1427 1428 if (ppc_md.cpu_die) 1429 ppc_md.cpu_die(); 1430 1431 /* If we return, we re-enter start_secondary */ 1432 start_secondary_resume(); 1433 } 1434 1435 #endif 1436