1 /* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #undef DEBUG 14 15 #include <linux/export.h> 16 #include <linux/string.h> 17 #include <linux/sched.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/reboot.h> 21 #include <linux/delay.h> 22 #include <linux/initrd.h> 23 #include <linux/seq_file.h> 24 #include <linux/ioport.h> 25 #include <linux/console.h> 26 #include <linux/utsname.h> 27 #include <linux/tty.h> 28 #include <linux/root_dev.h> 29 #include <linux/notifier.h> 30 #include <linux/cpu.h> 31 #include <linux/unistd.h> 32 #include <linux/serial.h> 33 #include <linux/serial_8250.h> 34 #include <linux/bootmem.h> 35 #include <linux/pci.h> 36 #include <linux/lockdep.h> 37 #include <linux/memblock.h> 38 #include <asm/io.h> 39 #include <asm/kdump.h> 40 #include <asm/prom.h> 41 #include <asm/processor.h> 42 #include <asm/pgtable.h> 43 #include <asm/smp.h> 44 #include <asm/elf.h> 45 #include <asm/machdep.h> 46 #include <asm/paca.h> 47 #include <asm/time.h> 48 #include <asm/cputable.h> 49 #include <asm/sections.h> 50 #include <asm/btext.h> 51 #include <asm/nvram.h> 52 #include <asm/setup.h> 53 #include <asm/system.h> 54 #include <asm/rtas.h> 55 #include <asm/iommu.h> 56 #include <asm/serial.h> 57 #include <asm/cache.h> 58 #include <asm/page.h> 59 #include <asm/mmu.h> 60 #include <asm/firmware.h> 61 #include <asm/xmon.h> 62 #include <asm/udbg.h> 63 #include <asm/kexec.h> 64 #include <asm/mmu_context.h> 65 #include <asm/code-patching.h> 66 #include <asm/kvm_ppc.h> 67 68 #include "setup.h" 69 70 #ifdef DEBUG 71 #define DBG(fmt...) udbg_printf(fmt) 72 #else 73 #define DBG(fmt...) 74 #endif 75 76 int boot_cpuid = 0; 77 int __initdata spinning_secondaries; 78 u64 ppc64_pft_size; 79 80 /* Pick defaults since we might want to patch instructions 81 * before we've read this from the device tree. 82 */ 83 struct ppc64_caches ppc64_caches = { 84 .dline_size = 0x40, 85 .log_dline_size = 6, 86 .iline_size = 0x40, 87 .log_iline_size = 6 88 }; 89 EXPORT_SYMBOL_GPL(ppc64_caches); 90 91 /* 92 * These are used in binfmt_elf.c to put aux entries on the stack 93 * for each elf executable being started. 94 */ 95 int dcache_bsize; 96 int icache_bsize; 97 int ucache_bsize; 98 99 #ifdef CONFIG_SMP 100 101 static char *smt_enabled_cmdline; 102 103 /* Look for ibm,smt-enabled OF option */ 104 static void check_smt_enabled(void) 105 { 106 struct device_node *dn; 107 const char *smt_option; 108 109 /* Default to enabling all threads */ 110 smt_enabled_at_boot = threads_per_core; 111 112 /* Allow the command line to overrule the OF option */ 113 if (smt_enabled_cmdline) { 114 if (!strcmp(smt_enabled_cmdline, "on")) 115 smt_enabled_at_boot = threads_per_core; 116 else if (!strcmp(smt_enabled_cmdline, "off")) 117 smt_enabled_at_boot = 0; 118 else { 119 long smt; 120 int rc; 121 122 rc = strict_strtol(smt_enabled_cmdline, 10, &smt); 123 if (!rc) 124 smt_enabled_at_boot = 125 min(threads_per_core, (int)smt); 126 } 127 } else { 128 dn = of_find_node_by_path("/options"); 129 if (dn) { 130 smt_option = of_get_property(dn, "ibm,smt-enabled", 131 NULL); 132 133 if (smt_option) { 134 if (!strcmp(smt_option, "on")) 135 smt_enabled_at_boot = threads_per_core; 136 else if (!strcmp(smt_option, "off")) 137 smt_enabled_at_boot = 0; 138 } 139 140 of_node_put(dn); 141 } 142 } 143 } 144 145 /* Look for smt-enabled= cmdline option */ 146 static int __init early_smt_enabled(char *p) 147 { 148 smt_enabled_cmdline = p; 149 return 0; 150 } 151 early_param("smt-enabled", early_smt_enabled); 152 153 #else 154 #define check_smt_enabled() 155 #endif /* CONFIG_SMP */ 156 157 /* 158 * Early initialization entry point. This is called by head.S 159 * with MMU translation disabled. We rely on the "feature" of 160 * the CPU that ignores the top 2 bits of the address in real 161 * mode so we can access kernel globals normally provided we 162 * only toy with things in the RMO region. From here, we do 163 * some early parsing of the device-tree to setup out MEMBLOCK 164 * data structures, and allocate & initialize the hash table 165 * and segment tables so we can start running with translation 166 * enabled. 167 * 168 * It is this function which will call the probe() callback of 169 * the various platform types and copy the matching one to the 170 * global ppc_md structure. Your platform can eventually do 171 * some very early initializations from the probe() routine, but 172 * this is not recommended, be very careful as, for example, the 173 * device-tree is not accessible via normal means at this point. 174 */ 175 176 void __init early_setup(unsigned long dt_ptr) 177 { 178 /* -------- printk is _NOT_ safe to use here ! ------- */ 179 180 /* Identify CPU type */ 181 identify_cpu(0, mfspr(SPRN_PVR)); 182 183 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 184 initialise_paca(&boot_paca, 0); 185 setup_paca(&boot_paca); 186 187 /* Initialize lockdep early or else spinlocks will blow */ 188 lockdep_init(); 189 190 /* -------- printk is now safe to use ------- */ 191 192 /* Enable early debugging if any specified (see udbg.h) */ 193 udbg_early_init(); 194 195 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 196 197 /* 198 * Do early initialization using the flattened device 199 * tree, such as retrieving the physical memory map or 200 * calculating/retrieving the hash table size. 201 */ 202 early_init_devtree(__va(dt_ptr)); 203 204 /* Now we know the logical id of our boot cpu, setup the paca. */ 205 setup_paca(&paca[boot_cpuid]); 206 207 /* Fix up paca fields required for the boot cpu */ 208 get_paca()->cpu_start = 1; 209 210 /* Probe the machine type */ 211 probe_machine(); 212 213 setup_kdump_trampoline(); 214 215 DBG("Found, Initializing memory management...\n"); 216 217 /* Initialize the hash table or TLB handling */ 218 early_init_mmu(); 219 220 DBG(" <- early_setup()\n"); 221 } 222 223 #ifdef CONFIG_SMP 224 void early_setup_secondary(void) 225 { 226 /* Mark interrupts enabled in PACA */ 227 get_paca()->soft_enabled = 0; 228 229 /* Initialize the hash table or TLB handling */ 230 early_init_mmu_secondary(); 231 } 232 233 #endif /* CONFIG_SMP */ 234 235 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 236 void smp_release_cpus(void) 237 { 238 unsigned long *ptr; 239 int i; 240 241 DBG(" -> smp_release_cpus()\n"); 242 243 /* All secondary cpus are spinning on a common spinloop, release them 244 * all now so they can start to spin on their individual paca 245 * spinloops. For non SMP kernels, the secondary cpus never get out 246 * of the common spinloop. 247 */ 248 249 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 250 - PHYSICAL_START); 251 *ptr = __pa(generic_secondary_smp_init); 252 253 /* And wait a bit for them to catch up */ 254 for (i = 0; i < 100000; i++) { 255 mb(); 256 HMT_low(); 257 if (spinning_secondaries == 0) 258 break; 259 udelay(1); 260 } 261 DBG("spinning_secondaries = %d\n", spinning_secondaries); 262 263 DBG(" <- smp_release_cpus()\n"); 264 } 265 #endif /* CONFIG_SMP || CONFIG_KEXEC */ 266 267 /* 268 * Initialize some remaining members of the ppc64_caches and systemcfg 269 * structures 270 * (at least until we get rid of them completely). This is mostly some 271 * cache informations about the CPU that will be used by cache flush 272 * routines and/or provided to userland 273 */ 274 static void __init initialize_cache_info(void) 275 { 276 struct device_node *np; 277 unsigned long num_cpus = 0; 278 279 DBG(" -> initialize_cache_info()\n"); 280 281 for_each_node_by_type(np, "cpu") { 282 num_cpus += 1; 283 284 /* 285 * We're assuming *all* of the CPUs have the same 286 * d-cache and i-cache sizes... -Peter 287 */ 288 if (num_cpus == 1) { 289 const u32 *sizep, *lsizep; 290 u32 size, lsize; 291 292 size = 0; 293 lsize = cur_cpu_spec->dcache_bsize; 294 sizep = of_get_property(np, "d-cache-size", NULL); 295 if (sizep != NULL) 296 size = *sizep; 297 lsizep = of_get_property(np, "d-cache-block-size", 298 NULL); 299 /* fallback if block size missing */ 300 if (lsizep == NULL) 301 lsizep = of_get_property(np, 302 "d-cache-line-size", 303 NULL); 304 if (lsizep != NULL) 305 lsize = *lsizep; 306 if (sizep == 0 || lsizep == 0) 307 DBG("Argh, can't find dcache properties ! " 308 "sizep: %p, lsizep: %p\n", sizep, lsizep); 309 310 ppc64_caches.dsize = size; 311 ppc64_caches.dline_size = lsize; 312 ppc64_caches.log_dline_size = __ilog2(lsize); 313 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 314 315 size = 0; 316 lsize = cur_cpu_spec->icache_bsize; 317 sizep = of_get_property(np, "i-cache-size", NULL); 318 if (sizep != NULL) 319 size = *sizep; 320 lsizep = of_get_property(np, "i-cache-block-size", 321 NULL); 322 if (lsizep == NULL) 323 lsizep = of_get_property(np, 324 "i-cache-line-size", 325 NULL); 326 if (lsizep != NULL) 327 lsize = *lsizep; 328 if (sizep == 0 || lsizep == 0) 329 DBG("Argh, can't find icache properties ! " 330 "sizep: %p, lsizep: %p\n", sizep, lsizep); 331 332 ppc64_caches.isize = size; 333 ppc64_caches.iline_size = lsize; 334 ppc64_caches.log_iline_size = __ilog2(lsize); 335 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 336 } 337 } 338 339 DBG(" <- initialize_cache_info()\n"); 340 } 341 342 343 /* 344 * Do some initial setup of the system. The parameters are those which 345 * were passed in from the bootloader. 346 */ 347 void __init setup_system(void) 348 { 349 DBG(" -> setup_system()\n"); 350 351 /* Apply the CPUs-specific and firmware specific fixups to kernel 352 * text (nop out sections not relevant to this CPU or this firmware) 353 */ 354 do_feature_fixups(cur_cpu_spec->cpu_features, 355 &__start___ftr_fixup, &__stop___ftr_fixup); 356 do_feature_fixups(cur_cpu_spec->mmu_features, 357 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 358 do_feature_fixups(powerpc_firmware_features, 359 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 360 do_lwsync_fixups(cur_cpu_spec->cpu_features, 361 &__start___lwsync_fixup, &__stop___lwsync_fixup); 362 363 /* 364 * Unflatten the device-tree passed by prom_init or kexec 365 */ 366 unflatten_device_tree(); 367 368 /* 369 * Fill the ppc64_caches & systemcfg structures with informations 370 * retrieved from the device-tree. 371 */ 372 initialize_cache_info(); 373 374 #ifdef CONFIG_PPC_RTAS 375 /* 376 * Initialize RTAS if available 377 */ 378 rtas_initialize(); 379 #endif /* CONFIG_PPC_RTAS */ 380 381 /* 382 * Check if we have an initrd provided via the device-tree 383 */ 384 check_for_initrd(); 385 386 /* 387 * Do some platform specific early initializations, that includes 388 * setting up the hash table pointers. It also sets up some interrupt-mapping 389 * related options that will be used by finish_device_tree() 390 */ 391 if (ppc_md.init_early) 392 ppc_md.init_early(); 393 394 /* 395 * We can discover serial ports now since the above did setup the 396 * hash table management for us, thus ioremap works. We do that early 397 * so that further code can be debugged 398 */ 399 find_legacy_serial_ports(); 400 401 /* 402 * Register early console 403 */ 404 register_early_udbg_console(); 405 406 /* 407 * Initialize xmon 408 */ 409 xmon_setup(); 410 411 smp_setup_cpu_maps(); 412 check_smt_enabled(); 413 414 #ifdef CONFIG_SMP 415 /* Release secondary cpus out of their spinloops at 0x60 now that 416 * we can map physical -> logical CPU ids 417 */ 418 smp_release_cpus(); 419 #endif 420 421 printk("Starting Linux PPC64 %s\n", init_utsname()->version); 422 423 printk("-----------------------------------------------------\n"); 424 printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 425 printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); 426 if (ppc64_caches.dline_size != 0x80) 427 printk("ppc64_caches.dcache_line_size = 0x%x\n", 428 ppc64_caches.dline_size); 429 if (ppc64_caches.iline_size != 0x80) 430 printk("ppc64_caches.icache_line_size = 0x%x\n", 431 ppc64_caches.iline_size); 432 #ifdef CONFIG_PPC_STD_MMU_64 433 if (htab_address) 434 printk("htab_address = 0x%p\n", htab_address); 435 printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); 436 #endif /* CONFIG_PPC_STD_MMU_64 */ 437 if (PHYSICAL_START > 0) 438 printk("physical_start = 0x%llx\n", 439 (unsigned long long)PHYSICAL_START); 440 printk("-----------------------------------------------------\n"); 441 442 DBG(" <- setup_system()\n"); 443 } 444 445 /* This returns the limit below which memory accesses to the linear 446 * mapping are guarnateed not to cause a TLB or SLB miss. This is 447 * used to allocate interrupt or emergency stacks for which our 448 * exception entry path doesn't deal with being interrupted. 449 */ 450 static u64 safe_stack_limit(void) 451 { 452 #ifdef CONFIG_PPC_BOOK3E 453 /* Freescale BookE bolts the entire linear mapping */ 454 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 455 return linear_map_top; 456 /* Other BookE, we assume the first GB is bolted */ 457 return 1ul << 30; 458 #else 459 /* BookS, the first segment is bolted */ 460 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 461 return 1UL << SID_SHIFT_1T; 462 return 1UL << SID_SHIFT; 463 #endif 464 } 465 466 static void __init irqstack_early_init(void) 467 { 468 u64 limit = safe_stack_limit(); 469 unsigned int i; 470 471 /* 472 * Interrupt stacks must be in the first segment since we 473 * cannot afford to take SLB misses on them. 474 */ 475 for_each_possible_cpu(i) { 476 softirq_ctx[i] = (struct thread_info *) 477 __va(memblock_alloc_base(THREAD_SIZE, 478 THREAD_SIZE, limit)); 479 hardirq_ctx[i] = (struct thread_info *) 480 __va(memblock_alloc_base(THREAD_SIZE, 481 THREAD_SIZE, limit)); 482 } 483 } 484 485 #ifdef CONFIG_PPC_BOOK3E 486 static void __init exc_lvl_early_init(void) 487 { 488 extern unsigned int interrupt_base_book3e; 489 extern unsigned int exc_debug_debug_book3e; 490 491 unsigned int i; 492 493 for_each_possible_cpu(i) { 494 critirq_ctx[i] = (struct thread_info *) 495 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 496 dbgirq_ctx[i] = (struct thread_info *) 497 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 498 mcheckirq_ctx[i] = (struct thread_info *) 499 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 500 } 501 502 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 503 patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1, 504 (unsigned long)&exc_debug_debug_book3e, 0); 505 } 506 #else 507 #define exc_lvl_early_init() 508 #endif 509 510 /* 511 * Stack space used when we detect a bad kernel stack pointer, and 512 * early in SMP boots before relocation is enabled. 513 */ 514 static void __init emergency_stack_init(void) 515 { 516 u64 limit; 517 unsigned int i; 518 519 /* 520 * Emergency stacks must be under 256MB, we cannot afford to take 521 * SLB misses on them. The ABI also requires them to be 128-byte 522 * aligned. 523 * 524 * Since we use these as temporary stacks during secondary CPU 525 * bringup, we need to get at them in real mode. This means they 526 * must also be within the RMO region. 527 */ 528 limit = min(safe_stack_limit(), ppc64_rma_size); 529 530 for_each_possible_cpu(i) { 531 unsigned long sp; 532 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 533 sp += THREAD_SIZE; 534 paca[i].emergency_sp = __va(sp); 535 } 536 } 537 538 /* 539 * Called into from start_kernel this initializes bootmem, which is used 540 * to manage page allocation until mem_init is called. 541 */ 542 void __init setup_arch(char **cmdline_p) 543 { 544 ppc64_boot_msg(0x12, "Setup Arch"); 545 546 *cmdline_p = cmd_line; 547 548 /* 549 * Set cache line size based on type of cpu as a default. 550 * Systems with OF can look in the properties on the cpu node(s) 551 * for a possibly more accurate value. 552 */ 553 dcache_bsize = ppc64_caches.dline_size; 554 icache_bsize = ppc64_caches.iline_size; 555 556 /* reboot on panic */ 557 panic_timeout = 180; 558 559 if (ppc_md.panic) 560 setup_panic(); 561 562 init_mm.start_code = (unsigned long)_stext; 563 init_mm.end_code = (unsigned long) _etext; 564 init_mm.end_data = (unsigned long) _edata; 565 init_mm.brk = klimit; 566 567 irqstack_early_init(); 568 exc_lvl_early_init(); 569 emergency_stack_init(); 570 571 #ifdef CONFIG_PPC_STD_MMU_64 572 stabs_alloc(); 573 #endif 574 /* set up the bootmem stuff with available memory */ 575 do_init_bootmem(); 576 sparse_init(); 577 578 #ifdef CONFIG_DUMMY_CONSOLE 579 conswitchp = &dummy_con; 580 #endif 581 582 if (ppc_md.setup_arch) 583 ppc_md.setup_arch(); 584 585 paging_init(); 586 587 /* Initialize the MMU context management stuff */ 588 mmu_context_init(); 589 590 kvm_rma_init(); 591 592 ppc64_boot_msg(0x15, "Setup Done"); 593 } 594 595 596 /* ToDo: do something useful if ppc_md is not yet setup. */ 597 #define PPC64_LINUX_FUNCTION 0x0f000000 598 #define PPC64_IPL_MESSAGE 0xc0000000 599 #define PPC64_TERM_MESSAGE 0xb0000000 600 601 static void ppc64_do_msg(unsigned int src, const char *msg) 602 { 603 if (ppc_md.progress) { 604 char buf[128]; 605 606 sprintf(buf, "%08X\n", src); 607 ppc_md.progress(buf, 0); 608 snprintf(buf, 128, "%s", msg); 609 ppc_md.progress(buf, 0); 610 } 611 } 612 613 /* Print a boot progress message. */ 614 void ppc64_boot_msg(unsigned int src, const char *msg) 615 { 616 ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); 617 printk("[boot]%04x %s\n", src, msg); 618 } 619 620 #ifdef CONFIG_SMP 621 #define PCPU_DYN_SIZE () 622 623 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 624 { 625 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 626 __pa(MAX_DMA_ADDRESS)); 627 } 628 629 static void __init pcpu_fc_free(void *ptr, size_t size) 630 { 631 free_bootmem(__pa(ptr), size); 632 } 633 634 static int pcpu_cpu_distance(unsigned int from, unsigned int to) 635 { 636 if (cpu_to_node(from) == cpu_to_node(to)) 637 return LOCAL_DISTANCE; 638 else 639 return REMOTE_DISTANCE; 640 } 641 642 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 643 EXPORT_SYMBOL(__per_cpu_offset); 644 645 void __init setup_per_cpu_areas(void) 646 { 647 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 648 size_t atom_size; 649 unsigned long delta; 650 unsigned int cpu; 651 int rc; 652 653 /* 654 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 655 * to group units. For larger mappings, use 1M atom which 656 * should be large enough to contain a number of units. 657 */ 658 if (mmu_linear_psize == MMU_PAGE_4K) 659 atom_size = PAGE_SIZE; 660 else 661 atom_size = 1 << 20; 662 663 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 664 pcpu_fc_alloc, pcpu_fc_free); 665 if (rc < 0) 666 panic("cannot initialize percpu area (err=%d)", rc); 667 668 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 669 for_each_possible_cpu(cpu) { 670 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 671 paca[cpu].data_offset = __per_cpu_offset[cpu]; 672 } 673 } 674 #endif 675 676 677 #ifdef CONFIG_PPC_INDIRECT_IO 678 struct ppc_pci_io ppc_pci_io; 679 EXPORT_SYMBOL(ppc_pci_io); 680 #endif /* CONFIG_PPC_INDIRECT_IO */ 681 682