1 /* 2 * Common prep/pmac/chrp boot and setup code. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/string.h> 7 #include <linux/sched.h> 8 #include <linux/init.h> 9 #include <linux/kernel.h> 10 #include <linux/reboot.h> 11 #include <linux/delay.h> 12 #include <linux/initrd.h> 13 #include <linux/tty.h> 14 #include <linux/seq_file.h> 15 #include <linux/root_dev.h> 16 #include <linux/cpu.h> 17 #include <linux/console.h> 18 #include <linux/memblock.h> 19 #include <linux/export.h> 20 21 #include <asm/io.h> 22 #include <asm/prom.h> 23 #include <asm/processor.h> 24 #include <asm/pgtable.h> 25 #include <asm/setup.h> 26 #include <asm/smp.h> 27 #include <asm/elf.h> 28 #include <asm/cputable.h> 29 #include <asm/bootx.h> 30 #include <asm/btext.h> 31 #include <asm/machdep.h> 32 #include <asm/uaccess.h> 33 #include <asm/pmac_feature.h> 34 #include <asm/sections.h> 35 #include <asm/nvram.h> 36 #include <asm/xmon.h> 37 #include <asm/time.h> 38 #include <asm/serial.h> 39 #include <asm/udbg.h> 40 #include <asm/code-patching.h> 41 #include <asm/cpu_has_feature.h> 42 43 #define DBG(fmt...) 44 45 extern void bootx_init(unsigned long r4, unsigned long phys); 46 47 int boot_cpuid_phys; 48 EXPORT_SYMBOL_GPL(boot_cpuid_phys); 49 50 int smp_hw_index[NR_CPUS]; 51 EXPORT_SYMBOL(smp_hw_index); 52 53 unsigned long ISA_DMA_THRESHOLD; 54 unsigned int DMA_MODE_READ; 55 unsigned int DMA_MODE_WRITE; 56 57 EXPORT_SYMBOL(ISA_DMA_THRESHOLD); 58 EXPORT_SYMBOL(DMA_MODE_READ); 59 EXPORT_SYMBOL(DMA_MODE_WRITE); 60 61 /* 62 * These are used in binfmt_elf.c to put aux entries on the stack 63 * for each elf executable being started. 64 */ 65 int dcache_bsize; 66 int icache_bsize; 67 int ucache_bsize; 68 69 /* 70 * We're called here very early in the boot. 71 * 72 * Note that the kernel may be running at an address which is different 73 * from the address that it was linked at, so we must use RELOC/PTRRELOC 74 * to access static data (including strings). -- paulus 75 */ 76 notrace unsigned long __init early_init(unsigned long dt_ptr) 77 { 78 unsigned long offset = reloc_offset(); 79 80 /* First zero the BSS -- use memset_io, some platforms don't have 81 * caches on yet */ 82 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, 83 __bss_stop - __bss_start); 84 85 /* 86 * Identify the CPU type and fix up code sections 87 * that depend on which cpu we have. 88 */ 89 identify_cpu(offset, mfspr(SPRN_PVR)); 90 91 apply_feature_fixups(); 92 93 return KERNELBASE + offset; 94 } 95 96 97 /* 98 * This is run before start_kernel(), the kernel has been relocated 99 * and we are running with enough of the MMU enabled to have our 100 * proper kernel virtual addresses 101 * 102 * Find out what kind of machine we're on and save any data we need 103 * from the early boot process (devtree is copied on pmac by prom_init()). 104 * This is called very early on the boot process, after a minimal 105 * MMU environment has been set up but before MMU_init is called. 106 */ 107 extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */ 108 109 notrace void __init machine_init(u64 dt_ptr) 110 { 111 /* Enable early debugging if any specified (see udbg.h) */ 112 udbg_early_init(); 113 114 patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP); 115 patch_instruction(&memset_nocache_branch, PPC_INST_NOP); 116 117 /* Do some early initialization based on the flat device tree */ 118 early_init_devtree(__va(dt_ptr)); 119 120 early_init_mmu(); 121 122 setup_kdump_trampoline(); 123 } 124 125 /* Checks "l2cr=xxxx" command-line option */ 126 int __init ppc_setup_l2cr(char *str) 127 { 128 if (cpu_has_feature(CPU_FTR_L2CR)) { 129 unsigned long val = simple_strtoul(str, NULL, 0); 130 printk(KERN_INFO "l2cr set to %lx\n", val); 131 _set_L2CR(0); /* force invalidate by disable cache */ 132 _set_L2CR(val); /* and enable it */ 133 } 134 return 1; 135 } 136 __setup("l2cr=", ppc_setup_l2cr); 137 138 /* Checks "l3cr=xxxx" command-line option */ 139 int __init ppc_setup_l3cr(char *str) 140 { 141 if (cpu_has_feature(CPU_FTR_L3CR)) { 142 unsigned long val = simple_strtoul(str, NULL, 0); 143 printk(KERN_INFO "l3cr set to %lx\n", val); 144 _set_L3CR(val); /* and enable it */ 145 } 146 return 1; 147 } 148 __setup("l3cr=", ppc_setup_l3cr); 149 150 #ifdef CONFIG_GENERIC_NVRAM 151 152 /* Generic nvram hooks used by drivers/char/gen_nvram.c */ 153 unsigned char nvram_read_byte(int addr) 154 { 155 if (ppc_md.nvram_read_val) 156 return ppc_md.nvram_read_val(addr); 157 return 0xff; 158 } 159 EXPORT_SYMBOL(nvram_read_byte); 160 161 void nvram_write_byte(unsigned char val, int addr) 162 { 163 if (ppc_md.nvram_write_val) 164 ppc_md.nvram_write_val(addr, val); 165 } 166 EXPORT_SYMBOL(nvram_write_byte); 167 168 ssize_t nvram_get_size(void) 169 { 170 if (ppc_md.nvram_size) 171 return ppc_md.nvram_size(); 172 return -1; 173 } 174 EXPORT_SYMBOL(nvram_get_size); 175 176 void nvram_sync(void) 177 { 178 if (ppc_md.nvram_sync) 179 ppc_md.nvram_sync(); 180 } 181 EXPORT_SYMBOL(nvram_sync); 182 183 #endif /* CONFIG_NVRAM */ 184 185 int __init ppc_init(void) 186 { 187 /* clear the progress line */ 188 if (ppc_md.progress) 189 ppc_md.progress(" ", 0xffff); 190 191 /* call platform init */ 192 if (ppc_md.init != NULL) { 193 ppc_md.init(); 194 } 195 return 0; 196 } 197 198 arch_initcall(ppc_init); 199 200 void __init irqstack_early_init(void) 201 { 202 unsigned int i; 203 204 /* interrupt stacks must be in lowmem, we get that for free on ppc32 205 * as the memblock is limited to lowmem by default */ 206 for_each_possible_cpu(i) { 207 softirq_ctx[i] = (struct thread_info *) 208 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 209 hardirq_ctx[i] = (struct thread_info *) 210 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 211 } 212 } 213 214 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 215 void __init exc_lvl_early_init(void) 216 { 217 unsigned int i, hw_cpu; 218 219 /* interrupt stacks must be in lowmem, we get that for free on ppc32 220 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ 221 for_each_possible_cpu(i) { 222 #ifdef CONFIG_SMP 223 hw_cpu = get_hard_smp_processor_id(i); 224 #else 225 hw_cpu = 0; 226 #endif 227 228 critirq_ctx[hw_cpu] = (struct thread_info *) 229 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 230 #ifdef CONFIG_BOOKE 231 dbgirq_ctx[hw_cpu] = (struct thread_info *) 232 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 233 mcheckirq_ctx[hw_cpu] = (struct thread_info *) 234 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 235 #endif 236 } 237 } 238 #endif 239 240 void __init setup_power_save(void) 241 { 242 #ifdef CONFIG_6xx 243 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 244 cpu_has_feature(CPU_FTR_CAN_NAP)) 245 ppc_md.power_save = ppc6xx_idle; 246 #endif 247 248 #ifdef CONFIG_E500 249 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 250 cpu_has_feature(CPU_FTR_CAN_NAP)) 251 ppc_md.power_save = e500_idle; 252 #endif 253 } 254 255 __init void initialize_cache_info(void) 256 { 257 /* 258 * Set cache line size based on type of cpu as a default. 259 * Systems with OF can look in the properties on the cpu node(s) 260 * for a possibly more accurate value. 261 */ 262 dcache_bsize = cur_cpu_spec->dcache_bsize; 263 icache_bsize = cur_cpu_spec->icache_bsize; 264 ucache_bsize = 0; 265 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) 266 ucache_bsize = icache_bsize = dcache_bsize; 267 } 268