1 /* 2 * arch/ppc64/kernel/rtas_pci.c 3 * 4 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation 5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 6 * 7 * RTAS specific routines for PCI. 8 * 9 * Based on code from pci.c, chrp_pci.c and pSeries_pci.c 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/threads.h> 28 #include <linux/pci.h> 29 #include <linux/string.h> 30 #include <linux/init.h> 31 #include <linux/bootmem.h> 32 33 #include <asm/io.h> 34 #include <asm/pgtable.h> 35 #include <asm/irq.h> 36 #include <asm/prom.h> 37 #include <asm/machdep.h> 38 #include <asm/pci-bridge.h> 39 #include <asm/iommu.h> 40 #include <asm/rtas.h> 41 #include <asm/mpic.h> 42 #include <asm/ppc-pci.h> 43 44 /* RTAS tokens */ 45 static int read_pci_config; 46 static int write_pci_config; 47 static int ibm_read_pci_config; 48 static int ibm_write_pci_config; 49 50 static inline int config_access_valid(struct pci_dn *dn, int where) 51 { 52 if (where < 256) 53 return 1; 54 if (where < 4096 && dn->pci_ext_config_space) 55 return 1; 56 57 return 0; 58 } 59 60 static int of_device_available(struct device_node * dn) 61 { 62 char * status; 63 64 status = get_property(dn, "status", NULL); 65 66 if (!status) 67 return 1; 68 69 if (!strcmp(status, "okay")) 70 return 1; 71 72 return 0; 73 } 74 75 static int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val) 76 { 77 int returnval = -1; 78 unsigned long buid, addr; 79 int ret; 80 81 if (!pdn) 82 return PCIBIOS_DEVICE_NOT_FOUND; 83 if (!config_access_valid(pdn, where)) 84 return PCIBIOS_BAD_REGISTER_NUMBER; 85 86 addr = ((where & 0xf00) << 20) | (pdn->busno << 16) | 87 (pdn->devfn << 8) | (where & 0xff); 88 buid = pdn->phb->buid; 89 if (buid) { 90 ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval, 91 addr, BUID_HI(buid), BUID_LO(buid), size); 92 } else { 93 ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size); 94 } 95 *val = returnval; 96 97 if (ret) 98 return PCIBIOS_DEVICE_NOT_FOUND; 99 100 if (returnval == EEH_IO_ERROR_VALUE(size) && 101 eeh_dn_check_failure (pdn->node, NULL)) 102 return PCIBIOS_DEVICE_NOT_FOUND; 103 104 return PCIBIOS_SUCCESSFUL; 105 } 106 107 static int rtas_pci_read_config(struct pci_bus *bus, 108 unsigned int devfn, 109 int where, int size, u32 *val) 110 { 111 struct device_node *busdn, *dn; 112 113 if (bus->self) 114 busdn = pci_device_to_OF_node(bus->self); 115 else 116 busdn = bus->sysdata; /* must be a phb */ 117 118 /* Search only direct children of the bus */ 119 for (dn = busdn->child; dn; dn = dn->sibling) { 120 struct pci_dn *pdn = PCI_DN(dn); 121 if (pdn && pdn->devfn == devfn 122 && of_device_available(dn)) 123 return rtas_read_config(pdn, where, size, val); 124 } 125 126 return PCIBIOS_DEVICE_NOT_FOUND; 127 } 128 129 int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val) 130 { 131 unsigned long buid, addr; 132 int ret; 133 134 if (!pdn) 135 return PCIBIOS_DEVICE_NOT_FOUND; 136 if (!config_access_valid(pdn, where)) 137 return PCIBIOS_BAD_REGISTER_NUMBER; 138 139 addr = ((where & 0xf00) << 20) | (pdn->busno << 16) | 140 (pdn->devfn << 8) | (where & 0xff); 141 buid = pdn->phb->buid; 142 if (buid) { 143 ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr, 144 BUID_HI(buid), BUID_LO(buid), size, (ulong) val); 145 } else { 146 ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val); 147 } 148 149 if (ret) 150 return PCIBIOS_DEVICE_NOT_FOUND; 151 152 return PCIBIOS_SUCCESSFUL; 153 } 154 155 static int rtas_pci_write_config(struct pci_bus *bus, 156 unsigned int devfn, 157 int where, int size, u32 val) 158 { 159 struct device_node *busdn, *dn; 160 161 if (bus->self) 162 busdn = pci_device_to_OF_node(bus->self); 163 else 164 busdn = bus->sysdata; /* must be a phb */ 165 166 /* Search only direct children of the bus */ 167 for (dn = busdn->child; dn; dn = dn->sibling) { 168 struct pci_dn *pdn = PCI_DN(dn); 169 if (pdn && pdn->devfn == devfn 170 && of_device_available(dn)) 171 return rtas_write_config(pdn, where, size, val); 172 } 173 return PCIBIOS_DEVICE_NOT_FOUND; 174 } 175 176 struct pci_ops rtas_pci_ops = { 177 rtas_pci_read_config, 178 rtas_pci_write_config 179 }; 180 181 int is_python(struct device_node *dev) 182 { 183 char *model = (char *)get_property(dev, "model", NULL); 184 185 if (model && strstr(model, "Python")) 186 return 1; 187 188 return 0; 189 } 190 191 static int get_phb_reg_prop(struct device_node *dev, 192 unsigned int addr_size_words, 193 struct reg_property64 *reg) 194 { 195 unsigned int *ui_ptr = NULL, len; 196 197 /* Found a PHB, now figure out where his registers are mapped. */ 198 ui_ptr = (unsigned int *)get_property(dev, "reg", &len); 199 if (ui_ptr == NULL) 200 return 1; 201 202 if (addr_size_words == 1) { 203 reg->address = ((struct reg_property32 *)ui_ptr)->address; 204 reg->size = ((struct reg_property32 *)ui_ptr)->size; 205 } else { 206 *reg = *((struct reg_property64 *)ui_ptr); 207 } 208 209 return 0; 210 } 211 212 static void python_countermeasures(struct device_node *dev, 213 unsigned int addr_size_words) 214 { 215 struct reg_property64 reg_struct; 216 void __iomem *chip_regs; 217 volatile u32 val; 218 219 if (get_phb_reg_prop(dev, addr_size_words, ®_struct)) 220 return; 221 222 /* Python's register file is 1 MB in size. */ 223 chip_regs = ioremap(reg_struct.address & ~(0xfffffUL), 0x100000); 224 225 /* 226 * Firmware doesn't always clear this bit which is critical 227 * for good performance - Anton 228 */ 229 230 #define PRG_CL_RESET_VALID 0x00010000 231 232 val = in_be32(chip_regs + 0xf6030); 233 if (val & PRG_CL_RESET_VALID) { 234 printk(KERN_INFO "Python workaround: "); 235 val &= ~PRG_CL_RESET_VALID; 236 out_be32(chip_regs + 0xf6030, val); 237 /* 238 * We must read it back for changes to 239 * take effect 240 */ 241 val = in_be32(chip_regs + 0xf6030); 242 printk("reg0: %x\n", val); 243 } 244 245 iounmap(chip_regs); 246 } 247 248 void __init init_pci_config_tokens (void) 249 { 250 read_pci_config = rtas_token("read-pci-config"); 251 write_pci_config = rtas_token("write-pci-config"); 252 ibm_read_pci_config = rtas_token("ibm,read-pci-config"); 253 ibm_write_pci_config = rtas_token("ibm,write-pci-config"); 254 } 255 256 unsigned long __devinit get_phb_buid (struct device_node *phb) 257 { 258 int addr_cells; 259 unsigned int *buid_vals; 260 unsigned int len; 261 unsigned long buid; 262 263 if (ibm_read_pci_config == -1) return 0; 264 265 /* PHB's will always be children of the root node, 266 * or so it is promised by the current firmware. */ 267 if (phb->parent == NULL) 268 return 0; 269 if (phb->parent->parent) 270 return 0; 271 272 buid_vals = (unsigned int *) get_property(phb, "reg", &len); 273 if (buid_vals == NULL) 274 return 0; 275 276 addr_cells = prom_n_addr_cells(phb); 277 if (addr_cells == 1) { 278 buid = (unsigned long) buid_vals[0]; 279 } else { 280 buid = (((unsigned long)buid_vals[0]) << 32UL) | 281 (((unsigned long)buid_vals[1]) & 0xffffffff); 282 } 283 return buid; 284 } 285 286 static int phb_set_bus_ranges(struct device_node *dev, 287 struct pci_controller *phb) 288 { 289 int *bus_range; 290 unsigned int len; 291 292 bus_range = (int *) get_property(dev, "bus-range", &len); 293 if (bus_range == NULL || len < 2 * sizeof(int)) { 294 return 1; 295 } 296 297 phb->first_busno = bus_range[0]; 298 phb->last_busno = bus_range[1]; 299 300 return 0; 301 } 302 303 static int __devinit setup_phb(struct device_node *dev, 304 struct pci_controller *phb, 305 unsigned int addr_size_words) 306 { 307 if (is_python(dev)) 308 python_countermeasures(dev, addr_size_words); 309 310 if (phb_set_bus_ranges(dev, phb)) 311 return 1; 312 313 phb->ops = &rtas_pci_ops; 314 phb->buid = get_phb_buid(dev); 315 316 return 0; 317 } 318 319 unsigned long __init find_and_init_phbs(void) 320 { 321 struct device_node *node; 322 struct pci_controller *phb; 323 unsigned int root_size_cells = 0; 324 unsigned int index; 325 unsigned int *opprop = NULL; 326 struct device_node *root = of_find_node_by_path("/"); 327 328 if (ppc64_interrupt_controller == IC_OPEN_PIC) { 329 opprop = (unsigned int *)get_property(root, 330 "platform-open-pic", NULL); 331 } 332 333 root_size_cells = prom_n_size_cells(root); 334 335 index = 0; 336 337 for (node = of_get_next_child(root, NULL); 338 node != NULL; 339 node = of_get_next_child(root, node)) { 340 if (node->type == NULL || strcmp(node->type, "pci") != 0) 341 continue; 342 343 phb = pcibios_alloc_controller(node); 344 if (!phb) 345 continue; 346 setup_phb(node, phb, root_size_cells); 347 pci_process_bridge_OF_ranges(phb, node, 0); 348 pci_setup_phb_io(phb, index == 0); 349 #ifdef CONFIG_PPC_PSERIES 350 if (ppc64_interrupt_controller == IC_OPEN_PIC && pSeries_mpic) { 351 int addr = root_size_cells * (index + 2) - 1; 352 mpic_assign_isu(pSeries_mpic, index, opprop[addr]); 353 } 354 #endif 355 index++; 356 } 357 358 of_node_put(root); 359 pci_devs_phb_init(); 360 361 /* 362 * pci_probe_only and pci_assign_all_buses can be set via properties 363 * in chosen. 364 */ 365 if (of_chosen) { 366 int *prop; 367 368 prop = (int *)get_property(of_chosen, "linux,pci-probe-only", 369 NULL); 370 if (prop) 371 pci_probe_only = *prop; 372 373 prop = (int *)get_property(of_chosen, 374 "linux,pci-assign-all-buses", NULL); 375 if (prop) 376 pci_assign_all_buses = *prop; 377 } 378 379 return 0; 380 } 381 382 struct pci_controller * __devinit init_phb_dynamic(struct device_node *dn) 383 { 384 struct device_node *root = of_find_node_by_path("/"); 385 unsigned int root_size_cells = 0; 386 struct pci_controller *phb; 387 int primary; 388 389 root_size_cells = prom_n_size_cells(root); 390 391 primary = list_empty(&hose_list); 392 phb = pcibios_alloc_controller(dn); 393 if (!phb) 394 return NULL; 395 setup_phb(dn, phb, root_size_cells); 396 pci_process_bridge_OF_ranges(phb, dn, primary); 397 398 pci_setup_phb_io_dynamic(phb, primary); 399 of_node_put(root); 400 401 pci_devs_phb_init_dynamic(phb); 402 scan_phb(phb); 403 404 return phb; 405 } 406 EXPORT_SYMBOL(init_phb_dynamic); 407 408 /* RPA-specific bits for removing PHBs */ 409 int pcibios_remove_root_bus(struct pci_controller *phb) 410 { 411 struct pci_bus *b = phb->bus; 412 struct resource *res; 413 int rc, i; 414 415 res = b->resource[0]; 416 if (!res->flags) { 417 printk(KERN_ERR "%s: no IO resource for PHB %s\n", __FUNCTION__, 418 b->name); 419 return 1; 420 } 421 422 rc = unmap_bus_range(b); 423 if (rc) { 424 printk(KERN_ERR "%s: failed to unmap IO on bus %s\n", 425 __FUNCTION__, b->name); 426 return 1; 427 } 428 429 if (release_resource(res)) { 430 printk(KERN_ERR "%s: failed to release IO on bus %s\n", 431 __FUNCTION__, b->name); 432 return 1; 433 } 434 435 for (i = 1; i < 3; ++i) { 436 res = b->resource[i]; 437 if (!res->flags && i == 0) { 438 printk(KERN_ERR "%s: no MEM resource for PHB %s\n", 439 __FUNCTION__, b->name); 440 return 1; 441 } 442 if (res->flags && release_resource(res)) { 443 printk(KERN_ERR 444 "%s: failed to release IO %d on bus %s\n", 445 __FUNCTION__, i, b->name); 446 return 1; 447 } 448 } 449 450 list_del(&phb->list_node); 451 pcibios_free_controller(phb); 452 453 return 0; 454 } 455 EXPORT_SYMBOL(pcibios_remove_root_bus); 456