1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 6 * Paul Mackerras (paulus@cs.anu.edu.au) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/elf.h> 28 #include <linux/prctl.h> 29 #include <linux/init_task.h> 30 #include <linux/export.h> 31 #include <linux/kallsyms.h> 32 #include <linux/mqueue.h> 33 #include <linux/hardirq.h> 34 #include <linux/utsname.h> 35 #include <linux/ftrace.h> 36 #include <linux/kernel_stat.h> 37 #include <linux/personality.h> 38 #include <linux/random.h> 39 #include <linux/hw_breakpoint.h> 40 #include <linux/uaccess.h> 41 42 #include <asm/pgtable.h> 43 #include <asm/io.h> 44 #include <asm/processor.h> 45 #include <asm/mmu.h> 46 #include <asm/prom.h> 47 #include <asm/machdep.h> 48 #include <asm/time.h> 49 #include <asm/runlatch.h> 50 #include <asm/syscalls.h> 51 #include <asm/switch_to.h> 52 #include <asm/tm.h> 53 #include <asm/debug.h> 54 #ifdef CONFIG_PPC64 55 #include <asm/firmware.h> 56 #endif 57 #include <asm/code-patching.h> 58 #include <asm/livepatch.h> 59 60 #include <linux/kprobes.h> 61 #include <linux/kdebug.h> 62 63 /* Transactional Memory debug */ 64 #ifdef TM_DEBUG_SW 65 #define TM_DEBUG(x...) printk(KERN_INFO x) 66 #else 67 #define TM_DEBUG(x...) do { } while(0) 68 #endif 69 70 extern unsigned long _get_SP(void); 71 72 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 73 static void check_if_tm_restore_required(struct task_struct *tsk) 74 { 75 /* 76 * If we are saving the current thread's registers, and the 77 * thread is in a transactional state, set the TIF_RESTORE_TM 78 * bit so that we know to restore the registers before 79 * returning to userspace. 80 */ 81 if (tsk == current && tsk->thread.regs && 82 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 83 !test_thread_flag(TIF_RESTORE_TM)) { 84 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 85 set_thread_flag(TIF_RESTORE_TM); 86 } 87 } 88 #else 89 static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 90 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 91 92 bool strict_msr_control; 93 EXPORT_SYMBOL(strict_msr_control); 94 95 static int __init enable_strict_msr_control(char *str) 96 { 97 strict_msr_control = true; 98 pr_info("Enabling strict facility control\n"); 99 100 return 0; 101 } 102 early_param("ppc_strict_facility_enable", enable_strict_msr_control); 103 104 void msr_check_and_set(unsigned long bits) 105 { 106 unsigned long oldmsr = mfmsr(); 107 unsigned long newmsr; 108 109 newmsr = oldmsr | bits; 110 111 #ifdef CONFIG_VSX 112 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 113 newmsr |= MSR_VSX; 114 #endif 115 116 if (oldmsr != newmsr) 117 mtmsr_isync(newmsr); 118 } 119 120 void __msr_check_and_clear(unsigned long bits) 121 { 122 unsigned long oldmsr = mfmsr(); 123 unsigned long newmsr; 124 125 newmsr = oldmsr & ~bits; 126 127 #ifdef CONFIG_VSX 128 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 129 newmsr &= ~MSR_VSX; 130 #endif 131 132 if (oldmsr != newmsr) 133 mtmsr_isync(newmsr); 134 } 135 EXPORT_SYMBOL(__msr_check_and_clear); 136 137 #ifdef CONFIG_PPC_FPU 138 void giveup_fpu(struct task_struct *tsk) 139 { 140 check_if_tm_restore_required(tsk); 141 142 msr_check_and_set(MSR_FP); 143 __giveup_fpu(tsk); 144 msr_check_and_clear(MSR_FP); 145 } 146 EXPORT_SYMBOL(giveup_fpu); 147 148 /* 149 * Make sure the floating-point register state in the 150 * the thread_struct is up to date for task tsk. 151 */ 152 void flush_fp_to_thread(struct task_struct *tsk) 153 { 154 if (tsk->thread.regs) { 155 /* 156 * We need to disable preemption here because if we didn't, 157 * another process could get scheduled after the regs->msr 158 * test but before we have finished saving the FP registers 159 * to the thread_struct. That process could take over the 160 * FPU, and then when we get scheduled again we would store 161 * bogus values for the remaining FP registers. 162 */ 163 preempt_disable(); 164 if (tsk->thread.regs->msr & MSR_FP) { 165 /* 166 * This should only ever be called for current or 167 * for a stopped child process. Since we save away 168 * the FP register state on context switch, 169 * there is something wrong if a stopped child appears 170 * to still have its FP state in the CPU registers. 171 */ 172 BUG_ON(tsk != current); 173 giveup_fpu(tsk); 174 } 175 preempt_enable(); 176 } 177 } 178 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 179 180 void enable_kernel_fp(void) 181 { 182 WARN_ON(preemptible()); 183 184 msr_check_and_set(MSR_FP); 185 186 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 187 check_if_tm_restore_required(current); 188 __giveup_fpu(current); 189 } 190 } 191 EXPORT_SYMBOL(enable_kernel_fp); 192 #endif /* CONFIG_PPC_FPU */ 193 194 #ifdef CONFIG_ALTIVEC 195 void giveup_altivec(struct task_struct *tsk) 196 { 197 check_if_tm_restore_required(tsk); 198 199 msr_check_and_set(MSR_VEC); 200 __giveup_altivec(tsk); 201 msr_check_and_clear(MSR_VEC); 202 } 203 EXPORT_SYMBOL(giveup_altivec); 204 205 void enable_kernel_altivec(void) 206 { 207 WARN_ON(preemptible()); 208 209 msr_check_and_set(MSR_VEC); 210 211 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 212 check_if_tm_restore_required(current); 213 __giveup_altivec(current); 214 } 215 } 216 EXPORT_SYMBOL(enable_kernel_altivec); 217 218 /* 219 * Make sure the VMX/Altivec register state in the 220 * the thread_struct is up to date for task tsk. 221 */ 222 void flush_altivec_to_thread(struct task_struct *tsk) 223 { 224 if (tsk->thread.regs) { 225 preempt_disable(); 226 if (tsk->thread.regs->msr & MSR_VEC) { 227 BUG_ON(tsk != current); 228 giveup_altivec(tsk); 229 } 230 preempt_enable(); 231 } 232 } 233 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 234 #endif /* CONFIG_ALTIVEC */ 235 236 #ifdef CONFIG_VSX 237 void giveup_vsx(struct task_struct *tsk) 238 { 239 check_if_tm_restore_required(tsk); 240 241 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 242 if (tsk->thread.regs->msr & MSR_FP) 243 __giveup_fpu(tsk); 244 if (tsk->thread.regs->msr & MSR_VEC) 245 __giveup_altivec(tsk); 246 __giveup_vsx(tsk); 247 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 248 } 249 EXPORT_SYMBOL(giveup_vsx); 250 251 void enable_kernel_vsx(void) 252 { 253 WARN_ON(preemptible()); 254 255 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 256 257 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) { 258 check_if_tm_restore_required(current); 259 if (current->thread.regs->msr & MSR_FP) 260 __giveup_fpu(current); 261 if (current->thread.regs->msr & MSR_VEC) 262 __giveup_altivec(current); 263 __giveup_vsx(current); 264 } 265 } 266 EXPORT_SYMBOL(enable_kernel_vsx); 267 268 void flush_vsx_to_thread(struct task_struct *tsk) 269 { 270 if (tsk->thread.regs) { 271 preempt_disable(); 272 if (tsk->thread.regs->msr & MSR_VSX) { 273 BUG_ON(tsk != current); 274 giveup_vsx(tsk); 275 } 276 preempt_enable(); 277 } 278 } 279 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 280 #endif /* CONFIG_VSX */ 281 282 #ifdef CONFIG_SPE 283 void giveup_spe(struct task_struct *tsk) 284 { 285 check_if_tm_restore_required(tsk); 286 287 msr_check_and_set(MSR_SPE); 288 __giveup_spe(tsk); 289 msr_check_and_clear(MSR_SPE); 290 } 291 EXPORT_SYMBOL(giveup_spe); 292 293 void enable_kernel_spe(void) 294 { 295 WARN_ON(preemptible()); 296 297 msr_check_and_set(MSR_SPE); 298 299 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 300 check_if_tm_restore_required(current); 301 __giveup_spe(current); 302 } 303 } 304 EXPORT_SYMBOL(enable_kernel_spe); 305 306 void flush_spe_to_thread(struct task_struct *tsk) 307 { 308 if (tsk->thread.regs) { 309 preempt_disable(); 310 if (tsk->thread.regs->msr & MSR_SPE) { 311 BUG_ON(tsk != current); 312 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 313 giveup_spe(tsk); 314 } 315 preempt_enable(); 316 } 317 } 318 #endif /* CONFIG_SPE */ 319 320 static unsigned long msr_all_available; 321 322 static int __init init_msr_all_available(void) 323 { 324 #ifdef CONFIG_PPC_FPU 325 msr_all_available |= MSR_FP; 326 #endif 327 #ifdef CONFIG_ALTIVEC 328 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 329 msr_all_available |= MSR_VEC; 330 #endif 331 #ifdef CONFIG_VSX 332 if (cpu_has_feature(CPU_FTR_VSX)) 333 msr_all_available |= MSR_VSX; 334 #endif 335 #ifdef CONFIG_SPE 336 if (cpu_has_feature(CPU_FTR_SPE)) 337 msr_all_available |= MSR_SPE; 338 #endif 339 340 return 0; 341 } 342 early_initcall(init_msr_all_available); 343 344 void giveup_all(struct task_struct *tsk) 345 { 346 unsigned long usermsr; 347 348 if (!tsk->thread.regs) 349 return; 350 351 usermsr = tsk->thread.regs->msr; 352 353 if ((usermsr & msr_all_available) == 0) 354 return; 355 356 msr_check_and_set(msr_all_available); 357 358 #ifdef CONFIG_PPC_FPU 359 if (usermsr & MSR_FP) 360 __giveup_fpu(tsk); 361 #endif 362 #ifdef CONFIG_ALTIVEC 363 if (usermsr & MSR_VEC) 364 __giveup_altivec(tsk); 365 #endif 366 #ifdef CONFIG_VSX 367 if (usermsr & MSR_VSX) 368 __giveup_vsx(tsk); 369 #endif 370 #ifdef CONFIG_SPE 371 if (usermsr & MSR_SPE) 372 __giveup_spe(tsk); 373 #endif 374 375 msr_check_and_clear(msr_all_available); 376 } 377 EXPORT_SYMBOL(giveup_all); 378 379 void flush_all_to_thread(struct task_struct *tsk) 380 { 381 if (tsk->thread.regs) { 382 preempt_disable(); 383 BUG_ON(tsk != current); 384 giveup_all(tsk); 385 386 #ifdef CONFIG_SPE 387 if (tsk->thread.regs->msr & MSR_SPE) 388 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 389 #endif 390 391 preempt_enable(); 392 } 393 } 394 EXPORT_SYMBOL(flush_all_to_thread); 395 396 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 397 void do_send_trap(struct pt_regs *regs, unsigned long address, 398 unsigned long error_code, int signal_code, int breakpt) 399 { 400 siginfo_t info; 401 402 current->thread.trap_nr = signal_code; 403 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 404 11, SIGSEGV) == NOTIFY_STOP) 405 return; 406 407 /* Deliver the signal to userspace */ 408 info.si_signo = SIGTRAP; 409 info.si_errno = breakpt; /* breakpoint or watchpoint id */ 410 info.si_code = signal_code; 411 info.si_addr = (void __user *)address; 412 force_sig_info(SIGTRAP, &info, current); 413 } 414 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 415 void do_break (struct pt_regs *regs, unsigned long address, 416 unsigned long error_code) 417 { 418 siginfo_t info; 419 420 current->thread.trap_nr = TRAP_HWBKPT; 421 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 422 11, SIGSEGV) == NOTIFY_STOP) 423 return; 424 425 if (debugger_break_match(regs)) 426 return; 427 428 /* Clear the breakpoint */ 429 hw_breakpoint_disable(); 430 431 /* Deliver the signal to userspace */ 432 info.si_signo = SIGTRAP; 433 info.si_errno = 0; 434 info.si_code = TRAP_HWBKPT; 435 info.si_addr = (void __user *)address; 436 force_sig_info(SIGTRAP, &info, current); 437 } 438 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 439 440 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 441 442 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 443 /* 444 * Set the debug registers back to their default "safe" values. 445 */ 446 static void set_debug_reg_defaults(struct thread_struct *thread) 447 { 448 thread->debug.iac1 = thread->debug.iac2 = 0; 449 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 450 thread->debug.iac3 = thread->debug.iac4 = 0; 451 #endif 452 thread->debug.dac1 = thread->debug.dac2 = 0; 453 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 454 thread->debug.dvc1 = thread->debug.dvc2 = 0; 455 #endif 456 thread->debug.dbcr0 = 0; 457 #ifdef CONFIG_BOOKE 458 /* 459 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 460 */ 461 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 462 DBCR1_IAC3US | DBCR1_IAC4US; 463 /* 464 * Force Data Address Compare User/Supervisor bits to be User-only 465 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 466 */ 467 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 468 #else 469 thread->debug.dbcr1 = 0; 470 #endif 471 } 472 473 static void prime_debug_regs(struct debug_reg *debug) 474 { 475 /* 476 * We could have inherited MSR_DE from userspace, since 477 * it doesn't get cleared on exception entry. Make sure 478 * MSR_DE is clear before we enable any debug events. 479 */ 480 mtmsr(mfmsr() & ~MSR_DE); 481 482 mtspr(SPRN_IAC1, debug->iac1); 483 mtspr(SPRN_IAC2, debug->iac2); 484 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 485 mtspr(SPRN_IAC3, debug->iac3); 486 mtspr(SPRN_IAC4, debug->iac4); 487 #endif 488 mtspr(SPRN_DAC1, debug->dac1); 489 mtspr(SPRN_DAC2, debug->dac2); 490 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 491 mtspr(SPRN_DVC1, debug->dvc1); 492 mtspr(SPRN_DVC2, debug->dvc2); 493 #endif 494 mtspr(SPRN_DBCR0, debug->dbcr0); 495 mtspr(SPRN_DBCR1, debug->dbcr1); 496 #ifdef CONFIG_BOOKE 497 mtspr(SPRN_DBCR2, debug->dbcr2); 498 #endif 499 } 500 /* 501 * Unless neither the old or new thread are making use of the 502 * debug registers, set the debug registers from the values 503 * stored in the new thread. 504 */ 505 void switch_booke_debug_regs(struct debug_reg *new_debug) 506 { 507 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 508 || (new_debug->dbcr0 & DBCR0_IDM)) 509 prime_debug_regs(new_debug); 510 } 511 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 512 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 513 #ifndef CONFIG_HAVE_HW_BREAKPOINT 514 static void set_debug_reg_defaults(struct thread_struct *thread) 515 { 516 thread->hw_brk.address = 0; 517 thread->hw_brk.type = 0; 518 set_breakpoint(&thread->hw_brk); 519 } 520 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 521 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 522 523 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 524 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 525 { 526 mtspr(SPRN_DAC1, dabr); 527 #ifdef CONFIG_PPC_47x 528 isync(); 529 #endif 530 return 0; 531 } 532 #elif defined(CONFIG_PPC_BOOK3S) 533 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 534 { 535 mtspr(SPRN_DABR, dabr); 536 if (cpu_has_feature(CPU_FTR_DABRX)) 537 mtspr(SPRN_DABRX, dabrx); 538 return 0; 539 } 540 #else 541 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 542 { 543 return -EINVAL; 544 } 545 #endif 546 547 static inline int set_dabr(struct arch_hw_breakpoint *brk) 548 { 549 unsigned long dabr, dabrx; 550 551 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 552 dabrx = ((brk->type >> 3) & 0x7); 553 554 if (ppc_md.set_dabr) 555 return ppc_md.set_dabr(dabr, dabrx); 556 557 return __set_dabr(dabr, dabrx); 558 } 559 560 static inline int set_dawr(struct arch_hw_breakpoint *brk) 561 { 562 unsigned long dawr, dawrx, mrd; 563 564 dawr = brk->address; 565 566 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 567 << (63 - 58); //* read/write bits */ 568 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 569 << (63 - 59); //* translate */ 570 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 571 >> 3; //* PRIM bits */ 572 /* dawr length is stored in field MDR bits 48:53. Matches range in 573 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 574 0b111111=64DW. 575 brk->len is in bytes. 576 This aligns up to double word size, shifts and does the bias. 577 */ 578 mrd = ((brk->len + 7) >> 3) - 1; 579 dawrx |= (mrd & 0x3f) << (63 - 53); 580 581 if (ppc_md.set_dawr) 582 return ppc_md.set_dawr(dawr, dawrx); 583 mtspr(SPRN_DAWR, dawr); 584 mtspr(SPRN_DAWRX, dawrx); 585 return 0; 586 } 587 588 void __set_breakpoint(struct arch_hw_breakpoint *brk) 589 { 590 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); 591 592 if (cpu_has_feature(CPU_FTR_DAWR)) 593 set_dawr(brk); 594 else 595 set_dabr(brk); 596 } 597 598 void set_breakpoint(struct arch_hw_breakpoint *brk) 599 { 600 preempt_disable(); 601 __set_breakpoint(brk); 602 preempt_enable(); 603 } 604 605 #ifdef CONFIG_PPC64 606 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 607 #endif 608 609 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 610 struct arch_hw_breakpoint *b) 611 { 612 if (a->address != b->address) 613 return false; 614 if (a->type != b->type) 615 return false; 616 if (a->len != b->len) 617 return false; 618 return true; 619 } 620 621 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 622 static void tm_reclaim_thread(struct thread_struct *thr, 623 struct thread_info *ti, uint8_t cause) 624 { 625 unsigned long msr_diff = 0; 626 627 /* 628 * If FP/VSX registers have been already saved to the 629 * thread_struct, move them to the transact_fp array. 630 * We clear the TIF_RESTORE_TM bit since after the reclaim 631 * the thread will no longer be transactional. 632 */ 633 if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) { 634 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr; 635 if (msr_diff & MSR_FP) 636 memcpy(&thr->transact_fp, &thr->fp_state, 637 sizeof(struct thread_fp_state)); 638 if (msr_diff & MSR_VEC) 639 memcpy(&thr->transact_vr, &thr->vr_state, 640 sizeof(struct thread_vr_state)); 641 clear_ti_thread_flag(ti, TIF_RESTORE_TM); 642 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1; 643 } 644 645 /* 646 * Use the current MSR TM suspended bit to track if we have 647 * checkpointed state outstanding. 648 * On signal delivery, we'd normally reclaim the checkpointed 649 * state to obtain stack pointer (see:get_tm_stackpointer()). 650 * This will then directly return to userspace without going 651 * through __switch_to(). However, if the stack frame is bad, 652 * we need to exit this thread which calls __switch_to() which 653 * will again attempt to reclaim the already saved tm state. 654 * Hence we need to check that we've not already reclaimed 655 * this state. 656 * We do this using the current MSR, rather tracking it in 657 * some specific thread_struct bit, as it has the additional 658 * benifit of checking for a potential TM bad thing exception. 659 */ 660 if (!MSR_TM_SUSPENDED(mfmsr())) 661 return; 662 663 tm_reclaim(thr, thr->regs->msr, cause); 664 665 /* Having done the reclaim, we now have the checkpointed 666 * FP/VSX values in the registers. These might be valid 667 * even if we have previously called enable_kernel_fp() or 668 * flush_fp_to_thread(), so update thr->regs->msr to 669 * indicate their current validity. 670 */ 671 thr->regs->msr |= msr_diff; 672 } 673 674 void tm_reclaim_current(uint8_t cause) 675 { 676 tm_enable(); 677 tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 678 } 679 680 static inline void tm_reclaim_task(struct task_struct *tsk) 681 { 682 /* We have to work out if we're switching from/to a task that's in the 683 * middle of a transaction. 684 * 685 * In switching we need to maintain a 2nd register state as 686 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 687 * checkpointed (tbegin) state in ckpt_regs and saves the transactional 688 * (current) FPRs into oldtask->thread.transact_fpr[]. 689 * 690 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 691 */ 692 struct thread_struct *thr = &tsk->thread; 693 694 if (!thr->regs) 695 return; 696 697 if (!MSR_TM_ACTIVE(thr->regs->msr)) 698 goto out_and_saveregs; 699 700 /* Stash the original thread MSR, as giveup_fpu et al will 701 * modify it. We hold onto it to see whether the task used 702 * FP & vector regs. If the TIF_RESTORE_TM flag is set, 703 * ckpt_regs.msr is already set. 704 */ 705 if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM)) 706 thr->ckpt_regs.msr = thr->regs->msr; 707 708 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 709 "ccr=%lx, msr=%lx, trap=%lx)\n", 710 tsk->pid, thr->regs->nip, 711 thr->regs->ccr, thr->regs->msr, 712 thr->regs->trap); 713 714 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 715 716 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 717 tsk->pid); 718 719 out_and_saveregs: 720 /* Always save the regs here, even if a transaction's not active. 721 * This context-switches a thread's TM info SPRs. We do it here to 722 * be consistent with the restore path (in recheckpoint) which 723 * cannot happen later in _switch(). 724 */ 725 tm_save_sprs(thr); 726 } 727 728 extern void __tm_recheckpoint(struct thread_struct *thread, 729 unsigned long orig_msr); 730 731 void tm_recheckpoint(struct thread_struct *thread, 732 unsigned long orig_msr) 733 { 734 unsigned long flags; 735 736 /* We really can't be interrupted here as the TEXASR registers can't 737 * change and later in the trecheckpoint code, we have a userspace R1. 738 * So let's hard disable over this region. 739 */ 740 local_irq_save(flags); 741 hard_irq_disable(); 742 743 /* The TM SPRs are restored here, so that TEXASR.FS can be set 744 * before the trecheckpoint and no explosion occurs. 745 */ 746 tm_restore_sprs(thread); 747 748 __tm_recheckpoint(thread, orig_msr); 749 750 local_irq_restore(flags); 751 } 752 753 static inline void tm_recheckpoint_new_task(struct task_struct *new) 754 { 755 unsigned long msr; 756 757 if (!cpu_has_feature(CPU_FTR_TM)) 758 return; 759 760 /* Recheckpoint the registers of the thread we're about to switch to. 761 * 762 * If the task was using FP, we non-lazily reload both the original and 763 * the speculative FP register states. This is because the kernel 764 * doesn't see if/when a TM rollback occurs, so if we take an FP 765 * unavoidable later, we are unable to determine which set of FP regs 766 * need to be restored. 767 */ 768 if (!new->thread.regs) 769 return; 770 771 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 772 tm_restore_sprs(&new->thread); 773 return; 774 } 775 msr = new->thread.ckpt_regs.msr; 776 /* Recheckpoint to restore original checkpointed register state. */ 777 TM_DEBUG("*** tm_recheckpoint of pid %d " 778 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 779 new->pid, new->thread.regs->msr, msr); 780 781 /* This loads the checkpointed FP/VEC state, if used */ 782 tm_recheckpoint(&new->thread, msr); 783 784 /* This loads the speculative FP/VEC state, if used */ 785 if (msr & MSR_FP) { 786 do_load_up_transact_fpu(&new->thread); 787 new->thread.regs->msr |= 788 (MSR_FP | new->thread.fpexc_mode); 789 } 790 #ifdef CONFIG_ALTIVEC 791 if (msr & MSR_VEC) { 792 do_load_up_transact_altivec(&new->thread); 793 new->thread.regs->msr |= MSR_VEC; 794 } 795 #endif 796 /* We may as well turn on VSX too since all the state is restored now */ 797 if (msr & MSR_VSX) 798 new->thread.regs->msr |= MSR_VSX; 799 800 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 801 "(kernel msr 0x%lx)\n", 802 new->pid, mfmsr()); 803 } 804 805 static inline void __switch_to_tm(struct task_struct *prev) 806 { 807 if (cpu_has_feature(CPU_FTR_TM)) { 808 tm_enable(); 809 tm_reclaim_task(prev); 810 } 811 } 812 813 /* 814 * This is called if we are on the way out to userspace and the 815 * TIF_RESTORE_TM flag is set. It checks if we need to reload 816 * FP and/or vector state and does so if necessary. 817 * If userspace is inside a transaction (whether active or 818 * suspended) and FP/VMX/VSX instructions have ever been enabled 819 * inside that transaction, then we have to keep them enabled 820 * and keep the FP/VMX/VSX state loaded while ever the transaction 821 * continues. The reason is that if we didn't, and subsequently 822 * got a FP/VMX/VSX unavailable interrupt inside a transaction, 823 * we don't know whether it's the same transaction, and thus we 824 * don't know which of the checkpointed state and the transactional 825 * state to use. 826 */ 827 void restore_tm_state(struct pt_regs *regs) 828 { 829 unsigned long msr_diff; 830 831 clear_thread_flag(TIF_RESTORE_TM); 832 if (!MSR_TM_ACTIVE(regs->msr)) 833 return; 834 835 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 836 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 837 if (msr_diff & MSR_FP) { 838 msr_check_and_set(MSR_FP); 839 load_fp_state(¤t->thread.fp_state); 840 msr_check_and_clear(MSR_FP); 841 regs->msr |= current->thread.fpexc_mode; 842 } 843 if (msr_diff & MSR_VEC) { 844 msr_check_and_set(MSR_VEC); 845 load_vr_state(¤t->thread.vr_state); 846 msr_check_and_clear(MSR_VEC); 847 } 848 regs->msr |= msr_diff; 849 } 850 851 #else 852 #define tm_recheckpoint_new_task(new) 853 #define __switch_to_tm(prev) 854 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 855 856 static inline void save_sprs(struct thread_struct *t) 857 { 858 #ifdef CONFIG_ALTIVEC 859 if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC))) 860 t->vrsave = mfspr(SPRN_VRSAVE); 861 #endif 862 #ifdef CONFIG_PPC_BOOK3S_64 863 if (cpu_has_feature(CPU_FTR_DSCR)) 864 t->dscr = mfspr(SPRN_DSCR); 865 866 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 867 t->bescr = mfspr(SPRN_BESCR); 868 t->ebbhr = mfspr(SPRN_EBBHR); 869 t->ebbrr = mfspr(SPRN_EBBRR); 870 871 t->fscr = mfspr(SPRN_FSCR); 872 873 /* 874 * Note that the TAR is not available for use in the kernel. 875 * (To provide this, the TAR should be backed up/restored on 876 * exception entry/exit instead, and be in pt_regs. FIXME, 877 * this should be in pt_regs anyway (for debug).) 878 */ 879 t->tar = mfspr(SPRN_TAR); 880 } 881 #endif 882 } 883 884 static inline void restore_sprs(struct thread_struct *old_thread, 885 struct thread_struct *new_thread) 886 { 887 #ifdef CONFIG_ALTIVEC 888 if (cpu_has_feature(CPU_FTR_ALTIVEC) && 889 old_thread->vrsave != new_thread->vrsave) 890 mtspr(SPRN_VRSAVE, new_thread->vrsave); 891 #endif 892 #ifdef CONFIG_PPC_BOOK3S_64 893 if (cpu_has_feature(CPU_FTR_DSCR)) { 894 u64 dscr = get_paca()->dscr_default; 895 u64 fscr = old_thread->fscr & ~FSCR_DSCR; 896 897 if (new_thread->dscr_inherit) { 898 dscr = new_thread->dscr; 899 fscr |= FSCR_DSCR; 900 } 901 902 if (old_thread->dscr != dscr) 903 mtspr(SPRN_DSCR, dscr); 904 905 if (old_thread->fscr != fscr) 906 mtspr(SPRN_FSCR, fscr); 907 } 908 909 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 910 if (old_thread->bescr != new_thread->bescr) 911 mtspr(SPRN_BESCR, new_thread->bescr); 912 if (old_thread->ebbhr != new_thread->ebbhr) 913 mtspr(SPRN_EBBHR, new_thread->ebbhr); 914 if (old_thread->ebbrr != new_thread->ebbrr) 915 mtspr(SPRN_EBBRR, new_thread->ebbrr); 916 917 if (old_thread->tar != new_thread->tar) 918 mtspr(SPRN_TAR, new_thread->tar); 919 } 920 #endif 921 } 922 923 struct task_struct *__switch_to(struct task_struct *prev, 924 struct task_struct *new) 925 { 926 struct thread_struct *new_thread, *old_thread; 927 struct task_struct *last; 928 #ifdef CONFIG_PPC_BOOK3S_64 929 struct ppc64_tlb_batch *batch; 930 #endif 931 932 new_thread = &new->thread; 933 old_thread = ¤t->thread; 934 935 WARN_ON(!irqs_disabled()); 936 937 #ifdef CONFIG_PPC64 938 /* 939 * Collect processor utilization data per process 940 */ 941 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 942 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array); 943 long unsigned start_tb, current_tb; 944 start_tb = old_thread->start_tb; 945 cu->current_tb = current_tb = mfspr(SPRN_PURR); 946 old_thread->accum_tb += (current_tb - start_tb); 947 new_thread->start_tb = current_tb; 948 } 949 #endif /* CONFIG_PPC64 */ 950 951 #ifdef CONFIG_PPC_BOOK3S_64 952 batch = this_cpu_ptr(&ppc64_tlb_batch); 953 if (batch->active) { 954 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 955 if (batch->index) 956 __flush_tlb_pending(batch); 957 batch->active = 0; 958 } 959 #endif /* CONFIG_PPC_BOOK3S_64 */ 960 961 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 962 switch_booke_debug_regs(&new->thread.debug); 963 #else 964 /* 965 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 966 * schedule DABR 967 */ 968 #ifndef CONFIG_HAVE_HW_BREAKPOINT 969 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) 970 __set_breakpoint(&new->thread.hw_brk); 971 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 972 #endif 973 974 /* 975 * We need to save SPRs before treclaim/trecheckpoint as these will 976 * change a number of them. 977 */ 978 save_sprs(&prev->thread); 979 980 __switch_to_tm(prev); 981 982 /* Save FPU, Altivec, VSX and SPE state */ 983 giveup_all(prev); 984 985 /* 986 * We can't take a PMU exception inside _switch() since there is a 987 * window where the kernel stack SLB and the kernel stack are out 988 * of sync. Hard disable here. 989 */ 990 hard_irq_disable(); 991 992 tm_recheckpoint_new_task(new); 993 994 /* 995 * Call restore_sprs() before calling _switch(). If we move it after 996 * _switch() then we miss out on calling it for new tasks. The reason 997 * for this is we manually create a stack frame for new tasks that 998 * directly returns through ret_from_fork() or 999 * ret_from_kernel_thread(). See copy_thread() for details. 1000 */ 1001 restore_sprs(old_thread, new_thread); 1002 1003 last = _switch(old_thread, new_thread); 1004 1005 #ifdef CONFIG_PPC_BOOK3S_64 1006 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1007 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 1008 batch = this_cpu_ptr(&ppc64_tlb_batch); 1009 batch->active = 1; 1010 } 1011 #endif /* CONFIG_PPC_BOOK3S_64 */ 1012 1013 return last; 1014 } 1015 1016 static int instructions_to_print = 16; 1017 1018 static void show_instructions(struct pt_regs *regs) 1019 { 1020 int i; 1021 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 1022 sizeof(int)); 1023 1024 printk("Instruction dump:"); 1025 1026 for (i = 0; i < instructions_to_print; i++) { 1027 int instr; 1028 1029 if (!(i % 8)) 1030 printk("\n"); 1031 1032 #if !defined(CONFIG_BOOKE) 1033 /* If executing with the IMMU off, adjust pc rather 1034 * than print XXXXXXXX. 1035 */ 1036 if (!(regs->msr & MSR_IR)) 1037 pc = (unsigned long)phys_to_virt(pc); 1038 #endif 1039 1040 if (!__kernel_text_address(pc) || 1041 probe_kernel_address((unsigned int __user *)pc, instr)) { 1042 printk(KERN_CONT "XXXXXXXX "); 1043 } else { 1044 if (regs->nip == pc) 1045 printk(KERN_CONT "<%08x> ", instr); 1046 else 1047 printk(KERN_CONT "%08x ", instr); 1048 } 1049 1050 pc += sizeof(int); 1051 } 1052 1053 printk("\n"); 1054 } 1055 1056 struct regbit { 1057 unsigned long bit; 1058 const char *name; 1059 }; 1060 1061 static struct regbit msr_bits[] = { 1062 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 1063 {MSR_SF, "SF"}, 1064 {MSR_HV, "HV"}, 1065 #endif 1066 {MSR_VEC, "VEC"}, 1067 {MSR_VSX, "VSX"}, 1068 #ifdef CONFIG_BOOKE 1069 {MSR_CE, "CE"}, 1070 #endif 1071 {MSR_EE, "EE"}, 1072 {MSR_PR, "PR"}, 1073 {MSR_FP, "FP"}, 1074 {MSR_ME, "ME"}, 1075 #ifdef CONFIG_BOOKE 1076 {MSR_DE, "DE"}, 1077 #else 1078 {MSR_SE, "SE"}, 1079 {MSR_BE, "BE"}, 1080 #endif 1081 {MSR_IR, "IR"}, 1082 {MSR_DR, "DR"}, 1083 {MSR_PMM, "PMM"}, 1084 #ifndef CONFIG_BOOKE 1085 {MSR_RI, "RI"}, 1086 {MSR_LE, "LE"}, 1087 #endif 1088 {0, NULL} 1089 }; 1090 1091 static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 1092 { 1093 const char *s = ""; 1094 1095 for (; bits->bit; ++bits) 1096 if (val & bits->bit) { 1097 printk("%s%s", s, bits->name); 1098 s = sep; 1099 } 1100 } 1101 1102 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1103 static struct regbit msr_tm_bits[] = { 1104 {MSR_TS_T, "T"}, 1105 {MSR_TS_S, "S"}, 1106 {MSR_TM, "E"}, 1107 {0, NULL} 1108 }; 1109 1110 static void print_tm_bits(unsigned long val) 1111 { 1112 /* 1113 * This only prints something if at least one of the TM bit is set. 1114 * Inside the TM[], the output means: 1115 * E: Enabled (bit 32) 1116 * S: Suspended (bit 33) 1117 * T: Transactional (bit 34) 1118 */ 1119 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1120 printk(",TM["); 1121 print_bits(val, msr_tm_bits, ""); 1122 printk("]"); 1123 } 1124 } 1125 #else 1126 static void print_tm_bits(unsigned long val) {} 1127 #endif 1128 1129 static void print_msr_bits(unsigned long val) 1130 { 1131 printk("<"); 1132 print_bits(val, msr_bits, ","); 1133 print_tm_bits(val); 1134 printk(">"); 1135 } 1136 1137 #ifdef CONFIG_PPC64 1138 #define REG "%016lx" 1139 #define REGS_PER_LINE 4 1140 #define LAST_VOLATILE 13 1141 #else 1142 #define REG "%08lx" 1143 #define REGS_PER_LINE 8 1144 #define LAST_VOLATILE 12 1145 #endif 1146 1147 void show_regs(struct pt_regs * regs) 1148 { 1149 int i, trap; 1150 1151 show_regs_print_info(KERN_DEFAULT); 1152 1153 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 1154 regs->nip, regs->link, regs->ctr); 1155 printk("REGS: %p TRAP: %04lx %s (%s)\n", 1156 regs, regs->trap, print_tainted(), init_utsname()->release); 1157 printk("MSR: "REG" ", regs->msr); 1158 print_msr_bits(regs->msr); 1159 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 1160 trap = TRAP(regs); 1161 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 1162 printk("CFAR: "REG" ", regs->orig_gpr3); 1163 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1164 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 1165 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 1166 #else 1167 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 1168 #endif 1169 #ifdef CONFIG_PPC64 1170 printk("SOFTE: %ld ", regs->softe); 1171 #endif 1172 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1173 if (MSR_TM_ACTIVE(regs->msr)) 1174 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 1175 #endif 1176 1177 for (i = 0; i < 32; i++) { 1178 if ((i % REGS_PER_LINE) == 0) 1179 printk("\nGPR%02d: ", i); 1180 printk(REG " ", regs->gpr[i]); 1181 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 1182 break; 1183 } 1184 printk("\n"); 1185 #ifdef CONFIG_KALLSYMS 1186 /* 1187 * Lookup NIP late so we have the best change of getting the 1188 * above info out without failing 1189 */ 1190 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1191 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 1192 #endif 1193 show_stack(current, (unsigned long *) regs->gpr[1]); 1194 if (!user_mode(regs)) 1195 show_instructions(regs); 1196 } 1197 1198 void exit_thread(void) 1199 { 1200 } 1201 1202 void flush_thread(void) 1203 { 1204 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1205 flush_ptrace_hw_breakpoint(current); 1206 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 1207 set_debug_reg_defaults(¤t->thread); 1208 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1209 } 1210 1211 void 1212 release_thread(struct task_struct *t) 1213 { 1214 } 1215 1216 /* 1217 * this gets called so that we can store coprocessor state into memory and 1218 * copy the current task into the new thread. 1219 */ 1220 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 1221 { 1222 flush_all_to_thread(src); 1223 /* 1224 * Flush TM state out so we can copy it. __switch_to_tm() does this 1225 * flush but it removes the checkpointed state from the current CPU and 1226 * transitions the CPU out of TM mode. Hence we need to call 1227 * tm_recheckpoint_new_task() (on the same task) to restore the 1228 * checkpointed state back and the TM mode. 1229 */ 1230 __switch_to_tm(src); 1231 tm_recheckpoint_new_task(src); 1232 1233 *dst = *src; 1234 1235 clear_task_ebb(dst); 1236 1237 return 0; 1238 } 1239 1240 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1241 { 1242 #ifdef CONFIG_PPC_STD_MMU_64 1243 unsigned long sp_vsid; 1244 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1245 1246 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1247 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1248 << SLB_VSID_SHIFT_1T; 1249 else 1250 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1251 << SLB_VSID_SHIFT; 1252 sp_vsid |= SLB_VSID_KERNEL | llp; 1253 p->thread.ksp_vsid = sp_vsid; 1254 #endif 1255 } 1256 1257 /* 1258 * Copy a thread.. 1259 */ 1260 1261 /* 1262 * Copy architecture-specific thread state 1263 */ 1264 int copy_thread(unsigned long clone_flags, unsigned long usp, 1265 unsigned long kthread_arg, struct task_struct *p) 1266 { 1267 struct pt_regs *childregs, *kregs; 1268 extern void ret_from_fork(void); 1269 extern void ret_from_kernel_thread(void); 1270 void (*f)(void); 1271 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 1272 struct thread_info *ti = task_thread_info(p); 1273 1274 klp_init_thread_info(ti); 1275 1276 /* Copy registers */ 1277 sp -= sizeof(struct pt_regs); 1278 childregs = (struct pt_regs *) sp; 1279 if (unlikely(p->flags & PF_KTHREAD)) { 1280 /* kernel thread */ 1281 memset(childregs, 0, sizeof(struct pt_regs)); 1282 childregs->gpr[1] = sp + sizeof(struct pt_regs); 1283 /* function */ 1284 if (usp) 1285 childregs->gpr[14] = ppc_function_entry((void *)usp); 1286 #ifdef CONFIG_PPC64 1287 clear_tsk_thread_flag(p, TIF_32BIT); 1288 childregs->softe = 1; 1289 #endif 1290 childregs->gpr[15] = kthread_arg; 1291 p->thread.regs = NULL; /* no user register state */ 1292 ti->flags |= _TIF_RESTOREALL; 1293 f = ret_from_kernel_thread; 1294 } else { 1295 /* user thread */ 1296 struct pt_regs *regs = current_pt_regs(); 1297 CHECK_FULL_REGS(regs); 1298 *childregs = *regs; 1299 if (usp) 1300 childregs->gpr[1] = usp; 1301 p->thread.regs = childregs; 1302 childregs->gpr[3] = 0; /* Result from fork() */ 1303 if (clone_flags & CLONE_SETTLS) { 1304 #ifdef CONFIG_PPC64 1305 if (!is_32bit_task()) 1306 childregs->gpr[13] = childregs->gpr[6]; 1307 else 1308 #endif 1309 childregs->gpr[2] = childregs->gpr[6]; 1310 } 1311 1312 f = ret_from_fork; 1313 } 1314 sp -= STACK_FRAME_OVERHEAD; 1315 1316 /* 1317 * The way this works is that at some point in the future 1318 * some task will call _switch to switch to the new task. 1319 * That will pop off the stack frame created below and start 1320 * the new task running at ret_from_fork. The new task will 1321 * do some house keeping and then return from the fork or clone 1322 * system call, using the stack frame created above. 1323 */ 1324 ((unsigned long *)sp)[0] = 0; 1325 sp -= sizeof(struct pt_regs); 1326 kregs = (struct pt_regs *) sp; 1327 sp -= STACK_FRAME_OVERHEAD; 1328 p->thread.ksp = sp; 1329 #ifdef CONFIG_PPC32 1330 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 1331 _ALIGN_UP(sizeof(struct thread_info), 16); 1332 #endif 1333 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1334 p->thread.ptrace_bps[0] = NULL; 1335 #endif 1336 1337 p->thread.fp_save_area = NULL; 1338 #ifdef CONFIG_ALTIVEC 1339 p->thread.vr_save_area = NULL; 1340 #endif 1341 1342 setup_ksp_vsid(p, sp); 1343 1344 #ifdef CONFIG_PPC64 1345 if (cpu_has_feature(CPU_FTR_DSCR)) { 1346 p->thread.dscr_inherit = current->thread.dscr_inherit; 1347 p->thread.dscr = mfspr(SPRN_DSCR); 1348 } 1349 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1350 p->thread.ppr = INIT_PPR; 1351 #endif 1352 kregs->nip = ppc_function_entry(f); 1353 return 0; 1354 } 1355 1356 /* 1357 * Set up a thread for executing a new program 1358 */ 1359 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1360 { 1361 #ifdef CONFIG_PPC64 1362 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1363 #endif 1364 1365 /* 1366 * If we exec out of a kernel thread then thread.regs will not be 1367 * set. Do it now. 1368 */ 1369 if (!current->thread.regs) { 1370 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1371 current->thread.regs = regs - 1; 1372 } 1373 1374 memset(regs->gpr, 0, sizeof(regs->gpr)); 1375 regs->ctr = 0; 1376 regs->link = 0; 1377 regs->xer = 0; 1378 regs->ccr = 0; 1379 regs->gpr[1] = sp; 1380 1381 /* 1382 * We have just cleared all the nonvolatile GPRs, so make 1383 * FULL_REGS(regs) return true. This is necessary to allow 1384 * ptrace to examine the thread immediately after exec. 1385 */ 1386 regs->trap &= ~1UL; 1387 1388 #ifdef CONFIG_PPC32 1389 regs->mq = 0; 1390 regs->nip = start; 1391 regs->msr = MSR_USER; 1392 #else 1393 if (!is_32bit_task()) { 1394 unsigned long entry; 1395 1396 if (is_elf2_task()) { 1397 /* Look ma, no function descriptors! */ 1398 entry = start; 1399 1400 /* 1401 * Ulrich says: 1402 * The latest iteration of the ABI requires that when 1403 * calling a function (at its global entry point), 1404 * the caller must ensure r12 holds the entry point 1405 * address (so that the function can quickly 1406 * establish addressability). 1407 */ 1408 regs->gpr[12] = start; 1409 /* Make sure that's restored on entry to userspace. */ 1410 set_thread_flag(TIF_RESTOREALL); 1411 } else { 1412 unsigned long toc; 1413 1414 /* start is a relocated pointer to the function 1415 * descriptor for the elf _start routine. The first 1416 * entry in the function descriptor is the entry 1417 * address of _start and the second entry is the TOC 1418 * value we need to use. 1419 */ 1420 __get_user(entry, (unsigned long __user *)start); 1421 __get_user(toc, (unsigned long __user *)start+1); 1422 1423 /* Check whether the e_entry function descriptor entries 1424 * need to be relocated before we can use them. 1425 */ 1426 if (load_addr != 0) { 1427 entry += load_addr; 1428 toc += load_addr; 1429 } 1430 regs->gpr[2] = toc; 1431 } 1432 regs->nip = entry; 1433 regs->msr = MSR_USER64; 1434 } else { 1435 regs->nip = start; 1436 regs->gpr[2] = 0; 1437 regs->msr = MSR_USER32; 1438 } 1439 #endif 1440 #ifdef CONFIG_VSX 1441 current->thread.used_vsr = 0; 1442 #endif 1443 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1444 current->thread.fp_save_area = NULL; 1445 #ifdef CONFIG_ALTIVEC 1446 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1447 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1448 current->thread.vr_save_area = NULL; 1449 current->thread.vrsave = 0; 1450 current->thread.used_vr = 0; 1451 #endif /* CONFIG_ALTIVEC */ 1452 #ifdef CONFIG_SPE 1453 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1454 current->thread.acc = 0; 1455 current->thread.spefscr = 0; 1456 current->thread.used_spe = 0; 1457 #endif /* CONFIG_SPE */ 1458 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1459 if (cpu_has_feature(CPU_FTR_TM)) 1460 regs->msr |= MSR_TM; 1461 current->thread.tm_tfhar = 0; 1462 current->thread.tm_texasr = 0; 1463 current->thread.tm_tfiar = 0; 1464 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1465 } 1466 EXPORT_SYMBOL(start_thread); 1467 1468 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1469 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1470 1471 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1472 { 1473 struct pt_regs *regs = tsk->thread.regs; 1474 1475 /* This is a bit hairy. If we are an SPE enabled processor 1476 * (have embedded fp) we store the IEEE exception enable flags in 1477 * fpexc_mode. fpexc_mode is also used for setting FP exception 1478 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1479 if (val & PR_FP_EXC_SW_ENABLE) { 1480 #ifdef CONFIG_SPE 1481 if (cpu_has_feature(CPU_FTR_SPE)) { 1482 /* 1483 * When the sticky exception bits are set 1484 * directly by userspace, it must call prctl 1485 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1486 * in the existing prctl settings) or 1487 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1488 * the bits being set). <fenv.h> functions 1489 * saving and restoring the whole 1490 * floating-point environment need to do so 1491 * anyway to restore the prctl settings from 1492 * the saved environment. 1493 */ 1494 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1495 tsk->thread.fpexc_mode = val & 1496 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1497 return 0; 1498 } else { 1499 return -EINVAL; 1500 } 1501 #else 1502 return -EINVAL; 1503 #endif 1504 } 1505 1506 /* on a CONFIG_SPE this does not hurt us. The bits that 1507 * __pack_fe01 use do not overlap with bits used for 1508 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1509 * on CONFIG_SPE implementations are reserved so writing to 1510 * them does not change anything */ 1511 if (val > PR_FP_EXC_PRECISE) 1512 return -EINVAL; 1513 tsk->thread.fpexc_mode = __pack_fe01(val); 1514 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1515 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1516 | tsk->thread.fpexc_mode; 1517 return 0; 1518 } 1519 1520 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1521 { 1522 unsigned int val; 1523 1524 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1525 #ifdef CONFIG_SPE 1526 if (cpu_has_feature(CPU_FTR_SPE)) { 1527 /* 1528 * When the sticky exception bits are set 1529 * directly by userspace, it must call prctl 1530 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1531 * in the existing prctl settings) or 1532 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1533 * the bits being set). <fenv.h> functions 1534 * saving and restoring the whole 1535 * floating-point environment need to do so 1536 * anyway to restore the prctl settings from 1537 * the saved environment. 1538 */ 1539 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1540 val = tsk->thread.fpexc_mode; 1541 } else 1542 return -EINVAL; 1543 #else 1544 return -EINVAL; 1545 #endif 1546 else 1547 val = __unpack_fe01(tsk->thread.fpexc_mode); 1548 return put_user(val, (unsigned int __user *) adr); 1549 } 1550 1551 int set_endian(struct task_struct *tsk, unsigned int val) 1552 { 1553 struct pt_regs *regs = tsk->thread.regs; 1554 1555 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1556 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1557 return -EINVAL; 1558 1559 if (regs == NULL) 1560 return -EINVAL; 1561 1562 if (val == PR_ENDIAN_BIG) 1563 regs->msr &= ~MSR_LE; 1564 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1565 regs->msr |= MSR_LE; 1566 else 1567 return -EINVAL; 1568 1569 return 0; 1570 } 1571 1572 int get_endian(struct task_struct *tsk, unsigned long adr) 1573 { 1574 struct pt_regs *regs = tsk->thread.regs; 1575 unsigned int val; 1576 1577 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1578 !cpu_has_feature(CPU_FTR_REAL_LE)) 1579 return -EINVAL; 1580 1581 if (regs == NULL) 1582 return -EINVAL; 1583 1584 if (regs->msr & MSR_LE) { 1585 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1586 val = PR_ENDIAN_LITTLE; 1587 else 1588 val = PR_ENDIAN_PPC_LITTLE; 1589 } else 1590 val = PR_ENDIAN_BIG; 1591 1592 return put_user(val, (unsigned int __user *)adr); 1593 } 1594 1595 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1596 { 1597 tsk->thread.align_ctl = val; 1598 return 0; 1599 } 1600 1601 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1602 { 1603 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1604 } 1605 1606 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1607 unsigned long nbytes) 1608 { 1609 unsigned long stack_page; 1610 unsigned long cpu = task_cpu(p); 1611 1612 /* 1613 * Avoid crashing if the stack has overflowed and corrupted 1614 * task_cpu(p), which is in the thread_info struct. 1615 */ 1616 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1617 stack_page = (unsigned long) hardirq_ctx[cpu]; 1618 if (sp >= stack_page + sizeof(struct thread_struct) 1619 && sp <= stack_page + THREAD_SIZE - nbytes) 1620 return 1; 1621 1622 stack_page = (unsigned long) softirq_ctx[cpu]; 1623 if (sp >= stack_page + sizeof(struct thread_struct) 1624 && sp <= stack_page + THREAD_SIZE - nbytes) 1625 return 1; 1626 } 1627 return 0; 1628 } 1629 1630 int validate_sp(unsigned long sp, struct task_struct *p, 1631 unsigned long nbytes) 1632 { 1633 unsigned long stack_page = (unsigned long)task_stack_page(p); 1634 1635 if (sp >= stack_page + sizeof(struct thread_struct) 1636 && sp <= stack_page + THREAD_SIZE - nbytes) 1637 return 1; 1638 1639 return valid_irq_stack(sp, p, nbytes); 1640 } 1641 1642 EXPORT_SYMBOL(validate_sp); 1643 1644 unsigned long get_wchan(struct task_struct *p) 1645 { 1646 unsigned long ip, sp; 1647 int count = 0; 1648 1649 if (!p || p == current || p->state == TASK_RUNNING) 1650 return 0; 1651 1652 sp = p->thread.ksp; 1653 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1654 return 0; 1655 1656 do { 1657 sp = *(unsigned long *)sp; 1658 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1659 return 0; 1660 if (count > 0) { 1661 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 1662 if (!in_sched_functions(ip)) 1663 return ip; 1664 } 1665 } while (count++ < 16); 1666 return 0; 1667 } 1668 1669 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 1670 1671 void show_stack(struct task_struct *tsk, unsigned long *stack) 1672 { 1673 unsigned long sp, ip, lr, newsp; 1674 int count = 0; 1675 int firstframe = 1; 1676 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1677 int curr_frame = current->curr_ret_stack; 1678 extern void return_to_handler(void); 1679 unsigned long rth = (unsigned long)return_to_handler; 1680 #endif 1681 1682 sp = (unsigned long) stack; 1683 if (tsk == NULL) 1684 tsk = current; 1685 if (sp == 0) { 1686 if (tsk == current) 1687 sp = current_stack_pointer(); 1688 else 1689 sp = tsk->thread.ksp; 1690 } 1691 1692 lr = 0; 1693 printk("Call Trace:\n"); 1694 do { 1695 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 1696 return; 1697 1698 stack = (unsigned long *) sp; 1699 newsp = stack[0]; 1700 ip = stack[STACK_FRAME_LR_SAVE]; 1701 if (!firstframe || ip != lr) { 1702 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 1703 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1704 if ((ip == rth) && curr_frame >= 0) { 1705 printk(" (%pS)", 1706 (void *)current->ret_stack[curr_frame].ret); 1707 curr_frame--; 1708 } 1709 #endif 1710 if (firstframe) 1711 printk(" (unreliable)"); 1712 printk("\n"); 1713 } 1714 firstframe = 0; 1715 1716 /* 1717 * See if this is an exception frame. 1718 * We look for the "regshere" marker in the current frame. 1719 */ 1720 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1721 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 1722 struct pt_regs *regs = (struct pt_regs *) 1723 (sp + STACK_FRAME_OVERHEAD); 1724 lr = regs->link; 1725 printk("--- interrupt: %lx at %pS\n LR = %pS\n", 1726 regs->trap, (void *)regs->nip, (void *)lr); 1727 firstframe = 1; 1728 } 1729 1730 sp = newsp; 1731 } while (count++ < kstack_depth_to_print); 1732 } 1733 1734 #ifdef CONFIG_PPC64 1735 /* Called with hard IRQs off */ 1736 void notrace __ppc64_runlatch_on(void) 1737 { 1738 struct thread_info *ti = current_thread_info(); 1739 unsigned long ctrl; 1740 1741 ctrl = mfspr(SPRN_CTRLF); 1742 ctrl |= CTRL_RUNLATCH; 1743 mtspr(SPRN_CTRLT, ctrl); 1744 1745 ti->local_flags |= _TLF_RUNLATCH; 1746 } 1747 1748 /* Called with hard IRQs off */ 1749 void notrace __ppc64_runlatch_off(void) 1750 { 1751 struct thread_info *ti = current_thread_info(); 1752 unsigned long ctrl; 1753 1754 ti->local_flags &= ~_TLF_RUNLATCH; 1755 1756 ctrl = mfspr(SPRN_CTRLF); 1757 ctrl &= ~CTRL_RUNLATCH; 1758 mtspr(SPRN_CTRLT, ctrl); 1759 } 1760 #endif /* CONFIG_PPC64 */ 1761 1762 unsigned long arch_align_stack(unsigned long sp) 1763 { 1764 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1765 sp -= get_random_int() & ~PAGE_MASK; 1766 return sp & ~0xf; 1767 } 1768 1769 static inline unsigned long brk_rnd(void) 1770 { 1771 unsigned long rnd = 0; 1772 1773 /* 8MB for 32bit, 1GB for 64bit */ 1774 if (is_32bit_task()) 1775 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 1776 else 1777 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 1778 1779 return rnd << PAGE_SHIFT; 1780 } 1781 1782 unsigned long arch_randomize_brk(struct mm_struct *mm) 1783 { 1784 unsigned long base = mm->brk; 1785 unsigned long ret; 1786 1787 #ifdef CONFIG_PPC_STD_MMU_64 1788 /* 1789 * If we are using 1TB segments and we are allowed to randomise 1790 * the heap, we can put it above 1TB so it is backed by a 1TB 1791 * segment. Otherwise the heap will be in the bottom 1TB 1792 * which always uses 256MB segments and this may result in a 1793 * performance penalty. 1794 */ 1795 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 1796 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 1797 #endif 1798 1799 ret = PAGE_ALIGN(base + brk_rnd()); 1800 1801 if (ret < mm->brk) 1802 return mm->brk; 1803 1804 return ret; 1805 } 1806 1807