114cf11afSPaul Mackerras /* 214cf11afSPaul Mackerras * Derived from "arch/i386/kernel/process.c" 314cf11afSPaul Mackerras * Copyright (C) 1995 Linus Torvalds 414cf11afSPaul Mackerras * 514cf11afSPaul Mackerras * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 614cf11afSPaul Mackerras * Paul Mackerras (paulus@cs.anu.edu.au) 714cf11afSPaul Mackerras * 814cf11afSPaul Mackerras * PowerPC version 914cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 1014cf11afSPaul Mackerras * 1114cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1214cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1314cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1414cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1514cf11afSPaul Mackerras */ 1614cf11afSPaul Mackerras 1714cf11afSPaul Mackerras #include <linux/errno.h> 1814cf11afSPaul Mackerras #include <linux/sched.h> 19b17b0153SIngo Molnar #include <linux/sched/debug.h> 2029930025SIngo Molnar #include <linux/sched/task.h> 2168db0cf1SIngo Molnar #include <linux/sched/task_stack.h> 2214cf11afSPaul Mackerras #include <linux/kernel.h> 2314cf11afSPaul Mackerras #include <linux/mm.h> 2414cf11afSPaul Mackerras #include <linux/smp.h> 2514cf11afSPaul Mackerras #include <linux/stddef.h> 2614cf11afSPaul Mackerras #include <linux/unistd.h> 2714cf11afSPaul Mackerras #include <linux/ptrace.h> 2814cf11afSPaul Mackerras #include <linux/slab.h> 2914cf11afSPaul Mackerras #include <linux/user.h> 3014cf11afSPaul Mackerras #include <linux/elf.h> 3114cf11afSPaul Mackerras #include <linux/prctl.h> 3214cf11afSPaul Mackerras #include <linux/init_task.h> 334b16f8e2SPaul Gortmaker #include <linux/export.h> 3414cf11afSPaul Mackerras #include <linux/kallsyms.h> 3514cf11afSPaul Mackerras #include <linux/mqueue.h> 3614cf11afSPaul Mackerras #include <linux/hardirq.h> 3706d67d54SPaul Mackerras #include <linux/utsname.h> 386794c782SSteven Rostedt #include <linux/ftrace.h> 3979741dd3SMartin Schwidefsky #include <linux/kernel_stat.h> 40d839088cSAnton Blanchard #include <linux/personality.h> 41d839088cSAnton Blanchard #include <linux/random.h> 425aae8a53SK.Prasad #include <linux/hw_breakpoint.h> 437b051f66SAnton Blanchard #include <linux/uaccess.h> 447f92bc56SDaniel Axtens #include <linux/elf-randomize.h> 4514cf11afSPaul Mackerras 4614cf11afSPaul Mackerras #include <asm/pgtable.h> 4714cf11afSPaul Mackerras #include <asm/io.h> 4814cf11afSPaul Mackerras #include <asm/processor.h> 4914cf11afSPaul Mackerras #include <asm/mmu.h> 5014cf11afSPaul Mackerras #include <asm/prom.h> 5176032de8SMichael Ellerman #include <asm/machdep.h> 52c6622f63SPaul Mackerras #include <asm/time.h> 53ae3a197eSDavid Howells #include <asm/runlatch.h> 54a7f31841SArnd Bergmann #include <asm/syscalls.h> 55ae3a197eSDavid Howells #include <asm/switch_to.h> 56fb09692eSMichael Neuling #include <asm/tm.h> 57ae3a197eSDavid Howells #include <asm/debug.h> 5806d67d54SPaul Mackerras #ifdef CONFIG_PPC64 5906d67d54SPaul Mackerras #include <asm/firmware.h> 6006d67d54SPaul Mackerras #endif 617cedd601SAnton Blanchard #include <asm/code-patching.h> 627f92bc56SDaniel Axtens #include <asm/exec.h> 635d31a96eSMichael Ellerman #include <asm/livepatch.h> 64b92a226eSKevin Hao #include <asm/cpu_has_feature.h> 650545d543SDaniel Axtens #include <asm/asm-prototypes.h> 665d31a96eSMichael Ellerman 67d6a61bfcSLuis Machado #include <linux/kprobes.h> 68d6a61bfcSLuis Machado #include <linux/kdebug.h> 6914cf11afSPaul Mackerras 708b3c34cfSMichael Neuling /* Transactional Memory debug */ 718b3c34cfSMichael Neuling #ifdef TM_DEBUG_SW 728b3c34cfSMichael Neuling #define TM_DEBUG(x...) printk(KERN_INFO x) 738b3c34cfSMichael Neuling #else 748b3c34cfSMichael Neuling #define TM_DEBUG(x...) do { } while(0) 758b3c34cfSMichael Neuling #endif 768b3c34cfSMichael Neuling 7714cf11afSPaul Mackerras extern unsigned long _get_SP(void); 7814cf11afSPaul Mackerras 79d31626f7SPaul Mackerras #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 80b86fd2bdSAnton Blanchard static void check_if_tm_restore_required(struct task_struct *tsk) 81d31626f7SPaul Mackerras { 82d31626f7SPaul Mackerras /* 83d31626f7SPaul Mackerras * If we are saving the current thread's registers, and the 84d31626f7SPaul Mackerras * thread is in a transactional state, set the TIF_RESTORE_TM 85d31626f7SPaul Mackerras * bit so that we know to restore the registers before 86d31626f7SPaul Mackerras * returning to userspace. 87d31626f7SPaul Mackerras */ 88d31626f7SPaul Mackerras if (tsk == current && tsk->thread.regs && 89d31626f7SPaul Mackerras MSR_TM_ACTIVE(tsk->thread.regs->msr) && 90d31626f7SPaul Mackerras !test_thread_flag(TIF_RESTORE_TM)) { 91829023dfSAnshuman Khandual tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 92d31626f7SPaul Mackerras set_thread_flag(TIF_RESTORE_TM); 93d31626f7SPaul Mackerras } 94d31626f7SPaul Mackerras } 95dc16b553SCyril Bur 96dc16b553SCyril Bur static inline bool msr_tm_active(unsigned long msr) 97dc16b553SCyril Bur { 98dc16b553SCyril Bur return MSR_TM_ACTIVE(msr); 99dc16b553SCyril Bur } 100d31626f7SPaul Mackerras #else 101dc16b553SCyril Bur static inline bool msr_tm_active(unsigned long msr) { return false; } 102b86fd2bdSAnton Blanchard static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 103d31626f7SPaul Mackerras #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 104d31626f7SPaul Mackerras 1053eb5d588SAnton Blanchard bool strict_msr_control; 1063eb5d588SAnton Blanchard EXPORT_SYMBOL(strict_msr_control); 1073eb5d588SAnton Blanchard 1083eb5d588SAnton Blanchard static int __init enable_strict_msr_control(char *str) 1093eb5d588SAnton Blanchard { 1103eb5d588SAnton Blanchard strict_msr_control = true; 1113eb5d588SAnton Blanchard pr_info("Enabling strict facility control\n"); 1123eb5d588SAnton Blanchard 1133eb5d588SAnton Blanchard return 0; 1143eb5d588SAnton Blanchard } 1153eb5d588SAnton Blanchard early_param("ppc_strict_facility_enable", enable_strict_msr_control); 1163eb5d588SAnton Blanchard 1173cee070aSCyril Bur unsigned long msr_check_and_set(unsigned long bits) 118a0e72cf1SAnton Blanchard { 119a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 120a0e72cf1SAnton Blanchard unsigned long newmsr; 121a0e72cf1SAnton Blanchard 122a0e72cf1SAnton Blanchard newmsr = oldmsr | bits; 123a0e72cf1SAnton Blanchard 124a0e72cf1SAnton Blanchard #ifdef CONFIG_VSX 125a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 126a0e72cf1SAnton Blanchard newmsr |= MSR_VSX; 127a0e72cf1SAnton Blanchard #endif 128a0e72cf1SAnton Blanchard 129a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 130a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 1313cee070aSCyril Bur 1323cee070aSCyril Bur return newmsr; 133a0e72cf1SAnton Blanchard } 134a0e72cf1SAnton Blanchard 1353eb5d588SAnton Blanchard void __msr_check_and_clear(unsigned long bits) 136a0e72cf1SAnton Blanchard { 137a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 138a0e72cf1SAnton Blanchard unsigned long newmsr; 139a0e72cf1SAnton Blanchard 140a0e72cf1SAnton Blanchard newmsr = oldmsr & ~bits; 141a0e72cf1SAnton Blanchard 142a0e72cf1SAnton Blanchard #ifdef CONFIG_VSX 143a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 144a0e72cf1SAnton Blanchard newmsr &= ~MSR_VSX; 145a0e72cf1SAnton Blanchard #endif 146a0e72cf1SAnton Blanchard 147a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 148a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 149a0e72cf1SAnton Blanchard } 1503eb5d588SAnton Blanchard EXPORT_SYMBOL(__msr_check_and_clear); 151a0e72cf1SAnton Blanchard 152037f0eedSKevin Hao #ifdef CONFIG_PPC_FPU 1538792468dSCyril Bur void __giveup_fpu(struct task_struct *tsk) 1548792468dSCyril Bur { 1558eb98037SAnton Blanchard unsigned long msr; 1568eb98037SAnton Blanchard 1578792468dSCyril Bur save_fpu(tsk); 1588eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 1598eb98037SAnton Blanchard msr &= ~MSR_FP; 1608792468dSCyril Bur #ifdef CONFIG_VSX 1618792468dSCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 1628eb98037SAnton Blanchard msr &= ~MSR_VSX; 1638792468dSCyril Bur #endif 1648eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 1658792468dSCyril Bur } 1668792468dSCyril Bur 16798da581eSAnton Blanchard void giveup_fpu(struct task_struct *tsk) 16898da581eSAnton Blanchard { 16998da581eSAnton Blanchard check_if_tm_restore_required(tsk); 17098da581eSAnton Blanchard 171a0e72cf1SAnton Blanchard msr_check_and_set(MSR_FP); 17298da581eSAnton Blanchard __giveup_fpu(tsk); 173a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP); 17498da581eSAnton Blanchard } 17598da581eSAnton Blanchard EXPORT_SYMBOL(giveup_fpu); 17698da581eSAnton Blanchard 17714cf11afSPaul Mackerras /* 17814cf11afSPaul Mackerras * Make sure the floating-point register state in the 17914cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 18014cf11afSPaul Mackerras */ 18114cf11afSPaul Mackerras void flush_fp_to_thread(struct task_struct *tsk) 18214cf11afSPaul Mackerras { 18314cf11afSPaul Mackerras if (tsk->thread.regs) { 18414cf11afSPaul Mackerras /* 18514cf11afSPaul Mackerras * We need to disable preemption here because if we didn't, 18614cf11afSPaul Mackerras * another process could get scheduled after the regs->msr 18714cf11afSPaul Mackerras * test but before we have finished saving the FP registers 18814cf11afSPaul Mackerras * to the thread_struct. That process could take over the 18914cf11afSPaul Mackerras * FPU, and then when we get scheduled again we would store 19014cf11afSPaul Mackerras * bogus values for the remaining FP registers. 19114cf11afSPaul Mackerras */ 19214cf11afSPaul Mackerras preempt_disable(); 19314cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_FP) { 19414cf11afSPaul Mackerras /* 19514cf11afSPaul Mackerras * This should only ever be called for current or 19614cf11afSPaul Mackerras * for a stopped child process. Since we save away 197af1bbc3dSAnton Blanchard * the FP register state on context switch, 19814cf11afSPaul Mackerras * there is something wrong if a stopped child appears 19914cf11afSPaul Mackerras * to still have its FP state in the CPU registers. 20014cf11afSPaul Mackerras */ 20114cf11afSPaul Mackerras BUG_ON(tsk != current); 202b86fd2bdSAnton Blanchard giveup_fpu(tsk); 20314cf11afSPaul Mackerras } 20414cf11afSPaul Mackerras preempt_enable(); 20514cf11afSPaul Mackerras } 20614cf11afSPaul Mackerras } 207de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_fp_to_thread); 20814cf11afSPaul Mackerras 20914cf11afSPaul Mackerras void enable_kernel_fp(void) 21014cf11afSPaul Mackerras { 211e909fb83SCyril Bur unsigned long cpumsr; 212e909fb83SCyril Bur 21314cf11afSPaul Mackerras WARN_ON(preemptible()); 21414cf11afSPaul Mackerras 215e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP); 216611b0e5cSAnton Blanchard 217d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 218d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 219e909fb83SCyril Bur /* 220e909fb83SCyril Bur * If a thread has already been reclaimed then the 221e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 222e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 223e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 224e909fb83SCyril Bur * checkpointed structure. 225e909fb83SCyril Bur */ 226e909fb83SCyril Bur if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 227e909fb83SCyril Bur return; 228a0e72cf1SAnton Blanchard __giveup_fpu(current); 229b86fd2bdSAnton Blanchard } 230d64d02ceSAnton Blanchard } 23114cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_fp); 23270fe3d98SCyril Bur 2336a303833SBenjamin Herrenschmidt static int restore_fp(struct task_struct *tsk) 2346a303833SBenjamin Herrenschmidt { 235dc16b553SCyril Bur if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) { 23670fe3d98SCyril Bur load_fp_state(¤t->thread.fp_state); 23770fe3d98SCyril Bur current->thread.load_fp++; 23870fe3d98SCyril Bur return 1; 23970fe3d98SCyril Bur } 24070fe3d98SCyril Bur return 0; 24170fe3d98SCyril Bur } 24270fe3d98SCyril Bur #else 24370fe3d98SCyril Bur static int restore_fp(struct task_struct *tsk) { return 0; } 244d1e1cf2eSAnton Blanchard #endif /* CONFIG_PPC_FPU */ 24514cf11afSPaul Mackerras 24614cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 24770fe3d98SCyril Bur #define loadvec(thr) ((thr).load_vec) 24870fe3d98SCyril Bur 2496f515d84SCyril Bur static void __giveup_altivec(struct task_struct *tsk) 2506f515d84SCyril Bur { 2518eb98037SAnton Blanchard unsigned long msr; 2528eb98037SAnton Blanchard 2536f515d84SCyril Bur save_altivec(tsk); 2548eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 2558eb98037SAnton Blanchard msr &= ~MSR_VEC; 2566f515d84SCyril Bur #ifdef CONFIG_VSX 2576f515d84SCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 2588eb98037SAnton Blanchard msr &= ~MSR_VSX; 2596f515d84SCyril Bur #endif 2608eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 2616f515d84SCyril Bur } 2626f515d84SCyril Bur 26398da581eSAnton Blanchard void giveup_altivec(struct task_struct *tsk) 26498da581eSAnton Blanchard { 26598da581eSAnton Blanchard check_if_tm_restore_required(tsk); 26698da581eSAnton Blanchard 267a0e72cf1SAnton Blanchard msr_check_and_set(MSR_VEC); 26898da581eSAnton Blanchard __giveup_altivec(tsk); 269a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_VEC); 27098da581eSAnton Blanchard } 27198da581eSAnton Blanchard EXPORT_SYMBOL(giveup_altivec); 27298da581eSAnton Blanchard 27314cf11afSPaul Mackerras void enable_kernel_altivec(void) 27414cf11afSPaul Mackerras { 275e909fb83SCyril Bur unsigned long cpumsr; 276e909fb83SCyril Bur 27714cf11afSPaul Mackerras WARN_ON(preemptible()); 27814cf11afSPaul Mackerras 279e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_VEC); 280611b0e5cSAnton Blanchard 281d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 282d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 283e909fb83SCyril Bur /* 284e909fb83SCyril Bur * If a thread has already been reclaimed then the 285e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 286e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 287e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 288e909fb83SCyril Bur * checkpointed structure. 289e909fb83SCyril Bur */ 290e909fb83SCyril Bur if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 291e909fb83SCyril Bur return; 292a0e72cf1SAnton Blanchard __giveup_altivec(current); 293b86fd2bdSAnton Blanchard } 294d64d02ceSAnton Blanchard } 29514cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_altivec); 29614cf11afSPaul Mackerras 29714cf11afSPaul Mackerras /* 29814cf11afSPaul Mackerras * Make sure the VMX/Altivec register state in the 29914cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 30014cf11afSPaul Mackerras */ 30114cf11afSPaul Mackerras void flush_altivec_to_thread(struct task_struct *tsk) 30214cf11afSPaul Mackerras { 30314cf11afSPaul Mackerras if (tsk->thread.regs) { 30414cf11afSPaul Mackerras preempt_disable(); 30514cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_VEC) { 30614cf11afSPaul Mackerras BUG_ON(tsk != current); 307b86fd2bdSAnton Blanchard giveup_altivec(tsk); 30814cf11afSPaul Mackerras } 30914cf11afSPaul Mackerras preempt_enable(); 31014cf11afSPaul Mackerras } 31114cf11afSPaul Mackerras } 312de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 31370fe3d98SCyril Bur 31470fe3d98SCyril Bur static int restore_altivec(struct task_struct *tsk) 31570fe3d98SCyril Bur { 316dc16b553SCyril Bur if (cpu_has_feature(CPU_FTR_ALTIVEC) && 317dc16b553SCyril Bur (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) { 31870fe3d98SCyril Bur load_vr_state(&tsk->thread.vr_state); 31970fe3d98SCyril Bur tsk->thread.used_vr = 1; 32070fe3d98SCyril Bur tsk->thread.load_vec++; 32170fe3d98SCyril Bur 32270fe3d98SCyril Bur return 1; 32370fe3d98SCyril Bur } 32470fe3d98SCyril Bur return 0; 32570fe3d98SCyril Bur } 32670fe3d98SCyril Bur #else 32770fe3d98SCyril Bur #define loadvec(thr) 0 32870fe3d98SCyril Bur static inline int restore_altivec(struct task_struct *tsk) { return 0; } 32914cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 33014cf11afSPaul Mackerras 331ce48b210SMichael Neuling #ifdef CONFIG_VSX 332bf6a4d5bSCyril Bur static void __giveup_vsx(struct task_struct *tsk) 333a7d623d4SAnton Blanchard { 334*dc801081SBenjamin Herrenschmidt unsigned long msr = tsk->thread.regs->msr; 335*dc801081SBenjamin Herrenschmidt 336*dc801081SBenjamin Herrenschmidt /* 337*dc801081SBenjamin Herrenschmidt * We should never be ssetting MSR_VSX without also setting 338*dc801081SBenjamin Herrenschmidt * MSR_FP and MSR_VEC 339*dc801081SBenjamin Herrenschmidt */ 340*dc801081SBenjamin Herrenschmidt WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); 341*dc801081SBenjamin Herrenschmidt 342*dc801081SBenjamin Herrenschmidt /* __giveup_fpu will clear MSR_VSX */ 343*dc801081SBenjamin Herrenschmidt if (msr & MSR_FP) 344a7d623d4SAnton Blanchard __giveup_fpu(tsk); 345*dc801081SBenjamin Herrenschmidt if (msr & MSR_VEC) 346a7d623d4SAnton Blanchard __giveup_altivec(tsk); 347bf6a4d5bSCyril Bur } 348bf6a4d5bSCyril Bur 349bf6a4d5bSCyril Bur static void giveup_vsx(struct task_struct *tsk) 350bf6a4d5bSCyril Bur { 351bf6a4d5bSCyril Bur check_if_tm_restore_required(tsk); 352bf6a4d5bSCyril Bur 353bf6a4d5bSCyril Bur msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 354a7d623d4SAnton Blanchard __giveup_vsx(tsk); 355a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 356a7d623d4SAnton Blanchard } 357bf6a4d5bSCyril Bur 358bf6a4d5bSCyril Bur static void save_vsx(struct task_struct *tsk) 359bf6a4d5bSCyril Bur { 360bf6a4d5bSCyril Bur if (tsk->thread.regs->msr & MSR_FP) 361bf6a4d5bSCyril Bur save_fpu(tsk); 362bf6a4d5bSCyril Bur if (tsk->thread.regs->msr & MSR_VEC) 363bf6a4d5bSCyril Bur save_altivec(tsk); 364bf6a4d5bSCyril Bur } 365a7d623d4SAnton Blanchard 366ce48b210SMichael Neuling void enable_kernel_vsx(void) 367ce48b210SMichael Neuling { 368e909fb83SCyril Bur unsigned long cpumsr; 369e909fb83SCyril Bur 370ce48b210SMichael Neuling WARN_ON(preemptible()); 371ce48b210SMichael Neuling 372e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 373611b0e5cSAnton Blanchard 374a0e72cf1SAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) { 375d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 376e909fb83SCyril Bur /* 377e909fb83SCyril Bur * If a thread has already been reclaimed then the 378e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 379e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 380e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 381e909fb83SCyril Bur * checkpointed structure. 382e909fb83SCyril Bur */ 383e909fb83SCyril Bur if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 384e909fb83SCyril Bur return; 385a0e72cf1SAnton Blanchard __giveup_vsx(current); 386611b0e5cSAnton Blanchard } 387ce48b210SMichael Neuling } 388ce48b210SMichael Neuling EXPORT_SYMBOL(enable_kernel_vsx); 389ce48b210SMichael Neuling 390ce48b210SMichael Neuling void flush_vsx_to_thread(struct task_struct *tsk) 391ce48b210SMichael Neuling { 392ce48b210SMichael Neuling if (tsk->thread.regs) { 393ce48b210SMichael Neuling preempt_disable(); 394ce48b210SMichael Neuling if (tsk->thread.regs->msr & MSR_VSX) { 395ce48b210SMichael Neuling BUG_ON(tsk != current); 396ce48b210SMichael Neuling giveup_vsx(tsk); 397ce48b210SMichael Neuling } 398ce48b210SMichael Neuling preempt_enable(); 399ce48b210SMichael Neuling } 400ce48b210SMichael Neuling } 401de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 40270fe3d98SCyril Bur 40370fe3d98SCyril Bur static int restore_vsx(struct task_struct *tsk) 40470fe3d98SCyril Bur { 40570fe3d98SCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) { 40670fe3d98SCyril Bur tsk->thread.used_vsr = 1; 40770fe3d98SCyril Bur return 1; 40870fe3d98SCyril Bur } 40970fe3d98SCyril Bur 41070fe3d98SCyril Bur return 0; 41170fe3d98SCyril Bur } 41270fe3d98SCyril Bur #else 41370fe3d98SCyril Bur static inline int restore_vsx(struct task_struct *tsk) { return 0; } 414bf6a4d5bSCyril Bur static inline void save_vsx(struct task_struct *tsk) { } 415ce48b210SMichael Neuling #endif /* CONFIG_VSX */ 416ce48b210SMichael Neuling 41714cf11afSPaul Mackerras #ifdef CONFIG_SPE 41898da581eSAnton Blanchard void giveup_spe(struct task_struct *tsk) 41998da581eSAnton Blanchard { 42098da581eSAnton Blanchard check_if_tm_restore_required(tsk); 42198da581eSAnton Blanchard 422a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 42398da581eSAnton Blanchard __giveup_spe(tsk); 424a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_SPE); 42598da581eSAnton Blanchard } 42698da581eSAnton Blanchard EXPORT_SYMBOL(giveup_spe); 42714cf11afSPaul Mackerras 42814cf11afSPaul Mackerras void enable_kernel_spe(void) 42914cf11afSPaul Mackerras { 43014cf11afSPaul Mackerras WARN_ON(preemptible()); 43114cf11afSPaul Mackerras 432a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 433611b0e5cSAnton Blanchard 434d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 435d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 436a0e72cf1SAnton Blanchard __giveup_spe(current); 43714cf11afSPaul Mackerras } 438d64d02ceSAnton Blanchard } 43914cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_spe); 44014cf11afSPaul Mackerras 44114cf11afSPaul Mackerras void flush_spe_to_thread(struct task_struct *tsk) 44214cf11afSPaul Mackerras { 44314cf11afSPaul Mackerras if (tsk->thread.regs) { 44414cf11afSPaul Mackerras preempt_disable(); 44514cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_SPE) { 44614cf11afSPaul Mackerras BUG_ON(tsk != current); 447685659eeSyu liu tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 4480ee6c15eSKumar Gala giveup_spe(tsk); 44914cf11afSPaul Mackerras } 45014cf11afSPaul Mackerras preempt_enable(); 45114cf11afSPaul Mackerras } 45214cf11afSPaul Mackerras } 45314cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 45414cf11afSPaul Mackerras 455c2085059SAnton Blanchard static unsigned long msr_all_available; 456c2085059SAnton Blanchard 457c2085059SAnton Blanchard static int __init init_msr_all_available(void) 458c2085059SAnton Blanchard { 459c2085059SAnton Blanchard #ifdef CONFIG_PPC_FPU 460c2085059SAnton Blanchard msr_all_available |= MSR_FP; 461c2085059SAnton Blanchard #endif 462c2085059SAnton Blanchard #ifdef CONFIG_ALTIVEC 463c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC)) 464c2085059SAnton Blanchard msr_all_available |= MSR_VEC; 465c2085059SAnton Blanchard #endif 466c2085059SAnton Blanchard #ifdef CONFIG_VSX 467c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX)) 468c2085059SAnton Blanchard msr_all_available |= MSR_VSX; 469c2085059SAnton Blanchard #endif 470c2085059SAnton Blanchard #ifdef CONFIG_SPE 471c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_SPE)) 472c2085059SAnton Blanchard msr_all_available |= MSR_SPE; 473c2085059SAnton Blanchard #endif 474c2085059SAnton Blanchard 475c2085059SAnton Blanchard return 0; 476c2085059SAnton Blanchard } 477c2085059SAnton Blanchard early_initcall(init_msr_all_available); 478c2085059SAnton Blanchard 479c2085059SAnton Blanchard void giveup_all(struct task_struct *tsk) 480c2085059SAnton Blanchard { 481c2085059SAnton Blanchard unsigned long usermsr; 482c2085059SAnton Blanchard 483c2085059SAnton Blanchard if (!tsk->thread.regs) 484c2085059SAnton Blanchard return; 485c2085059SAnton Blanchard 486c2085059SAnton Blanchard usermsr = tsk->thread.regs->msr; 487c2085059SAnton Blanchard 488c2085059SAnton Blanchard if ((usermsr & msr_all_available) == 0) 489c2085059SAnton Blanchard return; 490c2085059SAnton Blanchard 491c2085059SAnton Blanchard msr_check_and_set(msr_all_available); 492b0f16b46SCyril Bur check_if_tm_restore_required(tsk); 493c2085059SAnton Blanchard 494c2085059SAnton Blanchard #ifdef CONFIG_PPC_FPU 495c2085059SAnton Blanchard if (usermsr & MSR_FP) 496c2085059SAnton Blanchard __giveup_fpu(tsk); 497c2085059SAnton Blanchard #endif 498c2085059SAnton Blanchard #ifdef CONFIG_ALTIVEC 499c2085059SAnton Blanchard if (usermsr & MSR_VEC) 500c2085059SAnton Blanchard __giveup_altivec(tsk); 501c2085059SAnton Blanchard #endif 502c2085059SAnton Blanchard #ifdef CONFIG_VSX 503c2085059SAnton Blanchard if (usermsr & MSR_VSX) 504c2085059SAnton Blanchard __giveup_vsx(tsk); 505c2085059SAnton Blanchard #endif 506c2085059SAnton Blanchard #ifdef CONFIG_SPE 507c2085059SAnton Blanchard if (usermsr & MSR_SPE) 508c2085059SAnton Blanchard __giveup_spe(tsk); 509c2085059SAnton Blanchard #endif 510c2085059SAnton Blanchard 511c2085059SAnton Blanchard msr_check_and_clear(msr_all_available); 512c2085059SAnton Blanchard } 513c2085059SAnton Blanchard EXPORT_SYMBOL(giveup_all); 514c2085059SAnton Blanchard 51570fe3d98SCyril Bur void restore_math(struct pt_regs *regs) 51670fe3d98SCyril Bur { 51770fe3d98SCyril Bur unsigned long msr; 51870fe3d98SCyril Bur 519bc4f65e4SNicholas Piggin /* 520bc4f65e4SNicholas Piggin * Syscall exit makes a similar initial check before branching 521bc4f65e4SNicholas Piggin * to restore_math. Keep them in synch. 522bc4f65e4SNicholas Piggin */ 523dc16b553SCyril Bur if (!msr_tm_active(regs->msr) && 524dc16b553SCyril Bur !current->thread.load_fp && !loadvec(current->thread)) 52570fe3d98SCyril Bur return; 52670fe3d98SCyril Bur 52770fe3d98SCyril Bur msr = regs->msr; 52870fe3d98SCyril Bur msr_check_and_set(msr_all_available); 52970fe3d98SCyril Bur 53070fe3d98SCyril Bur /* 53170fe3d98SCyril Bur * Only reload if the bit is not set in the user MSR, the bit BEING set 53270fe3d98SCyril Bur * indicates that the registers are hot 53370fe3d98SCyril Bur */ 53470fe3d98SCyril Bur if ((!(msr & MSR_FP)) && restore_fp(current)) 53570fe3d98SCyril Bur msr |= MSR_FP | current->thread.fpexc_mode; 53670fe3d98SCyril Bur 53770fe3d98SCyril Bur if ((!(msr & MSR_VEC)) && restore_altivec(current)) 53870fe3d98SCyril Bur msr |= MSR_VEC; 53970fe3d98SCyril Bur 54070fe3d98SCyril Bur if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && 54170fe3d98SCyril Bur restore_vsx(current)) { 54270fe3d98SCyril Bur msr |= MSR_VSX; 54370fe3d98SCyril Bur } 54470fe3d98SCyril Bur 54570fe3d98SCyril Bur msr_check_and_clear(msr_all_available); 54670fe3d98SCyril Bur 54770fe3d98SCyril Bur regs->msr = msr; 54870fe3d98SCyril Bur } 54970fe3d98SCyril Bur 550de2a20aaSCyril Bur void save_all(struct task_struct *tsk) 551de2a20aaSCyril Bur { 552de2a20aaSCyril Bur unsigned long usermsr; 553de2a20aaSCyril Bur 554de2a20aaSCyril Bur if (!tsk->thread.regs) 555de2a20aaSCyril Bur return; 556de2a20aaSCyril Bur 557de2a20aaSCyril Bur usermsr = tsk->thread.regs->msr; 558de2a20aaSCyril Bur 559de2a20aaSCyril Bur if ((usermsr & msr_all_available) == 0) 560de2a20aaSCyril Bur return; 561de2a20aaSCyril Bur 562de2a20aaSCyril Bur msr_check_and_set(msr_all_available); 563de2a20aaSCyril Bur 564bf6a4d5bSCyril Bur /* 565bf6a4d5bSCyril Bur * Saving the way the register space is in hardware, save_vsx boils 566bf6a4d5bSCyril Bur * down to a save_fpu() and save_altivec() 567bf6a4d5bSCyril Bur */ 568bf6a4d5bSCyril Bur if (usermsr & MSR_VSX) { 569bf6a4d5bSCyril Bur save_vsx(tsk); 570bf6a4d5bSCyril Bur } else { 571de2a20aaSCyril Bur if (usermsr & MSR_FP) 5728792468dSCyril Bur save_fpu(tsk); 573de2a20aaSCyril Bur 574de2a20aaSCyril Bur if (usermsr & MSR_VEC) 5756f515d84SCyril Bur save_altivec(tsk); 576bf6a4d5bSCyril Bur } 577de2a20aaSCyril Bur 578de2a20aaSCyril Bur if (usermsr & MSR_SPE) 579de2a20aaSCyril Bur __giveup_spe(tsk); 580de2a20aaSCyril Bur 581de2a20aaSCyril Bur msr_check_and_clear(msr_all_available); 582de2a20aaSCyril Bur } 583de2a20aaSCyril Bur 584579e633eSAnton Blanchard void flush_all_to_thread(struct task_struct *tsk) 585579e633eSAnton Blanchard { 586579e633eSAnton Blanchard if (tsk->thread.regs) { 587579e633eSAnton Blanchard preempt_disable(); 588579e633eSAnton Blanchard BUG_ON(tsk != current); 589de2a20aaSCyril Bur save_all(tsk); 590579e633eSAnton Blanchard 591579e633eSAnton Blanchard #ifdef CONFIG_SPE 592579e633eSAnton Blanchard if (tsk->thread.regs->msr & MSR_SPE) 593579e633eSAnton Blanchard tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 594579e633eSAnton Blanchard #endif 595579e633eSAnton Blanchard 596579e633eSAnton Blanchard preempt_enable(); 597579e633eSAnton Blanchard } 598579e633eSAnton Blanchard } 599579e633eSAnton Blanchard EXPORT_SYMBOL(flush_all_to_thread); 600579e633eSAnton Blanchard 6013bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6023bffb652SDave Kleikamp void do_send_trap(struct pt_regs *regs, unsigned long address, 6033bffb652SDave Kleikamp unsigned long error_code, int signal_code, int breakpt) 6043bffb652SDave Kleikamp { 6053bffb652SDave Kleikamp siginfo_t info; 6063bffb652SDave Kleikamp 60741ab5266SAnanth N Mavinakayanahalli current->thread.trap_nr = signal_code; 6083bffb652SDave Kleikamp if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 6093bffb652SDave Kleikamp 11, SIGSEGV) == NOTIFY_STOP) 6103bffb652SDave Kleikamp return; 6113bffb652SDave Kleikamp 6123bffb652SDave Kleikamp /* Deliver the signal to userspace */ 6133bffb652SDave Kleikamp info.si_signo = SIGTRAP; 6143bffb652SDave Kleikamp info.si_errno = breakpt; /* breakpoint or watchpoint id */ 6153bffb652SDave Kleikamp info.si_code = signal_code; 6163bffb652SDave Kleikamp info.si_addr = (void __user *)address; 6173bffb652SDave Kleikamp force_sig_info(SIGTRAP, &info, current); 6183bffb652SDave Kleikamp } 6193bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 6209422de3eSMichael Neuling void do_break (struct pt_regs *regs, unsigned long address, 621d6a61bfcSLuis Machado unsigned long error_code) 622d6a61bfcSLuis Machado { 623d6a61bfcSLuis Machado siginfo_t info; 624d6a61bfcSLuis Machado 62541ab5266SAnanth N Mavinakayanahalli current->thread.trap_nr = TRAP_HWBKPT; 626d6a61bfcSLuis Machado if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 627d6a61bfcSLuis Machado 11, SIGSEGV) == NOTIFY_STOP) 628d6a61bfcSLuis Machado return; 629d6a61bfcSLuis Machado 6309422de3eSMichael Neuling if (debugger_break_match(regs)) 631d6a61bfcSLuis Machado return; 632d6a61bfcSLuis Machado 6339422de3eSMichael Neuling /* Clear the breakpoint */ 6349422de3eSMichael Neuling hw_breakpoint_disable(); 635d6a61bfcSLuis Machado 636d6a61bfcSLuis Machado /* Deliver the signal to userspace */ 637d6a61bfcSLuis Machado info.si_signo = SIGTRAP; 638d6a61bfcSLuis Machado info.si_errno = 0; 639d6a61bfcSLuis Machado info.si_code = TRAP_HWBKPT; 640d6a61bfcSLuis Machado info.si_addr = (void __user *)address; 641d6a61bfcSLuis Machado force_sig_info(SIGTRAP, &info, current); 642d6a61bfcSLuis Machado } 6433bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 644d6a61bfcSLuis Machado 6459422de3eSMichael Neuling static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 646a2ceff5eSMichael Ellerman 6473bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6483bffb652SDave Kleikamp /* 6493bffb652SDave Kleikamp * Set the debug registers back to their default "safe" values. 6503bffb652SDave Kleikamp */ 6513bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 6523bffb652SDave Kleikamp { 65351ae8d4aSBharat Bhushan thread->debug.iac1 = thread->debug.iac2 = 0; 6543bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 65551ae8d4aSBharat Bhushan thread->debug.iac3 = thread->debug.iac4 = 0; 6563bffb652SDave Kleikamp #endif 65751ae8d4aSBharat Bhushan thread->debug.dac1 = thread->debug.dac2 = 0; 6583bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 65951ae8d4aSBharat Bhushan thread->debug.dvc1 = thread->debug.dvc2 = 0; 6603bffb652SDave Kleikamp #endif 66151ae8d4aSBharat Bhushan thread->debug.dbcr0 = 0; 6623bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 6633bffb652SDave Kleikamp /* 6643bffb652SDave Kleikamp * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 6653bffb652SDave Kleikamp */ 66651ae8d4aSBharat Bhushan thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 6673bffb652SDave Kleikamp DBCR1_IAC3US | DBCR1_IAC4US; 6683bffb652SDave Kleikamp /* 6693bffb652SDave Kleikamp * Force Data Address Compare User/Supervisor bits to be User-only 6703bffb652SDave Kleikamp * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 6713bffb652SDave Kleikamp */ 67251ae8d4aSBharat Bhushan thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 6733bffb652SDave Kleikamp #else 67451ae8d4aSBharat Bhushan thread->debug.dbcr1 = 0; 6753bffb652SDave Kleikamp #endif 6763bffb652SDave Kleikamp } 6773bffb652SDave Kleikamp 678f5f97210SScott Wood static void prime_debug_regs(struct debug_reg *debug) 6793bffb652SDave Kleikamp { 6806cecf76bSScott Wood /* 6816cecf76bSScott Wood * We could have inherited MSR_DE from userspace, since 6826cecf76bSScott Wood * it doesn't get cleared on exception entry. Make sure 6836cecf76bSScott Wood * MSR_DE is clear before we enable any debug events. 6846cecf76bSScott Wood */ 6856cecf76bSScott Wood mtmsr(mfmsr() & ~MSR_DE); 6866cecf76bSScott Wood 687f5f97210SScott Wood mtspr(SPRN_IAC1, debug->iac1); 688f5f97210SScott Wood mtspr(SPRN_IAC2, debug->iac2); 6893bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 690f5f97210SScott Wood mtspr(SPRN_IAC3, debug->iac3); 691f5f97210SScott Wood mtspr(SPRN_IAC4, debug->iac4); 6923bffb652SDave Kleikamp #endif 693f5f97210SScott Wood mtspr(SPRN_DAC1, debug->dac1); 694f5f97210SScott Wood mtspr(SPRN_DAC2, debug->dac2); 6953bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 696f5f97210SScott Wood mtspr(SPRN_DVC1, debug->dvc1); 697f5f97210SScott Wood mtspr(SPRN_DVC2, debug->dvc2); 6983bffb652SDave Kleikamp #endif 699f5f97210SScott Wood mtspr(SPRN_DBCR0, debug->dbcr0); 700f5f97210SScott Wood mtspr(SPRN_DBCR1, debug->dbcr1); 7013bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 702f5f97210SScott Wood mtspr(SPRN_DBCR2, debug->dbcr2); 7033bffb652SDave Kleikamp #endif 7043bffb652SDave Kleikamp } 7053bffb652SDave Kleikamp /* 7063bffb652SDave Kleikamp * Unless neither the old or new thread are making use of the 7073bffb652SDave Kleikamp * debug registers, set the debug registers from the values 7083bffb652SDave Kleikamp * stored in the new thread. 7093bffb652SDave Kleikamp */ 710f5f97210SScott Wood void switch_booke_debug_regs(struct debug_reg *new_debug) 7113bffb652SDave Kleikamp { 71251ae8d4aSBharat Bhushan if ((current->thread.debug.dbcr0 & DBCR0_IDM) 713f5f97210SScott Wood || (new_debug->dbcr0 & DBCR0_IDM)) 714f5f97210SScott Wood prime_debug_regs(new_debug); 7153bffb652SDave Kleikamp } 7163743c9b8SBharat Bhushan EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 7173bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 718e0780b72SK.Prasad #ifndef CONFIG_HAVE_HW_BREAKPOINT 7193bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 7203bffb652SDave Kleikamp { 7219422de3eSMichael Neuling thread->hw_brk.address = 0; 7229422de3eSMichael Neuling thread->hw_brk.type = 0; 723b9818c33SMichael Neuling set_breakpoint(&thread->hw_brk); 7243bffb652SDave Kleikamp } 725e0780b72SK.Prasad #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 7263bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 7273bffb652SDave Kleikamp 728172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 7299422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7309422de3eSMichael Neuling { 731c6c9eaceSBenjamin Herrenschmidt mtspr(SPRN_DAC1, dabr); 732221c185dSDave Kleikamp #ifdef CONFIG_PPC_47x 733221c185dSDave Kleikamp isync(); 734221c185dSDave Kleikamp #endif 7359422de3eSMichael Neuling return 0; 7369422de3eSMichael Neuling } 737c6c9eaceSBenjamin Herrenschmidt #elif defined(CONFIG_PPC_BOOK3S) 7389422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7399422de3eSMichael Neuling { 740cab0af98SMichael Ellerman mtspr(SPRN_DABR, dabr); 74182a9f16aSMichael Neuling if (cpu_has_feature(CPU_FTR_DABRX)) 7424474ef05SMichael Neuling mtspr(SPRN_DABRX, dabrx); 743cab0af98SMichael Ellerman return 0; 74414cf11afSPaul Mackerras } 7454ad8622dSChristophe Leroy #elif defined(CONFIG_PPC_8xx) 7464ad8622dSChristophe Leroy static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7474ad8622dSChristophe Leroy { 7484ad8622dSChristophe Leroy unsigned long addr = dabr & ~HW_BRK_TYPE_DABR; 7494ad8622dSChristophe Leroy unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */ 7504ad8622dSChristophe Leroy unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */ 7514ad8622dSChristophe Leroy 7524ad8622dSChristophe Leroy if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) 7534ad8622dSChristophe Leroy lctrl1 |= 0xa0000; 7544ad8622dSChristophe Leroy else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) 7554ad8622dSChristophe Leroy lctrl1 |= 0xf0000; 7564ad8622dSChristophe Leroy else if ((dabr & HW_BRK_TYPE_RDWR) == 0) 7574ad8622dSChristophe Leroy lctrl2 = 0; 7584ad8622dSChristophe Leroy 7594ad8622dSChristophe Leroy mtspr(SPRN_LCTRL2, 0); 7604ad8622dSChristophe Leroy mtspr(SPRN_CMPE, addr); 7614ad8622dSChristophe Leroy mtspr(SPRN_CMPF, addr + 4); 7624ad8622dSChristophe Leroy mtspr(SPRN_LCTRL1, lctrl1); 7634ad8622dSChristophe Leroy mtspr(SPRN_LCTRL2, lctrl2); 7644ad8622dSChristophe Leroy 7654ad8622dSChristophe Leroy return 0; 7664ad8622dSChristophe Leroy } 7679422de3eSMichael Neuling #else 7689422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7699422de3eSMichael Neuling { 7709422de3eSMichael Neuling return -EINVAL; 7719422de3eSMichael Neuling } 7729422de3eSMichael Neuling #endif 7739422de3eSMichael Neuling 7749422de3eSMichael Neuling static inline int set_dabr(struct arch_hw_breakpoint *brk) 7759422de3eSMichael Neuling { 7769422de3eSMichael Neuling unsigned long dabr, dabrx; 7779422de3eSMichael Neuling 7789422de3eSMichael Neuling dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 7799422de3eSMichael Neuling dabrx = ((brk->type >> 3) & 0x7); 7809422de3eSMichael Neuling 7819422de3eSMichael Neuling if (ppc_md.set_dabr) 7829422de3eSMichael Neuling return ppc_md.set_dabr(dabr, dabrx); 7839422de3eSMichael Neuling 7849422de3eSMichael Neuling return __set_dabr(dabr, dabrx); 7859422de3eSMichael Neuling } 7869422de3eSMichael Neuling 787bf99de36SMichael Neuling static inline int set_dawr(struct arch_hw_breakpoint *brk) 788bf99de36SMichael Neuling { 78905d694eaSMichael Neuling unsigned long dawr, dawrx, mrd; 790bf99de36SMichael Neuling 791bf99de36SMichael Neuling dawr = brk->address; 792bf99de36SMichael Neuling 793bf99de36SMichael Neuling dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 794bf99de36SMichael Neuling << (63 - 58); //* read/write bits */ 795bf99de36SMichael Neuling dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 796bf99de36SMichael Neuling << (63 - 59); //* translate */ 797bf99de36SMichael Neuling dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 798bf99de36SMichael Neuling >> 3; //* PRIM bits */ 79905d694eaSMichael Neuling /* dawr length is stored in field MDR bits 48:53. Matches range in 80005d694eaSMichael Neuling doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 80105d694eaSMichael Neuling 0b111111=64DW. 80205d694eaSMichael Neuling brk->len is in bytes. 80305d694eaSMichael Neuling This aligns up to double word size, shifts and does the bias. 80405d694eaSMichael Neuling */ 80505d694eaSMichael Neuling mrd = ((brk->len + 7) >> 3) - 1; 80605d694eaSMichael Neuling dawrx |= (mrd & 0x3f) << (63 - 53); 807bf99de36SMichael Neuling 808bf99de36SMichael Neuling if (ppc_md.set_dawr) 809bf99de36SMichael Neuling return ppc_md.set_dawr(dawr, dawrx); 810bf99de36SMichael Neuling mtspr(SPRN_DAWR, dawr); 811bf99de36SMichael Neuling mtspr(SPRN_DAWRX, dawrx); 812bf99de36SMichael Neuling return 0; 813bf99de36SMichael Neuling } 814bf99de36SMichael Neuling 81521f58507SPaul Gortmaker void __set_breakpoint(struct arch_hw_breakpoint *brk) 8169422de3eSMichael Neuling { 81769111bacSChristoph Lameter memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); 8189422de3eSMichael Neuling 819bf99de36SMichael Neuling if (cpu_has_feature(CPU_FTR_DAWR)) 82004c32a51SPaul Gortmaker set_dawr(brk); 82104c32a51SPaul Gortmaker else 82204c32a51SPaul Gortmaker set_dabr(brk); 8239422de3eSMichael Neuling } 82414cf11afSPaul Mackerras 82521f58507SPaul Gortmaker void set_breakpoint(struct arch_hw_breakpoint *brk) 82621f58507SPaul Gortmaker { 82721f58507SPaul Gortmaker preempt_disable(); 82821f58507SPaul Gortmaker __set_breakpoint(brk); 82921f58507SPaul Gortmaker preempt_enable(); 83021f58507SPaul Gortmaker } 83121f58507SPaul Gortmaker 83206d67d54SPaul Mackerras #ifdef CONFIG_PPC64 83306d67d54SPaul Mackerras DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 83406d67d54SPaul Mackerras #endif 83514cf11afSPaul Mackerras 8369422de3eSMichael Neuling static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 8379422de3eSMichael Neuling struct arch_hw_breakpoint *b) 8389422de3eSMichael Neuling { 8399422de3eSMichael Neuling if (a->address != b->address) 8409422de3eSMichael Neuling return false; 8419422de3eSMichael Neuling if (a->type != b->type) 8429422de3eSMichael Neuling return false; 8439422de3eSMichael Neuling if (a->len != b->len) 8449422de3eSMichael Neuling return false; 8459422de3eSMichael Neuling return true; 8469422de3eSMichael Neuling } 847d31626f7SPaul Mackerras 848fb09692eSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 8495d176f75SCyril Bur 8505d176f75SCyril Bur static inline bool tm_enabled(struct task_struct *tsk) 8515d176f75SCyril Bur { 8525d176f75SCyril Bur return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); 8535d176f75SCyril Bur } 8545d176f75SCyril Bur 855d31626f7SPaul Mackerras static void tm_reclaim_thread(struct thread_struct *thr, 856d31626f7SPaul Mackerras struct thread_info *ti, uint8_t cause) 857d31626f7SPaul Mackerras { 8587f821fc9SMichael Neuling /* 8597f821fc9SMichael Neuling * Use the current MSR TM suspended bit to track if we have 8607f821fc9SMichael Neuling * checkpointed state outstanding. 8617f821fc9SMichael Neuling * On signal delivery, we'd normally reclaim the checkpointed 8627f821fc9SMichael Neuling * state to obtain stack pointer (see:get_tm_stackpointer()). 8637f821fc9SMichael Neuling * This will then directly return to userspace without going 8647f821fc9SMichael Neuling * through __switch_to(). However, if the stack frame is bad, 8657f821fc9SMichael Neuling * we need to exit this thread which calls __switch_to() which 8667f821fc9SMichael Neuling * will again attempt to reclaim the already saved tm state. 8677f821fc9SMichael Neuling * Hence we need to check that we've not already reclaimed 8687f821fc9SMichael Neuling * this state. 8697f821fc9SMichael Neuling * We do this using the current MSR, rather tracking it in 8707f821fc9SMichael Neuling * some specific thread_struct bit, as it has the additional 871027dfac6SMichael Ellerman * benefit of checking for a potential TM bad thing exception. 8727f821fc9SMichael Neuling */ 8737f821fc9SMichael Neuling if (!MSR_TM_SUSPENDED(mfmsr())) 8747f821fc9SMichael Neuling return; 8757f821fc9SMichael Neuling 876f48e91e8SMichael Neuling /* 877f48e91e8SMichael Neuling * If we are in a transaction and FP is off then we can't have 878f48e91e8SMichael Neuling * used FP inside that transaction. Hence the checkpointed 879f48e91e8SMichael Neuling * state is the same as the live state. We need to copy the 880f48e91e8SMichael Neuling * live state to the checkpointed state so that when the 881f48e91e8SMichael Neuling * transaction is restored, the checkpointed state is correct 882f48e91e8SMichael Neuling * and the aborted transaction sees the correct state. We use 883f48e91e8SMichael Neuling * ckpt_regs.msr here as that's what tm_reclaim will use to 884f48e91e8SMichael Neuling * determine if it's going to write the checkpointed state or 885f48e91e8SMichael Neuling * not. So either this will write the checkpointed registers, 886f48e91e8SMichael Neuling * or reclaim will. Similarly for VMX. 887f48e91e8SMichael Neuling */ 888f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_FP) == 0) 889f48e91e8SMichael Neuling memcpy(&thr->ckfp_state, &thr->fp_state, 890f48e91e8SMichael Neuling sizeof(struct thread_fp_state)); 891f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_VEC) == 0) 892f48e91e8SMichael Neuling memcpy(&thr->ckvr_state, &thr->vr_state, 893f48e91e8SMichael Neuling sizeof(struct thread_vr_state)); 894f48e91e8SMichael Neuling 895dc310669SCyril Bur giveup_all(container_of(thr, struct task_struct, thread)); 896d31626f7SPaul Mackerras 897dc310669SCyril Bur tm_reclaim(thr, thr->ckpt_regs.msr, cause); 898d31626f7SPaul Mackerras } 899d31626f7SPaul Mackerras 900d31626f7SPaul Mackerras void tm_reclaim_current(uint8_t cause) 901d31626f7SPaul Mackerras { 902d31626f7SPaul Mackerras tm_enable(); 903d31626f7SPaul Mackerras tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 904d31626f7SPaul Mackerras } 905d31626f7SPaul Mackerras 906fb09692eSMichael Neuling static inline void tm_reclaim_task(struct task_struct *tsk) 907fb09692eSMichael Neuling { 908fb09692eSMichael Neuling /* We have to work out if we're switching from/to a task that's in the 909fb09692eSMichael Neuling * middle of a transaction. 910fb09692eSMichael Neuling * 911fb09692eSMichael Neuling * In switching we need to maintain a 2nd register state as 912fb09692eSMichael Neuling * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 913000ec280SCyril Bur * checkpointed (tbegin) state in ckpt_regs, ckfp_state and 914000ec280SCyril Bur * ckvr_state 915fb09692eSMichael Neuling * 916fb09692eSMichael Neuling * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 917fb09692eSMichael Neuling */ 918fb09692eSMichael Neuling struct thread_struct *thr = &tsk->thread; 919fb09692eSMichael Neuling 920fb09692eSMichael Neuling if (!thr->regs) 921fb09692eSMichael Neuling return; 922fb09692eSMichael Neuling 923fb09692eSMichael Neuling if (!MSR_TM_ACTIVE(thr->regs->msr)) 924fb09692eSMichael Neuling goto out_and_saveregs; 925fb09692eSMichael Neuling 926fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 927fb09692eSMichael Neuling "ccr=%lx, msr=%lx, trap=%lx)\n", 928fb09692eSMichael Neuling tsk->pid, thr->regs->nip, 929fb09692eSMichael Neuling thr->regs->ccr, thr->regs->msr, 930fb09692eSMichael Neuling thr->regs->trap); 931fb09692eSMichael Neuling 932d31626f7SPaul Mackerras tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 933fb09692eSMichael Neuling 934fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d complete\n", 935fb09692eSMichael Neuling tsk->pid); 936fb09692eSMichael Neuling 937fb09692eSMichael Neuling out_and_saveregs: 938fb09692eSMichael Neuling /* Always save the regs here, even if a transaction's not active. 939fb09692eSMichael Neuling * This context-switches a thread's TM info SPRs. We do it here to 940fb09692eSMichael Neuling * be consistent with the restore path (in recheckpoint) which 941fb09692eSMichael Neuling * cannot happen later in _switch(). 942fb09692eSMichael Neuling */ 943fb09692eSMichael Neuling tm_save_sprs(thr); 944fb09692eSMichael Neuling } 945fb09692eSMichael Neuling 946e6b8fd02SMichael Neuling extern void __tm_recheckpoint(struct thread_struct *thread, 947e6b8fd02SMichael Neuling unsigned long orig_msr); 948e6b8fd02SMichael Neuling 949e6b8fd02SMichael Neuling void tm_recheckpoint(struct thread_struct *thread, 950e6b8fd02SMichael Neuling unsigned long orig_msr) 951e6b8fd02SMichael Neuling { 952e6b8fd02SMichael Neuling unsigned long flags; 953e6b8fd02SMichael Neuling 9545d176f75SCyril Bur if (!(thread->regs->msr & MSR_TM)) 9555d176f75SCyril Bur return; 9565d176f75SCyril Bur 957e6b8fd02SMichael Neuling /* We really can't be interrupted here as the TEXASR registers can't 958e6b8fd02SMichael Neuling * change and later in the trecheckpoint code, we have a userspace R1. 959e6b8fd02SMichael Neuling * So let's hard disable over this region. 960e6b8fd02SMichael Neuling */ 961e6b8fd02SMichael Neuling local_irq_save(flags); 962e6b8fd02SMichael Neuling hard_irq_disable(); 963e6b8fd02SMichael Neuling 964e6b8fd02SMichael Neuling /* The TM SPRs are restored here, so that TEXASR.FS can be set 965e6b8fd02SMichael Neuling * before the trecheckpoint and no explosion occurs. 966e6b8fd02SMichael Neuling */ 967e6b8fd02SMichael Neuling tm_restore_sprs(thread); 968e6b8fd02SMichael Neuling 969e6b8fd02SMichael Neuling __tm_recheckpoint(thread, orig_msr); 970e6b8fd02SMichael Neuling 971e6b8fd02SMichael Neuling local_irq_restore(flags); 972e6b8fd02SMichael Neuling } 973e6b8fd02SMichael Neuling 974bc2a9408SMichael Neuling static inline void tm_recheckpoint_new_task(struct task_struct *new) 975fb09692eSMichael Neuling { 976fb09692eSMichael Neuling unsigned long msr; 977fb09692eSMichael Neuling 978fb09692eSMichael Neuling if (!cpu_has_feature(CPU_FTR_TM)) 979fb09692eSMichael Neuling return; 980fb09692eSMichael Neuling 981fb09692eSMichael Neuling /* Recheckpoint the registers of the thread we're about to switch to. 982fb09692eSMichael Neuling * 983fb09692eSMichael Neuling * If the task was using FP, we non-lazily reload both the original and 984fb09692eSMichael Neuling * the speculative FP register states. This is because the kernel 985fb09692eSMichael Neuling * doesn't see if/when a TM rollback occurs, so if we take an FP 986dc310669SCyril Bur * unavailable later, we are unable to determine which set of FP regs 987fb09692eSMichael Neuling * need to be restored. 988fb09692eSMichael Neuling */ 9895d176f75SCyril Bur if (!tm_enabled(new)) 990fb09692eSMichael Neuling return; 991fb09692eSMichael Neuling 992e6b8fd02SMichael Neuling if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 993fb09692eSMichael Neuling tm_restore_sprs(&new->thread); 994fb09692eSMichael Neuling return; 995e6b8fd02SMichael Neuling } 996829023dfSAnshuman Khandual msr = new->thread.ckpt_regs.msr; 997fb09692eSMichael Neuling /* Recheckpoint to restore original checkpointed register state. */ 998fb09692eSMichael Neuling TM_DEBUG("*** tm_recheckpoint of pid %d " 999fb09692eSMichael Neuling "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 1000fb09692eSMichael Neuling new->pid, new->thread.regs->msr, msr); 1001fb09692eSMichael Neuling 1002fb09692eSMichael Neuling tm_recheckpoint(&new->thread, msr); 1003fb09692eSMichael Neuling 1004dc310669SCyril Bur /* 1005dc310669SCyril Bur * The checkpointed state has been restored but the live state has 1006dc310669SCyril Bur * not, ensure all the math functionality is turned off to trigger 1007dc310669SCyril Bur * restore_math() to reload. 1008dc310669SCyril Bur */ 1009dc310669SCyril Bur new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); 1010fb09692eSMichael Neuling 1011fb09692eSMichael Neuling TM_DEBUG("*** tm_recheckpoint of pid %d complete " 1012fb09692eSMichael Neuling "(kernel msr 0x%lx)\n", 1013fb09692eSMichael Neuling new->pid, mfmsr()); 1014fb09692eSMichael Neuling } 1015fb09692eSMichael Neuling 1016dc310669SCyril Bur static inline void __switch_to_tm(struct task_struct *prev, 1017dc310669SCyril Bur struct task_struct *new) 1018fb09692eSMichael Neuling { 1019fb09692eSMichael Neuling if (cpu_has_feature(CPU_FTR_TM)) { 10205d176f75SCyril Bur if (tm_enabled(prev) || tm_enabled(new)) 1021fb09692eSMichael Neuling tm_enable(); 10225d176f75SCyril Bur 10235d176f75SCyril Bur if (tm_enabled(prev)) { 10245d176f75SCyril Bur prev->thread.load_tm++; 1025fb09692eSMichael Neuling tm_reclaim_task(prev); 10265d176f75SCyril Bur if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) 10275d176f75SCyril Bur prev->thread.regs->msr &= ~MSR_TM; 10285d176f75SCyril Bur } 10295d176f75SCyril Bur 1030dc310669SCyril Bur tm_recheckpoint_new_task(new); 1031fb09692eSMichael Neuling } 1032fb09692eSMichael Neuling } 1033d31626f7SPaul Mackerras 1034d31626f7SPaul Mackerras /* 1035d31626f7SPaul Mackerras * This is called if we are on the way out to userspace and the 1036d31626f7SPaul Mackerras * TIF_RESTORE_TM flag is set. It checks if we need to reload 1037d31626f7SPaul Mackerras * FP and/or vector state and does so if necessary. 1038d31626f7SPaul Mackerras * If userspace is inside a transaction (whether active or 1039d31626f7SPaul Mackerras * suspended) and FP/VMX/VSX instructions have ever been enabled 1040d31626f7SPaul Mackerras * inside that transaction, then we have to keep them enabled 1041d31626f7SPaul Mackerras * and keep the FP/VMX/VSX state loaded while ever the transaction 1042d31626f7SPaul Mackerras * continues. The reason is that if we didn't, and subsequently 1043d31626f7SPaul Mackerras * got a FP/VMX/VSX unavailable interrupt inside a transaction, 1044d31626f7SPaul Mackerras * we don't know whether it's the same transaction, and thus we 1045d31626f7SPaul Mackerras * don't know which of the checkpointed state and the transactional 1046d31626f7SPaul Mackerras * state to use. 1047d31626f7SPaul Mackerras */ 1048d31626f7SPaul Mackerras void restore_tm_state(struct pt_regs *regs) 1049d31626f7SPaul Mackerras { 1050d31626f7SPaul Mackerras unsigned long msr_diff; 1051d31626f7SPaul Mackerras 1052dc310669SCyril Bur /* 1053dc310669SCyril Bur * This is the only moment we should clear TIF_RESTORE_TM as 1054dc310669SCyril Bur * it is here that ckpt_regs.msr and pt_regs.msr become the same 1055dc310669SCyril Bur * again, anything else could lead to an incorrect ckpt_msr being 1056dc310669SCyril Bur * saved and therefore incorrect signal contexts. 1057dc310669SCyril Bur */ 1058d31626f7SPaul Mackerras clear_thread_flag(TIF_RESTORE_TM); 1059d31626f7SPaul Mackerras if (!MSR_TM_ACTIVE(regs->msr)) 1060d31626f7SPaul Mackerras return; 1061d31626f7SPaul Mackerras 1062829023dfSAnshuman Khandual msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 1063d31626f7SPaul Mackerras msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 106470fe3d98SCyril Bur 1065dc16b553SCyril Bur /* Ensure that restore_math() will restore */ 1066dc16b553SCyril Bur if (msr_diff & MSR_FP) 1067dc16b553SCyril Bur current->thread.load_fp = 1; 106839715bf9SValentin Rothberg #ifdef CONFIG_ALTIVEC 1069dc16b553SCyril Bur if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) 1070dc16b553SCyril Bur current->thread.load_vec = 1; 1071dc16b553SCyril Bur #endif 107270fe3d98SCyril Bur restore_math(regs); 107370fe3d98SCyril Bur 1074d31626f7SPaul Mackerras regs->msr |= msr_diff; 1075d31626f7SPaul Mackerras } 1076d31626f7SPaul Mackerras 1077fb09692eSMichael Neuling #else 1078fb09692eSMichael Neuling #define tm_recheckpoint_new_task(new) 1079dc310669SCyril Bur #define __switch_to_tm(prev, new) 1080fb09692eSMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 10819422de3eSMichael Neuling 1082152d523eSAnton Blanchard static inline void save_sprs(struct thread_struct *t) 1083152d523eSAnton Blanchard { 1084152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 108501d7c2a2SOliver O'Halloran if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1086152d523eSAnton Blanchard t->vrsave = mfspr(SPRN_VRSAVE); 1087152d523eSAnton Blanchard #endif 1088152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1089152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) 1090152d523eSAnton Blanchard t->dscr = mfspr(SPRN_DSCR); 1091152d523eSAnton Blanchard 1092152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1093152d523eSAnton Blanchard t->bescr = mfspr(SPRN_BESCR); 1094152d523eSAnton Blanchard t->ebbhr = mfspr(SPRN_EBBHR); 1095152d523eSAnton Blanchard t->ebbrr = mfspr(SPRN_EBBRR); 1096152d523eSAnton Blanchard 1097152d523eSAnton Blanchard t->fscr = mfspr(SPRN_FSCR); 1098152d523eSAnton Blanchard 1099152d523eSAnton Blanchard /* 1100152d523eSAnton Blanchard * Note that the TAR is not available for use in the kernel. 1101152d523eSAnton Blanchard * (To provide this, the TAR should be backed up/restored on 1102152d523eSAnton Blanchard * exception entry/exit instead, and be in pt_regs. FIXME, 1103152d523eSAnton Blanchard * this should be in pt_regs anyway (for debug).) 1104152d523eSAnton Blanchard */ 1105152d523eSAnton Blanchard t->tar = mfspr(SPRN_TAR); 1106152d523eSAnton Blanchard } 1107152d523eSAnton Blanchard #endif 1108152d523eSAnton Blanchard } 1109152d523eSAnton Blanchard 1110152d523eSAnton Blanchard static inline void restore_sprs(struct thread_struct *old_thread, 1111152d523eSAnton Blanchard struct thread_struct *new_thread) 1112152d523eSAnton Blanchard { 1113152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 1114152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC) && 1115152d523eSAnton Blanchard old_thread->vrsave != new_thread->vrsave) 1116152d523eSAnton Blanchard mtspr(SPRN_VRSAVE, new_thread->vrsave); 1117152d523eSAnton Blanchard #endif 1118152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1119152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) { 1120152d523eSAnton Blanchard u64 dscr = get_paca()->dscr_default; 1121b57bd2deSMichael Neuling if (new_thread->dscr_inherit) 1122152d523eSAnton Blanchard dscr = new_thread->dscr; 1123152d523eSAnton Blanchard 1124152d523eSAnton Blanchard if (old_thread->dscr != dscr) 1125152d523eSAnton Blanchard mtspr(SPRN_DSCR, dscr); 1126152d523eSAnton Blanchard } 1127152d523eSAnton Blanchard 1128152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1129152d523eSAnton Blanchard if (old_thread->bescr != new_thread->bescr) 1130152d523eSAnton Blanchard mtspr(SPRN_BESCR, new_thread->bescr); 1131152d523eSAnton Blanchard if (old_thread->ebbhr != new_thread->ebbhr) 1132152d523eSAnton Blanchard mtspr(SPRN_EBBHR, new_thread->ebbhr); 1133152d523eSAnton Blanchard if (old_thread->ebbrr != new_thread->ebbrr) 1134152d523eSAnton Blanchard mtspr(SPRN_EBBRR, new_thread->ebbrr); 1135152d523eSAnton Blanchard 1136b57bd2deSMichael Neuling if (old_thread->fscr != new_thread->fscr) 1137b57bd2deSMichael Neuling mtspr(SPRN_FSCR, new_thread->fscr); 1138b57bd2deSMichael Neuling 1139152d523eSAnton Blanchard if (old_thread->tar != new_thread->tar) 1140152d523eSAnton Blanchard mtspr(SPRN_TAR, new_thread->tar); 1141152d523eSAnton Blanchard } 1142152d523eSAnton Blanchard #endif 1143152d523eSAnton Blanchard } 1144152d523eSAnton Blanchard 114507d2a628SNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 114607d2a628SNicholas Piggin #define CP_SIZE 128 114707d2a628SNicholas Piggin static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE))); 114807d2a628SNicholas Piggin #endif 114907d2a628SNicholas Piggin 115014cf11afSPaul Mackerras struct task_struct *__switch_to(struct task_struct *prev, 115114cf11afSPaul Mackerras struct task_struct *new) 115214cf11afSPaul Mackerras { 115314cf11afSPaul Mackerras struct thread_struct *new_thread, *old_thread; 115414cf11afSPaul Mackerras struct task_struct *last; 1155d6bf29b4SPeter Zijlstra #ifdef CONFIG_PPC_BOOK3S_64 1156d6bf29b4SPeter Zijlstra struct ppc64_tlb_batch *batch; 1157d6bf29b4SPeter Zijlstra #endif 115814cf11afSPaul Mackerras 1159152d523eSAnton Blanchard new_thread = &new->thread; 1160152d523eSAnton Blanchard old_thread = ¤t->thread; 1161152d523eSAnton Blanchard 11627ba5fef7SMichael Neuling WARN_ON(!irqs_disabled()); 11637ba5fef7SMichael Neuling 116406d67d54SPaul Mackerras #ifdef CONFIG_PPC64 116506d67d54SPaul Mackerras /* 116606d67d54SPaul Mackerras * Collect processor utilization data per process 116706d67d54SPaul Mackerras */ 116806d67d54SPaul Mackerras if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 116969111bacSChristoph Lameter struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array); 117006d67d54SPaul Mackerras long unsigned start_tb, current_tb; 117106d67d54SPaul Mackerras start_tb = old_thread->start_tb; 117206d67d54SPaul Mackerras cu->current_tb = current_tb = mfspr(SPRN_PURR); 117306d67d54SPaul Mackerras old_thread->accum_tb += (current_tb - start_tb); 117406d67d54SPaul Mackerras new_thread->start_tb = current_tb; 117506d67d54SPaul Mackerras } 1176d6bf29b4SPeter Zijlstra #endif /* CONFIG_PPC64 */ 1177d6bf29b4SPeter Zijlstra 1178caca285eSAneesh Kumar K.V #ifdef CONFIG_PPC_STD_MMU_64 117969111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1180d6bf29b4SPeter Zijlstra if (batch->active) { 1181d6bf29b4SPeter Zijlstra current_thread_info()->local_flags |= _TLF_LAZY_MMU; 1182d6bf29b4SPeter Zijlstra if (batch->index) 1183d6bf29b4SPeter Zijlstra __flush_tlb_pending(batch); 1184d6bf29b4SPeter Zijlstra batch->active = 0; 1185d6bf29b4SPeter Zijlstra } 1186caca285eSAneesh Kumar K.V #endif /* CONFIG_PPC_STD_MMU_64 */ 118706d67d54SPaul Mackerras 1188f3d885ccSAnton Blanchard #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1189f3d885ccSAnton Blanchard switch_booke_debug_regs(&new->thread.debug); 1190f3d885ccSAnton Blanchard #else 1191f3d885ccSAnton Blanchard /* 1192f3d885ccSAnton Blanchard * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 1193f3d885ccSAnton Blanchard * schedule DABR 1194f3d885ccSAnton Blanchard */ 1195f3d885ccSAnton Blanchard #ifndef CONFIG_HAVE_HW_BREAKPOINT 1196f3d885ccSAnton Blanchard if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) 1197f3d885ccSAnton Blanchard __set_breakpoint(&new->thread.hw_brk); 1198f3d885ccSAnton Blanchard #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1199f3d885ccSAnton Blanchard #endif 1200f3d885ccSAnton Blanchard 1201f3d885ccSAnton Blanchard /* 1202f3d885ccSAnton Blanchard * We need to save SPRs before treclaim/trecheckpoint as these will 1203f3d885ccSAnton Blanchard * change a number of them. 1204f3d885ccSAnton Blanchard */ 1205f3d885ccSAnton Blanchard save_sprs(&prev->thread); 1206f3d885ccSAnton Blanchard 1207f3d885ccSAnton Blanchard /* Save FPU, Altivec, VSX and SPE state */ 1208f3d885ccSAnton Blanchard giveup_all(prev); 1209f3d885ccSAnton Blanchard 1210dc310669SCyril Bur __switch_to_tm(prev, new); 1211dc310669SCyril Bur 1212e4c0fc5fSNicholas Piggin if (!radix_enabled()) { 121344387e9fSAnton Blanchard /* 1214e4c0fc5fSNicholas Piggin * We can't take a PMU exception inside _switch() since there 1215e4c0fc5fSNicholas Piggin * is a window where the kernel stack SLB and the kernel stack 1216e4c0fc5fSNicholas Piggin * are out of sync. Hard disable here. 121744387e9fSAnton Blanchard */ 121844387e9fSAnton Blanchard hard_irq_disable(); 1219e4c0fc5fSNicholas Piggin } 1220bc2a9408SMichael Neuling 122120dbe670SAnton Blanchard /* 122220dbe670SAnton Blanchard * Call restore_sprs() before calling _switch(). If we move it after 122320dbe670SAnton Blanchard * _switch() then we miss out on calling it for new tasks. The reason 122420dbe670SAnton Blanchard * for this is we manually create a stack frame for new tasks that 122520dbe670SAnton Blanchard * directly returns through ret_from_fork() or 122620dbe670SAnton Blanchard * ret_from_kernel_thread(). See copy_thread() for details. 122720dbe670SAnton Blanchard */ 1228f3d885ccSAnton Blanchard restore_sprs(old_thread, new_thread); 1229f3d885ccSAnton Blanchard 123020dbe670SAnton Blanchard last = _switch(old_thread, new_thread); 123120dbe670SAnton Blanchard 1232caca285eSAneesh Kumar K.V #ifdef CONFIG_PPC_STD_MMU_64 1233d6bf29b4SPeter Zijlstra if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1234d6bf29b4SPeter Zijlstra current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 123569111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1236d6bf29b4SPeter Zijlstra batch->active = 1; 1237d6bf29b4SPeter Zijlstra } 123870fe3d98SCyril Bur 123907d2a628SNicholas Piggin if (current_thread_info()->task->thread.regs) { 124070fe3d98SCyril Bur restore_math(current_thread_info()->task->thread.regs); 124107d2a628SNicholas Piggin 124207d2a628SNicholas Piggin /* 124307d2a628SNicholas Piggin * The copy-paste buffer can only store into foreign real 124407d2a628SNicholas Piggin * addresses, so unprivileged processes can not see the 124507d2a628SNicholas Piggin * data or use it in any way unless they have foreign real 124607d2a628SNicholas Piggin * mappings. We don't have a VAS driver that allocates those 124707d2a628SNicholas Piggin * yet, so no cpabort is required. 124807d2a628SNicholas Piggin */ 124907d2a628SNicholas Piggin if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 125007d2a628SNicholas Piggin /* 125107d2a628SNicholas Piggin * DD1 allows paste into normal system memory, so we 125207d2a628SNicholas Piggin * do an unpaired copy here to clear the buffer and 125307d2a628SNicholas Piggin * prevent a covert channel being set up. 125407d2a628SNicholas Piggin * 125507d2a628SNicholas Piggin * cpabort is not used because it is quite expensive. 125607d2a628SNicholas Piggin */ 125707d2a628SNicholas Piggin asm volatile(PPC_COPY(%0, %1) 125807d2a628SNicholas Piggin : : "r"(dummy_copy_buffer), "r"(0)); 125907d2a628SNicholas Piggin } 126007d2a628SNicholas Piggin } 1261caca285eSAneesh Kumar K.V #endif /* CONFIG_PPC_STD_MMU_64 */ 1262d6bf29b4SPeter Zijlstra 126314cf11afSPaul Mackerras return last; 126414cf11afSPaul Mackerras } 126514cf11afSPaul Mackerras 126606d67d54SPaul Mackerras static int instructions_to_print = 16; 126706d67d54SPaul Mackerras 126806d67d54SPaul Mackerras static void show_instructions(struct pt_regs *regs) 126906d67d54SPaul Mackerras { 127006d67d54SPaul Mackerras int i; 127106d67d54SPaul Mackerras unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 127206d67d54SPaul Mackerras sizeof(int)); 127306d67d54SPaul Mackerras 127406d67d54SPaul Mackerras printk("Instruction dump:"); 127506d67d54SPaul Mackerras 127606d67d54SPaul Mackerras for (i = 0; i < instructions_to_print; i++) { 127706d67d54SPaul Mackerras int instr; 127806d67d54SPaul Mackerras 127906d67d54SPaul Mackerras if (!(i % 8)) 12802ffd04deSAndrew Donnellan pr_cont("\n"); 128106d67d54SPaul Mackerras 12820de2d820SScott Wood #if !defined(CONFIG_BOOKE) 12830de2d820SScott Wood /* If executing with the IMMU off, adjust pc rather 12840de2d820SScott Wood * than print XXXXXXXX. 12850de2d820SScott Wood */ 12860de2d820SScott Wood if (!(regs->msr & MSR_IR)) 12870de2d820SScott Wood pc = (unsigned long)phys_to_virt(pc); 12880de2d820SScott Wood #endif 12890de2d820SScott Wood 129000ae36deSAnton Blanchard if (!__kernel_text_address(pc) || 12917b051f66SAnton Blanchard probe_kernel_address((unsigned int __user *)pc, instr)) { 12922ffd04deSAndrew Donnellan pr_cont("XXXXXXXX "); 129306d67d54SPaul Mackerras } else { 129406d67d54SPaul Mackerras if (regs->nip == pc) 12952ffd04deSAndrew Donnellan pr_cont("<%08x> ", instr); 129606d67d54SPaul Mackerras else 12972ffd04deSAndrew Donnellan pr_cont("%08x ", instr); 129806d67d54SPaul Mackerras } 129906d67d54SPaul Mackerras 130006d67d54SPaul Mackerras pc += sizeof(int); 130106d67d54SPaul Mackerras } 130206d67d54SPaul Mackerras 13032ffd04deSAndrew Donnellan pr_cont("\n"); 130406d67d54SPaul Mackerras } 130506d67d54SPaul Mackerras 1306801c0b2cSMichael Neuling struct regbit { 130706d67d54SPaul Mackerras unsigned long bit; 130806d67d54SPaul Mackerras const char *name; 1309801c0b2cSMichael Neuling }; 1310801c0b2cSMichael Neuling 1311801c0b2cSMichael Neuling static struct regbit msr_bits[] = { 13123bfd0c9cSAnton Blanchard #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 13133bfd0c9cSAnton Blanchard {MSR_SF, "SF"}, 13143bfd0c9cSAnton Blanchard {MSR_HV, "HV"}, 13153bfd0c9cSAnton Blanchard #endif 13163bfd0c9cSAnton Blanchard {MSR_VEC, "VEC"}, 13173bfd0c9cSAnton Blanchard {MSR_VSX, "VSX"}, 13183bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13193bfd0c9cSAnton Blanchard {MSR_CE, "CE"}, 13203bfd0c9cSAnton Blanchard #endif 132106d67d54SPaul Mackerras {MSR_EE, "EE"}, 132206d67d54SPaul Mackerras {MSR_PR, "PR"}, 132306d67d54SPaul Mackerras {MSR_FP, "FP"}, 132406d67d54SPaul Mackerras {MSR_ME, "ME"}, 13253bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13261b98326bSKumar Gala {MSR_DE, "DE"}, 13273bfd0c9cSAnton Blanchard #else 13283bfd0c9cSAnton Blanchard {MSR_SE, "SE"}, 13293bfd0c9cSAnton Blanchard {MSR_BE, "BE"}, 13303bfd0c9cSAnton Blanchard #endif 133106d67d54SPaul Mackerras {MSR_IR, "IR"}, 133206d67d54SPaul Mackerras {MSR_DR, "DR"}, 13333bfd0c9cSAnton Blanchard {MSR_PMM, "PMM"}, 13343bfd0c9cSAnton Blanchard #ifndef CONFIG_BOOKE 13353bfd0c9cSAnton Blanchard {MSR_RI, "RI"}, 13363bfd0c9cSAnton Blanchard {MSR_LE, "LE"}, 13373bfd0c9cSAnton Blanchard #endif 133806d67d54SPaul Mackerras {0, NULL} 133906d67d54SPaul Mackerras }; 134006d67d54SPaul Mackerras 1341801c0b2cSMichael Neuling static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 134206d67d54SPaul Mackerras { 1343801c0b2cSMichael Neuling const char *s = ""; 134406d67d54SPaul Mackerras 134506d67d54SPaul Mackerras for (; bits->bit; ++bits) 134606d67d54SPaul Mackerras if (val & bits->bit) { 1347db5ba5aeSMichael Ellerman pr_cont("%s%s", s, bits->name); 1348801c0b2cSMichael Neuling s = sep; 134906d67d54SPaul Mackerras } 1350801c0b2cSMichael Neuling } 1351801c0b2cSMichael Neuling 1352801c0b2cSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1353801c0b2cSMichael Neuling static struct regbit msr_tm_bits[] = { 1354801c0b2cSMichael Neuling {MSR_TS_T, "T"}, 1355801c0b2cSMichael Neuling {MSR_TS_S, "S"}, 1356801c0b2cSMichael Neuling {MSR_TM, "E"}, 1357801c0b2cSMichael Neuling {0, NULL} 1358801c0b2cSMichael Neuling }; 1359801c0b2cSMichael Neuling 1360801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) 1361801c0b2cSMichael Neuling { 1362801c0b2cSMichael Neuling /* 1363801c0b2cSMichael Neuling * This only prints something if at least one of the TM bit is set. 1364801c0b2cSMichael Neuling * Inside the TM[], the output means: 1365801c0b2cSMichael Neuling * E: Enabled (bit 32) 1366801c0b2cSMichael Neuling * S: Suspended (bit 33) 1367801c0b2cSMichael Neuling * T: Transactional (bit 34) 1368801c0b2cSMichael Neuling */ 1369801c0b2cSMichael Neuling if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1370db5ba5aeSMichael Ellerman pr_cont(",TM["); 1371801c0b2cSMichael Neuling print_bits(val, msr_tm_bits, ""); 1372db5ba5aeSMichael Ellerman pr_cont("]"); 1373801c0b2cSMichael Neuling } 1374801c0b2cSMichael Neuling } 1375801c0b2cSMichael Neuling #else 1376801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) {} 1377801c0b2cSMichael Neuling #endif 1378801c0b2cSMichael Neuling 1379801c0b2cSMichael Neuling static void print_msr_bits(unsigned long val) 1380801c0b2cSMichael Neuling { 1381db5ba5aeSMichael Ellerman pr_cont("<"); 1382801c0b2cSMichael Neuling print_bits(val, msr_bits, ","); 1383801c0b2cSMichael Neuling print_tm_bits(val); 1384db5ba5aeSMichael Ellerman pr_cont(">"); 138506d67d54SPaul Mackerras } 138606d67d54SPaul Mackerras 138706d67d54SPaul Mackerras #ifdef CONFIG_PPC64 1388f6f7dde3Santon@samba.org #define REG "%016lx" 138906d67d54SPaul Mackerras #define REGS_PER_LINE 4 139006d67d54SPaul Mackerras #define LAST_VOLATILE 13 139106d67d54SPaul Mackerras #else 1392f6f7dde3Santon@samba.org #define REG "%08lx" 139306d67d54SPaul Mackerras #define REGS_PER_LINE 8 139406d67d54SPaul Mackerras #define LAST_VOLATILE 12 139506d67d54SPaul Mackerras #endif 139606d67d54SPaul Mackerras 139714cf11afSPaul Mackerras void show_regs(struct pt_regs * regs) 139814cf11afSPaul Mackerras { 139914cf11afSPaul Mackerras int i, trap; 140014cf11afSPaul Mackerras 1401a43cb95dSTejun Heo show_regs_print_info(KERN_DEFAULT); 1402a43cb95dSTejun Heo 140306d67d54SPaul Mackerras printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 140406d67d54SPaul Mackerras regs->nip, regs->link, regs->ctr); 140506d67d54SPaul Mackerras printk("REGS: %p TRAP: %04lx %s (%s)\n", 140696b644bdSSerge E. Hallyn regs, regs->trap, print_tainted(), init_utsname()->release); 140706d67d54SPaul Mackerras printk("MSR: "REG" ", regs->msr); 1408801c0b2cSMichael Neuling print_msr_bits(regs->msr); 1409f6f7dde3Santon@samba.org printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 141014cf11afSPaul Mackerras trap = TRAP(regs); 14115115a026SMichael Neuling if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 14127dae865fSMichael Ellerman pr_cont("CFAR: "REG" ", regs->orig_gpr3); 1413c5400649SAnton Blanchard if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1414ba28c9aaSKumar Gala #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 14157dae865fSMichael Ellerman pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 141614170789SKumar Gala #else 14177dae865fSMichael Ellerman pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 14189db8bcfdSAnton Blanchard #endif 14199db8bcfdSAnton Blanchard #ifdef CONFIG_PPC64 14207dae865fSMichael Ellerman pr_cont("SOFTE: %ld ", regs->softe); 14219db8bcfdSAnton Blanchard #endif 14229db8bcfdSAnton Blanchard #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 14236d888d1aSAnton Blanchard if (MSR_TM_ACTIVE(regs->msr)) 14247dae865fSMichael Ellerman pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 142514170789SKumar Gala #endif 142614cf11afSPaul Mackerras 142714cf11afSPaul Mackerras for (i = 0; i < 32; i++) { 142806d67d54SPaul Mackerras if ((i % REGS_PER_LINE) == 0) 14297dae865fSMichael Ellerman pr_cont("\nGPR%02d: ", i); 14307dae865fSMichael Ellerman pr_cont(REG " ", regs->gpr[i]); 143106d67d54SPaul Mackerras if (i == LAST_VOLATILE && !FULL_REGS(regs)) 143214cf11afSPaul Mackerras break; 143314cf11afSPaul Mackerras } 14347dae865fSMichael Ellerman pr_cont("\n"); 143514cf11afSPaul Mackerras #ifdef CONFIG_KALLSYMS 143614cf11afSPaul Mackerras /* 143714cf11afSPaul Mackerras * Lookup NIP late so we have the best change of getting the 143814cf11afSPaul Mackerras * above info out without failing 143914cf11afSPaul Mackerras */ 1440058c78f4SBenjamin Herrenschmidt printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1441058c78f4SBenjamin Herrenschmidt printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 144214cf11afSPaul Mackerras #endif 144314cf11afSPaul Mackerras show_stack(current, (unsigned long *) regs->gpr[1]); 144406d67d54SPaul Mackerras if (!user_mode(regs)) 144506d67d54SPaul Mackerras show_instructions(regs); 144614cf11afSPaul Mackerras } 144714cf11afSPaul Mackerras 144814cf11afSPaul Mackerras void flush_thread(void) 144914cf11afSPaul Mackerras { 1450e0780b72SK.Prasad #ifdef CONFIG_HAVE_HW_BREAKPOINT 14515aae8a53SK.Prasad flush_ptrace_hw_breakpoint(current); 1452e0780b72SK.Prasad #else /* CONFIG_HAVE_HW_BREAKPOINT */ 14533bffb652SDave Kleikamp set_debug_reg_defaults(¤t->thread); 1454e0780b72SK.Prasad #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 145514cf11afSPaul Mackerras } 145614cf11afSPaul Mackerras 145714cf11afSPaul Mackerras void 145814cf11afSPaul Mackerras release_thread(struct task_struct *t) 145914cf11afSPaul Mackerras { 146014cf11afSPaul Mackerras } 146114cf11afSPaul Mackerras 146214cf11afSPaul Mackerras /* 146355ccf3feSSuresh Siddha * this gets called so that we can store coprocessor state into memory and 146455ccf3feSSuresh Siddha * copy the current task into the new thread. 146514cf11afSPaul Mackerras */ 146655ccf3feSSuresh Siddha int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 146714cf11afSPaul Mackerras { 1468579e633eSAnton Blanchard flush_all_to_thread(src); 1469621b5060SMichael Neuling /* 1470621b5060SMichael Neuling * Flush TM state out so we can copy it. __switch_to_tm() does this 1471621b5060SMichael Neuling * flush but it removes the checkpointed state from the current CPU and 1472621b5060SMichael Neuling * transitions the CPU out of TM mode. Hence we need to call 1473621b5060SMichael Neuling * tm_recheckpoint_new_task() (on the same task) to restore the 1474621b5060SMichael Neuling * checkpointed state back and the TM mode. 14755d176f75SCyril Bur * 14765d176f75SCyril Bur * Can't pass dst because it isn't ready. Doesn't matter, passing 14775d176f75SCyril Bur * dst is only important for __switch_to() 1478621b5060SMichael Neuling */ 1479dc310669SCyril Bur __switch_to_tm(src, src); 1480330a1eb7SMichael Ellerman 148155ccf3feSSuresh Siddha *dst = *src; 1482330a1eb7SMichael Ellerman 1483330a1eb7SMichael Ellerman clear_task_ebb(dst); 1484330a1eb7SMichael Ellerman 148555ccf3feSSuresh Siddha return 0; 148614cf11afSPaul Mackerras } 148714cf11afSPaul Mackerras 1488cec15488SMichael Ellerman static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1489cec15488SMichael Ellerman { 1490cec15488SMichael Ellerman #ifdef CONFIG_PPC_STD_MMU_64 1491cec15488SMichael Ellerman unsigned long sp_vsid; 1492cec15488SMichael Ellerman unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1493cec15488SMichael Ellerman 1494caca285eSAneesh Kumar K.V if (radix_enabled()) 1495caca285eSAneesh Kumar K.V return; 1496caca285eSAneesh Kumar K.V 1497cec15488SMichael Ellerman if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1498cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1499cec15488SMichael Ellerman << SLB_VSID_SHIFT_1T; 1500cec15488SMichael Ellerman else 1501cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1502cec15488SMichael Ellerman << SLB_VSID_SHIFT; 1503cec15488SMichael Ellerman sp_vsid |= SLB_VSID_KERNEL | llp; 1504cec15488SMichael Ellerman p->thread.ksp_vsid = sp_vsid; 1505cec15488SMichael Ellerman #endif 1506cec15488SMichael Ellerman } 1507cec15488SMichael Ellerman 150814cf11afSPaul Mackerras /* 150914cf11afSPaul Mackerras * Copy a thread.. 151014cf11afSPaul Mackerras */ 1511efcac658SAlexey Kardashevskiy 15126eca8933SAlex Dowad /* 15136eca8933SAlex Dowad * Copy architecture-specific thread state 15146eca8933SAlex Dowad */ 15156f2c55b8SAlexey Dobriyan int copy_thread(unsigned long clone_flags, unsigned long usp, 15166eca8933SAlex Dowad unsigned long kthread_arg, struct task_struct *p) 151714cf11afSPaul Mackerras { 151814cf11afSPaul Mackerras struct pt_regs *childregs, *kregs; 151914cf11afSPaul Mackerras extern void ret_from_fork(void); 152058254e10SAl Viro extern void ret_from_kernel_thread(void); 152158254e10SAl Viro void (*f)(void); 15220cec6fd1SAl Viro unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 15235d31a96eSMichael Ellerman struct thread_info *ti = task_thread_info(p); 15245d31a96eSMichael Ellerman 15255d31a96eSMichael Ellerman klp_init_thread_info(ti); 152614cf11afSPaul Mackerras 152714cf11afSPaul Mackerras /* Copy registers */ 152814cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 152914cf11afSPaul Mackerras childregs = (struct pt_regs *) sp; 1530ab75819dSAl Viro if (unlikely(p->flags & PF_KTHREAD)) { 15316eca8933SAlex Dowad /* kernel thread */ 153258254e10SAl Viro memset(childregs, 0, sizeof(struct pt_regs)); 153314cf11afSPaul Mackerras childregs->gpr[1] = sp + sizeof(struct pt_regs); 15347cedd601SAnton Blanchard /* function */ 15357cedd601SAnton Blanchard if (usp) 15367cedd601SAnton Blanchard childregs->gpr[14] = ppc_function_entry((void *)usp); 153758254e10SAl Viro #ifdef CONFIG_PPC64 1538b5e2fc1cSAl Viro clear_tsk_thread_flag(p, TIF_32BIT); 1539138d1ce8SAl Viro childregs->softe = 1; 154006d67d54SPaul Mackerras #endif 15416eca8933SAlex Dowad childregs->gpr[15] = kthread_arg; 154214cf11afSPaul Mackerras p->thread.regs = NULL; /* no user register state */ 1543138d1ce8SAl Viro ti->flags |= _TIF_RESTOREALL; 154458254e10SAl Viro f = ret_from_kernel_thread; 154514cf11afSPaul Mackerras } else { 15466eca8933SAlex Dowad /* user thread */ 1547afa86fc4SAl Viro struct pt_regs *regs = current_pt_regs(); 154858254e10SAl Viro CHECK_FULL_REGS(regs); 154958254e10SAl Viro *childregs = *regs; 1550ea516b11SAl Viro if (usp) 155114cf11afSPaul Mackerras childregs->gpr[1] = usp; 155214cf11afSPaul Mackerras p->thread.regs = childregs; 155358254e10SAl Viro childregs->gpr[3] = 0; /* Result from fork() */ 155406d67d54SPaul Mackerras if (clone_flags & CLONE_SETTLS) { 155506d67d54SPaul Mackerras #ifdef CONFIG_PPC64 15569904b005SDenis Kirjanov if (!is_32bit_task()) 155706d67d54SPaul Mackerras childregs->gpr[13] = childregs->gpr[6]; 155806d67d54SPaul Mackerras else 155906d67d54SPaul Mackerras #endif 156014cf11afSPaul Mackerras childregs->gpr[2] = childregs->gpr[6]; 156114cf11afSPaul Mackerras } 156258254e10SAl Viro 156358254e10SAl Viro f = ret_from_fork; 156406d67d54SPaul Mackerras } 1565d272f667SCyril Bur childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); 156614cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 156714cf11afSPaul Mackerras 156814cf11afSPaul Mackerras /* 156914cf11afSPaul Mackerras * The way this works is that at some point in the future 157014cf11afSPaul Mackerras * some task will call _switch to switch to the new task. 157114cf11afSPaul Mackerras * That will pop off the stack frame created below and start 157214cf11afSPaul Mackerras * the new task running at ret_from_fork. The new task will 157314cf11afSPaul Mackerras * do some house keeping and then return from the fork or clone 157414cf11afSPaul Mackerras * system call, using the stack frame created above. 157514cf11afSPaul Mackerras */ 1576af945cf4SLi Zhong ((unsigned long *)sp)[0] = 0; 157714cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 157814cf11afSPaul Mackerras kregs = (struct pt_regs *) sp; 157914cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 158014cf11afSPaul Mackerras p->thread.ksp = sp; 1581cbc9565eSBenjamin Herrenschmidt #ifdef CONFIG_PPC32 158285218827SKumar Gala p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 158385218827SKumar Gala _ALIGN_UP(sizeof(struct thread_info), 16); 1584cbc9565eSBenjamin Herrenschmidt #endif 158528d170abSOleg Nesterov #ifdef CONFIG_HAVE_HW_BREAKPOINT 158628d170abSOleg Nesterov p->thread.ptrace_bps[0] = NULL; 158728d170abSOleg Nesterov #endif 158828d170abSOleg Nesterov 158918461960SPaul Mackerras p->thread.fp_save_area = NULL; 159018461960SPaul Mackerras #ifdef CONFIG_ALTIVEC 159118461960SPaul Mackerras p->thread.vr_save_area = NULL; 159218461960SPaul Mackerras #endif 159318461960SPaul Mackerras 1594cec15488SMichael Ellerman setup_ksp_vsid(p, sp); 159506d67d54SPaul Mackerras 1596efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64 1597efcac658SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_DSCR)) { 15981021cb26SAnton Blanchard p->thread.dscr_inherit = current->thread.dscr_inherit; 1599db1231dcSAnton Blanchard p->thread.dscr = mfspr(SPRN_DSCR); 1600efcac658SAlexey Kardashevskiy } 160192779245SHaren Myneni if (cpu_has_feature(CPU_FTR_HAS_PPR)) 160292779245SHaren Myneni p->thread.ppr = INIT_PPR; 1603efcac658SAlexey Kardashevskiy #endif 16047cedd601SAnton Blanchard kregs->nip = ppc_function_entry(f); 160514cf11afSPaul Mackerras return 0; 160614cf11afSPaul Mackerras } 160714cf11afSPaul Mackerras 160814cf11afSPaul Mackerras /* 160914cf11afSPaul Mackerras * Set up a thread for executing a new program 161014cf11afSPaul Mackerras */ 161106d67d54SPaul Mackerras void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 161214cf11afSPaul Mackerras { 161390eac727SMichael Ellerman #ifdef CONFIG_PPC64 161490eac727SMichael Ellerman unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 161590eac727SMichael Ellerman #endif 161690eac727SMichael Ellerman 161706d67d54SPaul Mackerras /* 161806d67d54SPaul Mackerras * If we exec out of a kernel thread then thread.regs will not be 161906d67d54SPaul Mackerras * set. Do it now. 162006d67d54SPaul Mackerras */ 162106d67d54SPaul Mackerras if (!current->thread.regs) { 16220cec6fd1SAl Viro struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 16230cec6fd1SAl Viro current->thread.regs = regs - 1; 162406d67d54SPaul Mackerras } 162506d67d54SPaul Mackerras 16268e96a87cSCyril Bur #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 16278e96a87cSCyril Bur /* 16288e96a87cSCyril Bur * Clear any transactional state, we're exec()ing. The cause is 16298e96a87cSCyril Bur * not important as there will never be a recheckpoint so it's not 16308e96a87cSCyril Bur * user visible. 16318e96a87cSCyril Bur */ 16328e96a87cSCyril Bur if (MSR_TM_SUSPENDED(mfmsr())) 16338e96a87cSCyril Bur tm_reclaim_current(0); 16348e96a87cSCyril Bur #endif 16358e96a87cSCyril Bur 163614cf11afSPaul Mackerras memset(regs->gpr, 0, sizeof(regs->gpr)); 163714cf11afSPaul Mackerras regs->ctr = 0; 163814cf11afSPaul Mackerras regs->link = 0; 163914cf11afSPaul Mackerras regs->xer = 0; 164014cf11afSPaul Mackerras regs->ccr = 0; 164114cf11afSPaul Mackerras regs->gpr[1] = sp; 164206d67d54SPaul Mackerras 1643474f8196SRoland McGrath /* 1644474f8196SRoland McGrath * We have just cleared all the nonvolatile GPRs, so make 1645474f8196SRoland McGrath * FULL_REGS(regs) return true. This is necessary to allow 1646474f8196SRoland McGrath * ptrace to examine the thread immediately after exec. 1647474f8196SRoland McGrath */ 1648474f8196SRoland McGrath regs->trap &= ~1UL; 1649474f8196SRoland McGrath 165006d67d54SPaul Mackerras #ifdef CONFIG_PPC32 165106d67d54SPaul Mackerras regs->mq = 0; 165206d67d54SPaul Mackerras regs->nip = start; 165314cf11afSPaul Mackerras regs->msr = MSR_USER; 165406d67d54SPaul Mackerras #else 16559904b005SDenis Kirjanov if (!is_32bit_task()) { 165694af3abfSRusty Russell unsigned long entry; 165706d67d54SPaul Mackerras 165894af3abfSRusty Russell if (is_elf2_task()) { 165994af3abfSRusty Russell /* Look ma, no function descriptors! */ 166094af3abfSRusty Russell entry = start; 166194af3abfSRusty Russell 166294af3abfSRusty Russell /* 166394af3abfSRusty Russell * Ulrich says: 166494af3abfSRusty Russell * The latest iteration of the ABI requires that when 166594af3abfSRusty Russell * calling a function (at its global entry point), 166694af3abfSRusty Russell * the caller must ensure r12 holds the entry point 166794af3abfSRusty Russell * address (so that the function can quickly 166894af3abfSRusty Russell * establish addressability). 166994af3abfSRusty Russell */ 167094af3abfSRusty Russell regs->gpr[12] = start; 167194af3abfSRusty Russell /* Make sure that's restored on entry to userspace. */ 167294af3abfSRusty Russell set_thread_flag(TIF_RESTOREALL); 167394af3abfSRusty Russell } else { 167494af3abfSRusty Russell unsigned long toc; 167594af3abfSRusty Russell 167694af3abfSRusty Russell /* start is a relocated pointer to the function 167794af3abfSRusty Russell * descriptor for the elf _start routine. The first 167894af3abfSRusty Russell * entry in the function descriptor is the entry 167994af3abfSRusty Russell * address of _start and the second entry is the TOC 168094af3abfSRusty Russell * value we need to use. 168106d67d54SPaul Mackerras */ 168206d67d54SPaul Mackerras __get_user(entry, (unsigned long __user *)start); 168306d67d54SPaul Mackerras __get_user(toc, (unsigned long __user *)start+1); 168406d67d54SPaul Mackerras 168506d67d54SPaul Mackerras /* Check whether the e_entry function descriptor entries 168606d67d54SPaul Mackerras * need to be relocated before we can use them. 168706d67d54SPaul Mackerras */ 168806d67d54SPaul Mackerras if (load_addr != 0) { 168906d67d54SPaul Mackerras entry += load_addr; 169006d67d54SPaul Mackerras toc += load_addr; 169106d67d54SPaul Mackerras } 169206d67d54SPaul Mackerras regs->gpr[2] = toc; 169394af3abfSRusty Russell } 169494af3abfSRusty Russell regs->nip = entry; 169506d67d54SPaul Mackerras regs->msr = MSR_USER64; 1696d4bf9a78SStephen Rothwell } else { 1697d4bf9a78SStephen Rothwell regs->nip = start; 1698d4bf9a78SStephen Rothwell regs->gpr[2] = 0; 1699d4bf9a78SStephen Rothwell regs->msr = MSR_USER32; 170006d67d54SPaul Mackerras } 170106d67d54SPaul Mackerras #endif 1702ce48b210SMichael Neuling #ifdef CONFIG_VSX 1703ce48b210SMichael Neuling current->thread.used_vsr = 0; 1704ce48b210SMichael Neuling #endif 17051195892cSBreno Leitao current->thread.load_fp = 0; 1706de79f7b9SPaul Mackerras memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 170718461960SPaul Mackerras current->thread.fp_save_area = NULL; 170814cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 1709de79f7b9SPaul Mackerras memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1710de79f7b9SPaul Mackerras current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 171118461960SPaul Mackerras current->thread.vr_save_area = NULL; 171214cf11afSPaul Mackerras current->thread.vrsave = 0; 171314cf11afSPaul Mackerras current->thread.used_vr = 0; 17141195892cSBreno Leitao current->thread.load_vec = 0; 171514cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 171614cf11afSPaul Mackerras #ifdef CONFIG_SPE 171714cf11afSPaul Mackerras memset(current->thread.evr, 0, sizeof(current->thread.evr)); 171814cf11afSPaul Mackerras current->thread.acc = 0; 171914cf11afSPaul Mackerras current->thread.spefscr = 0; 172014cf11afSPaul Mackerras current->thread.used_spe = 0; 172114cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 1722bc2a9408SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1723bc2a9408SMichael Neuling current->thread.tm_tfhar = 0; 1724bc2a9408SMichael Neuling current->thread.tm_texasr = 0; 1725bc2a9408SMichael Neuling current->thread.tm_tfiar = 0; 17267f22ced4SBreno Leitao current->thread.load_tm = 0; 1727bc2a9408SMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 172814cf11afSPaul Mackerras } 1729e1802b06SAnton Blanchard EXPORT_SYMBOL(start_thread); 173014cf11afSPaul Mackerras 173114cf11afSPaul Mackerras #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 173214cf11afSPaul Mackerras | PR_FP_EXC_RES | PR_FP_EXC_INV) 173314cf11afSPaul Mackerras 173414cf11afSPaul Mackerras int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 173514cf11afSPaul Mackerras { 173614cf11afSPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 173714cf11afSPaul Mackerras 173814cf11afSPaul Mackerras /* This is a bit hairy. If we are an SPE enabled processor 173914cf11afSPaul Mackerras * (have embedded fp) we store the IEEE exception enable flags in 174014cf11afSPaul Mackerras * fpexc_mode. fpexc_mode is also used for setting FP exception 174114cf11afSPaul Mackerras * mode (asyn, precise, disabled) for 'Classic' FP. */ 174214cf11afSPaul Mackerras if (val & PR_FP_EXC_SW_ENABLE) { 174314cf11afSPaul Mackerras #ifdef CONFIG_SPE 17445e14d21eSKumar Gala if (cpu_has_feature(CPU_FTR_SPE)) { 1745640e9225SJoseph Myers /* 1746640e9225SJoseph Myers * When the sticky exception bits are set 1747640e9225SJoseph Myers * directly by userspace, it must call prctl 1748640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1749640e9225SJoseph Myers * in the existing prctl settings) or 1750640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1751640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1752640e9225SJoseph Myers * saving and restoring the whole 1753640e9225SJoseph Myers * floating-point environment need to do so 1754640e9225SJoseph Myers * anyway to restore the prctl settings from 1755640e9225SJoseph Myers * the saved environment. 1756640e9225SJoseph Myers */ 1757640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 175814cf11afSPaul Mackerras tsk->thread.fpexc_mode = val & 175914cf11afSPaul Mackerras (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 176006d67d54SPaul Mackerras return 0; 17615e14d21eSKumar Gala } else { 17625e14d21eSKumar Gala return -EINVAL; 17635e14d21eSKumar Gala } 176414cf11afSPaul Mackerras #else 176514cf11afSPaul Mackerras return -EINVAL; 176614cf11afSPaul Mackerras #endif 176706d67d54SPaul Mackerras } 176806d67d54SPaul Mackerras 176914cf11afSPaul Mackerras /* on a CONFIG_SPE this does not hurt us. The bits that 177014cf11afSPaul Mackerras * __pack_fe01 use do not overlap with bits used for 177114cf11afSPaul Mackerras * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 177214cf11afSPaul Mackerras * on CONFIG_SPE implementations are reserved so writing to 177314cf11afSPaul Mackerras * them does not change anything */ 177414cf11afSPaul Mackerras if (val > PR_FP_EXC_PRECISE) 177514cf11afSPaul Mackerras return -EINVAL; 177614cf11afSPaul Mackerras tsk->thread.fpexc_mode = __pack_fe01(val); 177714cf11afSPaul Mackerras if (regs != NULL && (regs->msr & MSR_FP) != 0) 177814cf11afSPaul Mackerras regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 177914cf11afSPaul Mackerras | tsk->thread.fpexc_mode; 178014cf11afSPaul Mackerras return 0; 178114cf11afSPaul Mackerras } 178214cf11afSPaul Mackerras 178314cf11afSPaul Mackerras int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 178414cf11afSPaul Mackerras { 178514cf11afSPaul Mackerras unsigned int val; 178614cf11afSPaul Mackerras 178714cf11afSPaul Mackerras if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 178814cf11afSPaul Mackerras #ifdef CONFIG_SPE 1789640e9225SJoseph Myers if (cpu_has_feature(CPU_FTR_SPE)) { 1790640e9225SJoseph Myers /* 1791640e9225SJoseph Myers * When the sticky exception bits are set 1792640e9225SJoseph Myers * directly by userspace, it must call prctl 1793640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1794640e9225SJoseph Myers * in the existing prctl settings) or 1795640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1796640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1797640e9225SJoseph Myers * saving and restoring the whole 1798640e9225SJoseph Myers * floating-point environment need to do so 1799640e9225SJoseph Myers * anyway to restore the prctl settings from 1800640e9225SJoseph Myers * the saved environment. 1801640e9225SJoseph Myers */ 1802640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 180314cf11afSPaul Mackerras val = tsk->thread.fpexc_mode; 1804640e9225SJoseph Myers } else 18055e14d21eSKumar Gala return -EINVAL; 180614cf11afSPaul Mackerras #else 180714cf11afSPaul Mackerras return -EINVAL; 180814cf11afSPaul Mackerras #endif 180914cf11afSPaul Mackerras else 181014cf11afSPaul Mackerras val = __unpack_fe01(tsk->thread.fpexc_mode); 181114cf11afSPaul Mackerras return put_user(val, (unsigned int __user *) adr); 181214cf11afSPaul Mackerras } 181314cf11afSPaul Mackerras 1814fab5db97SPaul Mackerras int set_endian(struct task_struct *tsk, unsigned int val) 1815fab5db97SPaul Mackerras { 1816fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1817fab5db97SPaul Mackerras 1818fab5db97SPaul Mackerras if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1819fab5db97SPaul Mackerras (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1820fab5db97SPaul Mackerras return -EINVAL; 1821fab5db97SPaul Mackerras 1822fab5db97SPaul Mackerras if (regs == NULL) 1823fab5db97SPaul Mackerras return -EINVAL; 1824fab5db97SPaul Mackerras 1825fab5db97SPaul Mackerras if (val == PR_ENDIAN_BIG) 1826fab5db97SPaul Mackerras regs->msr &= ~MSR_LE; 1827fab5db97SPaul Mackerras else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1828fab5db97SPaul Mackerras regs->msr |= MSR_LE; 1829fab5db97SPaul Mackerras else 1830fab5db97SPaul Mackerras return -EINVAL; 1831fab5db97SPaul Mackerras 1832fab5db97SPaul Mackerras return 0; 1833fab5db97SPaul Mackerras } 1834fab5db97SPaul Mackerras 1835fab5db97SPaul Mackerras int get_endian(struct task_struct *tsk, unsigned long adr) 1836fab5db97SPaul Mackerras { 1837fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1838fab5db97SPaul Mackerras unsigned int val; 1839fab5db97SPaul Mackerras 1840fab5db97SPaul Mackerras if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1841fab5db97SPaul Mackerras !cpu_has_feature(CPU_FTR_REAL_LE)) 1842fab5db97SPaul Mackerras return -EINVAL; 1843fab5db97SPaul Mackerras 1844fab5db97SPaul Mackerras if (regs == NULL) 1845fab5db97SPaul Mackerras return -EINVAL; 1846fab5db97SPaul Mackerras 1847fab5db97SPaul Mackerras if (regs->msr & MSR_LE) { 1848fab5db97SPaul Mackerras if (cpu_has_feature(CPU_FTR_REAL_LE)) 1849fab5db97SPaul Mackerras val = PR_ENDIAN_LITTLE; 1850fab5db97SPaul Mackerras else 1851fab5db97SPaul Mackerras val = PR_ENDIAN_PPC_LITTLE; 1852fab5db97SPaul Mackerras } else 1853fab5db97SPaul Mackerras val = PR_ENDIAN_BIG; 1854fab5db97SPaul Mackerras 1855fab5db97SPaul Mackerras return put_user(val, (unsigned int __user *)adr); 1856fab5db97SPaul Mackerras } 1857fab5db97SPaul Mackerras 1858e9370ae1SPaul Mackerras int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1859e9370ae1SPaul Mackerras { 1860e9370ae1SPaul Mackerras tsk->thread.align_ctl = val; 1861e9370ae1SPaul Mackerras return 0; 1862e9370ae1SPaul Mackerras } 1863e9370ae1SPaul Mackerras 1864e9370ae1SPaul Mackerras int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1865e9370ae1SPaul Mackerras { 1866e9370ae1SPaul Mackerras return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1867e9370ae1SPaul Mackerras } 1868e9370ae1SPaul Mackerras 1869bb72c481SPaul Mackerras static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1870bb72c481SPaul Mackerras unsigned long nbytes) 1871bb72c481SPaul Mackerras { 1872bb72c481SPaul Mackerras unsigned long stack_page; 1873bb72c481SPaul Mackerras unsigned long cpu = task_cpu(p); 1874bb72c481SPaul Mackerras 1875bb72c481SPaul Mackerras /* 1876bb72c481SPaul Mackerras * Avoid crashing if the stack has overflowed and corrupted 1877bb72c481SPaul Mackerras * task_cpu(p), which is in the thread_info struct. 1878bb72c481SPaul Mackerras */ 1879bb72c481SPaul Mackerras if (cpu < NR_CPUS && cpu_possible(cpu)) { 1880bb72c481SPaul Mackerras stack_page = (unsigned long) hardirq_ctx[cpu]; 1881bb72c481SPaul Mackerras if (sp >= stack_page + sizeof(struct thread_struct) 1882bb72c481SPaul Mackerras && sp <= stack_page + THREAD_SIZE - nbytes) 1883bb72c481SPaul Mackerras return 1; 1884bb72c481SPaul Mackerras 1885bb72c481SPaul Mackerras stack_page = (unsigned long) softirq_ctx[cpu]; 1886bb72c481SPaul Mackerras if (sp >= stack_page + sizeof(struct thread_struct) 1887bb72c481SPaul Mackerras && sp <= stack_page + THREAD_SIZE - nbytes) 1888bb72c481SPaul Mackerras return 1; 1889bb72c481SPaul Mackerras } 1890bb72c481SPaul Mackerras return 0; 1891bb72c481SPaul Mackerras } 1892bb72c481SPaul Mackerras 18932f25194dSAnton Blanchard int validate_sp(unsigned long sp, struct task_struct *p, 189414cf11afSPaul Mackerras unsigned long nbytes) 189514cf11afSPaul Mackerras { 18960cec6fd1SAl Viro unsigned long stack_page = (unsigned long)task_stack_page(p); 189714cf11afSPaul Mackerras 189814cf11afSPaul Mackerras if (sp >= stack_page + sizeof(struct thread_struct) 189914cf11afSPaul Mackerras && sp <= stack_page + THREAD_SIZE - nbytes) 190014cf11afSPaul Mackerras return 1; 190114cf11afSPaul Mackerras 1902bb72c481SPaul Mackerras return valid_irq_stack(sp, p, nbytes); 190314cf11afSPaul Mackerras } 190414cf11afSPaul Mackerras 19052f25194dSAnton Blanchard EXPORT_SYMBOL(validate_sp); 19062f25194dSAnton Blanchard 190706d67d54SPaul Mackerras unsigned long get_wchan(struct task_struct *p) 190806d67d54SPaul Mackerras { 190906d67d54SPaul Mackerras unsigned long ip, sp; 191006d67d54SPaul Mackerras int count = 0; 191106d67d54SPaul Mackerras 191206d67d54SPaul Mackerras if (!p || p == current || p->state == TASK_RUNNING) 191306d67d54SPaul Mackerras return 0; 191406d67d54SPaul Mackerras 191506d67d54SPaul Mackerras sp = p->thread.ksp; 1916ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 191706d67d54SPaul Mackerras return 0; 191806d67d54SPaul Mackerras 191906d67d54SPaul Mackerras do { 192006d67d54SPaul Mackerras sp = *(unsigned long *)sp; 1921ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 192206d67d54SPaul Mackerras return 0; 192306d67d54SPaul Mackerras if (count > 0) { 1924ec2b36b9SBenjamin Herrenschmidt ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 192506d67d54SPaul Mackerras if (!in_sched_functions(ip)) 192606d67d54SPaul Mackerras return ip; 192706d67d54SPaul Mackerras } 192806d67d54SPaul Mackerras } while (count++ < 16); 192906d67d54SPaul Mackerras return 0; 193006d67d54SPaul Mackerras } 193106d67d54SPaul Mackerras 1932c4d04be1SJohannes Berg static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 193314cf11afSPaul Mackerras 193414cf11afSPaul Mackerras void show_stack(struct task_struct *tsk, unsigned long *stack) 193514cf11afSPaul Mackerras { 193606d67d54SPaul Mackerras unsigned long sp, ip, lr, newsp; 193714cf11afSPaul Mackerras int count = 0; 193806d67d54SPaul Mackerras int firstframe = 1; 19396794c782SSteven Rostedt #ifdef CONFIG_FUNCTION_GRAPH_TRACER 19406794c782SSteven Rostedt int curr_frame = current->curr_ret_stack; 19416794c782SSteven Rostedt extern void return_to_handler(void); 19429135c3ccSSteven Rostedt unsigned long rth = (unsigned long)return_to_handler; 19436794c782SSteven Rostedt #endif 194414cf11afSPaul Mackerras 194514cf11afSPaul Mackerras sp = (unsigned long) stack; 194614cf11afSPaul Mackerras if (tsk == NULL) 194714cf11afSPaul Mackerras tsk = current; 194814cf11afSPaul Mackerras if (sp == 0) { 194914cf11afSPaul Mackerras if (tsk == current) 1950acf620ecSAnton Blanchard sp = current_stack_pointer(); 195114cf11afSPaul Mackerras else 195214cf11afSPaul Mackerras sp = tsk->thread.ksp; 195314cf11afSPaul Mackerras } 195414cf11afSPaul Mackerras 195506d67d54SPaul Mackerras lr = 0; 195606d67d54SPaul Mackerras printk("Call Trace:\n"); 195714cf11afSPaul Mackerras do { 1958ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 195906d67d54SPaul Mackerras return; 196006d67d54SPaul Mackerras 196106d67d54SPaul Mackerras stack = (unsigned long *) sp; 196206d67d54SPaul Mackerras newsp = stack[0]; 1963ec2b36b9SBenjamin Herrenschmidt ip = stack[STACK_FRAME_LR_SAVE]; 196406d67d54SPaul Mackerras if (!firstframe || ip != lr) { 1965058c78f4SBenjamin Herrenschmidt printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 19666794c782SSteven Rostedt #ifdef CONFIG_FUNCTION_GRAPH_TRACER 19677d56c65aSAnton Blanchard if ((ip == rth) && curr_frame >= 0) { 19689a1f490fSMichael Ellerman pr_cont(" (%pS)", 19696794c782SSteven Rostedt (void *)current->ret_stack[curr_frame].ret); 19706794c782SSteven Rostedt curr_frame--; 19716794c782SSteven Rostedt } 19726794c782SSteven Rostedt #endif 197306d67d54SPaul Mackerras if (firstframe) 19749a1f490fSMichael Ellerman pr_cont(" (unreliable)"); 19759a1f490fSMichael Ellerman pr_cont("\n"); 197614cf11afSPaul Mackerras } 197706d67d54SPaul Mackerras firstframe = 0; 197806d67d54SPaul Mackerras 197906d67d54SPaul Mackerras /* 198006d67d54SPaul Mackerras * See if this is an exception frame. 198106d67d54SPaul Mackerras * We look for the "regshere" marker in the current frame. 198206d67d54SPaul Mackerras */ 1983ec2b36b9SBenjamin Herrenschmidt if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1984ec2b36b9SBenjamin Herrenschmidt && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 198506d67d54SPaul Mackerras struct pt_regs *regs = (struct pt_regs *) 198606d67d54SPaul Mackerras (sp + STACK_FRAME_OVERHEAD); 198706d67d54SPaul Mackerras lr = regs->link; 19889be9be2eSPaul Mackerras printk("--- interrupt: %lx at %pS\n LR = %pS\n", 1989058c78f4SBenjamin Herrenschmidt regs->trap, (void *)regs->nip, (void *)lr); 199006d67d54SPaul Mackerras firstframe = 1; 199114cf11afSPaul Mackerras } 199206d67d54SPaul Mackerras 199306d67d54SPaul Mackerras sp = newsp; 199406d67d54SPaul Mackerras } while (count++ < kstack_depth_to_print); 199506d67d54SPaul Mackerras } 199606d67d54SPaul Mackerras 1997cb2c9b27SAnton Blanchard #ifdef CONFIG_PPC64 1998fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 19990e37739bSMichael Ellerman void notrace __ppc64_runlatch_on(void) 2000cb2c9b27SAnton Blanchard { 2001fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2002cb2c9b27SAnton Blanchard unsigned long ctrl; 2003cb2c9b27SAnton Blanchard 2004cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2005cb2c9b27SAnton Blanchard ctrl |= CTRL_RUNLATCH; 2006cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2007cb2c9b27SAnton Blanchard 2008fae2e0fbSBenjamin Herrenschmidt ti->local_flags |= _TLF_RUNLATCH; 2009cb2c9b27SAnton Blanchard } 2010cb2c9b27SAnton Blanchard 2011fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 20120e37739bSMichael Ellerman void notrace __ppc64_runlatch_off(void) 2013cb2c9b27SAnton Blanchard { 2014fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2015cb2c9b27SAnton Blanchard unsigned long ctrl; 2016cb2c9b27SAnton Blanchard 2017fae2e0fbSBenjamin Herrenschmidt ti->local_flags &= ~_TLF_RUNLATCH; 2018cb2c9b27SAnton Blanchard 2019cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2020cb2c9b27SAnton Blanchard ctrl &= ~CTRL_RUNLATCH; 2021cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2022cb2c9b27SAnton Blanchard } 2023fe1952fcSBenjamin Herrenschmidt #endif /* CONFIG_PPC64 */ 2024f6a61680SBenjamin Herrenschmidt 2025d839088cSAnton Blanchard unsigned long arch_align_stack(unsigned long sp) 2026d839088cSAnton Blanchard { 2027d839088cSAnton Blanchard if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 2028d839088cSAnton Blanchard sp -= get_random_int() & ~PAGE_MASK; 2029d839088cSAnton Blanchard return sp & ~0xf; 2030d839088cSAnton Blanchard } 2031912f9ee2SAnton Blanchard 2032912f9ee2SAnton Blanchard static inline unsigned long brk_rnd(void) 2033912f9ee2SAnton Blanchard { 2034912f9ee2SAnton Blanchard unsigned long rnd = 0; 2035912f9ee2SAnton Blanchard 2036912f9ee2SAnton Blanchard /* 8MB for 32bit, 1GB for 64bit */ 2037912f9ee2SAnton Blanchard if (is_32bit_task()) 20385ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 2039912f9ee2SAnton Blanchard else 20405ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 2041912f9ee2SAnton Blanchard 2042912f9ee2SAnton Blanchard return rnd << PAGE_SHIFT; 2043912f9ee2SAnton Blanchard } 2044912f9ee2SAnton Blanchard 2045912f9ee2SAnton Blanchard unsigned long arch_randomize_brk(struct mm_struct *mm) 2046912f9ee2SAnton Blanchard { 20478bbde7a7SAnton Blanchard unsigned long base = mm->brk; 20488bbde7a7SAnton Blanchard unsigned long ret; 20498bbde7a7SAnton Blanchard 2050ce7a35c7SKumar Gala #ifdef CONFIG_PPC_STD_MMU_64 20518bbde7a7SAnton Blanchard /* 20528bbde7a7SAnton Blanchard * If we are using 1TB segments and we are allowed to randomise 20538bbde7a7SAnton Blanchard * the heap, we can put it above 1TB so it is backed by a 1TB 20548bbde7a7SAnton Blanchard * segment. Otherwise the heap will be in the bottom 1TB 20558bbde7a7SAnton Blanchard * which always uses 256MB segments and this may result in a 2056caca285eSAneesh Kumar K.V * performance penalty. We don't need to worry about radix. For 2057caca285eSAneesh Kumar K.V * radix, mmu_highuser_ssize remains unchanged from 256MB. 20588bbde7a7SAnton Blanchard */ 20598bbde7a7SAnton Blanchard if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 20608bbde7a7SAnton Blanchard base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 20618bbde7a7SAnton Blanchard #endif 20628bbde7a7SAnton Blanchard 20638bbde7a7SAnton Blanchard ret = PAGE_ALIGN(base + brk_rnd()); 2064912f9ee2SAnton Blanchard 2065912f9ee2SAnton Blanchard if (ret < mm->brk) 2066912f9ee2SAnton Blanchard return mm->brk; 2067912f9ee2SAnton Blanchard 2068912f9ee2SAnton Blanchard return ret; 2069912f9ee2SAnton Blanchard } 2070501cb16dSAnton Blanchard 2071