12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 214cf11afSPaul Mackerras /* 314cf11afSPaul Mackerras * Derived from "arch/i386/kernel/process.c" 414cf11afSPaul Mackerras * Copyright (C) 1995 Linus Torvalds 514cf11afSPaul Mackerras * 614cf11afSPaul Mackerras * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 714cf11afSPaul Mackerras * Paul Mackerras (paulus@cs.anu.edu.au) 814cf11afSPaul Mackerras * 914cf11afSPaul Mackerras * PowerPC version 1014cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 1114cf11afSPaul Mackerras */ 1214cf11afSPaul Mackerras 1314cf11afSPaul Mackerras #include <linux/errno.h> 1414cf11afSPaul Mackerras #include <linux/sched.h> 15b17b0153SIngo Molnar #include <linux/sched/debug.h> 1629930025SIngo Molnar #include <linux/sched/task.h> 1768db0cf1SIngo Molnar #include <linux/sched/task_stack.h> 1814cf11afSPaul Mackerras #include <linux/kernel.h> 1914cf11afSPaul Mackerras #include <linux/mm.h> 2014cf11afSPaul Mackerras #include <linux/smp.h> 2114cf11afSPaul Mackerras #include <linux/stddef.h> 2214cf11afSPaul Mackerras #include <linux/unistd.h> 2314cf11afSPaul Mackerras #include <linux/ptrace.h> 2414cf11afSPaul Mackerras #include <linux/slab.h> 2514cf11afSPaul Mackerras #include <linux/user.h> 2614cf11afSPaul Mackerras #include <linux/elf.h> 2714cf11afSPaul Mackerras #include <linux/prctl.h> 2814cf11afSPaul Mackerras #include <linux/init_task.h> 294b16f8e2SPaul Gortmaker #include <linux/export.h> 3014cf11afSPaul Mackerras #include <linux/kallsyms.h> 3114cf11afSPaul Mackerras #include <linux/mqueue.h> 3214cf11afSPaul Mackerras #include <linux/hardirq.h> 3306d67d54SPaul Mackerras #include <linux/utsname.h> 346794c782SSteven Rostedt #include <linux/ftrace.h> 3579741dd3SMartin Schwidefsky #include <linux/kernel_stat.h> 36d839088cSAnton Blanchard #include <linux/personality.h> 37d839088cSAnton Blanchard #include <linux/random.h> 385aae8a53SK.Prasad #include <linux/hw_breakpoint.h> 397b051f66SAnton Blanchard #include <linux/uaccess.h> 407f92bc56SDaniel Axtens #include <linux/elf-randomize.h> 4106bb53b3SRam Pai #include <linux/pkeys.h> 42fb2d9505SChristophe Leroy #include <linux/seq_buf.h> 4314cf11afSPaul Mackerras 4414cf11afSPaul Mackerras #include <asm/io.h> 4514cf11afSPaul Mackerras #include <asm/processor.h> 4614cf11afSPaul Mackerras #include <asm/mmu.h> 4714cf11afSPaul Mackerras #include <asm/prom.h> 4876032de8SMichael Ellerman #include <asm/machdep.h> 49c6622f63SPaul Mackerras #include <asm/time.h> 50ae3a197eSDavid Howells #include <asm/runlatch.h> 51a7f31841SArnd Bergmann #include <asm/syscalls.h> 52ae3a197eSDavid Howells #include <asm/switch_to.h> 53fb09692eSMichael Neuling #include <asm/tm.h> 54ae3a197eSDavid Howells #include <asm/debug.h> 5506d67d54SPaul Mackerras #ifdef CONFIG_PPC64 5606d67d54SPaul Mackerras #include <asm/firmware.h> 57c2e480baSMadhavan Srinivasan #include <asm/hw_irq.h> 5806d67d54SPaul Mackerras #endif 597cedd601SAnton Blanchard #include <asm/code-patching.h> 607f92bc56SDaniel Axtens #include <asm/exec.h> 615d31a96eSMichael Ellerman #include <asm/livepatch.h> 62b92a226eSKevin Hao #include <asm/cpu_has_feature.h> 630545d543SDaniel Axtens #include <asm/asm-prototypes.h> 64c9386bfdSChristophe Leroy #include <asm/stacktrace.h> 65c1fe190cSMichael Neuling #include <asm/hw_breakpoint.h> 665d31a96eSMichael Ellerman 67d6a61bfcSLuis Machado #include <linux/kprobes.h> 68d6a61bfcSLuis Machado #include <linux/kdebug.h> 6914cf11afSPaul Mackerras 708b3c34cfSMichael Neuling /* Transactional Memory debug */ 718b3c34cfSMichael Neuling #ifdef TM_DEBUG_SW 728b3c34cfSMichael Neuling #define TM_DEBUG(x...) printk(KERN_INFO x) 738b3c34cfSMichael Neuling #else 748b3c34cfSMichael Neuling #define TM_DEBUG(x...) do { } while(0) 758b3c34cfSMichael Neuling #endif 768b3c34cfSMichael Neuling 7714cf11afSPaul Mackerras extern unsigned long _get_SP(void); 7814cf11afSPaul Mackerras 79d31626f7SPaul Mackerras #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 8054820530SMichael Ellerman /* 8154820530SMichael Ellerman * Are we running in "Suspend disabled" mode? If so we have to block any 8254820530SMichael Ellerman * sigreturn that would get us into suspended state, and we also warn in some 8354820530SMichael Ellerman * other paths that we should never reach with suspend disabled. 8454820530SMichael Ellerman */ 8554820530SMichael Ellerman bool tm_suspend_disabled __ro_after_init = false; 8654820530SMichael Ellerman 87b86fd2bdSAnton Blanchard static void check_if_tm_restore_required(struct task_struct *tsk) 88d31626f7SPaul Mackerras { 89d31626f7SPaul Mackerras /* 90d31626f7SPaul Mackerras * If we are saving the current thread's registers, and the 91d31626f7SPaul Mackerras * thread is in a transactional state, set the TIF_RESTORE_TM 92d31626f7SPaul Mackerras * bit so that we know to restore the registers before 93d31626f7SPaul Mackerras * returning to userspace. 94d31626f7SPaul Mackerras */ 95d31626f7SPaul Mackerras if (tsk == current && tsk->thread.regs && 96d31626f7SPaul Mackerras MSR_TM_ACTIVE(tsk->thread.regs->msr) && 97d31626f7SPaul Mackerras !test_thread_flag(TIF_RESTORE_TM)) { 98829023dfSAnshuman Khandual tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 99d31626f7SPaul Mackerras set_thread_flag(TIF_RESTORE_TM); 100d31626f7SPaul Mackerras } 101d31626f7SPaul Mackerras } 102dc16b553SCyril Bur 103d31626f7SPaul Mackerras #else 104b86fd2bdSAnton Blanchard static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 105d31626f7SPaul Mackerras #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 106d31626f7SPaul Mackerras 1073eb5d588SAnton Blanchard bool strict_msr_control; 1083eb5d588SAnton Blanchard EXPORT_SYMBOL(strict_msr_control); 1093eb5d588SAnton Blanchard 1103eb5d588SAnton Blanchard static int __init enable_strict_msr_control(char *str) 1113eb5d588SAnton Blanchard { 1123eb5d588SAnton Blanchard strict_msr_control = true; 1133eb5d588SAnton Blanchard pr_info("Enabling strict facility control\n"); 1143eb5d588SAnton Blanchard 1153eb5d588SAnton Blanchard return 0; 1163eb5d588SAnton Blanchard } 1173eb5d588SAnton Blanchard early_param("ppc_strict_facility_enable", enable_strict_msr_control); 1183eb5d588SAnton Blanchard 119e2b36d59SNicholas Piggin /* notrace because it's called by restore_math */ 120e2b36d59SNicholas Piggin unsigned long notrace msr_check_and_set(unsigned long bits) 121a0e72cf1SAnton Blanchard { 122a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 123a0e72cf1SAnton Blanchard unsigned long newmsr; 124a0e72cf1SAnton Blanchard 125a0e72cf1SAnton Blanchard newmsr = oldmsr | bits; 126a0e72cf1SAnton Blanchard 127a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 128a0e72cf1SAnton Blanchard newmsr |= MSR_VSX; 129a0e72cf1SAnton Blanchard 130a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 131a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 1323cee070aSCyril Bur 1333cee070aSCyril Bur return newmsr; 134a0e72cf1SAnton Blanchard } 135d1c72112SSimon Guo EXPORT_SYMBOL_GPL(msr_check_and_set); 136a0e72cf1SAnton Blanchard 137e2b36d59SNicholas Piggin /* notrace because it's called by restore_math */ 138e2b36d59SNicholas Piggin void notrace __msr_check_and_clear(unsigned long bits) 139a0e72cf1SAnton Blanchard { 140a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 141a0e72cf1SAnton Blanchard unsigned long newmsr; 142a0e72cf1SAnton Blanchard 143a0e72cf1SAnton Blanchard newmsr = oldmsr & ~bits; 144a0e72cf1SAnton Blanchard 145a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 146a0e72cf1SAnton Blanchard newmsr &= ~MSR_VSX; 147a0e72cf1SAnton Blanchard 148a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 149a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 150a0e72cf1SAnton Blanchard } 1513eb5d588SAnton Blanchard EXPORT_SYMBOL(__msr_check_and_clear); 152a0e72cf1SAnton Blanchard 153037f0eedSKevin Hao #ifdef CONFIG_PPC_FPU 1541cdf039bSMathieu Malaterre static void __giveup_fpu(struct task_struct *tsk) 1558792468dSCyril Bur { 1568eb98037SAnton Blanchard unsigned long msr; 1578eb98037SAnton Blanchard 1588792468dSCyril Bur save_fpu(tsk); 1598eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 160fe1ef6bcSMark Cave-Ayland msr &= ~(MSR_FP|MSR_FE0|MSR_FE1); 1618792468dSCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 1628eb98037SAnton Blanchard msr &= ~MSR_VSX; 1638eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 1648792468dSCyril Bur } 1658792468dSCyril Bur 16698da581eSAnton Blanchard void giveup_fpu(struct task_struct *tsk) 16798da581eSAnton Blanchard { 16898da581eSAnton Blanchard check_if_tm_restore_required(tsk); 16998da581eSAnton Blanchard 170a0e72cf1SAnton Blanchard msr_check_and_set(MSR_FP); 17198da581eSAnton Blanchard __giveup_fpu(tsk); 172a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP); 17398da581eSAnton Blanchard } 17498da581eSAnton Blanchard EXPORT_SYMBOL(giveup_fpu); 17598da581eSAnton Blanchard 17614cf11afSPaul Mackerras /* 17714cf11afSPaul Mackerras * Make sure the floating-point register state in the 17814cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 17914cf11afSPaul Mackerras */ 18014cf11afSPaul Mackerras void flush_fp_to_thread(struct task_struct *tsk) 18114cf11afSPaul Mackerras { 18214cf11afSPaul Mackerras if (tsk->thread.regs) { 18314cf11afSPaul Mackerras /* 18414cf11afSPaul Mackerras * We need to disable preemption here because if we didn't, 18514cf11afSPaul Mackerras * another process could get scheduled after the regs->msr 18614cf11afSPaul Mackerras * test but before we have finished saving the FP registers 18714cf11afSPaul Mackerras * to the thread_struct. That process could take over the 18814cf11afSPaul Mackerras * FPU, and then when we get scheduled again we would store 18914cf11afSPaul Mackerras * bogus values for the remaining FP registers. 19014cf11afSPaul Mackerras */ 19114cf11afSPaul Mackerras preempt_disable(); 19214cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_FP) { 19314cf11afSPaul Mackerras /* 19414cf11afSPaul Mackerras * This should only ever be called for current or 19514cf11afSPaul Mackerras * for a stopped child process. Since we save away 196af1bbc3dSAnton Blanchard * the FP register state on context switch, 19714cf11afSPaul Mackerras * there is something wrong if a stopped child appears 19814cf11afSPaul Mackerras * to still have its FP state in the CPU registers. 19914cf11afSPaul Mackerras */ 20014cf11afSPaul Mackerras BUG_ON(tsk != current); 201b86fd2bdSAnton Blanchard giveup_fpu(tsk); 20214cf11afSPaul Mackerras } 20314cf11afSPaul Mackerras preempt_enable(); 20414cf11afSPaul Mackerras } 20514cf11afSPaul Mackerras } 206de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_fp_to_thread); 20714cf11afSPaul Mackerras 20814cf11afSPaul Mackerras void enable_kernel_fp(void) 20914cf11afSPaul Mackerras { 210e909fb83SCyril Bur unsigned long cpumsr; 211e909fb83SCyril Bur 21214cf11afSPaul Mackerras WARN_ON(preemptible()); 21314cf11afSPaul Mackerras 214e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP); 215611b0e5cSAnton Blanchard 216d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 217d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 218e909fb83SCyril Bur /* 219e909fb83SCyril Bur * If a thread has already been reclaimed then the 220e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 221e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 222e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 223e909fb83SCyril Bur * checkpointed structure. 224e909fb83SCyril Bur */ 2255c784c84SBreno Leitao if (!MSR_TM_ACTIVE(cpumsr) && 2265c784c84SBreno Leitao MSR_TM_ACTIVE(current->thread.regs->msr)) 227e909fb83SCyril Bur return; 228a0e72cf1SAnton Blanchard __giveup_fpu(current); 229b86fd2bdSAnton Blanchard } 230d64d02ceSAnton Blanchard } 23114cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_fp); 232c83c192aSChristophe Leroy #else 233c83c192aSChristophe Leroy static inline void __giveup_fpu(struct task_struct *tsk) { } 234d1e1cf2eSAnton Blanchard #endif /* CONFIG_PPC_FPU */ 23514cf11afSPaul Mackerras 23614cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 2376f515d84SCyril Bur static void __giveup_altivec(struct task_struct *tsk) 2386f515d84SCyril Bur { 2398eb98037SAnton Blanchard unsigned long msr; 2408eb98037SAnton Blanchard 2416f515d84SCyril Bur save_altivec(tsk); 2428eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 2438eb98037SAnton Blanchard msr &= ~MSR_VEC; 2446f515d84SCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 2458eb98037SAnton Blanchard msr &= ~MSR_VSX; 2468eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 2476f515d84SCyril Bur } 2486f515d84SCyril Bur 24998da581eSAnton Blanchard void giveup_altivec(struct task_struct *tsk) 25098da581eSAnton Blanchard { 25198da581eSAnton Blanchard check_if_tm_restore_required(tsk); 25298da581eSAnton Blanchard 253a0e72cf1SAnton Blanchard msr_check_and_set(MSR_VEC); 25498da581eSAnton Blanchard __giveup_altivec(tsk); 255a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_VEC); 25698da581eSAnton Blanchard } 25798da581eSAnton Blanchard EXPORT_SYMBOL(giveup_altivec); 25898da581eSAnton Blanchard 25914cf11afSPaul Mackerras void enable_kernel_altivec(void) 26014cf11afSPaul Mackerras { 261e909fb83SCyril Bur unsigned long cpumsr; 262e909fb83SCyril Bur 26314cf11afSPaul Mackerras WARN_ON(preemptible()); 26414cf11afSPaul Mackerras 265e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_VEC); 266611b0e5cSAnton Blanchard 267d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 268d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 269e909fb83SCyril Bur /* 270e909fb83SCyril Bur * If a thread has already been reclaimed then the 271e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 272e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 273e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 274e909fb83SCyril Bur * checkpointed structure. 275e909fb83SCyril Bur */ 2765c784c84SBreno Leitao if (!MSR_TM_ACTIVE(cpumsr) && 2775c784c84SBreno Leitao MSR_TM_ACTIVE(current->thread.regs->msr)) 278e909fb83SCyril Bur return; 279a0e72cf1SAnton Blanchard __giveup_altivec(current); 280b86fd2bdSAnton Blanchard } 281d64d02ceSAnton Blanchard } 28214cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_altivec); 28314cf11afSPaul Mackerras 28414cf11afSPaul Mackerras /* 28514cf11afSPaul Mackerras * Make sure the VMX/Altivec register state in the 28614cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 28714cf11afSPaul Mackerras */ 28814cf11afSPaul Mackerras void flush_altivec_to_thread(struct task_struct *tsk) 28914cf11afSPaul Mackerras { 29014cf11afSPaul Mackerras if (tsk->thread.regs) { 29114cf11afSPaul Mackerras preempt_disable(); 29214cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_VEC) { 29314cf11afSPaul Mackerras BUG_ON(tsk != current); 294b86fd2bdSAnton Blanchard giveup_altivec(tsk); 29514cf11afSPaul Mackerras } 29614cf11afSPaul Mackerras preempt_enable(); 29714cf11afSPaul Mackerras } 29814cf11afSPaul Mackerras } 299de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 30014cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 30114cf11afSPaul Mackerras 302ce48b210SMichael Neuling #ifdef CONFIG_VSX 303bf6a4d5bSCyril Bur static void __giveup_vsx(struct task_struct *tsk) 304a7d623d4SAnton Blanchard { 305dc801081SBenjamin Herrenschmidt unsigned long msr = tsk->thread.regs->msr; 306dc801081SBenjamin Herrenschmidt 307dc801081SBenjamin Herrenschmidt /* 308dc801081SBenjamin Herrenschmidt * We should never be ssetting MSR_VSX without also setting 309dc801081SBenjamin Herrenschmidt * MSR_FP and MSR_VEC 310dc801081SBenjamin Herrenschmidt */ 311dc801081SBenjamin Herrenschmidt WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); 312dc801081SBenjamin Herrenschmidt 313dc801081SBenjamin Herrenschmidt /* __giveup_fpu will clear MSR_VSX */ 314dc801081SBenjamin Herrenschmidt if (msr & MSR_FP) 315a7d623d4SAnton Blanchard __giveup_fpu(tsk); 316dc801081SBenjamin Herrenschmidt if (msr & MSR_VEC) 317a7d623d4SAnton Blanchard __giveup_altivec(tsk); 318bf6a4d5bSCyril Bur } 319bf6a4d5bSCyril Bur 320bf6a4d5bSCyril Bur static void giveup_vsx(struct task_struct *tsk) 321bf6a4d5bSCyril Bur { 322bf6a4d5bSCyril Bur check_if_tm_restore_required(tsk); 323bf6a4d5bSCyril Bur 324bf6a4d5bSCyril Bur msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 325a7d623d4SAnton Blanchard __giveup_vsx(tsk); 326a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 327a7d623d4SAnton Blanchard } 328bf6a4d5bSCyril Bur 329ce48b210SMichael Neuling void enable_kernel_vsx(void) 330ce48b210SMichael Neuling { 331e909fb83SCyril Bur unsigned long cpumsr; 332e909fb83SCyril Bur 333ce48b210SMichael Neuling WARN_ON(preemptible()); 334ce48b210SMichael Neuling 335e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 336611b0e5cSAnton Blanchard 3375a69aec9SBenjamin Herrenschmidt if (current->thread.regs && 3385a69aec9SBenjamin Herrenschmidt (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { 339d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 340e909fb83SCyril Bur /* 341e909fb83SCyril Bur * If a thread has already been reclaimed then the 342e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 343e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 344e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 345e909fb83SCyril Bur * checkpointed structure. 346e909fb83SCyril Bur */ 3475c784c84SBreno Leitao if (!MSR_TM_ACTIVE(cpumsr) && 3485c784c84SBreno Leitao MSR_TM_ACTIVE(current->thread.regs->msr)) 349e909fb83SCyril Bur return; 350a0e72cf1SAnton Blanchard __giveup_vsx(current); 351611b0e5cSAnton Blanchard } 352ce48b210SMichael Neuling } 353ce48b210SMichael Neuling EXPORT_SYMBOL(enable_kernel_vsx); 354ce48b210SMichael Neuling 355ce48b210SMichael Neuling void flush_vsx_to_thread(struct task_struct *tsk) 356ce48b210SMichael Neuling { 357ce48b210SMichael Neuling if (tsk->thread.regs) { 358ce48b210SMichael Neuling preempt_disable(); 3595a69aec9SBenjamin Herrenschmidt if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { 360ce48b210SMichael Neuling BUG_ON(tsk != current); 361ce48b210SMichael Neuling giveup_vsx(tsk); 362ce48b210SMichael Neuling } 363ce48b210SMichael Neuling preempt_enable(); 364ce48b210SMichael Neuling } 365ce48b210SMichael Neuling } 366de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 367ce48b210SMichael Neuling #endif /* CONFIG_VSX */ 368ce48b210SMichael Neuling 36914cf11afSPaul Mackerras #ifdef CONFIG_SPE 37098da581eSAnton Blanchard void giveup_spe(struct task_struct *tsk) 37198da581eSAnton Blanchard { 37298da581eSAnton Blanchard check_if_tm_restore_required(tsk); 37398da581eSAnton Blanchard 374a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 37598da581eSAnton Blanchard __giveup_spe(tsk); 376a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_SPE); 37798da581eSAnton Blanchard } 37898da581eSAnton Blanchard EXPORT_SYMBOL(giveup_spe); 37914cf11afSPaul Mackerras 38014cf11afSPaul Mackerras void enable_kernel_spe(void) 38114cf11afSPaul Mackerras { 38214cf11afSPaul Mackerras WARN_ON(preemptible()); 38314cf11afSPaul Mackerras 384a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 385611b0e5cSAnton Blanchard 386d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 387d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 388a0e72cf1SAnton Blanchard __giveup_spe(current); 38914cf11afSPaul Mackerras } 390d64d02ceSAnton Blanchard } 39114cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_spe); 39214cf11afSPaul Mackerras 39314cf11afSPaul Mackerras void flush_spe_to_thread(struct task_struct *tsk) 39414cf11afSPaul Mackerras { 39514cf11afSPaul Mackerras if (tsk->thread.regs) { 39614cf11afSPaul Mackerras preempt_disable(); 39714cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_SPE) { 39814cf11afSPaul Mackerras BUG_ON(tsk != current); 399685659eeSyu liu tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 4000ee6c15eSKumar Gala giveup_spe(tsk); 40114cf11afSPaul Mackerras } 40214cf11afSPaul Mackerras preempt_enable(); 40314cf11afSPaul Mackerras } 40414cf11afSPaul Mackerras } 40514cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 40614cf11afSPaul Mackerras 407c2085059SAnton Blanchard static unsigned long msr_all_available; 408c2085059SAnton Blanchard 409c2085059SAnton Blanchard static int __init init_msr_all_available(void) 410c2085059SAnton Blanchard { 411c83c192aSChristophe Leroy if (IS_ENABLED(CONFIG_PPC_FPU)) 412c2085059SAnton Blanchard msr_all_available |= MSR_FP; 413c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC)) 414c2085059SAnton Blanchard msr_all_available |= MSR_VEC; 415c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX)) 416c2085059SAnton Blanchard msr_all_available |= MSR_VSX; 417c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_SPE)) 418c2085059SAnton Blanchard msr_all_available |= MSR_SPE; 419c2085059SAnton Blanchard 420c2085059SAnton Blanchard return 0; 421c2085059SAnton Blanchard } 422c2085059SAnton Blanchard early_initcall(init_msr_all_available); 423c2085059SAnton Blanchard 424c2085059SAnton Blanchard void giveup_all(struct task_struct *tsk) 425c2085059SAnton Blanchard { 426c2085059SAnton Blanchard unsigned long usermsr; 427c2085059SAnton Blanchard 428c2085059SAnton Blanchard if (!tsk->thread.regs) 429c2085059SAnton Blanchard return; 430c2085059SAnton Blanchard 4318205d5d9SGustavo Romero check_if_tm_restore_required(tsk); 4328205d5d9SGustavo Romero 433c2085059SAnton Blanchard usermsr = tsk->thread.regs->msr; 434c2085059SAnton Blanchard 435c2085059SAnton Blanchard if ((usermsr & msr_all_available) == 0) 436c2085059SAnton Blanchard return; 437c2085059SAnton Blanchard 438c2085059SAnton Blanchard msr_check_and_set(msr_all_available); 439c2085059SAnton Blanchard 44096c79b6bSBenjamin Herrenschmidt WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 44196c79b6bSBenjamin Herrenschmidt 442c2085059SAnton Blanchard if (usermsr & MSR_FP) 443c2085059SAnton Blanchard __giveup_fpu(tsk); 444c2085059SAnton Blanchard if (usermsr & MSR_VEC) 445c2085059SAnton Blanchard __giveup_altivec(tsk); 446c2085059SAnton Blanchard if (usermsr & MSR_SPE) 447c2085059SAnton Blanchard __giveup_spe(tsk); 448c2085059SAnton Blanchard 449c2085059SAnton Blanchard msr_check_and_clear(msr_all_available); 450c2085059SAnton Blanchard } 451c2085059SAnton Blanchard EXPORT_SYMBOL(giveup_all); 452c2085059SAnton Blanchard 4536cc0c16dSNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 4546cc0c16dSNicholas Piggin #ifdef CONFIG_PPC_FPU 45501eb0187SNicholas Piggin static bool should_restore_fp(void) 4566cc0c16dSNicholas Piggin { 45701eb0187SNicholas Piggin if (current->thread.load_fp) { 4586cc0c16dSNicholas Piggin current->thread.load_fp++; 45901eb0187SNicholas Piggin return true; 4606cc0c16dSNicholas Piggin } 46101eb0187SNicholas Piggin return false; 46201eb0187SNicholas Piggin } 46301eb0187SNicholas Piggin 46401eb0187SNicholas Piggin static void do_restore_fp(void) 46501eb0187SNicholas Piggin { 46601eb0187SNicholas Piggin load_fp_state(¤t->thread.fp_state); 4676cc0c16dSNicholas Piggin } 4686cc0c16dSNicholas Piggin #else 46901eb0187SNicholas Piggin static bool should_restore_fp(void) { return false; } 47001eb0187SNicholas Piggin static void do_restore_fp(void) { } 4716cc0c16dSNicholas Piggin #endif /* CONFIG_PPC_FPU */ 4726cc0c16dSNicholas Piggin 4736cc0c16dSNicholas Piggin #ifdef CONFIG_ALTIVEC 47401eb0187SNicholas Piggin static bool should_restore_altivec(void) 4756cc0c16dSNicholas Piggin { 47601eb0187SNicholas Piggin if (cpu_has_feature(CPU_FTR_ALTIVEC) && (current->thread.load_vec)) { 47701eb0187SNicholas Piggin current->thread.load_vec++; 47801eb0187SNicholas Piggin return true; 4796cc0c16dSNicholas Piggin } 48001eb0187SNicholas Piggin return false; 48101eb0187SNicholas Piggin } 48201eb0187SNicholas Piggin 48301eb0187SNicholas Piggin static void do_restore_altivec(void) 48401eb0187SNicholas Piggin { 48501eb0187SNicholas Piggin load_vr_state(¤t->thread.vr_state); 48601eb0187SNicholas Piggin current->thread.used_vr = 1; 4876cc0c16dSNicholas Piggin } 4886cc0c16dSNicholas Piggin #else 48901eb0187SNicholas Piggin static bool should_restore_altivec(void) { return false; } 49001eb0187SNicholas Piggin static void do_restore_altivec(void) { } 4916cc0c16dSNicholas Piggin #endif /* CONFIG_ALTIVEC */ 4926cc0c16dSNicholas Piggin 49301eb0187SNicholas Piggin static bool should_restore_vsx(void) 4946cc0c16dSNicholas Piggin { 49501eb0187SNicholas Piggin if (cpu_has_feature(CPU_FTR_VSX)) 49601eb0187SNicholas Piggin return true; 49701eb0187SNicholas Piggin return false; 4986cc0c16dSNicholas Piggin } 49980739c2bSChristophe Leroy #ifdef CONFIG_VSX 50001eb0187SNicholas Piggin static void do_restore_vsx(void) 50101eb0187SNicholas Piggin { 50201eb0187SNicholas Piggin current->thread.used_vsr = 1; 5036cc0c16dSNicholas Piggin } 5046cc0c16dSNicholas Piggin #else 50501eb0187SNicholas Piggin static void do_restore_vsx(void) { } 5066cc0c16dSNicholas Piggin #endif /* CONFIG_VSX */ 5076cc0c16dSNicholas Piggin 508e2b36d59SNicholas Piggin /* 509e2b36d59SNicholas Piggin * The exception exit path calls restore_math() with interrupts hard disabled 510e2b36d59SNicholas Piggin * but the soft irq state not "reconciled". ftrace code that calls 511e2b36d59SNicholas Piggin * local_irq_save/restore causes warnings. 512e2b36d59SNicholas Piggin * 513e2b36d59SNicholas Piggin * Rather than complicate the exit path, just don't trace restore_math. This 514e2b36d59SNicholas Piggin * could be done by having ftrace entry code check for this un-reconciled 515e2b36d59SNicholas Piggin * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and 516e2b36d59SNicholas Piggin * temporarily fix it up for the duration of the ftrace call. 517e2b36d59SNicholas Piggin */ 518e2b36d59SNicholas Piggin void notrace restore_math(struct pt_regs *regs) 51970fe3d98SCyril Bur { 52070fe3d98SCyril Bur unsigned long msr; 52101eb0187SNicholas Piggin unsigned long new_msr = 0; 52270fe3d98SCyril Bur 52370fe3d98SCyril Bur msr = regs->msr; 52470fe3d98SCyril Bur 52570fe3d98SCyril Bur /* 52601eb0187SNicholas Piggin * new_msr tracks the facilities that are to be restored. Only reload 52701eb0187SNicholas Piggin * if the bit is not set in the user MSR (if it is set, the registers 52801eb0187SNicholas Piggin * are live for the user thread). 52970fe3d98SCyril Bur */ 53001eb0187SNicholas Piggin if ((!(msr & MSR_FP)) && should_restore_fp()) 531b91eb518SMichael Ellerman new_msr |= MSR_FP; 53270fe3d98SCyril Bur 53301eb0187SNicholas Piggin if ((!(msr & MSR_VEC)) && should_restore_altivec()) 53401eb0187SNicholas Piggin new_msr |= MSR_VEC; 53570fe3d98SCyril Bur 53601eb0187SNicholas Piggin if ((!(msr & MSR_VSX)) && should_restore_vsx()) { 53701eb0187SNicholas Piggin if (((msr | new_msr) & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) 53801eb0187SNicholas Piggin new_msr |= MSR_VSX; 53970fe3d98SCyril Bur } 54070fe3d98SCyril Bur 54101eb0187SNicholas Piggin if (new_msr) { 542b91eb518SMichael Ellerman unsigned long fpexc_mode = 0; 543b91eb518SMichael Ellerman 54401eb0187SNicholas Piggin msr_check_and_set(new_msr); 54570fe3d98SCyril Bur 546b91eb518SMichael Ellerman if (new_msr & MSR_FP) { 54701eb0187SNicholas Piggin do_restore_fp(); 54801eb0187SNicholas Piggin 549b91eb518SMichael Ellerman // This also covers VSX, because VSX implies FP 550b91eb518SMichael Ellerman fpexc_mode = current->thread.fpexc_mode; 551b91eb518SMichael Ellerman } 552b91eb518SMichael Ellerman 55301eb0187SNicholas Piggin if (new_msr & MSR_VEC) 55401eb0187SNicholas Piggin do_restore_altivec(); 55501eb0187SNicholas Piggin 55601eb0187SNicholas Piggin if (new_msr & MSR_VSX) 55701eb0187SNicholas Piggin do_restore_vsx(); 55801eb0187SNicholas Piggin 55901eb0187SNicholas Piggin msr_check_and_clear(new_msr); 56001eb0187SNicholas Piggin 561b91eb518SMichael Ellerman regs->msr |= new_msr | fpexc_mode; 56201eb0187SNicholas Piggin } 56370fe3d98SCyril Bur } 56460d62bfdSChristophe Leroy #endif /* CONFIG_PPC_BOOK3S_64 */ 56570fe3d98SCyril Bur 5661cdf039bSMathieu Malaterre static void save_all(struct task_struct *tsk) 567de2a20aaSCyril Bur { 568de2a20aaSCyril Bur unsigned long usermsr; 569de2a20aaSCyril Bur 570de2a20aaSCyril Bur if (!tsk->thread.regs) 571de2a20aaSCyril Bur return; 572de2a20aaSCyril Bur 573de2a20aaSCyril Bur usermsr = tsk->thread.regs->msr; 574de2a20aaSCyril Bur 575de2a20aaSCyril Bur if ((usermsr & msr_all_available) == 0) 576de2a20aaSCyril Bur return; 577de2a20aaSCyril Bur 578de2a20aaSCyril Bur msr_check_and_set(msr_all_available); 579de2a20aaSCyril Bur 58096c79b6bSBenjamin Herrenschmidt WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 58196c79b6bSBenjamin Herrenschmidt 582de2a20aaSCyril Bur if (usermsr & MSR_FP) 5838792468dSCyril Bur save_fpu(tsk); 584de2a20aaSCyril Bur 585de2a20aaSCyril Bur if (usermsr & MSR_VEC) 5866f515d84SCyril Bur save_altivec(tsk); 587de2a20aaSCyril Bur 588de2a20aaSCyril Bur if (usermsr & MSR_SPE) 589de2a20aaSCyril Bur __giveup_spe(tsk); 590de2a20aaSCyril Bur 591de2a20aaSCyril Bur msr_check_and_clear(msr_all_available); 592c76662e8SRam Pai thread_pkey_regs_save(&tsk->thread); 593de2a20aaSCyril Bur } 594de2a20aaSCyril Bur 595579e633eSAnton Blanchard void flush_all_to_thread(struct task_struct *tsk) 596579e633eSAnton Blanchard { 597579e633eSAnton Blanchard if (tsk->thread.regs) { 598579e633eSAnton Blanchard preempt_disable(); 599579e633eSAnton Blanchard BUG_ON(tsk != current); 600579e633eSAnton Blanchard #ifdef CONFIG_SPE 601579e633eSAnton Blanchard if (tsk->thread.regs->msr & MSR_SPE) 602579e633eSAnton Blanchard tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 603579e633eSAnton Blanchard #endif 604e9013785SFelipe Rechia save_all(tsk); 605579e633eSAnton Blanchard 606579e633eSAnton Blanchard preempt_enable(); 607579e633eSAnton Blanchard } 608579e633eSAnton Blanchard } 609579e633eSAnton Blanchard EXPORT_SYMBOL(flush_all_to_thread); 610579e633eSAnton Blanchard 6113bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6123bffb652SDave Kleikamp void do_send_trap(struct pt_regs *regs, unsigned long address, 61347355040SEric W. Biederman unsigned long error_code, int breakpt) 6143bffb652SDave Kleikamp { 61547355040SEric W. Biederman current->thread.trap_nr = TRAP_HWBKPT; 6163bffb652SDave Kleikamp if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 6173bffb652SDave Kleikamp 11, SIGSEGV) == NOTIFY_STOP) 6183bffb652SDave Kleikamp return; 6193bffb652SDave Kleikamp 6203bffb652SDave Kleikamp /* Deliver the signal to userspace */ 621f71dd7dcSEric W. Biederman force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ 622f71dd7dcSEric W. Biederman (void __user *)address); 6233bffb652SDave Kleikamp } 6243bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 6255b905d77SRavi Bangoria 6265b905d77SRavi Bangoria static void do_break_handler(struct pt_regs *regs) 6275b905d77SRavi Bangoria { 6285b905d77SRavi Bangoria struct arch_hw_breakpoint null_brk = {0}; 6295b905d77SRavi Bangoria struct arch_hw_breakpoint *info; 6305b905d77SRavi Bangoria struct ppc_inst instr = ppc_inst(0); 6315b905d77SRavi Bangoria int type = 0; 6325b905d77SRavi Bangoria int size = 0; 6335b905d77SRavi Bangoria unsigned long ea; 6345b905d77SRavi Bangoria int i; 6355b905d77SRavi Bangoria 6365b905d77SRavi Bangoria /* 6375b905d77SRavi Bangoria * If underneath hw supports only one watchpoint, we know it 6385b905d77SRavi Bangoria * caused exception. 8xx also falls into this category. 6395b905d77SRavi Bangoria */ 6405b905d77SRavi Bangoria if (nr_wp_slots() == 1) { 6415b905d77SRavi Bangoria __set_breakpoint(0, &null_brk); 6425b905d77SRavi Bangoria current->thread.hw_brk[0] = null_brk; 6435b905d77SRavi Bangoria current->thread.hw_brk[0].flags |= HW_BRK_FLAG_DISABLED; 6445b905d77SRavi Bangoria return; 6455b905d77SRavi Bangoria } 6465b905d77SRavi Bangoria 6475b905d77SRavi Bangoria /* Otherwise findout which DAWR caused exception and disable it. */ 6485b905d77SRavi Bangoria wp_get_instr_detail(regs, &instr, &type, &size, &ea); 6495b905d77SRavi Bangoria 6505b905d77SRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) { 6515b905d77SRavi Bangoria info = ¤t->thread.hw_brk[i]; 6525b905d77SRavi Bangoria if (!info->address) 6535b905d77SRavi Bangoria continue; 6545b905d77SRavi Bangoria 6555b905d77SRavi Bangoria if (wp_check_constraints(regs, instr, ea, type, size, info)) { 6565b905d77SRavi Bangoria __set_breakpoint(i, &null_brk); 6575b905d77SRavi Bangoria current->thread.hw_brk[i] = null_brk; 6585b905d77SRavi Bangoria current->thread.hw_brk[i].flags |= HW_BRK_FLAG_DISABLED; 6595b905d77SRavi Bangoria } 6605b905d77SRavi Bangoria } 6615b905d77SRavi Bangoria } 6625b905d77SRavi Bangoria 6639422de3eSMichael Neuling void do_break (struct pt_regs *regs, unsigned long address, 664d6a61bfcSLuis Machado unsigned long error_code) 665d6a61bfcSLuis Machado { 66641ab5266SAnanth N Mavinakayanahalli current->thread.trap_nr = TRAP_HWBKPT; 667d6a61bfcSLuis Machado if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 668d6a61bfcSLuis Machado 11, SIGSEGV) == NOTIFY_STOP) 669d6a61bfcSLuis Machado return; 670d6a61bfcSLuis Machado 6719422de3eSMichael Neuling if (debugger_break_match(regs)) 672d6a61bfcSLuis Machado return; 673d6a61bfcSLuis Machado 6745b905d77SRavi Bangoria /* 6755b905d77SRavi Bangoria * We reach here only when watchpoint exception is generated by ptrace 6765b905d77SRavi Bangoria * event (or hw is buggy!). Now if CONFIG_HAVE_HW_BREAKPOINT is set, 6775b905d77SRavi Bangoria * watchpoint is already handled by hw_breakpoint_handler() so we don't 6785b905d77SRavi Bangoria * have to do anything. But when CONFIG_HAVE_HW_BREAKPOINT is not set, 6795b905d77SRavi Bangoria * we need to manually handle the watchpoint here. 6805b905d77SRavi Bangoria */ 6815b905d77SRavi Bangoria if (!IS_ENABLED(CONFIG_HAVE_HW_BREAKPOINT)) 6825b905d77SRavi Bangoria do_break_handler(regs); 6835b905d77SRavi Bangoria 684d6a61bfcSLuis Machado /* Deliver the signal to userspace */ 6852e1661d2SEric W. Biederman force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address); 686d6a61bfcSLuis Machado } 6873bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 688d6a61bfcSLuis Machado 6894a8a9379SRavi Bangoria static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]); 690a2ceff5eSMichael Ellerman 6913bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6923bffb652SDave Kleikamp /* 6933bffb652SDave Kleikamp * Set the debug registers back to their default "safe" values. 6943bffb652SDave Kleikamp */ 6953bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 6963bffb652SDave Kleikamp { 69751ae8d4aSBharat Bhushan thread->debug.iac1 = thread->debug.iac2 = 0; 6983bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 69951ae8d4aSBharat Bhushan thread->debug.iac3 = thread->debug.iac4 = 0; 7003bffb652SDave Kleikamp #endif 70151ae8d4aSBharat Bhushan thread->debug.dac1 = thread->debug.dac2 = 0; 7023bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 70351ae8d4aSBharat Bhushan thread->debug.dvc1 = thread->debug.dvc2 = 0; 7043bffb652SDave Kleikamp #endif 70551ae8d4aSBharat Bhushan thread->debug.dbcr0 = 0; 7063bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 7073bffb652SDave Kleikamp /* 7083bffb652SDave Kleikamp * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 7093bffb652SDave Kleikamp */ 71051ae8d4aSBharat Bhushan thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 7113bffb652SDave Kleikamp DBCR1_IAC3US | DBCR1_IAC4US; 7123bffb652SDave Kleikamp /* 7133bffb652SDave Kleikamp * Force Data Address Compare User/Supervisor bits to be User-only 7143bffb652SDave Kleikamp * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 7153bffb652SDave Kleikamp */ 71651ae8d4aSBharat Bhushan thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 7173bffb652SDave Kleikamp #else 71851ae8d4aSBharat Bhushan thread->debug.dbcr1 = 0; 7193bffb652SDave Kleikamp #endif 7203bffb652SDave Kleikamp } 7213bffb652SDave Kleikamp 722f5f97210SScott Wood static void prime_debug_regs(struct debug_reg *debug) 7233bffb652SDave Kleikamp { 7246cecf76bSScott Wood /* 7256cecf76bSScott Wood * We could have inherited MSR_DE from userspace, since 7266cecf76bSScott Wood * it doesn't get cleared on exception entry. Make sure 7276cecf76bSScott Wood * MSR_DE is clear before we enable any debug events. 7286cecf76bSScott Wood */ 7296cecf76bSScott Wood mtmsr(mfmsr() & ~MSR_DE); 7306cecf76bSScott Wood 731f5f97210SScott Wood mtspr(SPRN_IAC1, debug->iac1); 732f5f97210SScott Wood mtspr(SPRN_IAC2, debug->iac2); 7333bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 734f5f97210SScott Wood mtspr(SPRN_IAC3, debug->iac3); 735f5f97210SScott Wood mtspr(SPRN_IAC4, debug->iac4); 7363bffb652SDave Kleikamp #endif 737f5f97210SScott Wood mtspr(SPRN_DAC1, debug->dac1); 738f5f97210SScott Wood mtspr(SPRN_DAC2, debug->dac2); 7393bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 740f5f97210SScott Wood mtspr(SPRN_DVC1, debug->dvc1); 741f5f97210SScott Wood mtspr(SPRN_DVC2, debug->dvc2); 7423bffb652SDave Kleikamp #endif 743f5f97210SScott Wood mtspr(SPRN_DBCR0, debug->dbcr0); 744f5f97210SScott Wood mtspr(SPRN_DBCR1, debug->dbcr1); 7453bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 746f5f97210SScott Wood mtspr(SPRN_DBCR2, debug->dbcr2); 7473bffb652SDave Kleikamp #endif 7483bffb652SDave Kleikamp } 7493bffb652SDave Kleikamp /* 7503bffb652SDave Kleikamp * Unless neither the old or new thread are making use of the 7513bffb652SDave Kleikamp * debug registers, set the debug registers from the values 7523bffb652SDave Kleikamp * stored in the new thread. 7533bffb652SDave Kleikamp */ 754f5f97210SScott Wood void switch_booke_debug_regs(struct debug_reg *new_debug) 7553bffb652SDave Kleikamp { 75651ae8d4aSBharat Bhushan if ((current->thread.debug.dbcr0 & DBCR0_IDM) 757f5f97210SScott Wood || (new_debug->dbcr0 & DBCR0_IDM)) 758f5f97210SScott Wood prime_debug_regs(new_debug); 7593bffb652SDave Kleikamp } 7603743c9b8SBharat Bhushan EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 7613bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 762e0780b72SK.Prasad #ifndef CONFIG_HAVE_HW_BREAKPOINT 763303e6a9dSRavi Bangoria static void set_breakpoint(int i, struct arch_hw_breakpoint *brk) 764b5ac51d7SChristophe Leroy { 765b5ac51d7SChristophe Leroy preempt_disable(); 766303e6a9dSRavi Bangoria __set_breakpoint(i, brk); 767b5ac51d7SChristophe Leroy preempt_enable(); 768b5ac51d7SChristophe Leroy } 769b5ac51d7SChristophe Leroy 7703bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 7713bffb652SDave Kleikamp { 772303e6a9dSRavi Bangoria int i; 773303e6a9dSRavi Bangoria struct arch_hw_breakpoint null_brk = {0}; 774303e6a9dSRavi Bangoria 775303e6a9dSRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) { 776303e6a9dSRavi Bangoria thread->hw_brk[i] = null_brk; 777252988cbSNicholas Piggin if (ppc_breakpoint_available()) 778303e6a9dSRavi Bangoria set_breakpoint(i, &thread->hw_brk[i]); 779303e6a9dSRavi Bangoria } 780303e6a9dSRavi Bangoria } 781303e6a9dSRavi Bangoria 782303e6a9dSRavi Bangoria static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 783303e6a9dSRavi Bangoria struct arch_hw_breakpoint *b) 784303e6a9dSRavi Bangoria { 785303e6a9dSRavi Bangoria if (a->address != b->address) 786303e6a9dSRavi Bangoria return false; 787303e6a9dSRavi Bangoria if (a->type != b->type) 788303e6a9dSRavi Bangoria return false; 789303e6a9dSRavi Bangoria if (a->len != b->len) 790303e6a9dSRavi Bangoria return false; 791303e6a9dSRavi Bangoria /* no need to check hw_len. it's calculated from address and len */ 792303e6a9dSRavi Bangoria return true; 793303e6a9dSRavi Bangoria } 794303e6a9dSRavi Bangoria 795303e6a9dSRavi Bangoria static void switch_hw_breakpoint(struct task_struct *new) 796303e6a9dSRavi Bangoria { 797303e6a9dSRavi Bangoria int i; 798303e6a9dSRavi Bangoria 799303e6a9dSRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) { 800303e6a9dSRavi Bangoria if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]), 801303e6a9dSRavi Bangoria &new->thread.hw_brk[i]))) 802303e6a9dSRavi Bangoria continue; 803303e6a9dSRavi Bangoria 804303e6a9dSRavi Bangoria __set_breakpoint(i, &new->thread.hw_brk[i]); 805303e6a9dSRavi Bangoria } 8063bffb652SDave Kleikamp } 807e0780b72SK.Prasad #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 8083bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 8093bffb652SDave Kleikamp 810172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 8119422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 8129422de3eSMichael Neuling { 813c6c9eaceSBenjamin Herrenschmidt mtspr(SPRN_DAC1, dabr); 81404d476bfSChristophe Leroy if (IS_ENABLED(CONFIG_PPC_47x)) 815221c185dSDave Kleikamp isync(); 8169422de3eSMichael Neuling return 0; 8179422de3eSMichael Neuling } 818c6c9eaceSBenjamin Herrenschmidt #elif defined(CONFIG_PPC_BOOK3S) 8199422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 8209422de3eSMichael Neuling { 821cab0af98SMichael Ellerman mtspr(SPRN_DABR, dabr); 82282a9f16aSMichael Neuling if (cpu_has_feature(CPU_FTR_DABRX)) 8234474ef05SMichael Neuling mtspr(SPRN_DABRX, dabrx); 824cab0af98SMichael Ellerman return 0; 82514cf11afSPaul Mackerras } 8269422de3eSMichael Neuling #else 8279422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 8289422de3eSMichael Neuling { 8299422de3eSMichael Neuling return -EINVAL; 8309422de3eSMichael Neuling } 8319422de3eSMichael Neuling #endif 8329422de3eSMichael Neuling 8339422de3eSMichael Neuling static inline int set_dabr(struct arch_hw_breakpoint *brk) 8349422de3eSMichael Neuling { 8359422de3eSMichael Neuling unsigned long dabr, dabrx; 8369422de3eSMichael Neuling 8379422de3eSMichael Neuling dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 8389422de3eSMichael Neuling dabrx = ((brk->type >> 3) & 0x7); 8399422de3eSMichael Neuling 8409422de3eSMichael Neuling if (ppc_md.set_dabr) 8419422de3eSMichael Neuling return ppc_md.set_dabr(dabr, dabrx); 8429422de3eSMichael Neuling 8439422de3eSMichael Neuling return __set_dabr(dabr, dabrx); 8449422de3eSMichael Neuling } 8459422de3eSMichael Neuling 84639413ae0SChristophe Leroy static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk) 84739413ae0SChristophe Leroy { 84839413ae0SChristophe Leroy unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW | 84939413ae0SChristophe Leroy LCTRL1_CRWF_RW; 85039413ae0SChristophe Leroy unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN; 851e68ef121SRavi Bangoria unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE); 852e68ef121SRavi Bangoria unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE); 85339413ae0SChristophe Leroy 85439413ae0SChristophe Leroy if (start_addr == 0) 85539413ae0SChristophe Leroy lctrl2 |= LCTRL2_LW0LA_F; 856e68ef121SRavi Bangoria else if (end_addr == 0) 85739413ae0SChristophe Leroy lctrl2 |= LCTRL2_LW0LA_E; 85839413ae0SChristophe Leroy else 85939413ae0SChristophe Leroy lctrl2 |= LCTRL2_LW0LA_EandF; 86039413ae0SChristophe Leroy 86139413ae0SChristophe Leroy mtspr(SPRN_LCTRL2, 0); 86239413ae0SChristophe Leroy 86339413ae0SChristophe Leroy if ((brk->type & HW_BRK_TYPE_RDWR) == 0) 86439413ae0SChristophe Leroy return 0; 86539413ae0SChristophe Leroy 86639413ae0SChristophe Leroy if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) 86739413ae0SChristophe Leroy lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO; 86839413ae0SChristophe Leroy if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) 86939413ae0SChristophe Leroy lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO; 87039413ae0SChristophe Leroy 87139413ae0SChristophe Leroy mtspr(SPRN_CMPE, start_addr - 1); 872e68ef121SRavi Bangoria mtspr(SPRN_CMPF, end_addr); 87339413ae0SChristophe Leroy mtspr(SPRN_LCTRL1, lctrl1); 87439413ae0SChristophe Leroy mtspr(SPRN_LCTRL2, lctrl2); 87539413ae0SChristophe Leroy 87639413ae0SChristophe Leroy return 0; 87739413ae0SChristophe Leroy } 87839413ae0SChristophe Leroy 8794a8a9379SRavi Bangoria void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk) 8809422de3eSMichael Neuling { 8814a8a9379SRavi Bangoria memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk)); 8829422de3eSMichael Neuling 883c1fe190cSMichael Neuling if (dawr_enabled()) 884252988cbSNicholas Piggin // Power8 or later 8854a8a9379SRavi Bangoria set_dawr(nr, brk); 88639413ae0SChristophe Leroy else if (IS_ENABLED(CONFIG_PPC_8xx)) 88739413ae0SChristophe Leroy set_breakpoint_8xx(brk); 888252988cbSNicholas Piggin else if (!cpu_has_feature(CPU_FTR_ARCH_207S)) 889252988cbSNicholas Piggin // Power7 or earlier 89004c32a51SPaul Gortmaker set_dabr(brk); 891252988cbSNicholas Piggin else 892252988cbSNicholas Piggin // Shouldn't happen due to higher level checks 893252988cbSNicholas Piggin WARN_ON_ONCE(1); 8949422de3eSMichael Neuling } 89514cf11afSPaul Mackerras 896404b27d6SMichael Neuling /* Check if we have DAWR or DABR hardware */ 897404b27d6SMichael Neuling bool ppc_breakpoint_available(void) 898404b27d6SMichael Neuling { 899c1fe190cSMichael Neuling if (dawr_enabled()) 900c1fe190cSMichael Neuling return true; /* POWER8 DAWR or POWER9 forced DAWR */ 901404b27d6SMichael Neuling if (cpu_has_feature(CPU_FTR_ARCH_207S)) 902404b27d6SMichael Neuling return false; /* POWER9 with DAWR disabled */ 903404b27d6SMichael Neuling /* DABR: Everything but POWER8 and POWER9 */ 904404b27d6SMichael Neuling return true; 905404b27d6SMichael Neuling } 906404b27d6SMichael Neuling EXPORT_SYMBOL_GPL(ppc_breakpoint_available); 907404b27d6SMichael Neuling 908fb09692eSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 9095d176f75SCyril Bur 9105d176f75SCyril Bur static inline bool tm_enabled(struct task_struct *tsk) 9115d176f75SCyril Bur { 9125d176f75SCyril Bur return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); 9135d176f75SCyril Bur } 9145d176f75SCyril Bur 915edd00b83SCyril Bur static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause) 916d31626f7SPaul Mackerras { 9177f821fc9SMichael Neuling /* 9187f821fc9SMichael Neuling * Use the current MSR TM suspended bit to track if we have 9197f821fc9SMichael Neuling * checkpointed state outstanding. 9207f821fc9SMichael Neuling * On signal delivery, we'd normally reclaim the checkpointed 9217f821fc9SMichael Neuling * state to obtain stack pointer (see:get_tm_stackpointer()). 9227f821fc9SMichael Neuling * This will then directly return to userspace without going 9237f821fc9SMichael Neuling * through __switch_to(). However, if the stack frame is bad, 9247f821fc9SMichael Neuling * we need to exit this thread which calls __switch_to() which 9257f821fc9SMichael Neuling * will again attempt to reclaim the already saved tm state. 9267f821fc9SMichael Neuling * Hence we need to check that we've not already reclaimed 9277f821fc9SMichael Neuling * this state. 9287f821fc9SMichael Neuling * We do this using the current MSR, rather tracking it in 9297f821fc9SMichael Neuling * some specific thread_struct bit, as it has the additional 930027dfac6SMichael Ellerman * benefit of checking for a potential TM bad thing exception. 9317f821fc9SMichael Neuling */ 9327f821fc9SMichael Neuling if (!MSR_TM_SUSPENDED(mfmsr())) 9337f821fc9SMichael Neuling return; 9347f821fc9SMichael Neuling 93591381b9cSCyril Bur giveup_all(container_of(thr, struct task_struct, thread)); 93691381b9cSCyril Bur 937eb5c3f1cSCyril Bur tm_reclaim(thr, cause); 938eb5c3f1cSCyril Bur 939f48e91e8SMichael Neuling /* 940f48e91e8SMichael Neuling * If we are in a transaction and FP is off then we can't have 941f48e91e8SMichael Neuling * used FP inside that transaction. Hence the checkpointed 942f48e91e8SMichael Neuling * state is the same as the live state. We need to copy the 943f48e91e8SMichael Neuling * live state to the checkpointed state so that when the 944f48e91e8SMichael Neuling * transaction is restored, the checkpointed state is correct 945f48e91e8SMichael Neuling * and the aborted transaction sees the correct state. We use 946f48e91e8SMichael Neuling * ckpt_regs.msr here as that's what tm_reclaim will use to 947f48e91e8SMichael Neuling * determine if it's going to write the checkpointed state or 948f48e91e8SMichael Neuling * not. So either this will write the checkpointed registers, 949f48e91e8SMichael Neuling * or reclaim will. Similarly for VMX. 950f48e91e8SMichael Neuling */ 951f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_FP) == 0) 952f48e91e8SMichael Neuling memcpy(&thr->ckfp_state, &thr->fp_state, 953f48e91e8SMichael Neuling sizeof(struct thread_fp_state)); 954f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_VEC) == 0) 955f48e91e8SMichael Neuling memcpy(&thr->ckvr_state, &thr->vr_state, 956f48e91e8SMichael Neuling sizeof(struct thread_vr_state)); 957d31626f7SPaul Mackerras } 958d31626f7SPaul Mackerras 959d31626f7SPaul Mackerras void tm_reclaim_current(uint8_t cause) 960d31626f7SPaul Mackerras { 961d31626f7SPaul Mackerras tm_enable(); 962edd00b83SCyril Bur tm_reclaim_thread(¤t->thread, cause); 963d31626f7SPaul Mackerras } 964d31626f7SPaul Mackerras 965fb09692eSMichael Neuling static inline void tm_reclaim_task(struct task_struct *tsk) 966fb09692eSMichael Neuling { 967fb09692eSMichael Neuling /* We have to work out if we're switching from/to a task that's in the 968fb09692eSMichael Neuling * middle of a transaction. 969fb09692eSMichael Neuling * 970fb09692eSMichael Neuling * In switching we need to maintain a 2nd register state as 971fb09692eSMichael Neuling * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 972000ec280SCyril Bur * checkpointed (tbegin) state in ckpt_regs, ckfp_state and 973000ec280SCyril Bur * ckvr_state 974fb09692eSMichael Neuling * 975fb09692eSMichael Neuling * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 976fb09692eSMichael Neuling */ 977fb09692eSMichael Neuling struct thread_struct *thr = &tsk->thread; 978fb09692eSMichael Neuling 979fb09692eSMichael Neuling if (!thr->regs) 980fb09692eSMichael Neuling return; 981fb09692eSMichael Neuling 982fb09692eSMichael Neuling if (!MSR_TM_ACTIVE(thr->regs->msr)) 983fb09692eSMichael Neuling goto out_and_saveregs; 984fb09692eSMichael Neuling 98592fb8690SMichael Neuling WARN_ON(tm_suspend_disabled); 98692fb8690SMichael Neuling 987fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 988fb09692eSMichael Neuling "ccr=%lx, msr=%lx, trap=%lx)\n", 989fb09692eSMichael Neuling tsk->pid, thr->regs->nip, 990fb09692eSMichael Neuling thr->regs->ccr, thr->regs->msr, 991fb09692eSMichael Neuling thr->regs->trap); 992fb09692eSMichael Neuling 993edd00b83SCyril Bur tm_reclaim_thread(thr, TM_CAUSE_RESCHED); 994fb09692eSMichael Neuling 995fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d complete\n", 996fb09692eSMichael Neuling tsk->pid); 997fb09692eSMichael Neuling 998fb09692eSMichael Neuling out_and_saveregs: 999fb09692eSMichael Neuling /* Always save the regs here, even if a transaction's not active. 1000fb09692eSMichael Neuling * This context-switches a thread's TM info SPRs. We do it here to 1001fb09692eSMichael Neuling * be consistent with the restore path (in recheckpoint) which 1002fb09692eSMichael Neuling * cannot happen later in _switch(). 1003fb09692eSMichael Neuling */ 1004fb09692eSMichael Neuling tm_save_sprs(thr); 1005fb09692eSMichael Neuling } 1006fb09692eSMichael Neuling 1007eb5c3f1cSCyril Bur extern void __tm_recheckpoint(struct thread_struct *thread); 1008e6b8fd02SMichael Neuling 1009eb5c3f1cSCyril Bur void tm_recheckpoint(struct thread_struct *thread) 1010e6b8fd02SMichael Neuling { 1011e6b8fd02SMichael Neuling unsigned long flags; 1012e6b8fd02SMichael Neuling 10135d176f75SCyril Bur if (!(thread->regs->msr & MSR_TM)) 10145d176f75SCyril Bur return; 10155d176f75SCyril Bur 1016e6b8fd02SMichael Neuling /* We really can't be interrupted here as the TEXASR registers can't 1017e6b8fd02SMichael Neuling * change and later in the trecheckpoint code, we have a userspace R1. 1018e6b8fd02SMichael Neuling * So let's hard disable over this region. 1019e6b8fd02SMichael Neuling */ 1020e6b8fd02SMichael Neuling local_irq_save(flags); 1021e6b8fd02SMichael Neuling hard_irq_disable(); 1022e6b8fd02SMichael Neuling 1023e6b8fd02SMichael Neuling /* The TM SPRs are restored here, so that TEXASR.FS can be set 1024e6b8fd02SMichael Neuling * before the trecheckpoint and no explosion occurs. 1025e6b8fd02SMichael Neuling */ 1026e6b8fd02SMichael Neuling tm_restore_sprs(thread); 1027e6b8fd02SMichael Neuling 1028eb5c3f1cSCyril Bur __tm_recheckpoint(thread); 1029e6b8fd02SMichael Neuling 1030e6b8fd02SMichael Neuling local_irq_restore(flags); 1031e6b8fd02SMichael Neuling } 1032e6b8fd02SMichael Neuling 1033bc2a9408SMichael Neuling static inline void tm_recheckpoint_new_task(struct task_struct *new) 1034fb09692eSMichael Neuling { 1035fb09692eSMichael Neuling if (!cpu_has_feature(CPU_FTR_TM)) 1036fb09692eSMichael Neuling return; 1037fb09692eSMichael Neuling 1038fb09692eSMichael Neuling /* Recheckpoint the registers of the thread we're about to switch to. 1039fb09692eSMichael Neuling * 1040fb09692eSMichael Neuling * If the task was using FP, we non-lazily reload both the original and 1041fb09692eSMichael Neuling * the speculative FP register states. This is because the kernel 1042fb09692eSMichael Neuling * doesn't see if/when a TM rollback occurs, so if we take an FP 1043dc310669SCyril Bur * unavailable later, we are unable to determine which set of FP regs 1044fb09692eSMichael Neuling * need to be restored. 1045fb09692eSMichael Neuling */ 10465d176f75SCyril Bur if (!tm_enabled(new)) 1047fb09692eSMichael Neuling return; 1048fb09692eSMichael Neuling 1049e6b8fd02SMichael Neuling if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 1050fb09692eSMichael Neuling tm_restore_sprs(&new->thread); 1051fb09692eSMichael Neuling return; 1052e6b8fd02SMichael Neuling } 1053fb09692eSMichael Neuling /* Recheckpoint to restore original checkpointed register state. */ 1054eb5c3f1cSCyril Bur TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", 1055eb5c3f1cSCyril Bur new->pid, new->thread.regs->msr); 1056fb09692eSMichael Neuling 1057eb5c3f1cSCyril Bur tm_recheckpoint(&new->thread); 1058fb09692eSMichael Neuling 1059dc310669SCyril Bur /* 1060dc310669SCyril Bur * The checkpointed state has been restored but the live state has 1061dc310669SCyril Bur * not, ensure all the math functionality is turned off to trigger 1062dc310669SCyril Bur * restore_math() to reload. 1063dc310669SCyril Bur */ 1064dc310669SCyril Bur new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); 1065fb09692eSMichael Neuling 1066fb09692eSMichael Neuling TM_DEBUG("*** tm_recheckpoint of pid %d complete " 1067fb09692eSMichael Neuling "(kernel msr 0x%lx)\n", 1068fb09692eSMichael Neuling new->pid, mfmsr()); 1069fb09692eSMichael Neuling } 1070fb09692eSMichael Neuling 1071dc310669SCyril Bur static inline void __switch_to_tm(struct task_struct *prev, 1072dc310669SCyril Bur struct task_struct *new) 1073fb09692eSMichael Neuling { 1074fb09692eSMichael Neuling if (cpu_has_feature(CPU_FTR_TM)) { 10755d176f75SCyril Bur if (tm_enabled(prev) || tm_enabled(new)) 1076fb09692eSMichael Neuling tm_enable(); 10775d176f75SCyril Bur 10785d176f75SCyril Bur if (tm_enabled(prev)) { 10795d176f75SCyril Bur prev->thread.load_tm++; 1080fb09692eSMichael Neuling tm_reclaim_task(prev); 10815d176f75SCyril Bur if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) 10825d176f75SCyril Bur prev->thread.regs->msr &= ~MSR_TM; 10835d176f75SCyril Bur } 10845d176f75SCyril Bur 1085dc310669SCyril Bur tm_recheckpoint_new_task(new); 1086fb09692eSMichael Neuling } 1087fb09692eSMichael Neuling } 1088d31626f7SPaul Mackerras 1089d31626f7SPaul Mackerras /* 1090d31626f7SPaul Mackerras * This is called if we are on the way out to userspace and the 1091d31626f7SPaul Mackerras * TIF_RESTORE_TM flag is set. It checks if we need to reload 1092d31626f7SPaul Mackerras * FP and/or vector state and does so if necessary. 1093d31626f7SPaul Mackerras * If userspace is inside a transaction (whether active or 1094d31626f7SPaul Mackerras * suspended) and FP/VMX/VSX instructions have ever been enabled 1095d31626f7SPaul Mackerras * inside that transaction, then we have to keep them enabled 1096d31626f7SPaul Mackerras * and keep the FP/VMX/VSX state loaded while ever the transaction 1097d31626f7SPaul Mackerras * continues. The reason is that if we didn't, and subsequently 1098d31626f7SPaul Mackerras * got a FP/VMX/VSX unavailable interrupt inside a transaction, 1099d31626f7SPaul Mackerras * we don't know whether it's the same transaction, and thus we 1100d31626f7SPaul Mackerras * don't know which of the checkpointed state and the transactional 1101d31626f7SPaul Mackerras * state to use. 1102d31626f7SPaul Mackerras */ 1103d31626f7SPaul Mackerras void restore_tm_state(struct pt_regs *regs) 1104d31626f7SPaul Mackerras { 1105d31626f7SPaul Mackerras unsigned long msr_diff; 1106d31626f7SPaul Mackerras 1107dc310669SCyril Bur /* 1108dc310669SCyril Bur * This is the only moment we should clear TIF_RESTORE_TM as 1109dc310669SCyril Bur * it is here that ckpt_regs.msr and pt_regs.msr become the same 1110dc310669SCyril Bur * again, anything else could lead to an incorrect ckpt_msr being 1111dc310669SCyril Bur * saved and therefore incorrect signal contexts. 1112dc310669SCyril Bur */ 1113d31626f7SPaul Mackerras clear_thread_flag(TIF_RESTORE_TM); 1114d31626f7SPaul Mackerras if (!MSR_TM_ACTIVE(regs->msr)) 1115d31626f7SPaul Mackerras return; 1116d31626f7SPaul Mackerras 1117829023dfSAnshuman Khandual msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 1118d31626f7SPaul Mackerras msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 111970fe3d98SCyril Bur 1120dc16b553SCyril Bur /* Ensure that restore_math() will restore */ 1121dc16b553SCyril Bur if (msr_diff & MSR_FP) 1122dc16b553SCyril Bur current->thread.load_fp = 1; 112339715bf9SValentin Rothberg #ifdef CONFIG_ALTIVEC 1124dc16b553SCyril Bur if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) 1125dc16b553SCyril Bur current->thread.load_vec = 1; 1126dc16b553SCyril Bur #endif 112770fe3d98SCyril Bur restore_math(regs); 112870fe3d98SCyril Bur 1129d31626f7SPaul Mackerras regs->msr |= msr_diff; 1130d31626f7SPaul Mackerras } 1131d31626f7SPaul Mackerras 1132fb09692eSMichael Neuling #else 1133fb09692eSMichael Neuling #define tm_recheckpoint_new_task(new) 1134dc310669SCyril Bur #define __switch_to_tm(prev, new) 1135fb09692eSMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 11369422de3eSMichael Neuling 1137152d523eSAnton Blanchard static inline void save_sprs(struct thread_struct *t) 1138152d523eSAnton Blanchard { 1139152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 114001d7c2a2SOliver O'Halloran if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1141152d523eSAnton Blanchard t->vrsave = mfspr(SPRN_VRSAVE); 1142152d523eSAnton Blanchard #endif 1143152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1144152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) 1145152d523eSAnton Blanchard t->dscr = mfspr(SPRN_DSCR); 1146152d523eSAnton Blanchard 1147152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1148152d523eSAnton Blanchard t->bescr = mfspr(SPRN_BESCR); 1149152d523eSAnton Blanchard t->ebbhr = mfspr(SPRN_EBBHR); 1150152d523eSAnton Blanchard t->ebbrr = mfspr(SPRN_EBBRR); 1151152d523eSAnton Blanchard 1152152d523eSAnton Blanchard t->fscr = mfspr(SPRN_FSCR); 1153152d523eSAnton Blanchard 1154152d523eSAnton Blanchard /* 1155152d523eSAnton Blanchard * Note that the TAR is not available for use in the kernel. 1156152d523eSAnton Blanchard * (To provide this, the TAR should be backed up/restored on 1157152d523eSAnton Blanchard * exception entry/exit instead, and be in pt_regs. FIXME, 1158152d523eSAnton Blanchard * this should be in pt_regs anyway (for debug).) 1159152d523eSAnton Blanchard */ 1160152d523eSAnton Blanchard t->tar = mfspr(SPRN_TAR); 1161152d523eSAnton Blanchard } 1162152d523eSAnton Blanchard #endif 116306bb53b3SRam Pai 116406bb53b3SRam Pai thread_pkey_regs_save(t); 1165152d523eSAnton Blanchard } 1166152d523eSAnton Blanchard 1167152d523eSAnton Blanchard static inline void restore_sprs(struct thread_struct *old_thread, 1168152d523eSAnton Blanchard struct thread_struct *new_thread) 1169152d523eSAnton Blanchard { 1170152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 1171152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC) && 1172152d523eSAnton Blanchard old_thread->vrsave != new_thread->vrsave) 1173152d523eSAnton Blanchard mtspr(SPRN_VRSAVE, new_thread->vrsave); 1174152d523eSAnton Blanchard #endif 1175152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1176152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) { 1177152d523eSAnton Blanchard u64 dscr = get_paca()->dscr_default; 1178b57bd2deSMichael Neuling if (new_thread->dscr_inherit) 1179152d523eSAnton Blanchard dscr = new_thread->dscr; 1180152d523eSAnton Blanchard 1181152d523eSAnton Blanchard if (old_thread->dscr != dscr) 1182152d523eSAnton Blanchard mtspr(SPRN_DSCR, dscr); 1183152d523eSAnton Blanchard } 1184152d523eSAnton Blanchard 1185152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1186152d523eSAnton Blanchard if (old_thread->bescr != new_thread->bescr) 1187152d523eSAnton Blanchard mtspr(SPRN_BESCR, new_thread->bescr); 1188152d523eSAnton Blanchard if (old_thread->ebbhr != new_thread->ebbhr) 1189152d523eSAnton Blanchard mtspr(SPRN_EBBHR, new_thread->ebbhr); 1190152d523eSAnton Blanchard if (old_thread->ebbrr != new_thread->ebbrr) 1191152d523eSAnton Blanchard mtspr(SPRN_EBBRR, new_thread->ebbrr); 1192152d523eSAnton Blanchard 1193b57bd2deSMichael Neuling if (old_thread->fscr != new_thread->fscr) 1194b57bd2deSMichael Neuling mtspr(SPRN_FSCR, new_thread->fscr); 1195b57bd2deSMichael Neuling 1196152d523eSAnton Blanchard if (old_thread->tar != new_thread->tar) 1197152d523eSAnton Blanchard mtspr(SPRN_TAR, new_thread->tar); 1198152d523eSAnton Blanchard } 1199ec233edeSSukadev Bhattiprolu 12003449f191SAlastair D'Silva if (cpu_has_feature(CPU_FTR_P9_TIDR) && 1201ec233edeSSukadev Bhattiprolu old_thread->tidr != new_thread->tidr) 1202ec233edeSSukadev Bhattiprolu mtspr(SPRN_TIDR, new_thread->tidr); 1203152d523eSAnton Blanchard #endif 120406bb53b3SRam Pai 120506bb53b3SRam Pai thread_pkey_regs_restore(new_thread, old_thread); 1206152d523eSAnton Blanchard } 1207152d523eSAnton Blanchard 120814cf11afSPaul Mackerras struct task_struct *__switch_to(struct task_struct *prev, 120914cf11afSPaul Mackerras struct task_struct *new) 121014cf11afSPaul Mackerras { 121114cf11afSPaul Mackerras struct thread_struct *new_thread, *old_thread; 121214cf11afSPaul Mackerras struct task_struct *last; 1213d6bf29b4SPeter Zijlstra #ifdef CONFIG_PPC_BOOK3S_64 1214d6bf29b4SPeter Zijlstra struct ppc64_tlb_batch *batch; 1215d6bf29b4SPeter Zijlstra #endif 121614cf11afSPaul Mackerras 1217152d523eSAnton Blanchard new_thread = &new->thread; 1218152d523eSAnton Blanchard old_thread = ¤t->thread; 1219152d523eSAnton Blanchard 12207ba5fef7SMichael Neuling WARN_ON(!irqs_disabled()); 12217ba5fef7SMichael Neuling 12224e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 122369111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1224d6bf29b4SPeter Zijlstra if (batch->active) { 1225d6bf29b4SPeter Zijlstra current_thread_info()->local_flags |= _TLF_LAZY_MMU; 1226d6bf29b4SPeter Zijlstra if (batch->index) 1227d6bf29b4SPeter Zijlstra __flush_tlb_pending(batch); 1228d6bf29b4SPeter Zijlstra batch->active = 0; 1229d6bf29b4SPeter Zijlstra } 12304e003747SMichael Ellerman #endif /* CONFIG_PPC_BOOK3S_64 */ 123106d67d54SPaul Mackerras 1232f3d885ccSAnton Blanchard #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1233f3d885ccSAnton Blanchard switch_booke_debug_regs(&new->thread.debug); 1234f3d885ccSAnton Blanchard #else 1235f3d885ccSAnton Blanchard /* 1236f3d885ccSAnton Blanchard * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 1237f3d885ccSAnton Blanchard * schedule DABR 1238f3d885ccSAnton Blanchard */ 1239f3d885ccSAnton Blanchard #ifndef CONFIG_HAVE_HW_BREAKPOINT 1240303e6a9dSRavi Bangoria switch_hw_breakpoint(new); 1241f3d885ccSAnton Blanchard #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1242f3d885ccSAnton Blanchard #endif 1243f3d885ccSAnton Blanchard 1244f3d885ccSAnton Blanchard /* 1245f3d885ccSAnton Blanchard * We need to save SPRs before treclaim/trecheckpoint as these will 1246f3d885ccSAnton Blanchard * change a number of them. 1247f3d885ccSAnton Blanchard */ 1248f3d885ccSAnton Blanchard save_sprs(&prev->thread); 1249f3d885ccSAnton Blanchard 1250f3d885ccSAnton Blanchard /* Save FPU, Altivec, VSX and SPE state */ 1251f3d885ccSAnton Blanchard giveup_all(prev); 1252f3d885ccSAnton Blanchard 1253dc310669SCyril Bur __switch_to_tm(prev, new); 1254dc310669SCyril Bur 1255e4c0fc5fSNicholas Piggin if (!radix_enabled()) { 125644387e9fSAnton Blanchard /* 1257e4c0fc5fSNicholas Piggin * We can't take a PMU exception inside _switch() since there 1258e4c0fc5fSNicholas Piggin * is a window where the kernel stack SLB and the kernel stack 1259e4c0fc5fSNicholas Piggin * are out of sync. Hard disable here. 126044387e9fSAnton Blanchard */ 126144387e9fSAnton Blanchard hard_irq_disable(); 1262e4c0fc5fSNicholas Piggin } 1263bc2a9408SMichael Neuling 126420dbe670SAnton Blanchard /* 126520dbe670SAnton Blanchard * Call restore_sprs() before calling _switch(). If we move it after 126620dbe670SAnton Blanchard * _switch() then we miss out on calling it for new tasks. The reason 126720dbe670SAnton Blanchard * for this is we manually create a stack frame for new tasks that 126820dbe670SAnton Blanchard * directly returns through ret_from_fork() or 126920dbe670SAnton Blanchard * ret_from_kernel_thread(). See copy_thread() for details. 127020dbe670SAnton Blanchard */ 1271f3d885ccSAnton Blanchard restore_sprs(old_thread, new_thread); 1272f3d885ccSAnton Blanchard 127320dbe670SAnton Blanchard last = _switch(old_thread, new_thread); 127420dbe670SAnton Blanchard 12754e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 1276d6bf29b4SPeter Zijlstra if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1277d6bf29b4SPeter Zijlstra current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 127869111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1279d6bf29b4SPeter Zijlstra batch->active = 1; 1280d6bf29b4SPeter Zijlstra } 128170fe3d98SCyril Bur 128205b98791SChristophe Leroy if (current->thread.regs) { 128305b98791SChristophe Leroy restore_math(current->thread.regs); 128407d2a628SNicholas Piggin 128507d2a628SNicholas Piggin /* 1286dc462267SNicholas Piggin * On POWER9 the copy-paste buffer can only paste into 1287dc462267SNicholas Piggin * foreign real addresses, so unprivileged processes can not 1288dc462267SNicholas Piggin * see the data or use it in any way unless they have 1289dc462267SNicholas Piggin * foreign real mappings. If the new process has the foreign 1290dc462267SNicholas Piggin * real address mappings, we must issue a cp_abort to clear 1291dc462267SNicholas Piggin * any state and prevent snooping, corruption or a covert 1292dc462267SNicholas Piggin * channel. ISA v3.1 supports paste into local memory. 129307d2a628SNicholas Piggin */ 1294c420644cSHaren Myneni if (current->mm && 1295dc462267SNicholas Piggin (cpu_has_feature(CPU_FTR_ARCH_31) || 1296dc462267SNicholas Piggin atomic_read(¤t->mm->context.vas_windows))) 12979d2a4d71SSukadev Bhattiprolu asm volatile(PPC_CP_ABORT); 129807d2a628SNicholas Piggin } 12994e003747SMichael Ellerman #endif /* CONFIG_PPC_BOOK3S_64 */ 1300d6bf29b4SPeter Zijlstra 130114cf11afSPaul Mackerras return last; 130214cf11afSPaul Mackerras } 130314cf11afSPaul Mackerras 1304df13102fSChristophe Leroy #define NR_INSN_TO_PRINT 16 130506d67d54SPaul Mackerras 130606d67d54SPaul Mackerras static void show_instructions(struct pt_regs *regs) 130706d67d54SPaul Mackerras { 130806d67d54SPaul Mackerras int i; 1309a6e2c226SAneesh Kumar K.V unsigned long nip = regs->nip; 1310df13102fSChristophe Leroy unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); 131106d67d54SPaul Mackerras 131206d67d54SPaul Mackerras printk("Instruction dump:"); 131306d67d54SPaul Mackerras 1314a6e2c226SAneesh Kumar K.V /* 1315a6e2c226SAneesh Kumar K.V * If we were executing with the MMU off for instructions, adjust pc 1316a6e2c226SAneesh Kumar K.V * rather than printing XXXXXXXX. 1317a6e2c226SAneesh Kumar K.V */ 1318a6e2c226SAneesh Kumar K.V if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) { 1319a6e2c226SAneesh Kumar K.V pc = (unsigned long)phys_to_virt(pc); 1320a6e2c226SAneesh Kumar K.V nip = (unsigned long)phys_to_virt(regs->nip); 1321a6e2c226SAneesh Kumar K.V } 1322a6e2c226SAneesh Kumar K.V 1323df13102fSChristophe Leroy for (i = 0; i < NR_INSN_TO_PRINT; i++) { 132406d67d54SPaul Mackerras int instr; 132506d67d54SPaul Mackerras 132606d67d54SPaul Mackerras if (!(i % 8)) 13272ffd04deSAndrew Donnellan pr_cont("\n"); 132806d67d54SPaul Mackerras 132900ae36deSAnton Blanchard if (!__kernel_text_address(pc) || 133025f12ae4SChristoph Hellwig get_kernel_nofault(instr, (const void *)pc)) { 13312ffd04deSAndrew Donnellan pr_cont("XXXXXXXX "); 133206d67d54SPaul Mackerras } else { 1333a6e2c226SAneesh Kumar K.V if (nip == pc) 13342ffd04deSAndrew Donnellan pr_cont("<%08x> ", instr); 133506d67d54SPaul Mackerras else 13362ffd04deSAndrew Donnellan pr_cont("%08x ", instr); 133706d67d54SPaul Mackerras } 133806d67d54SPaul Mackerras 133906d67d54SPaul Mackerras pc += sizeof(int); 134006d67d54SPaul Mackerras } 134106d67d54SPaul Mackerras 13422ffd04deSAndrew Donnellan pr_cont("\n"); 134306d67d54SPaul Mackerras } 134406d67d54SPaul Mackerras 134588b0fe17SMurilo Opsfelder Araujo void show_user_instructions(struct pt_regs *regs) 134688b0fe17SMurilo Opsfelder Araujo { 134788b0fe17SMurilo Opsfelder Araujo unsigned long pc; 1348df13102fSChristophe Leroy int n = NR_INSN_TO_PRINT; 1349fb2d9505SChristophe Leroy struct seq_buf s; 1350fb2d9505SChristophe Leroy char buf[96]; /* enough for 8 times 9 + 2 chars */ 135188b0fe17SMurilo Opsfelder Araujo 1352df13102fSChristophe Leroy pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); 135388b0fe17SMurilo Opsfelder Araujo 1354fb2d9505SChristophe Leroy seq_buf_init(&s, buf, sizeof(buf)); 135588b0fe17SMurilo Opsfelder Araujo 1356fb2d9505SChristophe Leroy while (n) { 1357fb2d9505SChristophe Leroy int i; 1358fb2d9505SChristophe Leroy 1359fb2d9505SChristophe Leroy seq_buf_clear(&s); 1360fb2d9505SChristophe Leroy 1361fb2d9505SChristophe Leroy for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) { 136288b0fe17SMurilo Opsfelder Araujo int instr; 136388b0fe17SMurilo Opsfelder Araujo 1364c0ee37e8SChristoph Hellwig if (copy_from_user_nofault(&instr, (void __user *)pc, 1365c0ee37e8SChristoph Hellwig sizeof(instr))) { 1366fb2d9505SChristophe Leroy seq_buf_printf(&s, "XXXXXXXX "); 1367fb2d9505SChristophe Leroy continue; 1368fb2d9505SChristophe Leroy } 1369fb2d9505SChristophe Leroy seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr); 137088b0fe17SMurilo Opsfelder Araujo } 137188b0fe17SMurilo Opsfelder Araujo 1372fb2d9505SChristophe Leroy if (!seq_buf_has_overflowed(&s)) 1373fb2d9505SChristophe Leroy pr_info("%s[%d]: code: %s\n", current->comm, 1374fb2d9505SChristophe Leroy current->pid, s.buffer); 137588b0fe17SMurilo Opsfelder Araujo } 137688b0fe17SMurilo Opsfelder Araujo } 137788b0fe17SMurilo Opsfelder Araujo 1378801c0b2cSMichael Neuling struct regbit { 137906d67d54SPaul Mackerras unsigned long bit; 138006d67d54SPaul Mackerras const char *name; 1381801c0b2cSMichael Neuling }; 1382801c0b2cSMichael Neuling 1383801c0b2cSMichael Neuling static struct regbit msr_bits[] = { 13843bfd0c9cSAnton Blanchard #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 13853bfd0c9cSAnton Blanchard {MSR_SF, "SF"}, 13863bfd0c9cSAnton Blanchard {MSR_HV, "HV"}, 13873bfd0c9cSAnton Blanchard #endif 13883bfd0c9cSAnton Blanchard {MSR_VEC, "VEC"}, 13893bfd0c9cSAnton Blanchard {MSR_VSX, "VSX"}, 13903bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13913bfd0c9cSAnton Blanchard {MSR_CE, "CE"}, 13923bfd0c9cSAnton Blanchard #endif 139306d67d54SPaul Mackerras {MSR_EE, "EE"}, 139406d67d54SPaul Mackerras {MSR_PR, "PR"}, 139506d67d54SPaul Mackerras {MSR_FP, "FP"}, 139606d67d54SPaul Mackerras {MSR_ME, "ME"}, 13973bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13981b98326bSKumar Gala {MSR_DE, "DE"}, 13993bfd0c9cSAnton Blanchard #else 14003bfd0c9cSAnton Blanchard {MSR_SE, "SE"}, 14013bfd0c9cSAnton Blanchard {MSR_BE, "BE"}, 14023bfd0c9cSAnton Blanchard #endif 140306d67d54SPaul Mackerras {MSR_IR, "IR"}, 140406d67d54SPaul Mackerras {MSR_DR, "DR"}, 14053bfd0c9cSAnton Blanchard {MSR_PMM, "PMM"}, 14063bfd0c9cSAnton Blanchard #ifndef CONFIG_BOOKE 14073bfd0c9cSAnton Blanchard {MSR_RI, "RI"}, 14083bfd0c9cSAnton Blanchard {MSR_LE, "LE"}, 14093bfd0c9cSAnton Blanchard #endif 141006d67d54SPaul Mackerras {0, NULL} 141106d67d54SPaul Mackerras }; 141206d67d54SPaul Mackerras 1413801c0b2cSMichael Neuling static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 141406d67d54SPaul Mackerras { 1415801c0b2cSMichael Neuling const char *s = ""; 141606d67d54SPaul Mackerras 141706d67d54SPaul Mackerras for (; bits->bit; ++bits) 141806d67d54SPaul Mackerras if (val & bits->bit) { 1419db5ba5aeSMichael Ellerman pr_cont("%s%s", s, bits->name); 1420801c0b2cSMichael Neuling s = sep; 142106d67d54SPaul Mackerras } 1422801c0b2cSMichael Neuling } 1423801c0b2cSMichael Neuling 1424801c0b2cSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1425801c0b2cSMichael Neuling static struct regbit msr_tm_bits[] = { 1426801c0b2cSMichael Neuling {MSR_TS_T, "T"}, 1427801c0b2cSMichael Neuling {MSR_TS_S, "S"}, 1428801c0b2cSMichael Neuling {MSR_TM, "E"}, 1429801c0b2cSMichael Neuling {0, NULL} 1430801c0b2cSMichael Neuling }; 1431801c0b2cSMichael Neuling 1432801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) 1433801c0b2cSMichael Neuling { 1434801c0b2cSMichael Neuling /* 1435801c0b2cSMichael Neuling * This only prints something if at least one of the TM bit is set. 1436801c0b2cSMichael Neuling * Inside the TM[], the output means: 1437801c0b2cSMichael Neuling * E: Enabled (bit 32) 1438801c0b2cSMichael Neuling * S: Suspended (bit 33) 1439801c0b2cSMichael Neuling * T: Transactional (bit 34) 1440801c0b2cSMichael Neuling */ 1441801c0b2cSMichael Neuling if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1442db5ba5aeSMichael Ellerman pr_cont(",TM["); 1443801c0b2cSMichael Neuling print_bits(val, msr_tm_bits, ""); 1444db5ba5aeSMichael Ellerman pr_cont("]"); 1445801c0b2cSMichael Neuling } 1446801c0b2cSMichael Neuling } 1447801c0b2cSMichael Neuling #else 1448801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) {} 1449801c0b2cSMichael Neuling #endif 1450801c0b2cSMichael Neuling 1451801c0b2cSMichael Neuling static void print_msr_bits(unsigned long val) 1452801c0b2cSMichael Neuling { 1453db5ba5aeSMichael Ellerman pr_cont("<"); 1454801c0b2cSMichael Neuling print_bits(val, msr_bits, ","); 1455801c0b2cSMichael Neuling print_tm_bits(val); 1456db5ba5aeSMichael Ellerman pr_cont(">"); 145706d67d54SPaul Mackerras } 145806d67d54SPaul Mackerras 145906d67d54SPaul Mackerras #ifdef CONFIG_PPC64 1460f6f7dde3Santon@samba.org #define REG "%016lx" 146106d67d54SPaul Mackerras #define REGS_PER_LINE 4 146206d67d54SPaul Mackerras #define LAST_VOLATILE 13 146306d67d54SPaul Mackerras #else 1464f6f7dde3Santon@samba.org #define REG "%08lx" 146506d67d54SPaul Mackerras #define REGS_PER_LINE 8 146606d67d54SPaul Mackerras #define LAST_VOLATILE 12 146706d67d54SPaul Mackerras #endif 146806d67d54SPaul Mackerras 146914cf11afSPaul Mackerras void show_regs(struct pt_regs * regs) 147014cf11afSPaul Mackerras { 147114cf11afSPaul Mackerras int i, trap; 147214cf11afSPaul Mackerras 1473a43cb95dSTejun Heo show_regs_print_info(KERN_DEFAULT); 1474a43cb95dSTejun Heo 147506d67d54SPaul Mackerras printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 147606d67d54SPaul Mackerras regs->nip, regs->link, regs->ctr); 1477182dc9c7SMichael Ellerman printk("REGS: %px TRAP: %04lx %s (%s)\n", 147896b644bdSSerge E. Hallyn regs, regs->trap, print_tainted(), init_utsname()->release); 147906d67d54SPaul Mackerras printk("MSR: "REG" ", regs->msr); 1480801c0b2cSMichael Neuling print_msr_bits(regs->msr); 1481f6fc73fbSMichael Ellerman pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 148214cf11afSPaul Mackerras trap = TRAP(regs); 1483912237eaSNicholas Piggin if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR)) 14847dae865fSMichael Ellerman pr_cont("CFAR: "REG" ", regs->orig_gpr3); 14852ec42996SChristophe Leroy if (trap == 0x200 || trap == 0x300 || trap == 0x600) { 14862ec42996SChristophe Leroy if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE)) 14877dae865fSMichael Ellerman pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 14882ec42996SChristophe Leroy else 14897dae865fSMichael Ellerman pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 14902ec42996SChristophe Leroy } 14912ec42996SChristophe Leroy 14929db8bcfdSAnton Blanchard #ifdef CONFIG_PPC64 14933130a7bbSNicholas Piggin pr_cont("IRQMASK: %lx ", regs->softe); 14949db8bcfdSAnton Blanchard #endif 14959db8bcfdSAnton Blanchard #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 14966d888d1aSAnton Blanchard if (MSR_TM_ACTIVE(regs->msr)) 14977dae865fSMichael Ellerman pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 149814170789SKumar Gala #endif 149914cf11afSPaul Mackerras 150014cf11afSPaul Mackerras for (i = 0; i < 32; i++) { 150106d67d54SPaul Mackerras if ((i % REGS_PER_LINE) == 0) 15027dae865fSMichael Ellerman pr_cont("\nGPR%02d: ", i); 15037dae865fSMichael Ellerman pr_cont(REG " ", regs->gpr[i]); 150406d67d54SPaul Mackerras if (i == LAST_VOLATILE && !FULL_REGS(regs)) 150514cf11afSPaul Mackerras break; 150614cf11afSPaul Mackerras } 15077dae865fSMichael Ellerman pr_cont("\n"); 150814cf11afSPaul Mackerras /* 150914cf11afSPaul Mackerras * Lookup NIP late so we have the best change of getting the 151014cf11afSPaul Mackerras * above info out without failing 151114cf11afSPaul Mackerras */ 15128f020c7cSChristophe Leroy if (IS_ENABLED(CONFIG_KALLSYMS)) { 1513058c78f4SBenjamin Herrenschmidt printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1514058c78f4SBenjamin Herrenschmidt printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 15158f020c7cSChristophe Leroy } 15169cb8f069SDmitry Safonov show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT); 151706d67d54SPaul Mackerras if (!user_mode(regs)) 151806d67d54SPaul Mackerras show_instructions(regs); 151914cf11afSPaul Mackerras } 152014cf11afSPaul Mackerras 152114cf11afSPaul Mackerras void flush_thread(void) 152214cf11afSPaul Mackerras { 1523e0780b72SK.Prasad #ifdef CONFIG_HAVE_HW_BREAKPOINT 15245aae8a53SK.Prasad flush_ptrace_hw_breakpoint(current); 1525e0780b72SK.Prasad #else /* CONFIG_HAVE_HW_BREAKPOINT */ 15263bffb652SDave Kleikamp set_debug_reg_defaults(¤t->thread); 1527e0780b72SK.Prasad #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 152814cf11afSPaul Mackerras } 152914cf11afSPaul Mackerras 1530425d3314SNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 1531425d3314SNicholas Piggin void arch_setup_new_exec(void) 1532425d3314SNicholas Piggin { 1533425d3314SNicholas Piggin if (radix_enabled()) 1534425d3314SNicholas Piggin return; 1535425d3314SNicholas Piggin hash__setup_new_exec(); 1536425d3314SNicholas Piggin } 1537425d3314SNicholas Piggin #endif 1538425d3314SNicholas Piggin 1539ec233edeSSukadev Bhattiprolu #ifdef CONFIG_PPC64 154071cc64a8SAlastair D'Silva /** 154171cc64a8SAlastair D'Silva * Assign a TIDR (thread ID) for task @t and set it in the thread 1542ec233edeSSukadev Bhattiprolu * structure. For now, we only support setting TIDR for 'current' task. 154371cc64a8SAlastair D'Silva * 154471cc64a8SAlastair D'Silva * Since the TID value is a truncated form of it PID, it is possible 154571cc64a8SAlastair D'Silva * (but unlikely) for 2 threads to have the same TID. In the unlikely event 154671cc64a8SAlastair D'Silva * that 2 threads share the same TID and are waiting, one of the following 154771cc64a8SAlastair D'Silva * cases will happen: 154871cc64a8SAlastair D'Silva * 154971cc64a8SAlastair D'Silva * 1. The correct thread is running, the wrong thread is not 155071cc64a8SAlastair D'Silva * In this situation, the correct thread is woken and proceeds to pass it's 155171cc64a8SAlastair D'Silva * condition check. 155271cc64a8SAlastair D'Silva * 155371cc64a8SAlastair D'Silva * 2. Neither threads are running 155471cc64a8SAlastair D'Silva * In this situation, neither thread will be woken. When scheduled, the waiting 155571cc64a8SAlastair D'Silva * threads will execute either a wait, which will return immediately, followed 155671cc64a8SAlastair D'Silva * by a condition check, which will pass for the correct thread and fail 155771cc64a8SAlastair D'Silva * for the wrong thread, or they will execute the condition check immediately. 155871cc64a8SAlastair D'Silva * 155971cc64a8SAlastair D'Silva * 3. The wrong thread is running, the correct thread is not 156071cc64a8SAlastair D'Silva * The wrong thread will be woken, but will fail it's condition check and 156171cc64a8SAlastair D'Silva * re-execute wait. The correct thread, when scheduled, will execute either 156271cc64a8SAlastair D'Silva * it's condition check (which will pass), or wait, which returns immediately 156371cc64a8SAlastair D'Silva * when called the first time after the thread is scheduled, followed by it's 156471cc64a8SAlastair D'Silva * condition check (which will pass). 156571cc64a8SAlastair D'Silva * 156671cc64a8SAlastair D'Silva * 4. Both threads are running 156771cc64a8SAlastair D'Silva * Both threads will be woken. The wrong thread will fail it's condition check 156871cc64a8SAlastair D'Silva * and execute another wait, while the correct thread will pass it's condition 156971cc64a8SAlastair D'Silva * check. 157071cc64a8SAlastair D'Silva * 157171cc64a8SAlastair D'Silva * @t: the task to set the thread ID for 1572ec233edeSSukadev Bhattiprolu */ 1573ec233edeSSukadev Bhattiprolu int set_thread_tidr(struct task_struct *t) 1574ec233edeSSukadev Bhattiprolu { 15753449f191SAlastair D'Silva if (!cpu_has_feature(CPU_FTR_P9_TIDR)) 1576ec233edeSSukadev Bhattiprolu return -EINVAL; 1577ec233edeSSukadev Bhattiprolu 1578ec233edeSSukadev Bhattiprolu if (t != current) 1579ec233edeSSukadev Bhattiprolu return -EINVAL; 1580ec233edeSSukadev Bhattiprolu 15817e4d4233SVaibhav Jain if (t->thread.tidr) 15827e4d4233SVaibhav Jain return 0; 15837e4d4233SVaibhav Jain 158471cc64a8SAlastair D'Silva t->thread.tidr = (u16)task_pid_nr(t); 1585ec233edeSSukadev Bhattiprolu mtspr(SPRN_TIDR, t->thread.tidr); 1586ec233edeSSukadev Bhattiprolu 1587ec233edeSSukadev Bhattiprolu return 0; 1588ec233edeSSukadev Bhattiprolu } 1589b1db5513SChristophe Lombard EXPORT_SYMBOL_GPL(set_thread_tidr); 1590ec233edeSSukadev Bhattiprolu 1591ec233edeSSukadev Bhattiprolu #endif /* CONFIG_PPC64 */ 1592ec233edeSSukadev Bhattiprolu 159314cf11afSPaul Mackerras void 159414cf11afSPaul Mackerras release_thread(struct task_struct *t) 159514cf11afSPaul Mackerras { 159614cf11afSPaul Mackerras } 159714cf11afSPaul Mackerras 159814cf11afSPaul Mackerras /* 159955ccf3feSSuresh Siddha * this gets called so that we can store coprocessor state into memory and 160055ccf3feSSuresh Siddha * copy the current task into the new thread. 160114cf11afSPaul Mackerras */ 160255ccf3feSSuresh Siddha int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 160314cf11afSPaul Mackerras { 1604579e633eSAnton Blanchard flush_all_to_thread(src); 1605621b5060SMichael Neuling /* 1606621b5060SMichael Neuling * Flush TM state out so we can copy it. __switch_to_tm() does this 1607621b5060SMichael Neuling * flush but it removes the checkpointed state from the current CPU and 1608621b5060SMichael Neuling * transitions the CPU out of TM mode. Hence we need to call 1609621b5060SMichael Neuling * tm_recheckpoint_new_task() (on the same task) to restore the 1610621b5060SMichael Neuling * checkpointed state back and the TM mode. 16115d176f75SCyril Bur * 16125d176f75SCyril Bur * Can't pass dst because it isn't ready. Doesn't matter, passing 16135d176f75SCyril Bur * dst is only important for __switch_to() 1614621b5060SMichael Neuling */ 1615dc310669SCyril Bur __switch_to_tm(src, src); 1616330a1eb7SMichael Ellerman 161755ccf3feSSuresh Siddha *dst = *src; 1618330a1eb7SMichael Ellerman 1619330a1eb7SMichael Ellerman clear_task_ebb(dst); 1620330a1eb7SMichael Ellerman 162155ccf3feSSuresh Siddha return 0; 162214cf11afSPaul Mackerras } 162314cf11afSPaul Mackerras 1624cec15488SMichael Ellerman static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1625cec15488SMichael Ellerman { 16264e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 1627cec15488SMichael Ellerman unsigned long sp_vsid; 1628cec15488SMichael Ellerman unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1629cec15488SMichael Ellerman 1630caca285eSAneesh Kumar K.V if (radix_enabled()) 1631caca285eSAneesh Kumar K.V return; 1632caca285eSAneesh Kumar K.V 1633cec15488SMichael Ellerman if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1634cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1635cec15488SMichael Ellerman << SLB_VSID_SHIFT_1T; 1636cec15488SMichael Ellerman else 1637cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1638cec15488SMichael Ellerman << SLB_VSID_SHIFT; 1639cec15488SMichael Ellerman sp_vsid |= SLB_VSID_KERNEL | llp; 1640cec15488SMichael Ellerman p->thread.ksp_vsid = sp_vsid; 1641cec15488SMichael Ellerman #endif 1642cec15488SMichael Ellerman } 1643cec15488SMichael Ellerman 164414cf11afSPaul Mackerras /* 164514cf11afSPaul Mackerras * Copy a thread.. 164614cf11afSPaul Mackerras */ 1647efcac658SAlexey Kardashevskiy 16486eca8933SAlex Dowad /* 16496eca8933SAlex Dowad * Copy architecture-specific thread state 16506eca8933SAlex Dowad */ 1651714acdbdSChristian Brauner int copy_thread(unsigned long clone_flags, unsigned long usp, 1652facd04a9SNicholas Piggin unsigned long kthread_arg, struct task_struct *p, 1653facd04a9SNicholas Piggin unsigned long tls) 165414cf11afSPaul Mackerras { 165514cf11afSPaul Mackerras struct pt_regs *childregs, *kregs; 165614cf11afSPaul Mackerras extern void ret_from_fork(void); 16577fa95f9aSNicholas Piggin extern void ret_from_fork_scv(void); 165858254e10SAl Viro extern void ret_from_kernel_thread(void); 165958254e10SAl Viro void (*f)(void); 16600cec6fd1SAl Viro unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 16615d31a96eSMichael Ellerman struct thread_info *ti = task_thread_info(p); 16626b424efaSRavi Bangoria #ifdef CONFIG_HAVE_HW_BREAKPOINT 16636b424efaSRavi Bangoria int i; 16646b424efaSRavi Bangoria #endif 16655d31a96eSMichael Ellerman 1666ed1cd6deSChristophe Leroy klp_init_thread_info(p); 166714cf11afSPaul Mackerras 166814cf11afSPaul Mackerras /* Copy registers */ 166914cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 167014cf11afSPaul Mackerras childregs = (struct pt_regs *) sp; 1671ab75819dSAl Viro if (unlikely(p->flags & PF_KTHREAD)) { 16726eca8933SAlex Dowad /* kernel thread */ 167358254e10SAl Viro memset(childregs, 0, sizeof(struct pt_regs)); 167414cf11afSPaul Mackerras childregs->gpr[1] = sp + sizeof(struct pt_regs); 16757cedd601SAnton Blanchard /* function */ 16767cedd601SAnton Blanchard if (usp) 16777cedd601SAnton Blanchard childregs->gpr[14] = ppc_function_entry((void *)usp); 167858254e10SAl Viro #ifdef CONFIG_PPC64 1679b5e2fc1cSAl Viro clear_tsk_thread_flag(p, TIF_32BIT); 1680c2e480baSMadhavan Srinivasan childregs->softe = IRQS_ENABLED; 168106d67d54SPaul Mackerras #endif 16826eca8933SAlex Dowad childregs->gpr[15] = kthread_arg; 168314cf11afSPaul Mackerras p->thread.regs = NULL; /* no user register state */ 1684138d1ce8SAl Viro ti->flags |= _TIF_RESTOREALL; 168558254e10SAl Viro f = ret_from_kernel_thread; 168614cf11afSPaul Mackerras } else { 16876eca8933SAlex Dowad /* user thread */ 1688afa86fc4SAl Viro struct pt_regs *regs = current_pt_regs(); 168958254e10SAl Viro CHECK_FULL_REGS(regs); 169058254e10SAl Viro *childregs = *regs; 1691ea516b11SAl Viro if (usp) 169214cf11afSPaul Mackerras childregs->gpr[1] = usp; 169314cf11afSPaul Mackerras p->thread.regs = childregs; 16947fa95f9aSNicholas Piggin /* 64s sets this in ret_from_fork */ 16957fa95f9aSNicholas Piggin if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64)) 169658254e10SAl Viro childregs->gpr[3] = 0; /* Result from fork() */ 169706d67d54SPaul Mackerras if (clone_flags & CLONE_SETTLS) { 16989904b005SDenis Kirjanov if (!is_32bit_task()) 1699facd04a9SNicholas Piggin childregs->gpr[13] = tls; 170006d67d54SPaul Mackerras else 1701facd04a9SNicholas Piggin childregs->gpr[2] = tls; 170214cf11afSPaul Mackerras } 170358254e10SAl Viro 17047fa95f9aSNicholas Piggin if (trap_is_scv(regs)) 17057fa95f9aSNicholas Piggin f = ret_from_fork_scv; 17067fa95f9aSNicholas Piggin else 170758254e10SAl Viro f = ret_from_fork; 170806d67d54SPaul Mackerras } 1709d272f667SCyril Bur childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); 171014cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 171114cf11afSPaul Mackerras 171214cf11afSPaul Mackerras /* 171314cf11afSPaul Mackerras * The way this works is that at some point in the future 171414cf11afSPaul Mackerras * some task will call _switch to switch to the new task. 171514cf11afSPaul Mackerras * That will pop off the stack frame created below and start 171614cf11afSPaul Mackerras * the new task running at ret_from_fork. The new task will 171714cf11afSPaul Mackerras * do some house keeping and then return from the fork or clone 171814cf11afSPaul Mackerras * system call, using the stack frame created above. 171914cf11afSPaul Mackerras */ 1720af945cf4SLi Zhong ((unsigned long *)sp)[0] = 0; 172114cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 172214cf11afSPaul Mackerras kregs = (struct pt_regs *) sp; 172314cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 172414cf11afSPaul Mackerras p->thread.ksp = sp; 1725cbc9565eSBenjamin Herrenschmidt #ifdef CONFIG_PPC32 1726a7916a1dSChristophe Leroy p->thread.ksp_limit = (unsigned long)end_of_stack(p); 1727cbc9565eSBenjamin Herrenschmidt #endif 172828d170abSOleg Nesterov #ifdef CONFIG_HAVE_HW_BREAKPOINT 17296b424efaSRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) 17306b424efaSRavi Bangoria p->thread.ptrace_bps[i] = NULL; 173128d170abSOleg Nesterov #endif 173228d170abSOleg Nesterov 173318461960SPaul Mackerras p->thread.fp_save_area = NULL; 173418461960SPaul Mackerras #ifdef CONFIG_ALTIVEC 173518461960SPaul Mackerras p->thread.vr_save_area = NULL; 173618461960SPaul Mackerras #endif 173718461960SPaul Mackerras 1738cec15488SMichael Ellerman setup_ksp_vsid(p, sp); 173906d67d54SPaul Mackerras 1740efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64 1741efcac658SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_DSCR)) { 17421021cb26SAnton Blanchard p->thread.dscr_inherit = current->thread.dscr_inherit; 1743db1231dcSAnton Blanchard p->thread.dscr = mfspr(SPRN_DSCR); 1744efcac658SAlexey Kardashevskiy } 174592779245SHaren Myneni if (cpu_has_feature(CPU_FTR_HAS_PPR)) 17464c2de74cSNicholas Piggin childregs->ppr = DEFAULT_PPR; 1747ec233edeSSukadev Bhattiprolu 1748ec233edeSSukadev Bhattiprolu p->thread.tidr = 0; 1749efcac658SAlexey Kardashevskiy #endif 17507cedd601SAnton Blanchard kregs->nip = ppc_function_entry(f); 175114cf11afSPaul Mackerras return 0; 175214cf11afSPaul Mackerras } 175314cf11afSPaul Mackerras 17545434ae74SNicholas Piggin void preload_new_slb_context(unsigned long start, unsigned long sp); 17555434ae74SNicholas Piggin 175614cf11afSPaul Mackerras /* 175714cf11afSPaul Mackerras * Set up a thread for executing a new program 175814cf11afSPaul Mackerras */ 175906d67d54SPaul Mackerras void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 176014cf11afSPaul Mackerras { 176190eac727SMichael Ellerman #ifdef CONFIG_PPC64 176290eac727SMichael Ellerman unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 17635434ae74SNicholas Piggin 1764bfac2799SChristophe Leroy if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !radix_enabled()) 17655434ae74SNicholas Piggin preload_new_slb_context(start, sp); 17665434ae74SNicholas Piggin #endif 176790eac727SMichael Ellerman 176806d67d54SPaul Mackerras /* 176906d67d54SPaul Mackerras * If we exec out of a kernel thread then thread.regs will not be 177006d67d54SPaul Mackerras * set. Do it now. 177106d67d54SPaul Mackerras */ 177206d67d54SPaul Mackerras if (!current->thread.regs) { 17730cec6fd1SAl Viro struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 17740cec6fd1SAl Viro current->thread.regs = regs - 1; 177506d67d54SPaul Mackerras } 177606d67d54SPaul Mackerras 17778e96a87cSCyril Bur #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 17788e96a87cSCyril Bur /* 17798e96a87cSCyril Bur * Clear any transactional state, we're exec()ing. The cause is 17808e96a87cSCyril Bur * not important as there will never be a recheckpoint so it's not 17818e96a87cSCyril Bur * user visible. 17828e96a87cSCyril Bur */ 17838e96a87cSCyril Bur if (MSR_TM_SUSPENDED(mfmsr())) 17848e96a87cSCyril Bur tm_reclaim_current(0); 17858e96a87cSCyril Bur #endif 17868e96a87cSCyril Bur 178714cf11afSPaul Mackerras memset(regs->gpr, 0, sizeof(regs->gpr)); 178814cf11afSPaul Mackerras regs->ctr = 0; 178914cf11afSPaul Mackerras regs->link = 0; 179014cf11afSPaul Mackerras regs->xer = 0; 179114cf11afSPaul Mackerras regs->ccr = 0; 179214cf11afSPaul Mackerras regs->gpr[1] = sp; 179306d67d54SPaul Mackerras 1794474f8196SRoland McGrath /* 1795474f8196SRoland McGrath * We have just cleared all the nonvolatile GPRs, so make 1796474f8196SRoland McGrath * FULL_REGS(regs) return true. This is necessary to allow 1797474f8196SRoland McGrath * ptrace to examine the thread immediately after exec. 1798474f8196SRoland McGrath */ 1799feb9df34SNicholas Piggin SET_FULL_REGS(regs); 1800474f8196SRoland McGrath 180106d67d54SPaul Mackerras #ifdef CONFIG_PPC32 180206d67d54SPaul Mackerras regs->mq = 0; 180306d67d54SPaul Mackerras regs->nip = start; 180414cf11afSPaul Mackerras regs->msr = MSR_USER; 180506d67d54SPaul Mackerras #else 18069904b005SDenis Kirjanov if (!is_32bit_task()) { 180794af3abfSRusty Russell unsigned long entry; 180806d67d54SPaul Mackerras 180994af3abfSRusty Russell if (is_elf2_task()) { 181094af3abfSRusty Russell /* Look ma, no function descriptors! */ 181194af3abfSRusty Russell entry = start; 181294af3abfSRusty Russell 181394af3abfSRusty Russell /* 181494af3abfSRusty Russell * Ulrich says: 181594af3abfSRusty Russell * The latest iteration of the ABI requires that when 181694af3abfSRusty Russell * calling a function (at its global entry point), 181794af3abfSRusty Russell * the caller must ensure r12 holds the entry point 181894af3abfSRusty Russell * address (so that the function can quickly 181994af3abfSRusty Russell * establish addressability). 182094af3abfSRusty Russell */ 182194af3abfSRusty Russell regs->gpr[12] = start; 182294af3abfSRusty Russell /* Make sure that's restored on entry to userspace. */ 182394af3abfSRusty Russell set_thread_flag(TIF_RESTOREALL); 182494af3abfSRusty Russell } else { 182594af3abfSRusty Russell unsigned long toc; 182694af3abfSRusty Russell 182794af3abfSRusty Russell /* start is a relocated pointer to the function 182894af3abfSRusty Russell * descriptor for the elf _start routine. The first 182994af3abfSRusty Russell * entry in the function descriptor is the entry 183094af3abfSRusty Russell * address of _start and the second entry is the TOC 183194af3abfSRusty Russell * value we need to use. 183206d67d54SPaul Mackerras */ 183306d67d54SPaul Mackerras __get_user(entry, (unsigned long __user *)start); 183406d67d54SPaul Mackerras __get_user(toc, (unsigned long __user *)start+1); 183506d67d54SPaul Mackerras 183606d67d54SPaul Mackerras /* Check whether the e_entry function descriptor entries 183706d67d54SPaul Mackerras * need to be relocated before we can use them. 183806d67d54SPaul Mackerras */ 183906d67d54SPaul Mackerras if (load_addr != 0) { 184006d67d54SPaul Mackerras entry += load_addr; 184106d67d54SPaul Mackerras toc += load_addr; 184206d67d54SPaul Mackerras } 184306d67d54SPaul Mackerras regs->gpr[2] = toc; 184494af3abfSRusty Russell } 184594af3abfSRusty Russell regs->nip = entry; 184606d67d54SPaul Mackerras regs->msr = MSR_USER64; 1847d4bf9a78SStephen Rothwell } else { 1848d4bf9a78SStephen Rothwell regs->nip = start; 1849d4bf9a78SStephen Rothwell regs->gpr[2] = 0; 1850d4bf9a78SStephen Rothwell regs->msr = MSR_USER32; 185106d67d54SPaul Mackerras } 185206d67d54SPaul Mackerras #endif 1853ce48b210SMichael Neuling #ifdef CONFIG_VSX 1854ce48b210SMichael Neuling current->thread.used_vsr = 0; 1855ce48b210SMichael Neuling #endif 18565434ae74SNicholas Piggin current->thread.load_slb = 0; 18571195892cSBreno Leitao current->thread.load_fp = 0; 1858de79f7b9SPaul Mackerras memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 185918461960SPaul Mackerras current->thread.fp_save_area = NULL; 186014cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 1861de79f7b9SPaul Mackerras memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1862de79f7b9SPaul Mackerras current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 186318461960SPaul Mackerras current->thread.vr_save_area = NULL; 186414cf11afSPaul Mackerras current->thread.vrsave = 0; 186514cf11afSPaul Mackerras current->thread.used_vr = 0; 18661195892cSBreno Leitao current->thread.load_vec = 0; 186714cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 186814cf11afSPaul Mackerras #ifdef CONFIG_SPE 186914cf11afSPaul Mackerras memset(current->thread.evr, 0, sizeof(current->thread.evr)); 187014cf11afSPaul Mackerras current->thread.acc = 0; 187114cf11afSPaul Mackerras current->thread.spefscr = 0; 187214cf11afSPaul Mackerras current->thread.used_spe = 0; 187314cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 1874bc2a9408SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1875bc2a9408SMichael Neuling current->thread.tm_tfhar = 0; 1876bc2a9408SMichael Neuling current->thread.tm_texasr = 0; 1877bc2a9408SMichael Neuling current->thread.tm_tfiar = 0; 18787f22ced4SBreno Leitao current->thread.load_tm = 0; 1879bc2a9408SMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 188006bb53b3SRam Pai 188106bb53b3SRam Pai thread_pkey_regs_init(¤t->thread); 188214cf11afSPaul Mackerras } 1883e1802b06SAnton Blanchard EXPORT_SYMBOL(start_thread); 188414cf11afSPaul Mackerras 188514cf11afSPaul Mackerras #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 188614cf11afSPaul Mackerras | PR_FP_EXC_RES | PR_FP_EXC_INV) 188714cf11afSPaul Mackerras 188814cf11afSPaul Mackerras int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 188914cf11afSPaul Mackerras { 189014cf11afSPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 189114cf11afSPaul Mackerras 189214cf11afSPaul Mackerras /* This is a bit hairy. If we are an SPE enabled processor 189314cf11afSPaul Mackerras * (have embedded fp) we store the IEEE exception enable flags in 189414cf11afSPaul Mackerras * fpexc_mode. fpexc_mode is also used for setting FP exception 189514cf11afSPaul Mackerras * mode (asyn, precise, disabled) for 'Classic' FP. */ 189614cf11afSPaul Mackerras if (val & PR_FP_EXC_SW_ENABLE) { 18975e14d21eSKumar Gala if (cpu_has_feature(CPU_FTR_SPE)) { 1898640e9225SJoseph Myers /* 1899640e9225SJoseph Myers * When the sticky exception bits are set 1900640e9225SJoseph Myers * directly by userspace, it must call prctl 1901640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1902640e9225SJoseph Myers * in the existing prctl settings) or 1903640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1904640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1905640e9225SJoseph Myers * saving and restoring the whole 1906640e9225SJoseph Myers * floating-point environment need to do so 1907640e9225SJoseph Myers * anyway to restore the prctl settings from 1908640e9225SJoseph Myers * the saved environment. 1909640e9225SJoseph Myers */ 1910532ed190SChristophe Leroy #ifdef CONFIG_SPE 1911640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 191214cf11afSPaul Mackerras tsk->thread.fpexc_mode = val & 191314cf11afSPaul Mackerras (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1914532ed190SChristophe Leroy #endif 191506d67d54SPaul Mackerras return 0; 19165e14d21eSKumar Gala } else { 19175e14d21eSKumar Gala return -EINVAL; 19185e14d21eSKumar Gala } 191906d67d54SPaul Mackerras } 192006d67d54SPaul Mackerras 192114cf11afSPaul Mackerras /* on a CONFIG_SPE this does not hurt us. The bits that 192214cf11afSPaul Mackerras * __pack_fe01 use do not overlap with bits used for 192314cf11afSPaul Mackerras * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 192414cf11afSPaul Mackerras * on CONFIG_SPE implementations are reserved so writing to 192514cf11afSPaul Mackerras * them does not change anything */ 192614cf11afSPaul Mackerras if (val > PR_FP_EXC_PRECISE) 192714cf11afSPaul Mackerras return -EINVAL; 192814cf11afSPaul Mackerras tsk->thread.fpexc_mode = __pack_fe01(val); 192914cf11afSPaul Mackerras if (regs != NULL && (regs->msr & MSR_FP) != 0) 193014cf11afSPaul Mackerras regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 193114cf11afSPaul Mackerras | tsk->thread.fpexc_mode; 193214cf11afSPaul Mackerras return 0; 193314cf11afSPaul Mackerras } 193414cf11afSPaul Mackerras 193514cf11afSPaul Mackerras int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 193614cf11afSPaul Mackerras { 1937*d208e13cSMichael Ellerman unsigned int val = 0; 193814cf11afSPaul Mackerras 1939532ed190SChristophe Leroy if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) { 1940640e9225SJoseph Myers if (cpu_has_feature(CPU_FTR_SPE)) { 1941640e9225SJoseph Myers /* 1942640e9225SJoseph Myers * When the sticky exception bits are set 1943640e9225SJoseph Myers * directly by userspace, it must call prctl 1944640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1945640e9225SJoseph Myers * in the existing prctl settings) or 1946640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1947640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1948640e9225SJoseph Myers * saving and restoring the whole 1949640e9225SJoseph Myers * floating-point environment need to do so 1950640e9225SJoseph Myers * anyway to restore the prctl settings from 1951640e9225SJoseph Myers * the saved environment. 1952640e9225SJoseph Myers */ 1953532ed190SChristophe Leroy #ifdef CONFIG_SPE 1954640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 195514cf11afSPaul Mackerras val = tsk->thread.fpexc_mode; 1956532ed190SChristophe Leroy #endif 1957640e9225SJoseph Myers } else 19585e14d21eSKumar Gala return -EINVAL; 1959532ed190SChristophe Leroy } else { 196014cf11afSPaul Mackerras val = __unpack_fe01(tsk->thread.fpexc_mode); 1961532ed190SChristophe Leroy } 196214cf11afSPaul Mackerras return put_user(val, (unsigned int __user *) adr); 196314cf11afSPaul Mackerras } 196414cf11afSPaul Mackerras 1965fab5db97SPaul Mackerras int set_endian(struct task_struct *tsk, unsigned int val) 1966fab5db97SPaul Mackerras { 1967fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1968fab5db97SPaul Mackerras 1969fab5db97SPaul Mackerras if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1970fab5db97SPaul Mackerras (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1971fab5db97SPaul Mackerras return -EINVAL; 1972fab5db97SPaul Mackerras 1973fab5db97SPaul Mackerras if (regs == NULL) 1974fab5db97SPaul Mackerras return -EINVAL; 1975fab5db97SPaul Mackerras 1976fab5db97SPaul Mackerras if (val == PR_ENDIAN_BIG) 1977fab5db97SPaul Mackerras regs->msr &= ~MSR_LE; 1978fab5db97SPaul Mackerras else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1979fab5db97SPaul Mackerras regs->msr |= MSR_LE; 1980fab5db97SPaul Mackerras else 1981fab5db97SPaul Mackerras return -EINVAL; 1982fab5db97SPaul Mackerras 1983fab5db97SPaul Mackerras return 0; 1984fab5db97SPaul Mackerras } 1985fab5db97SPaul Mackerras 1986fab5db97SPaul Mackerras int get_endian(struct task_struct *tsk, unsigned long adr) 1987fab5db97SPaul Mackerras { 1988fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1989fab5db97SPaul Mackerras unsigned int val; 1990fab5db97SPaul Mackerras 1991fab5db97SPaul Mackerras if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1992fab5db97SPaul Mackerras !cpu_has_feature(CPU_FTR_REAL_LE)) 1993fab5db97SPaul Mackerras return -EINVAL; 1994fab5db97SPaul Mackerras 1995fab5db97SPaul Mackerras if (regs == NULL) 1996fab5db97SPaul Mackerras return -EINVAL; 1997fab5db97SPaul Mackerras 1998fab5db97SPaul Mackerras if (regs->msr & MSR_LE) { 1999fab5db97SPaul Mackerras if (cpu_has_feature(CPU_FTR_REAL_LE)) 2000fab5db97SPaul Mackerras val = PR_ENDIAN_LITTLE; 2001fab5db97SPaul Mackerras else 2002fab5db97SPaul Mackerras val = PR_ENDIAN_PPC_LITTLE; 2003fab5db97SPaul Mackerras } else 2004fab5db97SPaul Mackerras val = PR_ENDIAN_BIG; 2005fab5db97SPaul Mackerras 2006fab5db97SPaul Mackerras return put_user(val, (unsigned int __user *)adr); 2007fab5db97SPaul Mackerras } 2008fab5db97SPaul Mackerras 2009e9370ae1SPaul Mackerras int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 2010e9370ae1SPaul Mackerras { 2011e9370ae1SPaul Mackerras tsk->thread.align_ctl = val; 2012e9370ae1SPaul Mackerras return 0; 2013e9370ae1SPaul Mackerras } 2014e9370ae1SPaul Mackerras 2015e9370ae1SPaul Mackerras int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 2016e9370ae1SPaul Mackerras { 2017e9370ae1SPaul Mackerras return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 2018e9370ae1SPaul Mackerras } 2019e9370ae1SPaul Mackerras 2020bb72c481SPaul Mackerras static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 2021bb72c481SPaul Mackerras unsigned long nbytes) 2022bb72c481SPaul Mackerras { 2023bb72c481SPaul Mackerras unsigned long stack_page; 2024bb72c481SPaul Mackerras unsigned long cpu = task_cpu(p); 2025bb72c481SPaul Mackerras 2026bb72c481SPaul Mackerras stack_page = (unsigned long)hardirq_ctx[cpu]; 2027a7916a1dSChristophe Leroy if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2028bb72c481SPaul Mackerras return 1; 2029bb72c481SPaul Mackerras 2030bb72c481SPaul Mackerras stack_page = (unsigned long)softirq_ctx[cpu]; 2031a7916a1dSChristophe Leroy if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2032bb72c481SPaul Mackerras return 1; 2033a7916a1dSChristophe Leroy 2034bb72c481SPaul Mackerras return 0; 2035bb72c481SPaul Mackerras } 2036bb72c481SPaul Mackerras 2037a2e36683SNicholas Piggin static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p, 2038a2e36683SNicholas Piggin unsigned long nbytes) 2039a2e36683SNicholas Piggin { 2040a2e36683SNicholas Piggin #ifdef CONFIG_PPC64 2041a2e36683SNicholas Piggin unsigned long stack_page; 2042a2e36683SNicholas Piggin unsigned long cpu = task_cpu(p); 2043a2e36683SNicholas Piggin 2044a2e36683SNicholas Piggin stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE; 2045a2e36683SNicholas Piggin if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2046a2e36683SNicholas Piggin return 1; 2047a2e36683SNicholas Piggin 2048a2e36683SNicholas Piggin # ifdef CONFIG_PPC_BOOK3S_64 2049a2e36683SNicholas Piggin stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE; 2050a2e36683SNicholas Piggin if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2051a2e36683SNicholas Piggin return 1; 2052a2e36683SNicholas Piggin 2053a2e36683SNicholas Piggin stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE; 2054a2e36683SNicholas Piggin if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2055a2e36683SNicholas Piggin return 1; 2056a2e36683SNicholas Piggin # endif 2057a2e36683SNicholas Piggin #endif 2058a2e36683SNicholas Piggin 2059a2e36683SNicholas Piggin return 0; 2060a2e36683SNicholas Piggin } 2061a2e36683SNicholas Piggin 2062a2e36683SNicholas Piggin 20632f25194dSAnton Blanchard int validate_sp(unsigned long sp, struct task_struct *p, 206414cf11afSPaul Mackerras unsigned long nbytes) 206514cf11afSPaul Mackerras { 20660cec6fd1SAl Viro unsigned long stack_page = (unsigned long)task_stack_page(p); 206714cf11afSPaul Mackerras 2068a7916a1dSChristophe Leroy if (sp < THREAD_SIZE) 2069a7916a1dSChristophe Leroy return 0; 2070a7916a1dSChristophe Leroy 2071a7916a1dSChristophe Leroy if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 207214cf11afSPaul Mackerras return 1; 207314cf11afSPaul Mackerras 2074a2e36683SNicholas Piggin if (valid_irq_stack(sp, p, nbytes)) 2075a2e36683SNicholas Piggin return 1; 2076a2e36683SNicholas Piggin 2077a2e36683SNicholas Piggin return valid_emergency_stack(sp, p, nbytes); 207814cf11afSPaul Mackerras } 207914cf11afSPaul Mackerras 20802f25194dSAnton Blanchard EXPORT_SYMBOL(validate_sp); 20812f25194dSAnton Blanchard 2082018cce33SChristophe Leroy static unsigned long __get_wchan(struct task_struct *p) 208306d67d54SPaul Mackerras { 208406d67d54SPaul Mackerras unsigned long ip, sp; 208506d67d54SPaul Mackerras int count = 0; 208606d67d54SPaul Mackerras 208706d67d54SPaul Mackerras if (!p || p == current || p->state == TASK_RUNNING) 208806d67d54SPaul Mackerras return 0; 208906d67d54SPaul Mackerras 209006d67d54SPaul Mackerras sp = p->thread.ksp; 2091ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 209206d67d54SPaul Mackerras return 0; 209306d67d54SPaul Mackerras 209406d67d54SPaul Mackerras do { 209506d67d54SPaul Mackerras sp = *(unsigned long *)sp; 20964ca360f3SKautuk Consul if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) || 20974ca360f3SKautuk Consul p->state == TASK_RUNNING) 209806d67d54SPaul Mackerras return 0; 209906d67d54SPaul Mackerras if (count > 0) { 2100ec2b36b9SBenjamin Herrenschmidt ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 210106d67d54SPaul Mackerras if (!in_sched_functions(ip)) 210206d67d54SPaul Mackerras return ip; 210306d67d54SPaul Mackerras } 210406d67d54SPaul Mackerras } while (count++ < 16); 210506d67d54SPaul Mackerras return 0; 210606d67d54SPaul Mackerras } 210706d67d54SPaul Mackerras 2108018cce33SChristophe Leroy unsigned long get_wchan(struct task_struct *p) 2109018cce33SChristophe Leroy { 2110018cce33SChristophe Leroy unsigned long ret; 2111018cce33SChristophe Leroy 2112018cce33SChristophe Leroy if (!try_get_task_stack(p)) 2113018cce33SChristophe Leroy return 0; 2114018cce33SChristophe Leroy 2115018cce33SChristophe Leroy ret = __get_wchan(p); 2116018cce33SChristophe Leroy 2117018cce33SChristophe Leroy put_task_stack(p); 2118018cce33SChristophe Leroy 2119018cce33SChristophe Leroy return ret; 2120018cce33SChristophe Leroy } 2121018cce33SChristophe Leroy 2122c4d04be1SJohannes Berg static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 212314cf11afSPaul Mackerras 21249cb8f069SDmitry Safonov void show_stack(struct task_struct *tsk, unsigned long *stack, 2125b9677a8cSDmitry Safonov const char *loglvl) 212614cf11afSPaul Mackerras { 212706d67d54SPaul Mackerras unsigned long sp, ip, lr, newsp; 212814cf11afSPaul Mackerras int count = 0; 212906d67d54SPaul Mackerras int firstframe = 1; 21307c1bb6bbSNaveen N. Rao unsigned long ret_addr; 21317c1bb6bbSNaveen N. Rao int ftrace_idx = 0; 213214cf11afSPaul Mackerras 213314cf11afSPaul Mackerras if (tsk == NULL) 213414cf11afSPaul Mackerras tsk = current; 2135018cce33SChristophe Leroy 2136018cce33SChristophe Leroy if (!try_get_task_stack(tsk)) 2137018cce33SChristophe Leroy return; 2138018cce33SChristophe Leroy 2139018cce33SChristophe Leroy sp = (unsigned long) stack; 214014cf11afSPaul Mackerras if (sp == 0) { 214114cf11afSPaul Mackerras if (tsk == current) 21423d13e839SMichael Ellerman sp = current_stack_frame(); 214314cf11afSPaul Mackerras else 214414cf11afSPaul Mackerras sp = tsk->thread.ksp; 214514cf11afSPaul Mackerras } 214614cf11afSPaul Mackerras 214706d67d54SPaul Mackerras lr = 0; 2148b9677a8cSDmitry Safonov printk("%sCall Trace:\n", loglvl); 214914cf11afSPaul Mackerras do { 2150ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 2151018cce33SChristophe Leroy break; 215206d67d54SPaul Mackerras 215306d67d54SPaul Mackerras stack = (unsigned long *) sp; 215406d67d54SPaul Mackerras newsp = stack[0]; 2155ec2b36b9SBenjamin Herrenschmidt ip = stack[STACK_FRAME_LR_SAVE]; 215606d67d54SPaul Mackerras if (!firstframe || ip != lr) { 2157b9677a8cSDmitry Safonov printk("%s["REG"] ["REG"] %pS", 2158b9677a8cSDmitry Safonov loglvl, sp, ip, (void *)ip); 21597c1bb6bbSNaveen N. Rao ret_addr = ftrace_graph_ret_addr(current, 21607c1bb6bbSNaveen N. Rao &ftrace_idx, ip, stack); 21617c1bb6bbSNaveen N. Rao if (ret_addr != ip) 21627c1bb6bbSNaveen N. Rao pr_cont(" (%pS)", (void *)ret_addr); 216306d67d54SPaul Mackerras if (firstframe) 21649a1f490fSMichael Ellerman pr_cont(" (unreliable)"); 21659a1f490fSMichael Ellerman pr_cont("\n"); 216614cf11afSPaul Mackerras } 216706d67d54SPaul Mackerras firstframe = 0; 216806d67d54SPaul Mackerras 216906d67d54SPaul Mackerras /* 217006d67d54SPaul Mackerras * See if this is an exception frame. 217106d67d54SPaul Mackerras * We look for the "regshere" marker in the current frame. 217206d67d54SPaul Mackerras */ 2173ec2b36b9SBenjamin Herrenschmidt if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 2174ec2b36b9SBenjamin Herrenschmidt && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 217506d67d54SPaul Mackerras struct pt_regs *regs = (struct pt_regs *) 217606d67d54SPaul Mackerras (sp + STACK_FRAME_OVERHEAD); 217706d67d54SPaul Mackerras lr = regs->link; 2178b9677a8cSDmitry Safonov printk("%s--- interrupt: %lx at %pS\n LR = %pS\n", 2179b9677a8cSDmitry Safonov loglvl, regs->trap, 2180b9677a8cSDmitry Safonov (void *)regs->nip, (void *)lr); 218106d67d54SPaul Mackerras firstframe = 1; 218214cf11afSPaul Mackerras } 218306d67d54SPaul Mackerras 218406d67d54SPaul Mackerras sp = newsp; 218506d67d54SPaul Mackerras } while (count++ < kstack_depth_to_print); 2186018cce33SChristophe Leroy 2187018cce33SChristophe Leroy put_task_stack(tsk); 218806d67d54SPaul Mackerras } 218906d67d54SPaul Mackerras 2190cb2c9b27SAnton Blanchard #ifdef CONFIG_PPC64 2191fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 21920e37739bSMichael Ellerman void notrace __ppc64_runlatch_on(void) 2193cb2c9b27SAnton Blanchard { 2194fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2195d1d0d5ffSNicholas Piggin 2196d1d0d5ffSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2197d1d0d5ffSNicholas Piggin /* 2198d1d0d5ffSNicholas Piggin * Least significant bit (RUN) is the only writable bit of 2199d1d0d5ffSNicholas Piggin * the CTRL register, so we can avoid mfspr. 2.06 is not the 2200d1d0d5ffSNicholas Piggin * earliest ISA where this is the case, but it's convenient. 2201d1d0d5ffSNicholas Piggin */ 2202d1d0d5ffSNicholas Piggin mtspr(SPRN_CTRLT, CTRL_RUNLATCH); 2203d1d0d5ffSNicholas Piggin } else { 2204cb2c9b27SAnton Blanchard unsigned long ctrl; 2205cb2c9b27SAnton Blanchard 2206d1d0d5ffSNicholas Piggin /* 2207d1d0d5ffSNicholas Piggin * Some architectures (e.g., Cell) have writable fields other 2208d1d0d5ffSNicholas Piggin * than RUN, so do the read-modify-write. 2209d1d0d5ffSNicholas Piggin */ 2210cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2211cb2c9b27SAnton Blanchard ctrl |= CTRL_RUNLATCH; 2212cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2213d1d0d5ffSNicholas Piggin } 2214cb2c9b27SAnton Blanchard 2215fae2e0fbSBenjamin Herrenschmidt ti->local_flags |= _TLF_RUNLATCH; 2216cb2c9b27SAnton Blanchard } 2217cb2c9b27SAnton Blanchard 2218fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 22190e37739bSMichael Ellerman void notrace __ppc64_runlatch_off(void) 2220cb2c9b27SAnton Blanchard { 2221fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2222cb2c9b27SAnton Blanchard 2223fae2e0fbSBenjamin Herrenschmidt ti->local_flags &= ~_TLF_RUNLATCH; 2224cb2c9b27SAnton Blanchard 2225d1d0d5ffSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2226d1d0d5ffSNicholas Piggin mtspr(SPRN_CTRLT, 0); 2227d1d0d5ffSNicholas Piggin } else { 2228d1d0d5ffSNicholas Piggin unsigned long ctrl; 2229d1d0d5ffSNicholas Piggin 2230cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2231cb2c9b27SAnton Blanchard ctrl &= ~CTRL_RUNLATCH; 2232cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2233cb2c9b27SAnton Blanchard } 2234d1d0d5ffSNicholas Piggin } 2235fe1952fcSBenjamin Herrenschmidt #endif /* CONFIG_PPC64 */ 2236f6a61680SBenjamin Herrenschmidt 2237d839088cSAnton Blanchard unsigned long arch_align_stack(unsigned long sp) 2238d839088cSAnton Blanchard { 2239d839088cSAnton Blanchard if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 2240d839088cSAnton Blanchard sp -= get_random_int() & ~PAGE_MASK; 2241d839088cSAnton Blanchard return sp & ~0xf; 2242d839088cSAnton Blanchard } 2243912f9ee2SAnton Blanchard 2244912f9ee2SAnton Blanchard static inline unsigned long brk_rnd(void) 2245912f9ee2SAnton Blanchard { 2246912f9ee2SAnton Blanchard unsigned long rnd = 0; 2247912f9ee2SAnton Blanchard 2248912f9ee2SAnton Blanchard /* 8MB for 32bit, 1GB for 64bit */ 2249912f9ee2SAnton Blanchard if (is_32bit_task()) 22505ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 2251912f9ee2SAnton Blanchard else 22525ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 2253912f9ee2SAnton Blanchard 2254912f9ee2SAnton Blanchard return rnd << PAGE_SHIFT; 2255912f9ee2SAnton Blanchard } 2256912f9ee2SAnton Blanchard 2257912f9ee2SAnton Blanchard unsigned long arch_randomize_brk(struct mm_struct *mm) 2258912f9ee2SAnton Blanchard { 22598bbde7a7SAnton Blanchard unsigned long base = mm->brk; 22608bbde7a7SAnton Blanchard unsigned long ret; 22618bbde7a7SAnton Blanchard 22624e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 22638bbde7a7SAnton Blanchard /* 22648bbde7a7SAnton Blanchard * If we are using 1TB segments and we are allowed to randomise 22658bbde7a7SAnton Blanchard * the heap, we can put it above 1TB so it is backed by a 1TB 22668bbde7a7SAnton Blanchard * segment. Otherwise the heap will be in the bottom 1TB 22678bbde7a7SAnton Blanchard * which always uses 256MB segments and this may result in a 2268caca285eSAneesh Kumar K.V * performance penalty. We don't need to worry about radix. For 2269caca285eSAneesh Kumar K.V * radix, mmu_highuser_ssize remains unchanged from 256MB. 22708bbde7a7SAnton Blanchard */ 22718bbde7a7SAnton Blanchard if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 22728bbde7a7SAnton Blanchard base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 22738bbde7a7SAnton Blanchard #endif 22748bbde7a7SAnton Blanchard 22758bbde7a7SAnton Blanchard ret = PAGE_ALIGN(base + brk_rnd()); 2276912f9ee2SAnton Blanchard 2277912f9ee2SAnton Blanchard if (ret < mm->brk) 2278912f9ee2SAnton Blanchard return mm->brk; 2279912f9ee2SAnton Blanchard 2280912f9ee2SAnton Blanchard return ret; 2281912f9ee2SAnton Blanchard } 2282501cb16dSAnton Blanchard 2283