12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 214cf11afSPaul Mackerras /* 314cf11afSPaul Mackerras * Derived from "arch/i386/kernel/process.c" 414cf11afSPaul Mackerras * Copyright (C) 1995 Linus Torvalds 514cf11afSPaul Mackerras * 614cf11afSPaul Mackerras * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 714cf11afSPaul Mackerras * Paul Mackerras (paulus@cs.anu.edu.au) 814cf11afSPaul Mackerras * 914cf11afSPaul Mackerras * PowerPC version 1014cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 1114cf11afSPaul Mackerras */ 1214cf11afSPaul Mackerras 1314cf11afSPaul Mackerras #include <linux/errno.h> 1414cf11afSPaul Mackerras #include <linux/sched.h> 15b17b0153SIngo Molnar #include <linux/sched/debug.h> 1629930025SIngo Molnar #include <linux/sched/task.h> 1768db0cf1SIngo Molnar #include <linux/sched/task_stack.h> 1814cf11afSPaul Mackerras #include <linux/kernel.h> 1914cf11afSPaul Mackerras #include <linux/mm.h> 2014cf11afSPaul Mackerras #include <linux/smp.h> 2114cf11afSPaul Mackerras #include <linux/stddef.h> 2214cf11afSPaul Mackerras #include <linux/unistd.h> 2314cf11afSPaul Mackerras #include <linux/ptrace.h> 2414cf11afSPaul Mackerras #include <linux/slab.h> 2514cf11afSPaul Mackerras #include <linux/user.h> 2614cf11afSPaul Mackerras #include <linux/elf.h> 2714cf11afSPaul Mackerras #include <linux/prctl.h> 2814cf11afSPaul Mackerras #include <linux/init_task.h> 294b16f8e2SPaul Gortmaker #include <linux/export.h> 3014cf11afSPaul Mackerras #include <linux/kallsyms.h> 3114cf11afSPaul Mackerras #include <linux/mqueue.h> 3214cf11afSPaul Mackerras #include <linux/hardirq.h> 3306d67d54SPaul Mackerras #include <linux/utsname.h> 346794c782SSteven Rostedt #include <linux/ftrace.h> 3579741dd3SMartin Schwidefsky #include <linux/kernel_stat.h> 36d839088cSAnton Blanchard #include <linux/personality.h> 37d839088cSAnton Blanchard #include <linux/random.h> 385aae8a53SK.Prasad #include <linux/hw_breakpoint.h> 397b051f66SAnton Blanchard #include <linux/uaccess.h> 407f92bc56SDaniel Axtens #include <linux/elf-randomize.h> 4106bb53b3SRam Pai #include <linux/pkeys.h> 42fb2d9505SChristophe Leroy #include <linux/seq_buf.h> 4314cf11afSPaul Mackerras 4414cf11afSPaul Mackerras #include <asm/io.h> 4514cf11afSPaul Mackerras #include <asm/processor.h> 4614cf11afSPaul Mackerras #include <asm/mmu.h> 4714cf11afSPaul Mackerras #include <asm/prom.h> 4876032de8SMichael Ellerman #include <asm/machdep.h> 49c6622f63SPaul Mackerras #include <asm/time.h> 50ae3a197eSDavid Howells #include <asm/runlatch.h> 51a7f31841SArnd Bergmann #include <asm/syscalls.h> 52ae3a197eSDavid Howells #include <asm/switch_to.h> 53fb09692eSMichael Neuling #include <asm/tm.h> 54ae3a197eSDavid Howells #include <asm/debug.h> 5506d67d54SPaul Mackerras #ifdef CONFIG_PPC64 5606d67d54SPaul Mackerras #include <asm/firmware.h> 57c2e480baSMadhavan Srinivasan #include <asm/hw_irq.h> 5806d67d54SPaul Mackerras #endif 597cedd601SAnton Blanchard #include <asm/code-patching.h> 607f92bc56SDaniel Axtens #include <asm/exec.h> 615d31a96eSMichael Ellerman #include <asm/livepatch.h> 62b92a226eSKevin Hao #include <asm/cpu_has_feature.h> 630545d543SDaniel Axtens #include <asm/asm-prototypes.h> 64c9386bfdSChristophe Leroy #include <asm/stacktrace.h> 65c1fe190cSMichael Neuling #include <asm/hw_breakpoint.h> 665d31a96eSMichael Ellerman 67d6a61bfcSLuis Machado #include <linux/kprobes.h> 68d6a61bfcSLuis Machado #include <linux/kdebug.h> 6914cf11afSPaul Mackerras 708b3c34cfSMichael Neuling /* Transactional Memory debug */ 718b3c34cfSMichael Neuling #ifdef TM_DEBUG_SW 728b3c34cfSMichael Neuling #define TM_DEBUG(x...) printk(KERN_INFO x) 738b3c34cfSMichael Neuling #else 748b3c34cfSMichael Neuling #define TM_DEBUG(x...) do { } while(0) 758b3c34cfSMichael Neuling #endif 768b3c34cfSMichael Neuling 7714cf11afSPaul Mackerras extern unsigned long _get_SP(void); 7814cf11afSPaul Mackerras 79d31626f7SPaul Mackerras #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 8054820530SMichael Ellerman /* 8154820530SMichael Ellerman * Are we running in "Suspend disabled" mode? If so we have to block any 8254820530SMichael Ellerman * sigreturn that would get us into suspended state, and we also warn in some 8354820530SMichael Ellerman * other paths that we should never reach with suspend disabled. 8454820530SMichael Ellerman */ 8554820530SMichael Ellerman bool tm_suspend_disabled __ro_after_init = false; 8654820530SMichael Ellerman 87b86fd2bdSAnton Blanchard static void check_if_tm_restore_required(struct task_struct *tsk) 88d31626f7SPaul Mackerras { 89d31626f7SPaul Mackerras /* 90d31626f7SPaul Mackerras * If we are saving the current thread's registers, and the 91d31626f7SPaul Mackerras * thread is in a transactional state, set the TIF_RESTORE_TM 92d31626f7SPaul Mackerras * bit so that we know to restore the registers before 93d31626f7SPaul Mackerras * returning to userspace. 94d31626f7SPaul Mackerras */ 95d31626f7SPaul Mackerras if (tsk == current && tsk->thread.regs && 96d31626f7SPaul Mackerras MSR_TM_ACTIVE(tsk->thread.regs->msr) && 97d31626f7SPaul Mackerras !test_thread_flag(TIF_RESTORE_TM)) { 98829023dfSAnshuman Khandual tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 99d31626f7SPaul Mackerras set_thread_flag(TIF_RESTORE_TM); 100d31626f7SPaul Mackerras } 101d31626f7SPaul Mackerras } 102dc16b553SCyril Bur 103d31626f7SPaul Mackerras #else 104b86fd2bdSAnton Blanchard static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 105d31626f7SPaul Mackerras #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 106d31626f7SPaul Mackerras 1073eb5d588SAnton Blanchard bool strict_msr_control; 1083eb5d588SAnton Blanchard EXPORT_SYMBOL(strict_msr_control); 1093eb5d588SAnton Blanchard 1103eb5d588SAnton Blanchard static int __init enable_strict_msr_control(char *str) 1113eb5d588SAnton Blanchard { 1123eb5d588SAnton Blanchard strict_msr_control = true; 1133eb5d588SAnton Blanchard pr_info("Enabling strict facility control\n"); 1143eb5d588SAnton Blanchard 1153eb5d588SAnton Blanchard return 0; 1163eb5d588SAnton Blanchard } 1173eb5d588SAnton Blanchard early_param("ppc_strict_facility_enable", enable_strict_msr_control); 1183eb5d588SAnton Blanchard 119e2b36d59SNicholas Piggin /* notrace because it's called by restore_math */ 120e2b36d59SNicholas Piggin unsigned long notrace msr_check_and_set(unsigned long bits) 121a0e72cf1SAnton Blanchard { 122a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 123a0e72cf1SAnton Blanchard unsigned long newmsr; 124a0e72cf1SAnton Blanchard 125a0e72cf1SAnton Blanchard newmsr = oldmsr | bits; 126a0e72cf1SAnton Blanchard 127a0e72cf1SAnton Blanchard #ifdef CONFIG_VSX 128a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 129a0e72cf1SAnton Blanchard newmsr |= MSR_VSX; 130a0e72cf1SAnton Blanchard #endif 131a0e72cf1SAnton Blanchard 132a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 133a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 1343cee070aSCyril Bur 1353cee070aSCyril Bur return newmsr; 136a0e72cf1SAnton Blanchard } 137d1c72112SSimon Guo EXPORT_SYMBOL_GPL(msr_check_and_set); 138a0e72cf1SAnton Blanchard 139e2b36d59SNicholas Piggin /* notrace because it's called by restore_math */ 140e2b36d59SNicholas Piggin void notrace __msr_check_and_clear(unsigned long bits) 141a0e72cf1SAnton Blanchard { 142a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 143a0e72cf1SAnton Blanchard unsigned long newmsr; 144a0e72cf1SAnton Blanchard 145a0e72cf1SAnton Blanchard newmsr = oldmsr & ~bits; 146a0e72cf1SAnton Blanchard 147a0e72cf1SAnton Blanchard #ifdef CONFIG_VSX 148a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 149a0e72cf1SAnton Blanchard newmsr &= ~MSR_VSX; 150a0e72cf1SAnton Blanchard #endif 151a0e72cf1SAnton Blanchard 152a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 153a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 154a0e72cf1SAnton Blanchard } 1553eb5d588SAnton Blanchard EXPORT_SYMBOL(__msr_check_and_clear); 156a0e72cf1SAnton Blanchard 157037f0eedSKevin Hao #ifdef CONFIG_PPC_FPU 1581cdf039bSMathieu Malaterre static void __giveup_fpu(struct task_struct *tsk) 1598792468dSCyril Bur { 1608eb98037SAnton Blanchard unsigned long msr; 1618eb98037SAnton Blanchard 1628792468dSCyril Bur save_fpu(tsk); 1638eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 164fe1ef6bcSMark Cave-Ayland msr &= ~(MSR_FP|MSR_FE0|MSR_FE1); 1658792468dSCyril Bur #ifdef CONFIG_VSX 1668792468dSCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 1678eb98037SAnton Blanchard msr &= ~MSR_VSX; 1688792468dSCyril Bur #endif 1698eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 1708792468dSCyril Bur } 1718792468dSCyril Bur 17298da581eSAnton Blanchard void giveup_fpu(struct task_struct *tsk) 17398da581eSAnton Blanchard { 17498da581eSAnton Blanchard check_if_tm_restore_required(tsk); 17598da581eSAnton Blanchard 176a0e72cf1SAnton Blanchard msr_check_and_set(MSR_FP); 17798da581eSAnton Blanchard __giveup_fpu(tsk); 178a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP); 17998da581eSAnton Blanchard } 18098da581eSAnton Blanchard EXPORT_SYMBOL(giveup_fpu); 18198da581eSAnton Blanchard 18214cf11afSPaul Mackerras /* 18314cf11afSPaul Mackerras * Make sure the floating-point register state in the 18414cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 18514cf11afSPaul Mackerras */ 18614cf11afSPaul Mackerras void flush_fp_to_thread(struct task_struct *tsk) 18714cf11afSPaul Mackerras { 18814cf11afSPaul Mackerras if (tsk->thread.regs) { 18914cf11afSPaul Mackerras /* 19014cf11afSPaul Mackerras * We need to disable preemption here because if we didn't, 19114cf11afSPaul Mackerras * another process could get scheduled after the regs->msr 19214cf11afSPaul Mackerras * test but before we have finished saving the FP registers 19314cf11afSPaul Mackerras * to the thread_struct. That process could take over the 19414cf11afSPaul Mackerras * FPU, and then when we get scheduled again we would store 19514cf11afSPaul Mackerras * bogus values for the remaining FP registers. 19614cf11afSPaul Mackerras */ 19714cf11afSPaul Mackerras preempt_disable(); 19814cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_FP) { 19914cf11afSPaul Mackerras /* 20014cf11afSPaul Mackerras * This should only ever be called for current or 20114cf11afSPaul Mackerras * for a stopped child process. Since we save away 202af1bbc3dSAnton Blanchard * the FP register state on context switch, 20314cf11afSPaul Mackerras * there is something wrong if a stopped child appears 20414cf11afSPaul Mackerras * to still have its FP state in the CPU registers. 20514cf11afSPaul Mackerras */ 20614cf11afSPaul Mackerras BUG_ON(tsk != current); 207b86fd2bdSAnton Blanchard giveup_fpu(tsk); 20814cf11afSPaul Mackerras } 20914cf11afSPaul Mackerras preempt_enable(); 21014cf11afSPaul Mackerras } 21114cf11afSPaul Mackerras } 212de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_fp_to_thread); 21314cf11afSPaul Mackerras 21414cf11afSPaul Mackerras void enable_kernel_fp(void) 21514cf11afSPaul Mackerras { 216e909fb83SCyril Bur unsigned long cpumsr; 217e909fb83SCyril Bur 21814cf11afSPaul Mackerras WARN_ON(preemptible()); 21914cf11afSPaul Mackerras 220e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP); 221611b0e5cSAnton Blanchard 222d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 223d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 224e909fb83SCyril Bur /* 225e909fb83SCyril Bur * If a thread has already been reclaimed then the 226e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 227e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 228e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 229e909fb83SCyril Bur * checkpointed structure. 230e909fb83SCyril Bur */ 2315c784c84SBreno Leitao if (!MSR_TM_ACTIVE(cpumsr) && 2325c784c84SBreno Leitao MSR_TM_ACTIVE(current->thread.regs->msr)) 233e909fb83SCyril Bur return; 234a0e72cf1SAnton Blanchard __giveup_fpu(current); 235b86fd2bdSAnton Blanchard } 236d64d02ceSAnton Blanchard } 23714cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_fp); 238d1e1cf2eSAnton Blanchard #endif /* CONFIG_PPC_FPU */ 23914cf11afSPaul Mackerras 24014cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 2416f515d84SCyril Bur static void __giveup_altivec(struct task_struct *tsk) 2426f515d84SCyril Bur { 2438eb98037SAnton Blanchard unsigned long msr; 2448eb98037SAnton Blanchard 2456f515d84SCyril Bur save_altivec(tsk); 2468eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 2478eb98037SAnton Blanchard msr &= ~MSR_VEC; 2486f515d84SCyril Bur #ifdef CONFIG_VSX 2496f515d84SCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 2508eb98037SAnton Blanchard msr &= ~MSR_VSX; 2516f515d84SCyril Bur #endif 2528eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 2536f515d84SCyril Bur } 2546f515d84SCyril Bur 25598da581eSAnton Blanchard void giveup_altivec(struct task_struct *tsk) 25698da581eSAnton Blanchard { 25798da581eSAnton Blanchard check_if_tm_restore_required(tsk); 25898da581eSAnton Blanchard 259a0e72cf1SAnton Blanchard msr_check_and_set(MSR_VEC); 26098da581eSAnton Blanchard __giveup_altivec(tsk); 261a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_VEC); 26298da581eSAnton Blanchard } 26398da581eSAnton Blanchard EXPORT_SYMBOL(giveup_altivec); 26498da581eSAnton Blanchard 26514cf11afSPaul Mackerras void enable_kernel_altivec(void) 26614cf11afSPaul Mackerras { 267e909fb83SCyril Bur unsigned long cpumsr; 268e909fb83SCyril Bur 26914cf11afSPaul Mackerras WARN_ON(preemptible()); 27014cf11afSPaul Mackerras 271e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_VEC); 272611b0e5cSAnton Blanchard 273d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 274d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 275e909fb83SCyril Bur /* 276e909fb83SCyril Bur * If a thread has already been reclaimed then the 277e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 278e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 279e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 280e909fb83SCyril Bur * checkpointed structure. 281e909fb83SCyril Bur */ 2825c784c84SBreno Leitao if (!MSR_TM_ACTIVE(cpumsr) && 2835c784c84SBreno Leitao MSR_TM_ACTIVE(current->thread.regs->msr)) 284e909fb83SCyril Bur return; 285a0e72cf1SAnton Blanchard __giveup_altivec(current); 286b86fd2bdSAnton Blanchard } 287d64d02ceSAnton Blanchard } 28814cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_altivec); 28914cf11afSPaul Mackerras 29014cf11afSPaul Mackerras /* 29114cf11afSPaul Mackerras * Make sure the VMX/Altivec register state in the 29214cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 29314cf11afSPaul Mackerras */ 29414cf11afSPaul Mackerras void flush_altivec_to_thread(struct task_struct *tsk) 29514cf11afSPaul Mackerras { 29614cf11afSPaul Mackerras if (tsk->thread.regs) { 29714cf11afSPaul Mackerras preempt_disable(); 29814cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_VEC) { 29914cf11afSPaul Mackerras BUG_ON(tsk != current); 300b86fd2bdSAnton Blanchard giveup_altivec(tsk); 30114cf11afSPaul Mackerras } 30214cf11afSPaul Mackerras preempt_enable(); 30314cf11afSPaul Mackerras } 30414cf11afSPaul Mackerras } 305de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 30614cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 30714cf11afSPaul Mackerras 308ce48b210SMichael Neuling #ifdef CONFIG_VSX 309bf6a4d5bSCyril Bur static void __giveup_vsx(struct task_struct *tsk) 310a7d623d4SAnton Blanchard { 311dc801081SBenjamin Herrenschmidt unsigned long msr = tsk->thread.regs->msr; 312dc801081SBenjamin Herrenschmidt 313dc801081SBenjamin Herrenschmidt /* 314dc801081SBenjamin Herrenschmidt * We should never be ssetting MSR_VSX without also setting 315dc801081SBenjamin Herrenschmidt * MSR_FP and MSR_VEC 316dc801081SBenjamin Herrenschmidt */ 317dc801081SBenjamin Herrenschmidt WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); 318dc801081SBenjamin Herrenschmidt 319dc801081SBenjamin Herrenschmidt /* __giveup_fpu will clear MSR_VSX */ 320dc801081SBenjamin Herrenschmidt if (msr & MSR_FP) 321a7d623d4SAnton Blanchard __giveup_fpu(tsk); 322dc801081SBenjamin Herrenschmidt if (msr & MSR_VEC) 323a7d623d4SAnton Blanchard __giveup_altivec(tsk); 324bf6a4d5bSCyril Bur } 325bf6a4d5bSCyril Bur 326bf6a4d5bSCyril Bur static void giveup_vsx(struct task_struct *tsk) 327bf6a4d5bSCyril Bur { 328bf6a4d5bSCyril Bur check_if_tm_restore_required(tsk); 329bf6a4d5bSCyril Bur 330bf6a4d5bSCyril Bur msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 331a7d623d4SAnton Blanchard __giveup_vsx(tsk); 332a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 333a7d623d4SAnton Blanchard } 334bf6a4d5bSCyril Bur 335ce48b210SMichael Neuling void enable_kernel_vsx(void) 336ce48b210SMichael Neuling { 337e909fb83SCyril Bur unsigned long cpumsr; 338e909fb83SCyril Bur 339ce48b210SMichael Neuling WARN_ON(preemptible()); 340ce48b210SMichael Neuling 341e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 342611b0e5cSAnton Blanchard 3435a69aec9SBenjamin Herrenschmidt if (current->thread.regs && 3445a69aec9SBenjamin Herrenschmidt (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { 345d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 346e909fb83SCyril Bur /* 347e909fb83SCyril Bur * If a thread has already been reclaimed then the 348e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 349e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 350e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 351e909fb83SCyril Bur * checkpointed structure. 352e909fb83SCyril Bur */ 3535c784c84SBreno Leitao if (!MSR_TM_ACTIVE(cpumsr) && 3545c784c84SBreno Leitao MSR_TM_ACTIVE(current->thread.regs->msr)) 355e909fb83SCyril Bur return; 356a0e72cf1SAnton Blanchard __giveup_vsx(current); 357611b0e5cSAnton Blanchard } 358ce48b210SMichael Neuling } 359ce48b210SMichael Neuling EXPORT_SYMBOL(enable_kernel_vsx); 360ce48b210SMichael Neuling 361ce48b210SMichael Neuling void flush_vsx_to_thread(struct task_struct *tsk) 362ce48b210SMichael Neuling { 363ce48b210SMichael Neuling if (tsk->thread.regs) { 364ce48b210SMichael Neuling preempt_disable(); 3655a69aec9SBenjamin Herrenschmidt if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { 366ce48b210SMichael Neuling BUG_ON(tsk != current); 367ce48b210SMichael Neuling giveup_vsx(tsk); 368ce48b210SMichael Neuling } 369ce48b210SMichael Neuling preempt_enable(); 370ce48b210SMichael Neuling } 371ce48b210SMichael Neuling } 372de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 373ce48b210SMichael Neuling #endif /* CONFIG_VSX */ 374ce48b210SMichael Neuling 37514cf11afSPaul Mackerras #ifdef CONFIG_SPE 37698da581eSAnton Blanchard void giveup_spe(struct task_struct *tsk) 37798da581eSAnton Blanchard { 37898da581eSAnton Blanchard check_if_tm_restore_required(tsk); 37998da581eSAnton Blanchard 380a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 38198da581eSAnton Blanchard __giveup_spe(tsk); 382a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_SPE); 38398da581eSAnton Blanchard } 38498da581eSAnton Blanchard EXPORT_SYMBOL(giveup_spe); 38514cf11afSPaul Mackerras 38614cf11afSPaul Mackerras void enable_kernel_spe(void) 38714cf11afSPaul Mackerras { 38814cf11afSPaul Mackerras WARN_ON(preemptible()); 38914cf11afSPaul Mackerras 390a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 391611b0e5cSAnton Blanchard 392d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 393d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 394a0e72cf1SAnton Blanchard __giveup_spe(current); 39514cf11afSPaul Mackerras } 396d64d02ceSAnton Blanchard } 39714cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_spe); 39814cf11afSPaul Mackerras 39914cf11afSPaul Mackerras void flush_spe_to_thread(struct task_struct *tsk) 40014cf11afSPaul Mackerras { 40114cf11afSPaul Mackerras if (tsk->thread.regs) { 40214cf11afSPaul Mackerras preempt_disable(); 40314cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_SPE) { 40414cf11afSPaul Mackerras BUG_ON(tsk != current); 405685659eeSyu liu tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 4060ee6c15eSKumar Gala giveup_spe(tsk); 40714cf11afSPaul Mackerras } 40814cf11afSPaul Mackerras preempt_enable(); 40914cf11afSPaul Mackerras } 41014cf11afSPaul Mackerras } 41114cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 41214cf11afSPaul Mackerras 413c2085059SAnton Blanchard static unsigned long msr_all_available; 414c2085059SAnton Blanchard 415c2085059SAnton Blanchard static int __init init_msr_all_available(void) 416c2085059SAnton Blanchard { 417c2085059SAnton Blanchard #ifdef CONFIG_PPC_FPU 418c2085059SAnton Blanchard msr_all_available |= MSR_FP; 419c2085059SAnton Blanchard #endif 420c2085059SAnton Blanchard #ifdef CONFIG_ALTIVEC 421c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC)) 422c2085059SAnton Blanchard msr_all_available |= MSR_VEC; 423c2085059SAnton Blanchard #endif 424c2085059SAnton Blanchard #ifdef CONFIG_VSX 425c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX)) 426c2085059SAnton Blanchard msr_all_available |= MSR_VSX; 427c2085059SAnton Blanchard #endif 428c2085059SAnton Blanchard #ifdef CONFIG_SPE 429c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_SPE)) 430c2085059SAnton Blanchard msr_all_available |= MSR_SPE; 431c2085059SAnton Blanchard #endif 432c2085059SAnton Blanchard 433c2085059SAnton Blanchard return 0; 434c2085059SAnton Blanchard } 435c2085059SAnton Blanchard early_initcall(init_msr_all_available); 436c2085059SAnton Blanchard 437c2085059SAnton Blanchard void giveup_all(struct task_struct *tsk) 438c2085059SAnton Blanchard { 439c2085059SAnton Blanchard unsigned long usermsr; 440c2085059SAnton Blanchard 441c2085059SAnton Blanchard if (!tsk->thread.regs) 442c2085059SAnton Blanchard return; 443c2085059SAnton Blanchard 4448205d5d9SGustavo Romero check_if_tm_restore_required(tsk); 4458205d5d9SGustavo Romero 446c2085059SAnton Blanchard usermsr = tsk->thread.regs->msr; 447c2085059SAnton Blanchard 448c2085059SAnton Blanchard if ((usermsr & msr_all_available) == 0) 449c2085059SAnton Blanchard return; 450c2085059SAnton Blanchard 451c2085059SAnton Blanchard msr_check_and_set(msr_all_available); 452c2085059SAnton Blanchard 45396c79b6bSBenjamin Herrenschmidt WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 45496c79b6bSBenjamin Herrenschmidt 455c2085059SAnton Blanchard #ifdef CONFIG_PPC_FPU 456c2085059SAnton Blanchard if (usermsr & MSR_FP) 457c2085059SAnton Blanchard __giveup_fpu(tsk); 458c2085059SAnton Blanchard #endif 459c2085059SAnton Blanchard #ifdef CONFIG_ALTIVEC 460c2085059SAnton Blanchard if (usermsr & MSR_VEC) 461c2085059SAnton Blanchard __giveup_altivec(tsk); 462c2085059SAnton Blanchard #endif 463c2085059SAnton Blanchard #ifdef CONFIG_SPE 464c2085059SAnton Blanchard if (usermsr & MSR_SPE) 465c2085059SAnton Blanchard __giveup_spe(tsk); 466c2085059SAnton Blanchard #endif 467c2085059SAnton Blanchard 468c2085059SAnton Blanchard msr_check_and_clear(msr_all_available); 469c2085059SAnton Blanchard } 470c2085059SAnton Blanchard EXPORT_SYMBOL(giveup_all); 471c2085059SAnton Blanchard 4726cc0c16dSNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 4736cc0c16dSNicholas Piggin #ifdef CONFIG_PPC_FPU 4746cc0c16dSNicholas Piggin static int restore_fp(struct task_struct *tsk) 4756cc0c16dSNicholas Piggin { 4766cc0c16dSNicholas Piggin if (tsk->thread.load_fp) { 4776cc0c16dSNicholas Piggin load_fp_state(¤t->thread.fp_state); 4786cc0c16dSNicholas Piggin current->thread.load_fp++; 4796cc0c16dSNicholas Piggin return 1; 4806cc0c16dSNicholas Piggin } 4816cc0c16dSNicholas Piggin return 0; 4826cc0c16dSNicholas Piggin } 4836cc0c16dSNicholas Piggin #else 4846cc0c16dSNicholas Piggin static int restore_fp(struct task_struct *tsk) { return 0; } 4856cc0c16dSNicholas Piggin #endif /* CONFIG_PPC_FPU */ 4866cc0c16dSNicholas Piggin 4876cc0c16dSNicholas Piggin #ifdef CONFIG_ALTIVEC 4886cc0c16dSNicholas Piggin #define loadvec(thr) ((thr).load_vec) 4896cc0c16dSNicholas Piggin static int restore_altivec(struct task_struct *tsk) 4906cc0c16dSNicholas Piggin { 4916cc0c16dSNicholas Piggin if (cpu_has_feature(CPU_FTR_ALTIVEC) && (tsk->thread.load_vec)) { 4926cc0c16dSNicholas Piggin load_vr_state(&tsk->thread.vr_state); 4936cc0c16dSNicholas Piggin tsk->thread.used_vr = 1; 4946cc0c16dSNicholas Piggin tsk->thread.load_vec++; 4956cc0c16dSNicholas Piggin 4966cc0c16dSNicholas Piggin return 1; 4976cc0c16dSNicholas Piggin } 4986cc0c16dSNicholas Piggin return 0; 4996cc0c16dSNicholas Piggin } 5006cc0c16dSNicholas Piggin #else 5016cc0c16dSNicholas Piggin #define loadvec(thr) 0 5026cc0c16dSNicholas Piggin static inline int restore_altivec(struct task_struct *tsk) { return 0; } 5036cc0c16dSNicholas Piggin #endif /* CONFIG_ALTIVEC */ 5046cc0c16dSNicholas Piggin 5056cc0c16dSNicholas Piggin #ifdef CONFIG_VSX 5066cc0c16dSNicholas Piggin static int restore_vsx(struct task_struct *tsk) 5076cc0c16dSNicholas Piggin { 5086cc0c16dSNicholas Piggin if (cpu_has_feature(CPU_FTR_VSX)) { 5096cc0c16dSNicholas Piggin tsk->thread.used_vsr = 1; 5106cc0c16dSNicholas Piggin return 1; 5116cc0c16dSNicholas Piggin } 5126cc0c16dSNicholas Piggin 5136cc0c16dSNicholas Piggin return 0; 5146cc0c16dSNicholas Piggin } 5156cc0c16dSNicholas Piggin #else 5166cc0c16dSNicholas Piggin static inline int restore_vsx(struct task_struct *tsk) { return 0; } 5176cc0c16dSNicholas Piggin #endif /* CONFIG_VSX */ 5186cc0c16dSNicholas Piggin 519e2b36d59SNicholas Piggin /* 520e2b36d59SNicholas Piggin * The exception exit path calls restore_math() with interrupts hard disabled 521e2b36d59SNicholas Piggin * but the soft irq state not "reconciled". ftrace code that calls 522e2b36d59SNicholas Piggin * local_irq_save/restore causes warnings. 523e2b36d59SNicholas Piggin * 524e2b36d59SNicholas Piggin * Rather than complicate the exit path, just don't trace restore_math. This 525e2b36d59SNicholas Piggin * could be done by having ftrace entry code check for this un-reconciled 526e2b36d59SNicholas Piggin * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and 527e2b36d59SNicholas Piggin * temporarily fix it up for the duration of the ftrace call. 528e2b36d59SNicholas Piggin */ 529e2b36d59SNicholas Piggin void notrace restore_math(struct pt_regs *regs) 53070fe3d98SCyril Bur { 53170fe3d98SCyril Bur unsigned long msr; 53270fe3d98SCyril Bur 5335c784c84SBreno Leitao if (!MSR_TM_ACTIVE(regs->msr) && 534dc16b553SCyril Bur !current->thread.load_fp && !loadvec(current->thread)) 53570fe3d98SCyril Bur return; 53670fe3d98SCyril Bur 53770fe3d98SCyril Bur msr = regs->msr; 53870fe3d98SCyril Bur msr_check_and_set(msr_all_available); 53970fe3d98SCyril Bur 54070fe3d98SCyril Bur /* 54170fe3d98SCyril Bur * Only reload if the bit is not set in the user MSR, the bit BEING set 54270fe3d98SCyril Bur * indicates that the registers are hot 54370fe3d98SCyril Bur */ 54470fe3d98SCyril Bur if ((!(msr & MSR_FP)) && restore_fp(current)) 54570fe3d98SCyril Bur msr |= MSR_FP | current->thread.fpexc_mode; 54670fe3d98SCyril Bur 54770fe3d98SCyril Bur if ((!(msr & MSR_VEC)) && restore_altivec(current)) 54870fe3d98SCyril Bur msr |= MSR_VEC; 54970fe3d98SCyril Bur 55070fe3d98SCyril Bur if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && 55170fe3d98SCyril Bur restore_vsx(current)) { 55270fe3d98SCyril Bur msr |= MSR_VSX; 55370fe3d98SCyril Bur } 55470fe3d98SCyril Bur 55570fe3d98SCyril Bur msr_check_and_clear(msr_all_available); 55670fe3d98SCyril Bur 55770fe3d98SCyril Bur regs->msr = msr; 55870fe3d98SCyril Bur } 5596cc0c16dSNicholas Piggin #endif 56070fe3d98SCyril Bur 5611cdf039bSMathieu Malaterre static void save_all(struct task_struct *tsk) 562de2a20aaSCyril Bur { 563de2a20aaSCyril Bur unsigned long usermsr; 564de2a20aaSCyril Bur 565de2a20aaSCyril Bur if (!tsk->thread.regs) 566de2a20aaSCyril Bur return; 567de2a20aaSCyril Bur 568de2a20aaSCyril Bur usermsr = tsk->thread.regs->msr; 569de2a20aaSCyril Bur 570de2a20aaSCyril Bur if ((usermsr & msr_all_available) == 0) 571de2a20aaSCyril Bur return; 572de2a20aaSCyril Bur 573de2a20aaSCyril Bur msr_check_and_set(msr_all_available); 574de2a20aaSCyril Bur 57596c79b6bSBenjamin Herrenschmidt WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 57696c79b6bSBenjamin Herrenschmidt 577de2a20aaSCyril Bur if (usermsr & MSR_FP) 5788792468dSCyril Bur save_fpu(tsk); 579de2a20aaSCyril Bur 580de2a20aaSCyril Bur if (usermsr & MSR_VEC) 5816f515d84SCyril Bur save_altivec(tsk); 582de2a20aaSCyril Bur 583de2a20aaSCyril Bur if (usermsr & MSR_SPE) 584de2a20aaSCyril Bur __giveup_spe(tsk); 585de2a20aaSCyril Bur 586de2a20aaSCyril Bur msr_check_and_clear(msr_all_available); 587c76662e8SRam Pai thread_pkey_regs_save(&tsk->thread); 588de2a20aaSCyril Bur } 589de2a20aaSCyril Bur 590579e633eSAnton Blanchard void flush_all_to_thread(struct task_struct *tsk) 591579e633eSAnton Blanchard { 592579e633eSAnton Blanchard if (tsk->thread.regs) { 593579e633eSAnton Blanchard preempt_disable(); 594579e633eSAnton Blanchard BUG_ON(tsk != current); 595579e633eSAnton Blanchard #ifdef CONFIG_SPE 596579e633eSAnton Blanchard if (tsk->thread.regs->msr & MSR_SPE) 597579e633eSAnton Blanchard tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 598579e633eSAnton Blanchard #endif 599e9013785SFelipe Rechia save_all(tsk); 600579e633eSAnton Blanchard 601579e633eSAnton Blanchard preempt_enable(); 602579e633eSAnton Blanchard } 603579e633eSAnton Blanchard } 604579e633eSAnton Blanchard EXPORT_SYMBOL(flush_all_to_thread); 605579e633eSAnton Blanchard 6063bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6073bffb652SDave Kleikamp void do_send_trap(struct pt_regs *regs, unsigned long address, 60847355040SEric W. Biederman unsigned long error_code, int breakpt) 6093bffb652SDave Kleikamp { 61047355040SEric W. Biederman current->thread.trap_nr = TRAP_HWBKPT; 6113bffb652SDave Kleikamp if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 6123bffb652SDave Kleikamp 11, SIGSEGV) == NOTIFY_STOP) 6133bffb652SDave Kleikamp return; 6143bffb652SDave Kleikamp 6153bffb652SDave Kleikamp /* Deliver the signal to userspace */ 616f71dd7dcSEric W. Biederman force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ 617f71dd7dcSEric W. Biederman (void __user *)address); 6183bffb652SDave Kleikamp } 6193bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 6209422de3eSMichael Neuling void do_break (struct pt_regs *regs, unsigned long address, 621d6a61bfcSLuis Machado unsigned long error_code) 622d6a61bfcSLuis Machado { 62341ab5266SAnanth N Mavinakayanahalli current->thread.trap_nr = TRAP_HWBKPT; 624d6a61bfcSLuis Machado if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 625d6a61bfcSLuis Machado 11, SIGSEGV) == NOTIFY_STOP) 626d6a61bfcSLuis Machado return; 627d6a61bfcSLuis Machado 6289422de3eSMichael Neuling if (debugger_break_match(regs)) 629d6a61bfcSLuis Machado return; 630d6a61bfcSLuis Machado 631d6a61bfcSLuis Machado /* Deliver the signal to userspace */ 6322e1661d2SEric W. Biederman force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address); 633d6a61bfcSLuis Machado } 6343bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 635d6a61bfcSLuis Machado 6364a8a9379SRavi Bangoria static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]); 637a2ceff5eSMichael Ellerman 6383bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6393bffb652SDave Kleikamp /* 6403bffb652SDave Kleikamp * Set the debug registers back to their default "safe" values. 6413bffb652SDave Kleikamp */ 6423bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 6433bffb652SDave Kleikamp { 64451ae8d4aSBharat Bhushan thread->debug.iac1 = thread->debug.iac2 = 0; 6453bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 64651ae8d4aSBharat Bhushan thread->debug.iac3 = thread->debug.iac4 = 0; 6473bffb652SDave Kleikamp #endif 64851ae8d4aSBharat Bhushan thread->debug.dac1 = thread->debug.dac2 = 0; 6493bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 65051ae8d4aSBharat Bhushan thread->debug.dvc1 = thread->debug.dvc2 = 0; 6513bffb652SDave Kleikamp #endif 65251ae8d4aSBharat Bhushan thread->debug.dbcr0 = 0; 6533bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 6543bffb652SDave Kleikamp /* 6553bffb652SDave Kleikamp * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 6563bffb652SDave Kleikamp */ 65751ae8d4aSBharat Bhushan thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 6583bffb652SDave Kleikamp DBCR1_IAC3US | DBCR1_IAC4US; 6593bffb652SDave Kleikamp /* 6603bffb652SDave Kleikamp * Force Data Address Compare User/Supervisor bits to be User-only 6613bffb652SDave Kleikamp * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 6623bffb652SDave Kleikamp */ 66351ae8d4aSBharat Bhushan thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 6643bffb652SDave Kleikamp #else 66551ae8d4aSBharat Bhushan thread->debug.dbcr1 = 0; 6663bffb652SDave Kleikamp #endif 6673bffb652SDave Kleikamp } 6683bffb652SDave Kleikamp 669f5f97210SScott Wood static void prime_debug_regs(struct debug_reg *debug) 6703bffb652SDave Kleikamp { 6716cecf76bSScott Wood /* 6726cecf76bSScott Wood * We could have inherited MSR_DE from userspace, since 6736cecf76bSScott Wood * it doesn't get cleared on exception entry. Make sure 6746cecf76bSScott Wood * MSR_DE is clear before we enable any debug events. 6756cecf76bSScott Wood */ 6766cecf76bSScott Wood mtmsr(mfmsr() & ~MSR_DE); 6776cecf76bSScott Wood 678f5f97210SScott Wood mtspr(SPRN_IAC1, debug->iac1); 679f5f97210SScott Wood mtspr(SPRN_IAC2, debug->iac2); 6803bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 681f5f97210SScott Wood mtspr(SPRN_IAC3, debug->iac3); 682f5f97210SScott Wood mtspr(SPRN_IAC4, debug->iac4); 6833bffb652SDave Kleikamp #endif 684f5f97210SScott Wood mtspr(SPRN_DAC1, debug->dac1); 685f5f97210SScott Wood mtspr(SPRN_DAC2, debug->dac2); 6863bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 687f5f97210SScott Wood mtspr(SPRN_DVC1, debug->dvc1); 688f5f97210SScott Wood mtspr(SPRN_DVC2, debug->dvc2); 6893bffb652SDave Kleikamp #endif 690f5f97210SScott Wood mtspr(SPRN_DBCR0, debug->dbcr0); 691f5f97210SScott Wood mtspr(SPRN_DBCR1, debug->dbcr1); 6923bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 693f5f97210SScott Wood mtspr(SPRN_DBCR2, debug->dbcr2); 6943bffb652SDave Kleikamp #endif 6953bffb652SDave Kleikamp } 6963bffb652SDave Kleikamp /* 6973bffb652SDave Kleikamp * Unless neither the old or new thread are making use of the 6983bffb652SDave Kleikamp * debug registers, set the debug registers from the values 6993bffb652SDave Kleikamp * stored in the new thread. 7003bffb652SDave Kleikamp */ 701f5f97210SScott Wood void switch_booke_debug_regs(struct debug_reg *new_debug) 7023bffb652SDave Kleikamp { 70351ae8d4aSBharat Bhushan if ((current->thread.debug.dbcr0 & DBCR0_IDM) 704f5f97210SScott Wood || (new_debug->dbcr0 & DBCR0_IDM)) 705f5f97210SScott Wood prime_debug_regs(new_debug); 7063bffb652SDave Kleikamp } 7073743c9b8SBharat Bhushan EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 7083bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 709e0780b72SK.Prasad #ifndef CONFIG_HAVE_HW_BREAKPOINT 710303e6a9dSRavi Bangoria static void set_breakpoint(int i, struct arch_hw_breakpoint *brk) 711b5ac51d7SChristophe Leroy { 712b5ac51d7SChristophe Leroy preempt_disable(); 713303e6a9dSRavi Bangoria __set_breakpoint(i, brk); 714b5ac51d7SChristophe Leroy preempt_enable(); 715b5ac51d7SChristophe Leroy } 716b5ac51d7SChristophe Leroy 7173bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 7183bffb652SDave Kleikamp { 719303e6a9dSRavi Bangoria int i; 720303e6a9dSRavi Bangoria struct arch_hw_breakpoint null_brk = {0}; 721303e6a9dSRavi Bangoria 722303e6a9dSRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) { 723303e6a9dSRavi Bangoria thread->hw_brk[i] = null_brk; 724252988cbSNicholas Piggin if (ppc_breakpoint_available()) 725303e6a9dSRavi Bangoria set_breakpoint(i, &thread->hw_brk[i]); 726303e6a9dSRavi Bangoria } 727303e6a9dSRavi Bangoria } 728303e6a9dSRavi Bangoria 729303e6a9dSRavi Bangoria static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 730303e6a9dSRavi Bangoria struct arch_hw_breakpoint *b) 731303e6a9dSRavi Bangoria { 732303e6a9dSRavi Bangoria if (a->address != b->address) 733303e6a9dSRavi Bangoria return false; 734303e6a9dSRavi Bangoria if (a->type != b->type) 735303e6a9dSRavi Bangoria return false; 736303e6a9dSRavi Bangoria if (a->len != b->len) 737303e6a9dSRavi Bangoria return false; 738303e6a9dSRavi Bangoria /* no need to check hw_len. it's calculated from address and len */ 739303e6a9dSRavi Bangoria return true; 740303e6a9dSRavi Bangoria } 741303e6a9dSRavi Bangoria 742303e6a9dSRavi Bangoria static void switch_hw_breakpoint(struct task_struct *new) 743303e6a9dSRavi Bangoria { 744303e6a9dSRavi Bangoria int i; 745303e6a9dSRavi Bangoria 746303e6a9dSRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) { 747303e6a9dSRavi Bangoria if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]), 748303e6a9dSRavi Bangoria &new->thread.hw_brk[i]))) 749303e6a9dSRavi Bangoria continue; 750303e6a9dSRavi Bangoria 751303e6a9dSRavi Bangoria __set_breakpoint(i, &new->thread.hw_brk[i]); 752303e6a9dSRavi Bangoria } 7533bffb652SDave Kleikamp } 754e0780b72SK.Prasad #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 7553bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 7563bffb652SDave Kleikamp 757172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 7589422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7599422de3eSMichael Neuling { 760c6c9eaceSBenjamin Herrenschmidt mtspr(SPRN_DAC1, dabr); 761221c185dSDave Kleikamp #ifdef CONFIG_PPC_47x 762221c185dSDave Kleikamp isync(); 763221c185dSDave Kleikamp #endif 7649422de3eSMichael Neuling return 0; 7659422de3eSMichael Neuling } 766c6c9eaceSBenjamin Herrenschmidt #elif defined(CONFIG_PPC_BOOK3S) 7679422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7689422de3eSMichael Neuling { 769cab0af98SMichael Ellerman mtspr(SPRN_DABR, dabr); 77082a9f16aSMichael Neuling if (cpu_has_feature(CPU_FTR_DABRX)) 7714474ef05SMichael Neuling mtspr(SPRN_DABRX, dabrx); 772cab0af98SMichael Ellerman return 0; 77314cf11afSPaul Mackerras } 7749422de3eSMichael Neuling #else 7759422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7769422de3eSMichael Neuling { 7779422de3eSMichael Neuling return -EINVAL; 7789422de3eSMichael Neuling } 7799422de3eSMichael Neuling #endif 7809422de3eSMichael Neuling 7819422de3eSMichael Neuling static inline int set_dabr(struct arch_hw_breakpoint *brk) 7829422de3eSMichael Neuling { 7839422de3eSMichael Neuling unsigned long dabr, dabrx; 7849422de3eSMichael Neuling 7859422de3eSMichael Neuling dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 7869422de3eSMichael Neuling dabrx = ((brk->type >> 3) & 0x7); 7879422de3eSMichael Neuling 7889422de3eSMichael Neuling if (ppc_md.set_dabr) 7899422de3eSMichael Neuling return ppc_md.set_dabr(dabr, dabrx); 7909422de3eSMichael Neuling 7919422de3eSMichael Neuling return __set_dabr(dabr, dabrx); 7929422de3eSMichael Neuling } 7939422de3eSMichael Neuling 79439413ae0SChristophe Leroy static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk) 79539413ae0SChristophe Leroy { 79639413ae0SChristophe Leroy unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW | 79739413ae0SChristophe Leroy LCTRL1_CRWF_RW; 79839413ae0SChristophe Leroy unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN; 799e68ef121SRavi Bangoria unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE); 800e68ef121SRavi Bangoria unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE); 80139413ae0SChristophe Leroy 80239413ae0SChristophe Leroy if (start_addr == 0) 80339413ae0SChristophe Leroy lctrl2 |= LCTRL2_LW0LA_F; 804e68ef121SRavi Bangoria else if (end_addr == 0) 80539413ae0SChristophe Leroy lctrl2 |= LCTRL2_LW0LA_E; 80639413ae0SChristophe Leroy else 80739413ae0SChristophe Leroy lctrl2 |= LCTRL2_LW0LA_EandF; 80839413ae0SChristophe Leroy 80939413ae0SChristophe Leroy mtspr(SPRN_LCTRL2, 0); 81039413ae0SChristophe Leroy 81139413ae0SChristophe Leroy if ((brk->type & HW_BRK_TYPE_RDWR) == 0) 81239413ae0SChristophe Leroy return 0; 81339413ae0SChristophe Leroy 81439413ae0SChristophe Leroy if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) 81539413ae0SChristophe Leroy lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO; 81639413ae0SChristophe Leroy if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) 81739413ae0SChristophe Leroy lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO; 81839413ae0SChristophe Leroy 81939413ae0SChristophe Leroy mtspr(SPRN_CMPE, start_addr - 1); 820e68ef121SRavi Bangoria mtspr(SPRN_CMPF, end_addr); 82139413ae0SChristophe Leroy mtspr(SPRN_LCTRL1, lctrl1); 82239413ae0SChristophe Leroy mtspr(SPRN_LCTRL2, lctrl2); 82339413ae0SChristophe Leroy 82439413ae0SChristophe Leroy return 0; 82539413ae0SChristophe Leroy } 82639413ae0SChristophe Leroy 8274a8a9379SRavi Bangoria void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk) 8289422de3eSMichael Neuling { 8294a8a9379SRavi Bangoria memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk)); 8309422de3eSMichael Neuling 831c1fe190cSMichael Neuling if (dawr_enabled()) 832252988cbSNicholas Piggin // Power8 or later 8334a8a9379SRavi Bangoria set_dawr(nr, brk); 83439413ae0SChristophe Leroy else if (IS_ENABLED(CONFIG_PPC_8xx)) 83539413ae0SChristophe Leroy set_breakpoint_8xx(brk); 836252988cbSNicholas Piggin else if (!cpu_has_feature(CPU_FTR_ARCH_207S)) 837252988cbSNicholas Piggin // Power7 or earlier 83804c32a51SPaul Gortmaker set_dabr(brk); 839252988cbSNicholas Piggin else 840252988cbSNicholas Piggin // Shouldn't happen due to higher level checks 841252988cbSNicholas Piggin WARN_ON_ONCE(1); 8429422de3eSMichael Neuling } 84314cf11afSPaul Mackerras 844404b27d6SMichael Neuling /* Check if we have DAWR or DABR hardware */ 845404b27d6SMichael Neuling bool ppc_breakpoint_available(void) 846404b27d6SMichael Neuling { 847c1fe190cSMichael Neuling if (dawr_enabled()) 848c1fe190cSMichael Neuling return true; /* POWER8 DAWR or POWER9 forced DAWR */ 849404b27d6SMichael Neuling if (cpu_has_feature(CPU_FTR_ARCH_207S)) 850404b27d6SMichael Neuling return false; /* POWER9 with DAWR disabled */ 851404b27d6SMichael Neuling /* DABR: Everything but POWER8 and POWER9 */ 852404b27d6SMichael Neuling return true; 853404b27d6SMichael Neuling } 854404b27d6SMichael Neuling EXPORT_SYMBOL_GPL(ppc_breakpoint_available); 855404b27d6SMichael Neuling 856fb09692eSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 8575d176f75SCyril Bur 8585d176f75SCyril Bur static inline bool tm_enabled(struct task_struct *tsk) 8595d176f75SCyril Bur { 8605d176f75SCyril Bur return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); 8615d176f75SCyril Bur } 8625d176f75SCyril Bur 863edd00b83SCyril Bur static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause) 864d31626f7SPaul Mackerras { 8657f821fc9SMichael Neuling /* 8667f821fc9SMichael Neuling * Use the current MSR TM suspended bit to track if we have 8677f821fc9SMichael Neuling * checkpointed state outstanding. 8687f821fc9SMichael Neuling * On signal delivery, we'd normally reclaim the checkpointed 8697f821fc9SMichael Neuling * state to obtain stack pointer (see:get_tm_stackpointer()). 8707f821fc9SMichael Neuling * This will then directly return to userspace without going 8717f821fc9SMichael Neuling * through __switch_to(). However, if the stack frame is bad, 8727f821fc9SMichael Neuling * we need to exit this thread which calls __switch_to() which 8737f821fc9SMichael Neuling * will again attempt to reclaim the already saved tm state. 8747f821fc9SMichael Neuling * Hence we need to check that we've not already reclaimed 8757f821fc9SMichael Neuling * this state. 8767f821fc9SMichael Neuling * We do this using the current MSR, rather tracking it in 8777f821fc9SMichael Neuling * some specific thread_struct bit, as it has the additional 878027dfac6SMichael Ellerman * benefit of checking for a potential TM bad thing exception. 8797f821fc9SMichael Neuling */ 8807f821fc9SMichael Neuling if (!MSR_TM_SUSPENDED(mfmsr())) 8817f821fc9SMichael Neuling return; 8827f821fc9SMichael Neuling 88391381b9cSCyril Bur giveup_all(container_of(thr, struct task_struct, thread)); 88491381b9cSCyril Bur 885eb5c3f1cSCyril Bur tm_reclaim(thr, cause); 886eb5c3f1cSCyril Bur 887f48e91e8SMichael Neuling /* 888f48e91e8SMichael Neuling * If we are in a transaction and FP is off then we can't have 889f48e91e8SMichael Neuling * used FP inside that transaction. Hence the checkpointed 890f48e91e8SMichael Neuling * state is the same as the live state. We need to copy the 891f48e91e8SMichael Neuling * live state to the checkpointed state so that when the 892f48e91e8SMichael Neuling * transaction is restored, the checkpointed state is correct 893f48e91e8SMichael Neuling * and the aborted transaction sees the correct state. We use 894f48e91e8SMichael Neuling * ckpt_regs.msr here as that's what tm_reclaim will use to 895f48e91e8SMichael Neuling * determine if it's going to write the checkpointed state or 896f48e91e8SMichael Neuling * not. So either this will write the checkpointed registers, 897f48e91e8SMichael Neuling * or reclaim will. Similarly for VMX. 898f48e91e8SMichael Neuling */ 899f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_FP) == 0) 900f48e91e8SMichael Neuling memcpy(&thr->ckfp_state, &thr->fp_state, 901f48e91e8SMichael Neuling sizeof(struct thread_fp_state)); 902f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_VEC) == 0) 903f48e91e8SMichael Neuling memcpy(&thr->ckvr_state, &thr->vr_state, 904f48e91e8SMichael Neuling sizeof(struct thread_vr_state)); 905d31626f7SPaul Mackerras } 906d31626f7SPaul Mackerras 907d31626f7SPaul Mackerras void tm_reclaim_current(uint8_t cause) 908d31626f7SPaul Mackerras { 909d31626f7SPaul Mackerras tm_enable(); 910edd00b83SCyril Bur tm_reclaim_thread(¤t->thread, cause); 911d31626f7SPaul Mackerras } 912d31626f7SPaul Mackerras 913fb09692eSMichael Neuling static inline void tm_reclaim_task(struct task_struct *tsk) 914fb09692eSMichael Neuling { 915fb09692eSMichael Neuling /* We have to work out if we're switching from/to a task that's in the 916fb09692eSMichael Neuling * middle of a transaction. 917fb09692eSMichael Neuling * 918fb09692eSMichael Neuling * In switching we need to maintain a 2nd register state as 919fb09692eSMichael Neuling * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 920000ec280SCyril Bur * checkpointed (tbegin) state in ckpt_regs, ckfp_state and 921000ec280SCyril Bur * ckvr_state 922fb09692eSMichael Neuling * 923fb09692eSMichael Neuling * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 924fb09692eSMichael Neuling */ 925fb09692eSMichael Neuling struct thread_struct *thr = &tsk->thread; 926fb09692eSMichael Neuling 927fb09692eSMichael Neuling if (!thr->regs) 928fb09692eSMichael Neuling return; 929fb09692eSMichael Neuling 930fb09692eSMichael Neuling if (!MSR_TM_ACTIVE(thr->regs->msr)) 931fb09692eSMichael Neuling goto out_and_saveregs; 932fb09692eSMichael Neuling 93392fb8690SMichael Neuling WARN_ON(tm_suspend_disabled); 93492fb8690SMichael Neuling 935fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 936fb09692eSMichael Neuling "ccr=%lx, msr=%lx, trap=%lx)\n", 937fb09692eSMichael Neuling tsk->pid, thr->regs->nip, 938fb09692eSMichael Neuling thr->regs->ccr, thr->regs->msr, 939fb09692eSMichael Neuling thr->regs->trap); 940fb09692eSMichael Neuling 941edd00b83SCyril Bur tm_reclaim_thread(thr, TM_CAUSE_RESCHED); 942fb09692eSMichael Neuling 943fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d complete\n", 944fb09692eSMichael Neuling tsk->pid); 945fb09692eSMichael Neuling 946fb09692eSMichael Neuling out_and_saveregs: 947fb09692eSMichael Neuling /* Always save the regs here, even if a transaction's not active. 948fb09692eSMichael Neuling * This context-switches a thread's TM info SPRs. We do it here to 949fb09692eSMichael Neuling * be consistent with the restore path (in recheckpoint) which 950fb09692eSMichael Neuling * cannot happen later in _switch(). 951fb09692eSMichael Neuling */ 952fb09692eSMichael Neuling tm_save_sprs(thr); 953fb09692eSMichael Neuling } 954fb09692eSMichael Neuling 955eb5c3f1cSCyril Bur extern void __tm_recheckpoint(struct thread_struct *thread); 956e6b8fd02SMichael Neuling 957eb5c3f1cSCyril Bur void tm_recheckpoint(struct thread_struct *thread) 958e6b8fd02SMichael Neuling { 959e6b8fd02SMichael Neuling unsigned long flags; 960e6b8fd02SMichael Neuling 9615d176f75SCyril Bur if (!(thread->regs->msr & MSR_TM)) 9625d176f75SCyril Bur return; 9635d176f75SCyril Bur 964e6b8fd02SMichael Neuling /* We really can't be interrupted here as the TEXASR registers can't 965e6b8fd02SMichael Neuling * change and later in the trecheckpoint code, we have a userspace R1. 966e6b8fd02SMichael Neuling * So let's hard disable over this region. 967e6b8fd02SMichael Neuling */ 968e6b8fd02SMichael Neuling local_irq_save(flags); 969e6b8fd02SMichael Neuling hard_irq_disable(); 970e6b8fd02SMichael Neuling 971e6b8fd02SMichael Neuling /* The TM SPRs are restored here, so that TEXASR.FS can be set 972e6b8fd02SMichael Neuling * before the trecheckpoint and no explosion occurs. 973e6b8fd02SMichael Neuling */ 974e6b8fd02SMichael Neuling tm_restore_sprs(thread); 975e6b8fd02SMichael Neuling 976eb5c3f1cSCyril Bur __tm_recheckpoint(thread); 977e6b8fd02SMichael Neuling 978e6b8fd02SMichael Neuling local_irq_restore(flags); 979e6b8fd02SMichael Neuling } 980e6b8fd02SMichael Neuling 981bc2a9408SMichael Neuling static inline void tm_recheckpoint_new_task(struct task_struct *new) 982fb09692eSMichael Neuling { 983fb09692eSMichael Neuling if (!cpu_has_feature(CPU_FTR_TM)) 984fb09692eSMichael Neuling return; 985fb09692eSMichael Neuling 986fb09692eSMichael Neuling /* Recheckpoint the registers of the thread we're about to switch to. 987fb09692eSMichael Neuling * 988fb09692eSMichael Neuling * If the task was using FP, we non-lazily reload both the original and 989fb09692eSMichael Neuling * the speculative FP register states. This is because the kernel 990fb09692eSMichael Neuling * doesn't see if/when a TM rollback occurs, so if we take an FP 991dc310669SCyril Bur * unavailable later, we are unable to determine which set of FP regs 992fb09692eSMichael Neuling * need to be restored. 993fb09692eSMichael Neuling */ 9945d176f75SCyril Bur if (!tm_enabled(new)) 995fb09692eSMichael Neuling return; 996fb09692eSMichael Neuling 997e6b8fd02SMichael Neuling if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 998fb09692eSMichael Neuling tm_restore_sprs(&new->thread); 999fb09692eSMichael Neuling return; 1000e6b8fd02SMichael Neuling } 1001fb09692eSMichael Neuling /* Recheckpoint to restore original checkpointed register state. */ 1002eb5c3f1cSCyril Bur TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", 1003eb5c3f1cSCyril Bur new->pid, new->thread.regs->msr); 1004fb09692eSMichael Neuling 1005eb5c3f1cSCyril Bur tm_recheckpoint(&new->thread); 1006fb09692eSMichael Neuling 1007dc310669SCyril Bur /* 1008dc310669SCyril Bur * The checkpointed state has been restored but the live state has 1009dc310669SCyril Bur * not, ensure all the math functionality is turned off to trigger 1010dc310669SCyril Bur * restore_math() to reload. 1011dc310669SCyril Bur */ 1012dc310669SCyril Bur new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); 1013fb09692eSMichael Neuling 1014fb09692eSMichael Neuling TM_DEBUG("*** tm_recheckpoint of pid %d complete " 1015fb09692eSMichael Neuling "(kernel msr 0x%lx)\n", 1016fb09692eSMichael Neuling new->pid, mfmsr()); 1017fb09692eSMichael Neuling } 1018fb09692eSMichael Neuling 1019dc310669SCyril Bur static inline void __switch_to_tm(struct task_struct *prev, 1020dc310669SCyril Bur struct task_struct *new) 1021fb09692eSMichael Neuling { 1022fb09692eSMichael Neuling if (cpu_has_feature(CPU_FTR_TM)) { 10235d176f75SCyril Bur if (tm_enabled(prev) || tm_enabled(new)) 1024fb09692eSMichael Neuling tm_enable(); 10255d176f75SCyril Bur 10265d176f75SCyril Bur if (tm_enabled(prev)) { 10275d176f75SCyril Bur prev->thread.load_tm++; 1028fb09692eSMichael Neuling tm_reclaim_task(prev); 10295d176f75SCyril Bur if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) 10305d176f75SCyril Bur prev->thread.regs->msr &= ~MSR_TM; 10315d176f75SCyril Bur } 10325d176f75SCyril Bur 1033dc310669SCyril Bur tm_recheckpoint_new_task(new); 1034fb09692eSMichael Neuling } 1035fb09692eSMichael Neuling } 1036d31626f7SPaul Mackerras 1037d31626f7SPaul Mackerras /* 1038d31626f7SPaul Mackerras * This is called if we are on the way out to userspace and the 1039d31626f7SPaul Mackerras * TIF_RESTORE_TM flag is set. It checks if we need to reload 1040d31626f7SPaul Mackerras * FP and/or vector state and does so if necessary. 1041d31626f7SPaul Mackerras * If userspace is inside a transaction (whether active or 1042d31626f7SPaul Mackerras * suspended) and FP/VMX/VSX instructions have ever been enabled 1043d31626f7SPaul Mackerras * inside that transaction, then we have to keep them enabled 1044d31626f7SPaul Mackerras * and keep the FP/VMX/VSX state loaded while ever the transaction 1045d31626f7SPaul Mackerras * continues. The reason is that if we didn't, and subsequently 1046d31626f7SPaul Mackerras * got a FP/VMX/VSX unavailable interrupt inside a transaction, 1047d31626f7SPaul Mackerras * we don't know whether it's the same transaction, and thus we 1048d31626f7SPaul Mackerras * don't know which of the checkpointed state and the transactional 1049d31626f7SPaul Mackerras * state to use. 1050d31626f7SPaul Mackerras */ 1051d31626f7SPaul Mackerras void restore_tm_state(struct pt_regs *regs) 1052d31626f7SPaul Mackerras { 1053d31626f7SPaul Mackerras unsigned long msr_diff; 1054d31626f7SPaul Mackerras 1055dc310669SCyril Bur /* 1056dc310669SCyril Bur * This is the only moment we should clear TIF_RESTORE_TM as 1057dc310669SCyril Bur * it is here that ckpt_regs.msr and pt_regs.msr become the same 1058dc310669SCyril Bur * again, anything else could lead to an incorrect ckpt_msr being 1059dc310669SCyril Bur * saved and therefore incorrect signal contexts. 1060dc310669SCyril Bur */ 1061d31626f7SPaul Mackerras clear_thread_flag(TIF_RESTORE_TM); 1062d31626f7SPaul Mackerras if (!MSR_TM_ACTIVE(regs->msr)) 1063d31626f7SPaul Mackerras return; 1064d31626f7SPaul Mackerras 1065829023dfSAnshuman Khandual msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 1066d31626f7SPaul Mackerras msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 106770fe3d98SCyril Bur 1068dc16b553SCyril Bur /* Ensure that restore_math() will restore */ 1069dc16b553SCyril Bur if (msr_diff & MSR_FP) 1070dc16b553SCyril Bur current->thread.load_fp = 1; 107139715bf9SValentin Rothberg #ifdef CONFIG_ALTIVEC 1072dc16b553SCyril Bur if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) 1073dc16b553SCyril Bur current->thread.load_vec = 1; 1074dc16b553SCyril Bur #endif 107570fe3d98SCyril Bur restore_math(regs); 107670fe3d98SCyril Bur 1077d31626f7SPaul Mackerras regs->msr |= msr_diff; 1078d31626f7SPaul Mackerras } 1079d31626f7SPaul Mackerras 1080fb09692eSMichael Neuling #else 1081fb09692eSMichael Neuling #define tm_recheckpoint_new_task(new) 1082dc310669SCyril Bur #define __switch_to_tm(prev, new) 1083fb09692eSMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 10849422de3eSMichael Neuling 1085152d523eSAnton Blanchard static inline void save_sprs(struct thread_struct *t) 1086152d523eSAnton Blanchard { 1087152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 108801d7c2a2SOliver O'Halloran if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1089152d523eSAnton Blanchard t->vrsave = mfspr(SPRN_VRSAVE); 1090152d523eSAnton Blanchard #endif 1091152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1092152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) 1093152d523eSAnton Blanchard t->dscr = mfspr(SPRN_DSCR); 1094152d523eSAnton Blanchard 1095152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1096152d523eSAnton Blanchard t->bescr = mfspr(SPRN_BESCR); 1097152d523eSAnton Blanchard t->ebbhr = mfspr(SPRN_EBBHR); 1098152d523eSAnton Blanchard t->ebbrr = mfspr(SPRN_EBBRR); 1099152d523eSAnton Blanchard 1100152d523eSAnton Blanchard t->fscr = mfspr(SPRN_FSCR); 1101152d523eSAnton Blanchard 1102152d523eSAnton Blanchard /* 1103152d523eSAnton Blanchard * Note that the TAR is not available for use in the kernel. 1104152d523eSAnton Blanchard * (To provide this, the TAR should be backed up/restored on 1105152d523eSAnton Blanchard * exception entry/exit instead, and be in pt_regs. FIXME, 1106152d523eSAnton Blanchard * this should be in pt_regs anyway (for debug).) 1107152d523eSAnton Blanchard */ 1108152d523eSAnton Blanchard t->tar = mfspr(SPRN_TAR); 1109152d523eSAnton Blanchard } 1110152d523eSAnton Blanchard #endif 111106bb53b3SRam Pai 111206bb53b3SRam Pai thread_pkey_regs_save(t); 1113152d523eSAnton Blanchard } 1114152d523eSAnton Blanchard 1115152d523eSAnton Blanchard static inline void restore_sprs(struct thread_struct *old_thread, 1116152d523eSAnton Blanchard struct thread_struct *new_thread) 1117152d523eSAnton Blanchard { 1118152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 1119152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC) && 1120152d523eSAnton Blanchard old_thread->vrsave != new_thread->vrsave) 1121152d523eSAnton Blanchard mtspr(SPRN_VRSAVE, new_thread->vrsave); 1122152d523eSAnton Blanchard #endif 1123152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1124152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) { 1125152d523eSAnton Blanchard u64 dscr = get_paca()->dscr_default; 1126b57bd2deSMichael Neuling if (new_thread->dscr_inherit) 1127152d523eSAnton Blanchard dscr = new_thread->dscr; 1128152d523eSAnton Blanchard 1129152d523eSAnton Blanchard if (old_thread->dscr != dscr) 1130152d523eSAnton Blanchard mtspr(SPRN_DSCR, dscr); 1131152d523eSAnton Blanchard } 1132152d523eSAnton Blanchard 1133152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1134152d523eSAnton Blanchard if (old_thread->bescr != new_thread->bescr) 1135152d523eSAnton Blanchard mtspr(SPRN_BESCR, new_thread->bescr); 1136152d523eSAnton Blanchard if (old_thread->ebbhr != new_thread->ebbhr) 1137152d523eSAnton Blanchard mtspr(SPRN_EBBHR, new_thread->ebbhr); 1138152d523eSAnton Blanchard if (old_thread->ebbrr != new_thread->ebbrr) 1139152d523eSAnton Blanchard mtspr(SPRN_EBBRR, new_thread->ebbrr); 1140152d523eSAnton Blanchard 1141b57bd2deSMichael Neuling if (old_thread->fscr != new_thread->fscr) 1142b57bd2deSMichael Neuling mtspr(SPRN_FSCR, new_thread->fscr); 1143b57bd2deSMichael Neuling 1144152d523eSAnton Blanchard if (old_thread->tar != new_thread->tar) 1145152d523eSAnton Blanchard mtspr(SPRN_TAR, new_thread->tar); 1146152d523eSAnton Blanchard } 1147ec233edeSSukadev Bhattiprolu 11483449f191SAlastair D'Silva if (cpu_has_feature(CPU_FTR_P9_TIDR) && 1149ec233edeSSukadev Bhattiprolu old_thread->tidr != new_thread->tidr) 1150ec233edeSSukadev Bhattiprolu mtspr(SPRN_TIDR, new_thread->tidr); 1151152d523eSAnton Blanchard #endif 115206bb53b3SRam Pai 115306bb53b3SRam Pai thread_pkey_regs_restore(new_thread, old_thread); 1154152d523eSAnton Blanchard } 1155152d523eSAnton Blanchard 115614cf11afSPaul Mackerras struct task_struct *__switch_to(struct task_struct *prev, 115714cf11afSPaul Mackerras struct task_struct *new) 115814cf11afSPaul Mackerras { 115914cf11afSPaul Mackerras struct thread_struct *new_thread, *old_thread; 116014cf11afSPaul Mackerras struct task_struct *last; 1161d6bf29b4SPeter Zijlstra #ifdef CONFIG_PPC_BOOK3S_64 1162d6bf29b4SPeter Zijlstra struct ppc64_tlb_batch *batch; 1163d6bf29b4SPeter Zijlstra #endif 116414cf11afSPaul Mackerras 1165152d523eSAnton Blanchard new_thread = &new->thread; 1166152d523eSAnton Blanchard old_thread = ¤t->thread; 1167152d523eSAnton Blanchard 11687ba5fef7SMichael Neuling WARN_ON(!irqs_disabled()); 11697ba5fef7SMichael Neuling 11704e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 117169111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1172d6bf29b4SPeter Zijlstra if (batch->active) { 1173d6bf29b4SPeter Zijlstra current_thread_info()->local_flags |= _TLF_LAZY_MMU; 1174d6bf29b4SPeter Zijlstra if (batch->index) 1175d6bf29b4SPeter Zijlstra __flush_tlb_pending(batch); 1176d6bf29b4SPeter Zijlstra batch->active = 0; 1177d6bf29b4SPeter Zijlstra } 11784e003747SMichael Ellerman #endif /* CONFIG_PPC_BOOK3S_64 */ 117906d67d54SPaul Mackerras 1180f3d885ccSAnton Blanchard #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1181f3d885ccSAnton Blanchard switch_booke_debug_regs(&new->thread.debug); 1182f3d885ccSAnton Blanchard #else 1183f3d885ccSAnton Blanchard /* 1184f3d885ccSAnton Blanchard * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 1185f3d885ccSAnton Blanchard * schedule DABR 1186f3d885ccSAnton Blanchard */ 1187f3d885ccSAnton Blanchard #ifndef CONFIG_HAVE_HW_BREAKPOINT 1188303e6a9dSRavi Bangoria switch_hw_breakpoint(new); 1189f3d885ccSAnton Blanchard #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1190f3d885ccSAnton Blanchard #endif 1191f3d885ccSAnton Blanchard 1192f3d885ccSAnton Blanchard /* 1193f3d885ccSAnton Blanchard * We need to save SPRs before treclaim/trecheckpoint as these will 1194f3d885ccSAnton Blanchard * change a number of them. 1195f3d885ccSAnton Blanchard */ 1196f3d885ccSAnton Blanchard save_sprs(&prev->thread); 1197f3d885ccSAnton Blanchard 1198f3d885ccSAnton Blanchard /* Save FPU, Altivec, VSX and SPE state */ 1199f3d885ccSAnton Blanchard giveup_all(prev); 1200f3d885ccSAnton Blanchard 1201dc310669SCyril Bur __switch_to_tm(prev, new); 1202dc310669SCyril Bur 1203e4c0fc5fSNicholas Piggin if (!radix_enabled()) { 120444387e9fSAnton Blanchard /* 1205e4c0fc5fSNicholas Piggin * We can't take a PMU exception inside _switch() since there 1206e4c0fc5fSNicholas Piggin * is a window where the kernel stack SLB and the kernel stack 1207e4c0fc5fSNicholas Piggin * are out of sync. Hard disable here. 120844387e9fSAnton Blanchard */ 120944387e9fSAnton Blanchard hard_irq_disable(); 1210e4c0fc5fSNicholas Piggin } 1211bc2a9408SMichael Neuling 121220dbe670SAnton Blanchard /* 121320dbe670SAnton Blanchard * Call restore_sprs() before calling _switch(). If we move it after 121420dbe670SAnton Blanchard * _switch() then we miss out on calling it for new tasks. The reason 121520dbe670SAnton Blanchard * for this is we manually create a stack frame for new tasks that 121620dbe670SAnton Blanchard * directly returns through ret_from_fork() or 121720dbe670SAnton Blanchard * ret_from_kernel_thread(). See copy_thread() for details. 121820dbe670SAnton Blanchard */ 1219f3d885ccSAnton Blanchard restore_sprs(old_thread, new_thread); 1220f3d885ccSAnton Blanchard 122120dbe670SAnton Blanchard last = _switch(old_thread, new_thread); 122220dbe670SAnton Blanchard 12234e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 1224d6bf29b4SPeter Zijlstra if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1225d6bf29b4SPeter Zijlstra current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 122669111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1227d6bf29b4SPeter Zijlstra batch->active = 1; 1228d6bf29b4SPeter Zijlstra } 122970fe3d98SCyril Bur 123005b98791SChristophe Leroy if (current->thread.regs) { 123105b98791SChristophe Leroy restore_math(current->thread.regs); 123207d2a628SNicholas Piggin 123307d2a628SNicholas Piggin /* 123407d2a628SNicholas Piggin * The copy-paste buffer can only store into foreign real 123507d2a628SNicholas Piggin * addresses, so unprivileged processes can not see the 123607d2a628SNicholas Piggin * data or use it in any way unless they have foreign real 12379d2a4d71SSukadev Bhattiprolu * mappings. If the new process has the foreign real address 12389d2a4d71SSukadev Bhattiprolu * mappings, we must issue a cp_abort to clear any state and 12399d2a4d71SSukadev Bhattiprolu * prevent snooping, corruption or a covert channel. 124007d2a628SNicholas Piggin */ 1241c420644cSHaren Myneni if (current->mm && 1242c420644cSHaren Myneni atomic_read(¤t->mm->context.vas_windows)) 12439d2a4d71SSukadev Bhattiprolu asm volatile(PPC_CP_ABORT); 124407d2a628SNicholas Piggin } 12454e003747SMichael Ellerman #endif /* CONFIG_PPC_BOOK3S_64 */ 1246d6bf29b4SPeter Zijlstra 124714cf11afSPaul Mackerras return last; 124814cf11afSPaul Mackerras } 124914cf11afSPaul Mackerras 1250df13102fSChristophe Leroy #define NR_INSN_TO_PRINT 16 125106d67d54SPaul Mackerras 125206d67d54SPaul Mackerras static void show_instructions(struct pt_regs *regs) 125306d67d54SPaul Mackerras { 125406d67d54SPaul Mackerras int i; 1255a6e2c226SAneesh Kumar K.V unsigned long nip = regs->nip; 1256df13102fSChristophe Leroy unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); 125706d67d54SPaul Mackerras 125806d67d54SPaul Mackerras printk("Instruction dump:"); 125906d67d54SPaul Mackerras 1260a6e2c226SAneesh Kumar K.V /* 1261a6e2c226SAneesh Kumar K.V * If we were executing with the MMU off for instructions, adjust pc 1262a6e2c226SAneesh Kumar K.V * rather than printing XXXXXXXX. 1263a6e2c226SAneesh Kumar K.V */ 1264a6e2c226SAneesh Kumar K.V if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) { 1265a6e2c226SAneesh Kumar K.V pc = (unsigned long)phys_to_virt(pc); 1266a6e2c226SAneesh Kumar K.V nip = (unsigned long)phys_to_virt(regs->nip); 1267a6e2c226SAneesh Kumar K.V } 1268a6e2c226SAneesh Kumar K.V 1269df13102fSChristophe Leroy for (i = 0; i < NR_INSN_TO_PRINT; i++) { 127006d67d54SPaul Mackerras int instr; 127106d67d54SPaul Mackerras 127206d67d54SPaul Mackerras if (!(i % 8)) 12732ffd04deSAndrew Donnellan pr_cont("\n"); 127406d67d54SPaul Mackerras 127500ae36deSAnton Blanchard if (!__kernel_text_address(pc) || 127625f12ae4SChristoph Hellwig get_kernel_nofault(instr, (const void *)pc)) { 12772ffd04deSAndrew Donnellan pr_cont("XXXXXXXX "); 127806d67d54SPaul Mackerras } else { 1279a6e2c226SAneesh Kumar K.V if (nip == pc) 12802ffd04deSAndrew Donnellan pr_cont("<%08x> ", instr); 128106d67d54SPaul Mackerras else 12822ffd04deSAndrew Donnellan pr_cont("%08x ", instr); 128306d67d54SPaul Mackerras } 128406d67d54SPaul Mackerras 128506d67d54SPaul Mackerras pc += sizeof(int); 128606d67d54SPaul Mackerras } 128706d67d54SPaul Mackerras 12882ffd04deSAndrew Donnellan pr_cont("\n"); 128906d67d54SPaul Mackerras } 129006d67d54SPaul Mackerras 129188b0fe17SMurilo Opsfelder Araujo void show_user_instructions(struct pt_regs *regs) 129288b0fe17SMurilo Opsfelder Araujo { 129388b0fe17SMurilo Opsfelder Araujo unsigned long pc; 1294df13102fSChristophe Leroy int n = NR_INSN_TO_PRINT; 1295fb2d9505SChristophe Leroy struct seq_buf s; 1296fb2d9505SChristophe Leroy char buf[96]; /* enough for 8 times 9 + 2 chars */ 129788b0fe17SMurilo Opsfelder Araujo 1298df13102fSChristophe Leroy pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); 129988b0fe17SMurilo Opsfelder Araujo 1300fb2d9505SChristophe Leroy seq_buf_init(&s, buf, sizeof(buf)); 130188b0fe17SMurilo Opsfelder Araujo 1302fb2d9505SChristophe Leroy while (n) { 1303fb2d9505SChristophe Leroy int i; 1304fb2d9505SChristophe Leroy 1305fb2d9505SChristophe Leroy seq_buf_clear(&s); 1306fb2d9505SChristophe Leroy 1307fb2d9505SChristophe Leroy for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) { 130888b0fe17SMurilo Opsfelder Araujo int instr; 130988b0fe17SMurilo Opsfelder Araujo 1310c0ee37e8SChristoph Hellwig if (copy_from_user_nofault(&instr, (void __user *)pc, 1311c0ee37e8SChristoph Hellwig sizeof(instr))) { 1312fb2d9505SChristophe Leroy seq_buf_printf(&s, "XXXXXXXX "); 1313fb2d9505SChristophe Leroy continue; 1314fb2d9505SChristophe Leroy } 1315fb2d9505SChristophe Leroy seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr); 131688b0fe17SMurilo Opsfelder Araujo } 131788b0fe17SMurilo Opsfelder Araujo 1318fb2d9505SChristophe Leroy if (!seq_buf_has_overflowed(&s)) 1319fb2d9505SChristophe Leroy pr_info("%s[%d]: code: %s\n", current->comm, 1320fb2d9505SChristophe Leroy current->pid, s.buffer); 132188b0fe17SMurilo Opsfelder Araujo } 132288b0fe17SMurilo Opsfelder Araujo } 132388b0fe17SMurilo Opsfelder Araujo 1324801c0b2cSMichael Neuling struct regbit { 132506d67d54SPaul Mackerras unsigned long bit; 132606d67d54SPaul Mackerras const char *name; 1327801c0b2cSMichael Neuling }; 1328801c0b2cSMichael Neuling 1329801c0b2cSMichael Neuling static struct regbit msr_bits[] = { 13303bfd0c9cSAnton Blanchard #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 13313bfd0c9cSAnton Blanchard {MSR_SF, "SF"}, 13323bfd0c9cSAnton Blanchard {MSR_HV, "HV"}, 13333bfd0c9cSAnton Blanchard #endif 13343bfd0c9cSAnton Blanchard {MSR_VEC, "VEC"}, 13353bfd0c9cSAnton Blanchard {MSR_VSX, "VSX"}, 13363bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13373bfd0c9cSAnton Blanchard {MSR_CE, "CE"}, 13383bfd0c9cSAnton Blanchard #endif 133906d67d54SPaul Mackerras {MSR_EE, "EE"}, 134006d67d54SPaul Mackerras {MSR_PR, "PR"}, 134106d67d54SPaul Mackerras {MSR_FP, "FP"}, 134206d67d54SPaul Mackerras {MSR_ME, "ME"}, 13433bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13441b98326bSKumar Gala {MSR_DE, "DE"}, 13453bfd0c9cSAnton Blanchard #else 13463bfd0c9cSAnton Blanchard {MSR_SE, "SE"}, 13473bfd0c9cSAnton Blanchard {MSR_BE, "BE"}, 13483bfd0c9cSAnton Blanchard #endif 134906d67d54SPaul Mackerras {MSR_IR, "IR"}, 135006d67d54SPaul Mackerras {MSR_DR, "DR"}, 13513bfd0c9cSAnton Blanchard {MSR_PMM, "PMM"}, 13523bfd0c9cSAnton Blanchard #ifndef CONFIG_BOOKE 13533bfd0c9cSAnton Blanchard {MSR_RI, "RI"}, 13543bfd0c9cSAnton Blanchard {MSR_LE, "LE"}, 13553bfd0c9cSAnton Blanchard #endif 135606d67d54SPaul Mackerras {0, NULL} 135706d67d54SPaul Mackerras }; 135806d67d54SPaul Mackerras 1359801c0b2cSMichael Neuling static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 136006d67d54SPaul Mackerras { 1361801c0b2cSMichael Neuling const char *s = ""; 136206d67d54SPaul Mackerras 136306d67d54SPaul Mackerras for (; bits->bit; ++bits) 136406d67d54SPaul Mackerras if (val & bits->bit) { 1365db5ba5aeSMichael Ellerman pr_cont("%s%s", s, bits->name); 1366801c0b2cSMichael Neuling s = sep; 136706d67d54SPaul Mackerras } 1368801c0b2cSMichael Neuling } 1369801c0b2cSMichael Neuling 1370801c0b2cSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1371801c0b2cSMichael Neuling static struct regbit msr_tm_bits[] = { 1372801c0b2cSMichael Neuling {MSR_TS_T, "T"}, 1373801c0b2cSMichael Neuling {MSR_TS_S, "S"}, 1374801c0b2cSMichael Neuling {MSR_TM, "E"}, 1375801c0b2cSMichael Neuling {0, NULL} 1376801c0b2cSMichael Neuling }; 1377801c0b2cSMichael Neuling 1378801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) 1379801c0b2cSMichael Neuling { 1380801c0b2cSMichael Neuling /* 1381801c0b2cSMichael Neuling * This only prints something if at least one of the TM bit is set. 1382801c0b2cSMichael Neuling * Inside the TM[], the output means: 1383801c0b2cSMichael Neuling * E: Enabled (bit 32) 1384801c0b2cSMichael Neuling * S: Suspended (bit 33) 1385801c0b2cSMichael Neuling * T: Transactional (bit 34) 1386801c0b2cSMichael Neuling */ 1387801c0b2cSMichael Neuling if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1388db5ba5aeSMichael Ellerman pr_cont(",TM["); 1389801c0b2cSMichael Neuling print_bits(val, msr_tm_bits, ""); 1390db5ba5aeSMichael Ellerman pr_cont("]"); 1391801c0b2cSMichael Neuling } 1392801c0b2cSMichael Neuling } 1393801c0b2cSMichael Neuling #else 1394801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) {} 1395801c0b2cSMichael Neuling #endif 1396801c0b2cSMichael Neuling 1397801c0b2cSMichael Neuling static void print_msr_bits(unsigned long val) 1398801c0b2cSMichael Neuling { 1399db5ba5aeSMichael Ellerman pr_cont("<"); 1400801c0b2cSMichael Neuling print_bits(val, msr_bits, ","); 1401801c0b2cSMichael Neuling print_tm_bits(val); 1402db5ba5aeSMichael Ellerman pr_cont(">"); 140306d67d54SPaul Mackerras } 140406d67d54SPaul Mackerras 140506d67d54SPaul Mackerras #ifdef CONFIG_PPC64 1406f6f7dde3Santon@samba.org #define REG "%016lx" 140706d67d54SPaul Mackerras #define REGS_PER_LINE 4 140806d67d54SPaul Mackerras #define LAST_VOLATILE 13 140906d67d54SPaul Mackerras #else 1410f6f7dde3Santon@samba.org #define REG "%08lx" 141106d67d54SPaul Mackerras #define REGS_PER_LINE 8 141206d67d54SPaul Mackerras #define LAST_VOLATILE 12 141306d67d54SPaul Mackerras #endif 141406d67d54SPaul Mackerras 141514cf11afSPaul Mackerras void show_regs(struct pt_regs * regs) 141614cf11afSPaul Mackerras { 141714cf11afSPaul Mackerras int i, trap; 141814cf11afSPaul Mackerras 1419a43cb95dSTejun Heo show_regs_print_info(KERN_DEFAULT); 1420a43cb95dSTejun Heo 142106d67d54SPaul Mackerras printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 142206d67d54SPaul Mackerras regs->nip, regs->link, regs->ctr); 1423182dc9c7SMichael Ellerman printk("REGS: %px TRAP: %04lx %s (%s)\n", 142496b644bdSSerge E. Hallyn regs, regs->trap, print_tainted(), init_utsname()->release); 142506d67d54SPaul Mackerras printk("MSR: "REG" ", regs->msr); 1426801c0b2cSMichael Neuling print_msr_bits(regs->msr); 1427f6fc73fbSMichael Ellerman pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 142814cf11afSPaul Mackerras trap = TRAP(regs); 1429912237eaSNicholas Piggin if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR)) 14307dae865fSMichael Ellerman pr_cont("CFAR: "REG" ", regs->orig_gpr3); 1431c5400649SAnton Blanchard if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1432ba28c9aaSKumar Gala #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 14337dae865fSMichael Ellerman pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 143414170789SKumar Gala #else 14357dae865fSMichael Ellerman pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 14369db8bcfdSAnton Blanchard #endif 14379db8bcfdSAnton Blanchard #ifdef CONFIG_PPC64 14383130a7bbSNicholas Piggin pr_cont("IRQMASK: %lx ", regs->softe); 14399db8bcfdSAnton Blanchard #endif 14409db8bcfdSAnton Blanchard #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 14416d888d1aSAnton Blanchard if (MSR_TM_ACTIVE(regs->msr)) 14427dae865fSMichael Ellerman pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 144314170789SKumar Gala #endif 144414cf11afSPaul Mackerras 144514cf11afSPaul Mackerras for (i = 0; i < 32; i++) { 144606d67d54SPaul Mackerras if ((i % REGS_PER_LINE) == 0) 14477dae865fSMichael Ellerman pr_cont("\nGPR%02d: ", i); 14487dae865fSMichael Ellerman pr_cont(REG " ", regs->gpr[i]); 144906d67d54SPaul Mackerras if (i == LAST_VOLATILE && !FULL_REGS(regs)) 145014cf11afSPaul Mackerras break; 145114cf11afSPaul Mackerras } 14527dae865fSMichael Ellerman pr_cont("\n"); 145314cf11afSPaul Mackerras #ifdef CONFIG_KALLSYMS 145414cf11afSPaul Mackerras /* 145514cf11afSPaul Mackerras * Lookup NIP late so we have the best change of getting the 145614cf11afSPaul Mackerras * above info out without failing 145714cf11afSPaul Mackerras */ 1458058c78f4SBenjamin Herrenschmidt printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1459058c78f4SBenjamin Herrenschmidt printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 146014cf11afSPaul Mackerras #endif 14619cb8f069SDmitry Safonov show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT); 146206d67d54SPaul Mackerras if (!user_mode(regs)) 146306d67d54SPaul Mackerras show_instructions(regs); 146414cf11afSPaul Mackerras } 146514cf11afSPaul Mackerras 146614cf11afSPaul Mackerras void flush_thread(void) 146714cf11afSPaul Mackerras { 1468e0780b72SK.Prasad #ifdef CONFIG_HAVE_HW_BREAKPOINT 14695aae8a53SK.Prasad flush_ptrace_hw_breakpoint(current); 1470e0780b72SK.Prasad #else /* CONFIG_HAVE_HW_BREAKPOINT */ 14713bffb652SDave Kleikamp set_debug_reg_defaults(¤t->thread); 1472e0780b72SK.Prasad #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 147314cf11afSPaul Mackerras } 147414cf11afSPaul Mackerras 1475425d3314SNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 1476425d3314SNicholas Piggin void arch_setup_new_exec(void) 1477425d3314SNicholas Piggin { 1478425d3314SNicholas Piggin if (radix_enabled()) 1479425d3314SNicholas Piggin return; 1480425d3314SNicholas Piggin hash__setup_new_exec(); 1481425d3314SNicholas Piggin } 1482425d3314SNicholas Piggin #endif 1483425d3314SNicholas Piggin 1484ec233edeSSukadev Bhattiprolu #ifdef CONFIG_PPC64 148571cc64a8SAlastair D'Silva /** 148671cc64a8SAlastair D'Silva * Assign a TIDR (thread ID) for task @t and set it in the thread 1487ec233edeSSukadev Bhattiprolu * structure. For now, we only support setting TIDR for 'current' task. 148871cc64a8SAlastair D'Silva * 148971cc64a8SAlastair D'Silva * Since the TID value is a truncated form of it PID, it is possible 149071cc64a8SAlastair D'Silva * (but unlikely) for 2 threads to have the same TID. In the unlikely event 149171cc64a8SAlastair D'Silva * that 2 threads share the same TID and are waiting, one of the following 149271cc64a8SAlastair D'Silva * cases will happen: 149371cc64a8SAlastair D'Silva * 149471cc64a8SAlastair D'Silva * 1. The correct thread is running, the wrong thread is not 149571cc64a8SAlastair D'Silva * In this situation, the correct thread is woken and proceeds to pass it's 149671cc64a8SAlastair D'Silva * condition check. 149771cc64a8SAlastair D'Silva * 149871cc64a8SAlastair D'Silva * 2. Neither threads are running 149971cc64a8SAlastair D'Silva * In this situation, neither thread will be woken. When scheduled, the waiting 150071cc64a8SAlastair D'Silva * threads will execute either a wait, which will return immediately, followed 150171cc64a8SAlastair D'Silva * by a condition check, which will pass for the correct thread and fail 150271cc64a8SAlastair D'Silva * for the wrong thread, or they will execute the condition check immediately. 150371cc64a8SAlastair D'Silva * 150471cc64a8SAlastair D'Silva * 3. The wrong thread is running, the correct thread is not 150571cc64a8SAlastair D'Silva * The wrong thread will be woken, but will fail it's condition check and 150671cc64a8SAlastair D'Silva * re-execute wait. The correct thread, when scheduled, will execute either 150771cc64a8SAlastair D'Silva * it's condition check (which will pass), or wait, which returns immediately 150871cc64a8SAlastair D'Silva * when called the first time after the thread is scheduled, followed by it's 150971cc64a8SAlastair D'Silva * condition check (which will pass). 151071cc64a8SAlastair D'Silva * 151171cc64a8SAlastair D'Silva * 4. Both threads are running 151271cc64a8SAlastair D'Silva * Both threads will be woken. The wrong thread will fail it's condition check 151371cc64a8SAlastair D'Silva * and execute another wait, while the correct thread will pass it's condition 151471cc64a8SAlastair D'Silva * check. 151571cc64a8SAlastair D'Silva * 151671cc64a8SAlastair D'Silva * @t: the task to set the thread ID for 1517ec233edeSSukadev Bhattiprolu */ 1518ec233edeSSukadev Bhattiprolu int set_thread_tidr(struct task_struct *t) 1519ec233edeSSukadev Bhattiprolu { 15203449f191SAlastair D'Silva if (!cpu_has_feature(CPU_FTR_P9_TIDR)) 1521ec233edeSSukadev Bhattiprolu return -EINVAL; 1522ec233edeSSukadev Bhattiprolu 1523ec233edeSSukadev Bhattiprolu if (t != current) 1524ec233edeSSukadev Bhattiprolu return -EINVAL; 1525ec233edeSSukadev Bhattiprolu 15267e4d4233SVaibhav Jain if (t->thread.tidr) 15277e4d4233SVaibhav Jain return 0; 15287e4d4233SVaibhav Jain 152971cc64a8SAlastair D'Silva t->thread.tidr = (u16)task_pid_nr(t); 1530ec233edeSSukadev Bhattiprolu mtspr(SPRN_TIDR, t->thread.tidr); 1531ec233edeSSukadev Bhattiprolu 1532ec233edeSSukadev Bhattiprolu return 0; 1533ec233edeSSukadev Bhattiprolu } 1534b1db5513SChristophe Lombard EXPORT_SYMBOL_GPL(set_thread_tidr); 1535ec233edeSSukadev Bhattiprolu 1536ec233edeSSukadev Bhattiprolu #endif /* CONFIG_PPC64 */ 1537ec233edeSSukadev Bhattiprolu 153814cf11afSPaul Mackerras void 153914cf11afSPaul Mackerras release_thread(struct task_struct *t) 154014cf11afSPaul Mackerras { 154114cf11afSPaul Mackerras } 154214cf11afSPaul Mackerras 154314cf11afSPaul Mackerras /* 154455ccf3feSSuresh Siddha * this gets called so that we can store coprocessor state into memory and 154555ccf3feSSuresh Siddha * copy the current task into the new thread. 154614cf11afSPaul Mackerras */ 154755ccf3feSSuresh Siddha int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 154814cf11afSPaul Mackerras { 1549579e633eSAnton Blanchard flush_all_to_thread(src); 1550621b5060SMichael Neuling /* 1551621b5060SMichael Neuling * Flush TM state out so we can copy it. __switch_to_tm() does this 1552621b5060SMichael Neuling * flush but it removes the checkpointed state from the current CPU and 1553621b5060SMichael Neuling * transitions the CPU out of TM mode. Hence we need to call 1554621b5060SMichael Neuling * tm_recheckpoint_new_task() (on the same task) to restore the 1555621b5060SMichael Neuling * checkpointed state back and the TM mode. 15565d176f75SCyril Bur * 15575d176f75SCyril Bur * Can't pass dst because it isn't ready. Doesn't matter, passing 15585d176f75SCyril Bur * dst is only important for __switch_to() 1559621b5060SMichael Neuling */ 1560dc310669SCyril Bur __switch_to_tm(src, src); 1561330a1eb7SMichael Ellerman 156255ccf3feSSuresh Siddha *dst = *src; 1563330a1eb7SMichael Ellerman 1564330a1eb7SMichael Ellerman clear_task_ebb(dst); 1565330a1eb7SMichael Ellerman 156655ccf3feSSuresh Siddha return 0; 156714cf11afSPaul Mackerras } 156814cf11afSPaul Mackerras 1569cec15488SMichael Ellerman static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1570cec15488SMichael Ellerman { 15714e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 1572cec15488SMichael Ellerman unsigned long sp_vsid; 1573cec15488SMichael Ellerman unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1574cec15488SMichael Ellerman 1575caca285eSAneesh Kumar K.V if (radix_enabled()) 1576caca285eSAneesh Kumar K.V return; 1577caca285eSAneesh Kumar K.V 1578cec15488SMichael Ellerman if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1579cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1580cec15488SMichael Ellerman << SLB_VSID_SHIFT_1T; 1581cec15488SMichael Ellerman else 1582cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1583cec15488SMichael Ellerman << SLB_VSID_SHIFT; 1584cec15488SMichael Ellerman sp_vsid |= SLB_VSID_KERNEL | llp; 1585cec15488SMichael Ellerman p->thread.ksp_vsid = sp_vsid; 1586cec15488SMichael Ellerman #endif 1587cec15488SMichael Ellerman } 1588cec15488SMichael Ellerman 158914cf11afSPaul Mackerras /* 159014cf11afSPaul Mackerras * Copy a thread.. 159114cf11afSPaul Mackerras */ 1592efcac658SAlexey Kardashevskiy 15936eca8933SAlex Dowad /* 15946eca8933SAlex Dowad * Copy architecture-specific thread state 15956eca8933SAlex Dowad */ 1596facd04a9SNicholas Piggin int copy_thread_tls(unsigned long clone_flags, unsigned long usp, 1597facd04a9SNicholas Piggin unsigned long kthread_arg, struct task_struct *p, 1598facd04a9SNicholas Piggin unsigned long tls) 159914cf11afSPaul Mackerras { 160014cf11afSPaul Mackerras struct pt_regs *childregs, *kregs; 160114cf11afSPaul Mackerras extern void ret_from_fork(void); 1602*7fa95f9aSNicholas Piggin extern void ret_from_fork_scv(void); 160358254e10SAl Viro extern void ret_from_kernel_thread(void); 160458254e10SAl Viro void (*f)(void); 16050cec6fd1SAl Viro unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 16065d31a96eSMichael Ellerman struct thread_info *ti = task_thread_info(p); 16076b424efaSRavi Bangoria #ifdef CONFIG_HAVE_HW_BREAKPOINT 16086b424efaSRavi Bangoria int i; 16096b424efaSRavi Bangoria #endif 16105d31a96eSMichael Ellerman 1611ed1cd6deSChristophe Leroy klp_init_thread_info(p); 161214cf11afSPaul Mackerras 161314cf11afSPaul Mackerras /* Copy registers */ 161414cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 161514cf11afSPaul Mackerras childregs = (struct pt_regs *) sp; 1616ab75819dSAl Viro if (unlikely(p->flags & PF_KTHREAD)) { 16176eca8933SAlex Dowad /* kernel thread */ 161858254e10SAl Viro memset(childregs, 0, sizeof(struct pt_regs)); 161914cf11afSPaul Mackerras childregs->gpr[1] = sp + sizeof(struct pt_regs); 16207cedd601SAnton Blanchard /* function */ 16217cedd601SAnton Blanchard if (usp) 16227cedd601SAnton Blanchard childregs->gpr[14] = ppc_function_entry((void *)usp); 162358254e10SAl Viro #ifdef CONFIG_PPC64 1624b5e2fc1cSAl Viro clear_tsk_thread_flag(p, TIF_32BIT); 1625c2e480baSMadhavan Srinivasan childregs->softe = IRQS_ENABLED; 162606d67d54SPaul Mackerras #endif 16276eca8933SAlex Dowad childregs->gpr[15] = kthread_arg; 162814cf11afSPaul Mackerras p->thread.regs = NULL; /* no user register state */ 1629138d1ce8SAl Viro ti->flags |= _TIF_RESTOREALL; 163058254e10SAl Viro f = ret_from_kernel_thread; 163114cf11afSPaul Mackerras } else { 16326eca8933SAlex Dowad /* user thread */ 1633afa86fc4SAl Viro struct pt_regs *regs = current_pt_regs(); 163458254e10SAl Viro CHECK_FULL_REGS(regs); 163558254e10SAl Viro *childregs = *regs; 1636ea516b11SAl Viro if (usp) 163714cf11afSPaul Mackerras childregs->gpr[1] = usp; 163814cf11afSPaul Mackerras p->thread.regs = childregs; 1639*7fa95f9aSNicholas Piggin /* 64s sets this in ret_from_fork */ 1640*7fa95f9aSNicholas Piggin if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64)) 164158254e10SAl Viro childregs->gpr[3] = 0; /* Result from fork() */ 164206d67d54SPaul Mackerras if (clone_flags & CLONE_SETTLS) { 16439904b005SDenis Kirjanov if (!is_32bit_task()) 1644facd04a9SNicholas Piggin childregs->gpr[13] = tls; 164506d67d54SPaul Mackerras else 1646facd04a9SNicholas Piggin childregs->gpr[2] = tls; 164714cf11afSPaul Mackerras } 164858254e10SAl Viro 1649*7fa95f9aSNicholas Piggin if (trap_is_scv(regs)) 1650*7fa95f9aSNicholas Piggin f = ret_from_fork_scv; 1651*7fa95f9aSNicholas Piggin else 165258254e10SAl Viro f = ret_from_fork; 165306d67d54SPaul Mackerras } 1654d272f667SCyril Bur childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); 165514cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 165614cf11afSPaul Mackerras 165714cf11afSPaul Mackerras /* 165814cf11afSPaul Mackerras * The way this works is that at some point in the future 165914cf11afSPaul Mackerras * some task will call _switch to switch to the new task. 166014cf11afSPaul Mackerras * That will pop off the stack frame created below and start 166114cf11afSPaul Mackerras * the new task running at ret_from_fork. The new task will 166214cf11afSPaul Mackerras * do some house keeping and then return from the fork or clone 166314cf11afSPaul Mackerras * system call, using the stack frame created above. 166414cf11afSPaul Mackerras */ 1665af945cf4SLi Zhong ((unsigned long *)sp)[0] = 0; 166614cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 166714cf11afSPaul Mackerras kregs = (struct pt_regs *) sp; 166814cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 166914cf11afSPaul Mackerras p->thread.ksp = sp; 1670cbc9565eSBenjamin Herrenschmidt #ifdef CONFIG_PPC32 1671a7916a1dSChristophe Leroy p->thread.ksp_limit = (unsigned long)end_of_stack(p); 1672cbc9565eSBenjamin Herrenschmidt #endif 167328d170abSOleg Nesterov #ifdef CONFIG_HAVE_HW_BREAKPOINT 16746b424efaSRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) 16756b424efaSRavi Bangoria p->thread.ptrace_bps[i] = NULL; 167628d170abSOleg Nesterov #endif 167728d170abSOleg Nesterov 167818461960SPaul Mackerras p->thread.fp_save_area = NULL; 167918461960SPaul Mackerras #ifdef CONFIG_ALTIVEC 168018461960SPaul Mackerras p->thread.vr_save_area = NULL; 168118461960SPaul Mackerras #endif 168218461960SPaul Mackerras 1683cec15488SMichael Ellerman setup_ksp_vsid(p, sp); 168406d67d54SPaul Mackerras 1685efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64 1686efcac658SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_DSCR)) { 16871021cb26SAnton Blanchard p->thread.dscr_inherit = current->thread.dscr_inherit; 1688db1231dcSAnton Blanchard p->thread.dscr = mfspr(SPRN_DSCR); 1689efcac658SAlexey Kardashevskiy } 169092779245SHaren Myneni if (cpu_has_feature(CPU_FTR_HAS_PPR)) 16914c2de74cSNicholas Piggin childregs->ppr = DEFAULT_PPR; 1692ec233edeSSukadev Bhattiprolu 1693ec233edeSSukadev Bhattiprolu p->thread.tidr = 0; 1694efcac658SAlexey Kardashevskiy #endif 16957cedd601SAnton Blanchard kregs->nip = ppc_function_entry(f); 169614cf11afSPaul Mackerras return 0; 169714cf11afSPaul Mackerras } 169814cf11afSPaul Mackerras 16995434ae74SNicholas Piggin void preload_new_slb_context(unsigned long start, unsigned long sp); 17005434ae74SNicholas Piggin 170114cf11afSPaul Mackerras /* 170214cf11afSPaul Mackerras * Set up a thread for executing a new program 170314cf11afSPaul Mackerras */ 170406d67d54SPaul Mackerras void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 170514cf11afSPaul Mackerras { 170690eac727SMichael Ellerman #ifdef CONFIG_PPC64 170790eac727SMichael Ellerman unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 17085434ae74SNicholas Piggin 17095434ae74SNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 1710f89bd8baSAneesh Kumar K.V if (!radix_enabled()) 17115434ae74SNicholas Piggin preload_new_slb_context(start, sp); 17125434ae74SNicholas Piggin #endif 171390eac727SMichael Ellerman #endif 171490eac727SMichael Ellerman 171506d67d54SPaul Mackerras /* 171606d67d54SPaul Mackerras * If we exec out of a kernel thread then thread.regs will not be 171706d67d54SPaul Mackerras * set. Do it now. 171806d67d54SPaul Mackerras */ 171906d67d54SPaul Mackerras if (!current->thread.regs) { 17200cec6fd1SAl Viro struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 17210cec6fd1SAl Viro current->thread.regs = regs - 1; 172206d67d54SPaul Mackerras } 172306d67d54SPaul Mackerras 17248e96a87cSCyril Bur #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 17258e96a87cSCyril Bur /* 17268e96a87cSCyril Bur * Clear any transactional state, we're exec()ing. The cause is 17278e96a87cSCyril Bur * not important as there will never be a recheckpoint so it's not 17288e96a87cSCyril Bur * user visible. 17298e96a87cSCyril Bur */ 17308e96a87cSCyril Bur if (MSR_TM_SUSPENDED(mfmsr())) 17318e96a87cSCyril Bur tm_reclaim_current(0); 17328e96a87cSCyril Bur #endif 17338e96a87cSCyril Bur 173414cf11afSPaul Mackerras memset(regs->gpr, 0, sizeof(regs->gpr)); 173514cf11afSPaul Mackerras regs->ctr = 0; 173614cf11afSPaul Mackerras regs->link = 0; 173714cf11afSPaul Mackerras regs->xer = 0; 173814cf11afSPaul Mackerras regs->ccr = 0; 173914cf11afSPaul Mackerras regs->gpr[1] = sp; 174006d67d54SPaul Mackerras 1741474f8196SRoland McGrath /* 1742474f8196SRoland McGrath * We have just cleared all the nonvolatile GPRs, so make 1743474f8196SRoland McGrath * FULL_REGS(regs) return true. This is necessary to allow 1744474f8196SRoland McGrath * ptrace to examine the thread immediately after exec. 1745474f8196SRoland McGrath */ 1746feb9df34SNicholas Piggin SET_FULL_REGS(regs); 1747474f8196SRoland McGrath 174806d67d54SPaul Mackerras #ifdef CONFIG_PPC32 174906d67d54SPaul Mackerras regs->mq = 0; 175006d67d54SPaul Mackerras regs->nip = start; 175114cf11afSPaul Mackerras regs->msr = MSR_USER; 175206d67d54SPaul Mackerras #else 17539904b005SDenis Kirjanov if (!is_32bit_task()) { 175494af3abfSRusty Russell unsigned long entry; 175506d67d54SPaul Mackerras 175694af3abfSRusty Russell if (is_elf2_task()) { 175794af3abfSRusty Russell /* Look ma, no function descriptors! */ 175894af3abfSRusty Russell entry = start; 175994af3abfSRusty Russell 176094af3abfSRusty Russell /* 176194af3abfSRusty Russell * Ulrich says: 176294af3abfSRusty Russell * The latest iteration of the ABI requires that when 176394af3abfSRusty Russell * calling a function (at its global entry point), 176494af3abfSRusty Russell * the caller must ensure r12 holds the entry point 176594af3abfSRusty Russell * address (so that the function can quickly 176694af3abfSRusty Russell * establish addressability). 176794af3abfSRusty Russell */ 176894af3abfSRusty Russell regs->gpr[12] = start; 176994af3abfSRusty Russell /* Make sure that's restored on entry to userspace. */ 177094af3abfSRusty Russell set_thread_flag(TIF_RESTOREALL); 177194af3abfSRusty Russell } else { 177294af3abfSRusty Russell unsigned long toc; 177394af3abfSRusty Russell 177494af3abfSRusty Russell /* start is a relocated pointer to the function 177594af3abfSRusty Russell * descriptor for the elf _start routine. The first 177694af3abfSRusty Russell * entry in the function descriptor is the entry 177794af3abfSRusty Russell * address of _start and the second entry is the TOC 177894af3abfSRusty Russell * value we need to use. 177906d67d54SPaul Mackerras */ 178006d67d54SPaul Mackerras __get_user(entry, (unsigned long __user *)start); 178106d67d54SPaul Mackerras __get_user(toc, (unsigned long __user *)start+1); 178206d67d54SPaul Mackerras 178306d67d54SPaul Mackerras /* Check whether the e_entry function descriptor entries 178406d67d54SPaul Mackerras * need to be relocated before we can use them. 178506d67d54SPaul Mackerras */ 178606d67d54SPaul Mackerras if (load_addr != 0) { 178706d67d54SPaul Mackerras entry += load_addr; 178806d67d54SPaul Mackerras toc += load_addr; 178906d67d54SPaul Mackerras } 179006d67d54SPaul Mackerras regs->gpr[2] = toc; 179194af3abfSRusty Russell } 179294af3abfSRusty Russell regs->nip = entry; 179306d67d54SPaul Mackerras regs->msr = MSR_USER64; 1794d4bf9a78SStephen Rothwell } else { 1795d4bf9a78SStephen Rothwell regs->nip = start; 1796d4bf9a78SStephen Rothwell regs->gpr[2] = 0; 1797d4bf9a78SStephen Rothwell regs->msr = MSR_USER32; 179806d67d54SPaul Mackerras } 179906d67d54SPaul Mackerras #endif 1800ce48b210SMichael Neuling #ifdef CONFIG_VSX 1801ce48b210SMichael Neuling current->thread.used_vsr = 0; 1802ce48b210SMichael Neuling #endif 18035434ae74SNicholas Piggin current->thread.load_slb = 0; 18041195892cSBreno Leitao current->thread.load_fp = 0; 1805de79f7b9SPaul Mackerras memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 180618461960SPaul Mackerras current->thread.fp_save_area = NULL; 180714cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 1808de79f7b9SPaul Mackerras memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1809de79f7b9SPaul Mackerras current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 181018461960SPaul Mackerras current->thread.vr_save_area = NULL; 181114cf11afSPaul Mackerras current->thread.vrsave = 0; 181214cf11afSPaul Mackerras current->thread.used_vr = 0; 18131195892cSBreno Leitao current->thread.load_vec = 0; 181414cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 181514cf11afSPaul Mackerras #ifdef CONFIG_SPE 181614cf11afSPaul Mackerras memset(current->thread.evr, 0, sizeof(current->thread.evr)); 181714cf11afSPaul Mackerras current->thread.acc = 0; 181814cf11afSPaul Mackerras current->thread.spefscr = 0; 181914cf11afSPaul Mackerras current->thread.used_spe = 0; 182014cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 1821bc2a9408SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1822bc2a9408SMichael Neuling current->thread.tm_tfhar = 0; 1823bc2a9408SMichael Neuling current->thread.tm_texasr = 0; 1824bc2a9408SMichael Neuling current->thread.tm_tfiar = 0; 18257f22ced4SBreno Leitao current->thread.load_tm = 0; 1826bc2a9408SMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 182706bb53b3SRam Pai 182806bb53b3SRam Pai thread_pkey_regs_init(¤t->thread); 182914cf11afSPaul Mackerras } 1830e1802b06SAnton Blanchard EXPORT_SYMBOL(start_thread); 183114cf11afSPaul Mackerras 183214cf11afSPaul Mackerras #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 183314cf11afSPaul Mackerras | PR_FP_EXC_RES | PR_FP_EXC_INV) 183414cf11afSPaul Mackerras 183514cf11afSPaul Mackerras int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 183614cf11afSPaul Mackerras { 183714cf11afSPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 183814cf11afSPaul Mackerras 183914cf11afSPaul Mackerras /* This is a bit hairy. If we are an SPE enabled processor 184014cf11afSPaul Mackerras * (have embedded fp) we store the IEEE exception enable flags in 184114cf11afSPaul Mackerras * fpexc_mode. fpexc_mode is also used for setting FP exception 184214cf11afSPaul Mackerras * mode (asyn, precise, disabled) for 'Classic' FP. */ 184314cf11afSPaul Mackerras if (val & PR_FP_EXC_SW_ENABLE) { 184414cf11afSPaul Mackerras #ifdef CONFIG_SPE 18455e14d21eSKumar Gala if (cpu_has_feature(CPU_FTR_SPE)) { 1846640e9225SJoseph Myers /* 1847640e9225SJoseph Myers * When the sticky exception bits are set 1848640e9225SJoseph Myers * directly by userspace, it must call prctl 1849640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1850640e9225SJoseph Myers * in the existing prctl settings) or 1851640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1852640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1853640e9225SJoseph Myers * saving and restoring the whole 1854640e9225SJoseph Myers * floating-point environment need to do so 1855640e9225SJoseph Myers * anyway to restore the prctl settings from 1856640e9225SJoseph Myers * the saved environment. 1857640e9225SJoseph Myers */ 1858640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 185914cf11afSPaul Mackerras tsk->thread.fpexc_mode = val & 186014cf11afSPaul Mackerras (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 186106d67d54SPaul Mackerras return 0; 18625e14d21eSKumar Gala } else { 18635e14d21eSKumar Gala return -EINVAL; 18645e14d21eSKumar Gala } 186514cf11afSPaul Mackerras #else 186614cf11afSPaul Mackerras return -EINVAL; 186714cf11afSPaul Mackerras #endif 186806d67d54SPaul Mackerras } 186906d67d54SPaul Mackerras 187014cf11afSPaul Mackerras /* on a CONFIG_SPE this does not hurt us. The bits that 187114cf11afSPaul Mackerras * __pack_fe01 use do not overlap with bits used for 187214cf11afSPaul Mackerras * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 187314cf11afSPaul Mackerras * on CONFIG_SPE implementations are reserved so writing to 187414cf11afSPaul Mackerras * them does not change anything */ 187514cf11afSPaul Mackerras if (val > PR_FP_EXC_PRECISE) 187614cf11afSPaul Mackerras return -EINVAL; 187714cf11afSPaul Mackerras tsk->thread.fpexc_mode = __pack_fe01(val); 187814cf11afSPaul Mackerras if (regs != NULL && (regs->msr & MSR_FP) != 0) 187914cf11afSPaul Mackerras regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 188014cf11afSPaul Mackerras | tsk->thread.fpexc_mode; 188114cf11afSPaul Mackerras return 0; 188214cf11afSPaul Mackerras } 188314cf11afSPaul Mackerras 188414cf11afSPaul Mackerras int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 188514cf11afSPaul Mackerras { 188614cf11afSPaul Mackerras unsigned int val; 188714cf11afSPaul Mackerras 188814cf11afSPaul Mackerras if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 188914cf11afSPaul Mackerras #ifdef CONFIG_SPE 1890640e9225SJoseph Myers if (cpu_has_feature(CPU_FTR_SPE)) { 1891640e9225SJoseph Myers /* 1892640e9225SJoseph Myers * When the sticky exception bits are set 1893640e9225SJoseph Myers * directly by userspace, it must call prctl 1894640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1895640e9225SJoseph Myers * in the existing prctl settings) or 1896640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1897640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1898640e9225SJoseph Myers * saving and restoring the whole 1899640e9225SJoseph Myers * floating-point environment need to do so 1900640e9225SJoseph Myers * anyway to restore the prctl settings from 1901640e9225SJoseph Myers * the saved environment. 1902640e9225SJoseph Myers */ 1903640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 190414cf11afSPaul Mackerras val = tsk->thread.fpexc_mode; 1905640e9225SJoseph Myers } else 19065e14d21eSKumar Gala return -EINVAL; 190714cf11afSPaul Mackerras #else 190814cf11afSPaul Mackerras return -EINVAL; 190914cf11afSPaul Mackerras #endif 191014cf11afSPaul Mackerras else 191114cf11afSPaul Mackerras val = __unpack_fe01(tsk->thread.fpexc_mode); 191214cf11afSPaul Mackerras return put_user(val, (unsigned int __user *) adr); 191314cf11afSPaul Mackerras } 191414cf11afSPaul Mackerras 1915fab5db97SPaul Mackerras int set_endian(struct task_struct *tsk, unsigned int val) 1916fab5db97SPaul Mackerras { 1917fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1918fab5db97SPaul Mackerras 1919fab5db97SPaul Mackerras if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1920fab5db97SPaul Mackerras (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1921fab5db97SPaul Mackerras return -EINVAL; 1922fab5db97SPaul Mackerras 1923fab5db97SPaul Mackerras if (regs == NULL) 1924fab5db97SPaul Mackerras return -EINVAL; 1925fab5db97SPaul Mackerras 1926fab5db97SPaul Mackerras if (val == PR_ENDIAN_BIG) 1927fab5db97SPaul Mackerras regs->msr &= ~MSR_LE; 1928fab5db97SPaul Mackerras else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1929fab5db97SPaul Mackerras regs->msr |= MSR_LE; 1930fab5db97SPaul Mackerras else 1931fab5db97SPaul Mackerras return -EINVAL; 1932fab5db97SPaul Mackerras 1933fab5db97SPaul Mackerras return 0; 1934fab5db97SPaul Mackerras } 1935fab5db97SPaul Mackerras 1936fab5db97SPaul Mackerras int get_endian(struct task_struct *tsk, unsigned long adr) 1937fab5db97SPaul Mackerras { 1938fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1939fab5db97SPaul Mackerras unsigned int val; 1940fab5db97SPaul Mackerras 1941fab5db97SPaul Mackerras if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1942fab5db97SPaul Mackerras !cpu_has_feature(CPU_FTR_REAL_LE)) 1943fab5db97SPaul Mackerras return -EINVAL; 1944fab5db97SPaul Mackerras 1945fab5db97SPaul Mackerras if (regs == NULL) 1946fab5db97SPaul Mackerras return -EINVAL; 1947fab5db97SPaul Mackerras 1948fab5db97SPaul Mackerras if (regs->msr & MSR_LE) { 1949fab5db97SPaul Mackerras if (cpu_has_feature(CPU_FTR_REAL_LE)) 1950fab5db97SPaul Mackerras val = PR_ENDIAN_LITTLE; 1951fab5db97SPaul Mackerras else 1952fab5db97SPaul Mackerras val = PR_ENDIAN_PPC_LITTLE; 1953fab5db97SPaul Mackerras } else 1954fab5db97SPaul Mackerras val = PR_ENDIAN_BIG; 1955fab5db97SPaul Mackerras 1956fab5db97SPaul Mackerras return put_user(val, (unsigned int __user *)adr); 1957fab5db97SPaul Mackerras } 1958fab5db97SPaul Mackerras 1959e9370ae1SPaul Mackerras int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1960e9370ae1SPaul Mackerras { 1961e9370ae1SPaul Mackerras tsk->thread.align_ctl = val; 1962e9370ae1SPaul Mackerras return 0; 1963e9370ae1SPaul Mackerras } 1964e9370ae1SPaul Mackerras 1965e9370ae1SPaul Mackerras int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1966e9370ae1SPaul Mackerras { 1967e9370ae1SPaul Mackerras return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1968e9370ae1SPaul Mackerras } 1969e9370ae1SPaul Mackerras 1970bb72c481SPaul Mackerras static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1971bb72c481SPaul Mackerras unsigned long nbytes) 1972bb72c481SPaul Mackerras { 1973bb72c481SPaul Mackerras unsigned long stack_page; 1974bb72c481SPaul Mackerras unsigned long cpu = task_cpu(p); 1975bb72c481SPaul Mackerras 1976bb72c481SPaul Mackerras stack_page = (unsigned long)hardirq_ctx[cpu]; 1977a7916a1dSChristophe Leroy if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 1978bb72c481SPaul Mackerras return 1; 1979bb72c481SPaul Mackerras 1980bb72c481SPaul Mackerras stack_page = (unsigned long)softirq_ctx[cpu]; 1981a7916a1dSChristophe Leroy if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 1982bb72c481SPaul Mackerras return 1; 1983a7916a1dSChristophe Leroy 1984bb72c481SPaul Mackerras return 0; 1985bb72c481SPaul Mackerras } 1986bb72c481SPaul Mackerras 1987a2e36683SNicholas Piggin static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p, 1988a2e36683SNicholas Piggin unsigned long nbytes) 1989a2e36683SNicholas Piggin { 1990a2e36683SNicholas Piggin #ifdef CONFIG_PPC64 1991a2e36683SNicholas Piggin unsigned long stack_page; 1992a2e36683SNicholas Piggin unsigned long cpu = task_cpu(p); 1993a2e36683SNicholas Piggin 1994a2e36683SNicholas Piggin stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE; 1995a2e36683SNicholas Piggin if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 1996a2e36683SNicholas Piggin return 1; 1997a2e36683SNicholas Piggin 1998a2e36683SNicholas Piggin # ifdef CONFIG_PPC_BOOK3S_64 1999a2e36683SNicholas Piggin stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE; 2000a2e36683SNicholas Piggin if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2001a2e36683SNicholas Piggin return 1; 2002a2e36683SNicholas Piggin 2003a2e36683SNicholas Piggin stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE; 2004a2e36683SNicholas Piggin if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2005a2e36683SNicholas Piggin return 1; 2006a2e36683SNicholas Piggin # endif 2007a2e36683SNicholas Piggin #endif 2008a2e36683SNicholas Piggin 2009a2e36683SNicholas Piggin return 0; 2010a2e36683SNicholas Piggin } 2011a2e36683SNicholas Piggin 2012a2e36683SNicholas Piggin 20132f25194dSAnton Blanchard int validate_sp(unsigned long sp, struct task_struct *p, 201414cf11afSPaul Mackerras unsigned long nbytes) 201514cf11afSPaul Mackerras { 20160cec6fd1SAl Viro unsigned long stack_page = (unsigned long)task_stack_page(p); 201714cf11afSPaul Mackerras 2018a7916a1dSChristophe Leroy if (sp < THREAD_SIZE) 2019a7916a1dSChristophe Leroy return 0; 2020a7916a1dSChristophe Leroy 2021a7916a1dSChristophe Leroy if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 202214cf11afSPaul Mackerras return 1; 202314cf11afSPaul Mackerras 2024a2e36683SNicholas Piggin if (valid_irq_stack(sp, p, nbytes)) 2025a2e36683SNicholas Piggin return 1; 2026a2e36683SNicholas Piggin 2027a2e36683SNicholas Piggin return valid_emergency_stack(sp, p, nbytes); 202814cf11afSPaul Mackerras } 202914cf11afSPaul Mackerras 20302f25194dSAnton Blanchard EXPORT_SYMBOL(validate_sp); 20312f25194dSAnton Blanchard 2032018cce33SChristophe Leroy static unsigned long __get_wchan(struct task_struct *p) 203306d67d54SPaul Mackerras { 203406d67d54SPaul Mackerras unsigned long ip, sp; 203506d67d54SPaul Mackerras int count = 0; 203606d67d54SPaul Mackerras 203706d67d54SPaul Mackerras if (!p || p == current || p->state == TASK_RUNNING) 203806d67d54SPaul Mackerras return 0; 203906d67d54SPaul Mackerras 204006d67d54SPaul Mackerras sp = p->thread.ksp; 2041ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 204206d67d54SPaul Mackerras return 0; 204306d67d54SPaul Mackerras 204406d67d54SPaul Mackerras do { 204506d67d54SPaul Mackerras sp = *(unsigned long *)sp; 20464ca360f3SKautuk Consul if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) || 20474ca360f3SKautuk Consul p->state == TASK_RUNNING) 204806d67d54SPaul Mackerras return 0; 204906d67d54SPaul Mackerras if (count > 0) { 2050ec2b36b9SBenjamin Herrenschmidt ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 205106d67d54SPaul Mackerras if (!in_sched_functions(ip)) 205206d67d54SPaul Mackerras return ip; 205306d67d54SPaul Mackerras } 205406d67d54SPaul Mackerras } while (count++ < 16); 205506d67d54SPaul Mackerras return 0; 205606d67d54SPaul Mackerras } 205706d67d54SPaul Mackerras 2058018cce33SChristophe Leroy unsigned long get_wchan(struct task_struct *p) 2059018cce33SChristophe Leroy { 2060018cce33SChristophe Leroy unsigned long ret; 2061018cce33SChristophe Leroy 2062018cce33SChristophe Leroy if (!try_get_task_stack(p)) 2063018cce33SChristophe Leroy return 0; 2064018cce33SChristophe Leroy 2065018cce33SChristophe Leroy ret = __get_wchan(p); 2066018cce33SChristophe Leroy 2067018cce33SChristophe Leroy put_task_stack(p); 2068018cce33SChristophe Leroy 2069018cce33SChristophe Leroy return ret; 2070018cce33SChristophe Leroy } 2071018cce33SChristophe Leroy 2072c4d04be1SJohannes Berg static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 207314cf11afSPaul Mackerras 20749cb8f069SDmitry Safonov void show_stack(struct task_struct *tsk, unsigned long *stack, 2075b9677a8cSDmitry Safonov const char *loglvl) 207614cf11afSPaul Mackerras { 207706d67d54SPaul Mackerras unsigned long sp, ip, lr, newsp; 207814cf11afSPaul Mackerras int count = 0; 207906d67d54SPaul Mackerras int firstframe = 1; 20806794c782SSteven Rostedt #ifdef CONFIG_FUNCTION_GRAPH_TRACER 20817c1bb6bbSNaveen N. Rao unsigned long ret_addr; 20827c1bb6bbSNaveen N. Rao int ftrace_idx = 0; 20836794c782SSteven Rostedt #endif 208414cf11afSPaul Mackerras 208514cf11afSPaul Mackerras if (tsk == NULL) 208614cf11afSPaul Mackerras tsk = current; 2087018cce33SChristophe Leroy 2088018cce33SChristophe Leroy if (!try_get_task_stack(tsk)) 2089018cce33SChristophe Leroy return; 2090018cce33SChristophe Leroy 2091018cce33SChristophe Leroy sp = (unsigned long) stack; 209214cf11afSPaul Mackerras if (sp == 0) { 209314cf11afSPaul Mackerras if (tsk == current) 20943d13e839SMichael Ellerman sp = current_stack_frame(); 209514cf11afSPaul Mackerras else 209614cf11afSPaul Mackerras sp = tsk->thread.ksp; 209714cf11afSPaul Mackerras } 209814cf11afSPaul Mackerras 209906d67d54SPaul Mackerras lr = 0; 2100b9677a8cSDmitry Safonov printk("%sCall Trace:\n", loglvl); 210114cf11afSPaul Mackerras do { 2102ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 2103018cce33SChristophe Leroy break; 210406d67d54SPaul Mackerras 210506d67d54SPaul Mackerras stack = (unsigned long *) sp; 210606d67d54SPaul Mackerras newsp = stack[0]; 2107ec2b36b9SBenjamin Herrenschmidt ip = stack[STACK_FRAME_LR_SAVE]; 210806d67d54SPaul Mackerras if (!firstframe || ip != lr) { 2109b9677a8cSDmitry Safonov printk("%s["REG"] ["REG"] %pS", 2110b9677a8cSDmitry Safonov loglvl, sp, ip, (void *)ip); 21116794c782SSteven Rostedt #ifdef CONFIG_FUNCTION_GRAPH_TRACER 21127c1bb6bbSNaveen N. Rao ret_addr = ftrace_graph_ret_addr(current, 21137c1bb6bbSNaveen N. Rao &ftrace_idx, ip, stack); 21147c1bb6bbSNaveen N. Rao if (ret_addr != ip) 21157c1bb6bbSNaveen N. Rao pr_cont(" (%pS)", (void *)ret_addr); 21166794c782SSteven Rostedt #endif 211706d67d54SPaul Mackerras if (firstframe) 21189a1f490fSMichael Ellerman pr_cont(" (unreliable)"); 21199a1f490fSMichael Ellerman pr_cont("\n"); 212014cf11afSPaul Mackerras } 212106d67d54SPaul Mackerras firstframe = 0; 212206d67d54SPaul Mackerras 212306d67d54SPaul Mackerras /* 212406d67d54SPaul Mackerras * See if this is an exception frame. 212506d67d54SPaul Mackerras * We look for the "regshere" marker in the current frame. 212606d67d54SPaul Mackerras */ 2127ec2b36b9SBenjamin Herrenschmidt if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 2128ec2b36b9SBenjamin Herrenschmidt && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 212906d67d54SPaul Mackerras struct pt_regs *regs = (struct pt_regs *) 213006d67d54SPaul Mackerras (sp + STACK_FRAME_OVERHEAD); 213106d67d54SPaul Mackerras lr = regs->link; 2132b9677a8cSDmitry Safonov printk("%s--- interrupt: %lx at %pS\n LR = %pS\n", 2133b9677a8cSDmitry Safonov loglvl, regs->trap, 2134b9677a8cSDmitry Safonov (void *)regs->nip, (void *)lr); 213506d67d54SPaul Mackerras firstframe = 1; 213614cf11afSPaul Mackerras } 213706d67d54SPaul Mackerras 213806d67d54SPaul Mackerras sp = newsp; 213906d67d54SPaul Mackerras } while (count++ < kstack_depth_to_print); 2140018cce33SChristophe Leroy 2141018cce33SChristophe Leroy put_task_stack(tsk); 214206d67d54SPaul Mackerras } 214306d67d54SPaul Mackerras 2144cb2c9b27SAnton Blanchard #ifdef CONFIG_PPC64 2145fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 21460e37739bSMichael Ellerman void notrace __ppc64_runlatch_on(void) 2147cb2c9b27SAnton Blanchard { 2148fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2149d1d0d5ffSNicholas Piggin 2150d1d0d5ffSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2151d1d0d5ffSNicholas Piggin /* 2152d1d0d5ffSNicholas Piggin * Least significant bit (RUN) is the only writable bit of 2153d1d0d5ffSNicholas Piggin * the CTRL register, so we can avoid mfspr. 2.06 is not the 2154d1d0d5ffSNicholas Piggin * earliest ISA where this is the case, but it's convenient. 2155d1d0d5ffSNicholas Piggin */ 2156d1d0d5ffSNicholas Piggin mtspr(SPRN_CTRLT, CTRL_RUNLATCH); 2157d1d0d5ffSNicholas Piggin } else { 2158cb2c9b27SAnton Blanchard unsigned long ctrl; 2159cb2c9b27SAnton Blanchard 2160d1d0d5ffSNicholas Piggin /* 2161d1d0d5ffSNicholas Piggin * Some architectures (e.g., Cell) have writable fields other 2162d1d0d5ffSNicholas Piggin * than RUN, so do the read-modify-write. 2163d1d0d5ffSNicholas Piggin */ 2164cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2165cb2c9b27SAnton Blanchard ctrl |= CTRL_RUNLATCH; 2166cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2167d1d0d5ffSNicholas Piggin } 2168cb2c9b27SAnton Blanchard 2169fae2e0fbSBenjamin Herrenschmidt ti->local_flags |= _TLF_RUNLATCH; 2170cb2c9b27SAnton Blanchard } 2171cb2c9b27SAnton Blanchard 2172fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 21730e37739bSMichael Ellerman void notrace __ppc64_runlatch_off(void) 2174cb2c9b27SAnton Blanchard { 2175fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2176cb2c9b27SAnton Blanchard 2177fae2e0fbSBenjamin Herrenschmidt ti->local_flags &= ~_TLF_RUNLATCH; 2178cb2c9b27SAnton Blanchard 2179d1d0d5ffSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2180d1d0d5ffSNicholas Piggin mtspr(SPRN_CTRLT, 0); 2181d1d0d5ffSNicholas Piggin } else { 2182d1d0d5ffSNicholas Piggin unsigned long ctrl; 2183d1d0d5ffSNicholas Piggin 2184cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2185cb2c9b27SAnton Blanchard ctrl &= ~CTRL_RUNLATCH; 2186cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2187cb2c9b27SAnton Blanchard } 2188d1d0d5ffSNicholas Piggin } 2189fe1952fcSBenjamin Herrenschmidt #endif /* CONFIG_PPC64 */ 2190f6a61680SBenjamin Herrenschmidt 2191d839088cSAnton Blanchard unsigned long arch_align_stack(unsigned long sp) 2192d839088cSAnton Blanchard { 2193d839088cSAnton Blanchard if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 2194d839088cSAnton Blanchard sp -= get_random_int() & ~PAGE_MASK; 2195d839088cSAnton Blanchard return sp & ~0xf; 2196d839088cSAnton Blanchard } 2197912f9ee2SAnton Blanchard 2198912f9ee2SAnton Blanchard static inline unsigned long brk_rnd(void) 2199912f9ee2SAnton Blanchard { 2200912f9ee2SAnton Blanchard unsigned long rnd = 0; 2201912f9ee2SAnton Blanchard 2202912f9ee2SAnton Blanchard /* 8MB for 32bit, 1GB for 64bit */ 2203912f9ee2SAnton Blanchard if (is_32bit_task()) 22045ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 2205912f9ee2SAnton Blanchard else 22065ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 2207912f9ee2SAnton Blanchard 2208912f9ee2SAnton Blanchard return rnd << PAGE_SHIFT; 2209912f9ee2SAnton Blanchard } 2210912f9ee2SAnton Blanchard 2211912f9ee2SAnton Blanchard unsigned long arch_randomize_brk(struct mm_struct *mm) 2212912f9ee2SAnton Blanchard { 22138bbde7a7SAnton Blanchard unsigned long base = mm->brk; 22148bbde7a7SAnton Blanchard unsigned long ret; 22158bbde7a7SAnton Blanchard 22164e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 22178bbde7a7SAnton Blanchard /* 22188bbde7a7SAnton Blanchard * If we are using 1TB segments and we are allowed to randomise 22198bbde7a7SAnton Blanchard * the heap, we can put it above 1TB so it is backed by a 1TB 22208bbde7a7SAnton Blanchard * segment. Otherwise the heap will be in the bottom 1TB 22218bbde7a7SAnton Blanchard * which always uses 256MB segments and this may result in a 2222caca285eSAneesh Kumar K.V * performance penalty. We don't need to worry about radix. For 2223caca285eSAneesh Kumar K.V * radix, mmu_highuser_ssize remains unchanged from 256MB. 22248bbde7a7SAnton Blanchard */ 22258bbde7a7SAnton Blanchard if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 22268bbde7a7SAnton Blanchard base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 22278bbde7a7SAnton Blanchard #endif 22288bbde7a7SAnton Blanchard 22298bbde7a7SAnton Blanchard ret = PAGE_ALIGN(base + brk_rnd()); 2230912f9ee2SAnton Blanchard 2231912f9ee2SAnton Blanchard if (ret < mm->brk) 2232912f9ee2SAnton Blanchard return mm->brk; 2233912f9ee2SAnton Blanchard 2234912f9ee2SAnton Blanchard return ret; 2235912f9ee2SAnton Blanchard } 2236501cb16dSAnton Blanchard 2237