114cf11afSPaul Mackerras /* 214cf11afSPaul Mackerras * Derived from "arch/i386/kernel/process.c" 314cf11afSPaul Mackerras * Copyright (C) 1995 Linus Torvalds 414cf11afSPaul Mackerras * 514cf11afSPaul Mackerras * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 614cf11afSPaul Mackerras * Paul Mackerras (paulus@cs.anu.edu.au) 714cf11afSPaul Mackerras * 814cf11afSPaul Mackerras * PowerPC version 914cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 1014cf11afSPaul Mackerras * 1114cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1214cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1314cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1414cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1514cf11afSPaul Mackerras */ 1614cf11afSPaul Mackerras 1714cf11afSPaul Mackerras #include <linux/errno.h> 1814cf11afSPaul Mackerras #include <linux/sched.h> 19b17b0153SIngo Molnar #include <linux/sched/debug.h> 2029930025SIngo Molnar #include <linux/sched/task.h> 2168db0cf1SIngo Molnar #include <linux/sched/task_stack.h> 2214cf11afSPaul Mackerras #include <linux/kernel.h> 2314cf11afSPaul Mackerras #include <linux/mm.h> 2414cf11afSPaul Mackerras #include <linux/smp.h> 2514cf11afSPaul Mackerras #include <linux/stddef.h> 2614cf11afSPaul Mackerras #include <linux/unistd.h> 2714cf11afSPaul Mackerras #include <linux/ptrace.h> 2814cf11afSPaul Mackerras #include <linux/slab.h> 2914cf11afSPaul Mackerras #include <linux/user.h> 3014cf11afSPaul Mackerras #include <linux/elf.h> 3114cf11afSPaul Mackerras #include <linux/prctl.h> 3214cf11afSPaul Mackerras #include <linux/init_task.h> 334b16f8e2SPaul Gortmaker #include <linux/export.h> 3414cf11afSPaul Mackerras #include <linux/kallsyms.h> 3514cf11afSPaul Mackerras #include <linux/mqueue.h> 3614cf11afSPaul Mackerras #include <linux/hardirq.h> 3706d67d54SPaul Mackerras #include <linux/utsname.h> 386794c782SSteven Rostedt #include <linux/ftrace.h> 3979741dd3SMartin Schwidefsky #include <linux/kernel_stat.h> 40d839088cSAnton Blanchard #include <linux/personality.h> 41d839088cSAnton Blanchard #include <linux/random.h> 425aae8a53SK.Prasad #include <linux/hw_breakpoint.h> 437b051f66SAnton Blanchard #include <linux/uaccess.h> 447f92bc56SDaniel Axtens #include <linux/elf-randomize.h> 4506bb53b3SRam Pai #include <linux/pkeys.h> 4614cf11afSPaul Mackerras 4714cf11afSPaul Mackerras #include <asm/pgtable.h> 4814cf11afSPaul Mackerras #include <asm/io.h> 4914cf11afSPaul Mackerras #include <asm/processor.h> 5014cf11afSPaul Mackerras #include <asm/mmu.h> 5114cf11afSPaul Mackerras #include <asm/prom.h> 5276032de8SMichael Ellerman #include <asm/machdep.h> 53c6622f63SPaul Mackerras #include <asm/time.h> 54ae3a197eSDavid Howells #include <asm/runlatch.h> 55a7f31841SArnd Bergmann #include <asm/syscalls.h> 56ae3a197eSDavid Howells #include <asm/switch_to.h> 57fb09692eSMichael Neuling #include <asm/tm.h> 58ae3a197eSDavid Howells #include <asm/debug.h> 5906d67d54SPaul Mackerras #ifdef CONFIG_PPC64 6006d67d54SPaul Mackerras #include <asm/firmware.h> 61c2e480baSMadhavan Srinivasan #include <asm/hw_irq.h> 6206d67d54SPaul Mackerras #endif 637cedd601SAnton Blanchard #include <asm/code-patching.h> 647f92bc56SDaniel Axtens #include <asm/exec.h> 655d31a96eSMichael Ellerman #include <asm/livepatch.h> 66b92a226eSKevin Hao #include <asm/cpu_has_feature.h> 670545d543SDaniel Axtens #include <asm/asm-prototypes.h> 685d31a96eSMichael Ellerman 69d6a61bfcSLuis Machado #include <linux/kprobes.h> 70d6a61bfcSLuis Machado #include <linux/kdebug.h> 7114cf11afSPaul Mackerras 728b3c34cfSMichael Neuling /* Transactional Memory debug */ 738b3c34cfSMichael Neuling #ifdef TM_DEBUG_SW 748b3c34cfSMichael Neuling #define TM_DEBUG(x...) printk(KERN_INFO x) 758b3c34cfSMichael Neuling #else 768b3c34cfSMichael Neuling #define TM_DEBUG(x...) do { } while(0) 778b3c34cfSMichael Neuling #endif 788b3c34cfSMichael Neuling 7914cf11afSPaul Mackerras extern unsigned long _get_SP(void); 8014cf11afSPaul Mackerras 81d31626f7SPaul Mackerras #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 8254820530SMichael Ellerman /* 8354820530SMichael Ellerman * Are we running in "Suspend disabled" mode? If so we have to block any 8454820530SMichael Ellerman * sigreturn that would get us into suspended state, and we also warn in some 8554820530SMichael Ellerman * other paths that we should never reach with suspend disabled. 8654820530SMichael Ellerman */ 8754820530SMichael Ellerman bool tm_suspend_disabled __ro_after_init = false; 8854820530SMichael Ellerman 89b86fd2bdSAnton Blanchard static void check_if_tm_restore_required(struct task_struct *tsk) 90d31626f7SPaul Mackerras { 91d31626f7SPaul Mackerras /* 92d31626f7SPaul Mackerras * If we are saving the current thread's registers, and the 93d31626f7SPaul Mackerras * thread is in a transactional state, set the TIF_RESTORE_TM 94d31626f7SPaul Mackerras * bit so that we know to restore the registers before 95d31626f7SPaul Mackerras * returning to userspace. 96d31626f7SPaul Mackerras */ 97d31626f7SPaul Mackerras if (tsk == current && tsk->thread.regs && 98d31626f7SPaul Mackerras MSR_TM_ACTIVE(tsk->thread.regs->msr) && 99d31626f7SPaul Mackerras !test_thread_flag(TIF_RESTORE_TM)) { 100829023dfSAnshuman Khandual tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 101d31626f7SPaul Mackerras set_thread_flag(TIF_RESTORE_TM); 102d31626f7SPaul Mackerras } 103d31626f7SPaul Mackerras } 104dc16b553SCyril Bur 105dc16b553SCyril Bur static inline bool msr_tm_active(unsigned long msr) 106dc16b553SCyril Bur { 107dc16b553SCyril Bur return MSR_TM_ACTIVE(msr); 108dc16b553SCyril Bur } 109a7771176SCyril Bur 110a7771176SCyril Bur static bool tm_active_with_fp(struct task_struct *tsk) 111a7771176SCyril Bur { 112a7771176SCyril Bur return msr_tm_active(tsk->thread.regs->msr) && 113a7771176SCyril Bur (tsk->thread.ckpt_regs.msr & MSR_FP); 114a7771176SCyril Bur } 115a7771176SCyril Bur 116a7771176SCyril Bur static bool tm_active_with_altivec(struct task_struct *tsk) 117a7771176SCyril Bur { 118a7771176SCyril Bur return msr_tm_active(tsk->thread.regs->msr) && 119a7771176SCyril Bur (tsk->thread.ckpt_regs.msr & MSR_VEC); 120a7771176SCyril Bur } 121d31626f7SPaul Mackerras #else 122dc16b553SCyril Bur static inline bool msr_tm_active(unsigned long msr) { return false; } 123b86fd2bdSAnton Blanchard static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 124a7771176SCyril Bur static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; } 125a7771176SCyril Bur static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; } 126d31626f7SPaul Mackerras #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 127d31626f7SPaul Mackerras 1283eb5d588SAnton Blanchard bool strict_msr_control; 1293eb5d588SAnton Blanchard EXPORT_SYMBOL(strict_msr_control); 1303eb5d588SAnton Blanchard 1313eb5d588SAnton Blanchard static int __init enable_strict_msr_control(char *str) 1323eb5d588SAnton Blanchard { 1333eb5d588SAnton Blanchard strict_msr_control = true; 1343eb5d588SAnton Blanchard pr_info("Enabling strict facility control\n"); 1353eb5d588SAnton Blanchard 1363eb5d588SAnton Blanchard return 0; 1373eb5d588SAnton Blanchard } 1383eb5d588SAnton Blanchard early_param("ppc_strict_facility_enable", enable_strict_msr_control); 1393eb5d588SAnton Blanchard 1403cee070aSCyril Bur unsigned long msr_check_and_set(unsigned long bits) 141a0e72cf1SAnton Blanchard { 142a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 143a0e72cf1SAnton Blanchard unsigned long newmsr; 144a0e72cf1SAnton Blanchard 145a0e72cf1SAnton Blanchard newmsr = oldmsr | bits; 146a0e72cf1SAnton Blanchard 147a0e72cf1SAnton Blanchard #ifdef CONFIG_VSX 148a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 149a0e72cf1SAnton Blanchard newmsr |= MSR_VSX; 150a0e72cf1SAnton Blanchard #endif 151a0e72cf1SAnton Blanchard 152a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 153a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 1543cee070aSCyril Bur 1553cee070aSCyril Bur return newmsr; 156a0e72cf1SAnton Blanchard } 157d1c72112SSimon Guo EXPORT_SYMBOL_GPL(msr_check_and_set); 158a0e72cf1SAnton Blanchard 1593eb5d588SAnton Blanchard void __msr_check_and_clear(unsigned long bits) 160a0e72cf1SAnton Blanchard { 161a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 162a0e72cf1SAnton Blanchard unsigned long newmsr; 163a0e72cf1SAnton Blanchard 164a0e72cf1SAnton Blanchard newmsr = oldmsr & ~bits; 165a0e72cf1SAnton Blanchard 166a0e72cf1SAnton Blanchard #ifdef CONFIG_VSX 167a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 168a0e72cf1SAnton Blanchard newmsr &= ~MSR_VSX; 169a0e72cf1SAnton Blanchard #endif 170a0e72cf1SAnton Blanchard 171a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 172a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 173a0e72cf1SAnton Blanchard } 1743eb5d588SAnton Blanchard EXPORT_SYMBOL(__msr_check_and_clear); 175a0e72cf1SAnton Blanchard 176037f0eedSKevin Hao #ifdef CONFIG_PPC_FPU 1771cdf039bSMathieu Malaterre static void __giveup_fpu(struct task_struct *tsk) 1788792468dSCyril Bur { 1798eb98037SAnton Blanchard unsigned long msr; 1808eb98037SAnton Blanchard 1818792468dSCyril Bur save_fpu(tsk); 1828eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 1838eb98037SAnton Blanchard msr &= ~MSR_FP; 1848792468dSCyril Bur #ifdef CONFIG_VSX 1858792468dSCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 1868eb98037SAnton Blanchard msr &= ~MSR_VSX; 1878792468dSCyril Bur #endif 1888eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 1898792468dSCyril Bur } 1908792468dSCyril Bur 19198da581eSAnton Blanchard void giveup_fpu(struct task_struct *tsk) 19298da581eSAnton Blanchard { 19398da581eSAnton Blanchard check_if_tm_restore_required(tsk); 19498da581eSAnton Blanchard 195a0e72cf1SAnton Blanchard msr_check_and_set(MSR_FP); 19698da581eSAnton Blanchard __giveup_fpu(tsk); 197a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP); 19898da581eSAnton Blanchard } 19998da581eSAnton Blanchard EXPORT_SYMBOL(giveup_fpu); 20098da581eSAnton Blanchard 20114cf11afSPaul Mackerras /* 20214cf11afSPaul Mackerras * Make sure the floating-point register state in the 20314cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 20414cf11afSPaul Mackerras */ 20514cf11afSPaul Mackerras void flush_fp_to_thread(struct task_struct *tsk) 20614cf11afSPaul Mackerras { 20714cf11afSPaul Mackerras if (tsk->thread.regs) { 20814cf11afSPaul Mackerras /* 20914cf11afSPaul Mackerras * We need to disable preemption here because if we didn't, 21014cf11afSPaul Mackerras * another process could get scheduled after the regs->msr 21114cf11afSPaul Mackerras * test but before we have finished saving the FP registers 21214cf11afSPaul Mackerras * to the thread_struct. That process could take over the 21314cf11afSPaul Mackerras * FPU, and then when we get scheduled again we would store 21414cf11afSPaul Mackerras * bogus values for the remaining FP registers. 21514cf11afSPaul Mackerras */ 21614cf11afSPaul Mackerras preempt_disable(); 21714cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_FP) { 21814cf11afSPaul Mackerras /* 21914cf11afSPaul Mackerras * This should only ever be called for current or 22014cf11afSPaul Mackerras * for a stopped child process. Since we save away 221af1bbc3dSAnton Blanchard * the FP register state on context switch, 22214cf11afSPaul Mackerras * there is something wrong if a stopped child appears 22314cf11afSPaul Mackerras * to still have its FP state in the CPU registers. 22414cf11afSPaul Mackerras */ 22514cf11afSPaul Mackerras BUG_ON(tsk != current); 226b86fd2bdSAnton Blanchard giveup_fpu(tsk); 22714cf11afSPaul Mackerras } 22814cf11afSPaul Mackerras preempt_enable(); 22914cf11afSPaul Mackerras } 23014cf11afSPaul Mackerras } 231de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_fp_to_thread); 23214cf11afSPaul Mackerras 23314cf11afSPaul Mackerras void enable_kernel_fp(void) 23414cf11afSPaul Mackerras { 235e909fb83SCyril Bur unsigned long cpumsr; 236e909fb83SCyril Bur 23714cf11afSPaul Mackerras WARN_ON(preemptible()); 23814cf11afSPaul Mackerras 239e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP); 240611b0e5cSAnton Blanchard 241d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 242d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 243e909fb83SCyril Bur /* 244e909fb83SCyril Bur * If a thread has already been reclaimed then the 245e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 246e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 247e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 248e909fb83SCyril Bur * checkpointed structure. 249e909fb83SCyril Bur */ 250e909fb83SCyril Bur if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 251e909fb83SCyril Bur return; 252a0e72cf1SAnton Blanchard __giveup_fpu(current); 253b86fd2bdSAnton Blanchard } 254d64d02ceSAnton Blanchard } 25514cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_fp); 25670fe3d98SCyril Bur 2576a303833SBenjamin Herrenschmidt static int restore_fp(struct task_struct *tsk) 2586a303833SBenjamin Herrenschmidt { 259a7771176SCyril Bur if (tsk->thread.load_fp || tm_active_with_fp(tsk)) { 26070fe3d98SCyril Bur load_fp_state(¤t->thread.fp_state); 26170fe3d98SCyril Bur current->thread.load_fp++; 26270fe3d98SCyril Bur return 1; 26370fe3d98SCyril Bur } 26470fe3d98SCyril Bur return 0; 26570fe3d98SCyril Bur } 26670fe3d98SCyril Bur #else 26770fe3d98SCyril Bur static int restore_fp(struct task_struct *tsk) { return 0; } 268d1e1cf2eSAnton Blanchard #endif /* CONFIG_PPC_FPU */ 26914cf11afSPaul Mackerras 27014cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 27170fe3d98SCyril Bur #define loadvec(thr) ((thr).load_vec) 27270fe3d98SCyril Bur 2736f515d84SCyril Bur static void __giveup_altivec(struct task_struct *tsk) 2746f515d84SCyril Bur { 2758eb98037SAnton Blanchard unsigned long msr; 2768eb98037SAnton Blanchard 2776f515d84SCyril Bur save_altivec(tsk); 2788eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 2798eb98037SAnton Blanchard msr &= ~MSR_VEC; 2806f515d84SCyril Bur #ifdef CONFIG_VSX 2816f515d84SCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 2828eb98037SAnton Blanchard msr &= ~MSR_VSX; 2836f515d84SCyril Bur #endif 2848eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 2856f515d84SCyril Bur } 2866f515d84SCyril Bur 28798da581eSAnton Blanchard void giveup_altivec(struct task_struct *tsk) 28898da581eSAnton Blanchard { 28998da581eSAnton Blanchard check_if_tm_restore_required(tsk); 29098da581eSAnton Blanchard 291a0e72cf1SAnton Blanchard msr_check_and_set(MSR_VEC); 29298da581eSAnton Blanchard __giveup_altivec(tsk); 293a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_VEC); 29498da581eSAnton Blanchard } 29598da581eSAnton Blanchard EXPORT_SYMBOL(giveup_altivec); 29698da581eSAnton Blanchard 29714cf11afSPaul Mackerras void enable_kernel_altivec(void) 29814cf11afSPaul Mackerras { 299e909fb83SCyril Bur unsigned long cpumsr; 300e909fb83SCyril Bur 30114cf11afSPaul Mackerras WARN_ON(preemptible()); 30214cf11afSPaul Mackerras 303e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_VEC); 304611b0e5cSAnton Blanchard 305d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 306d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 307e909fb83SCyril Bur /* 308e909fb83SCyril Bur * If a thread has already been reclaimed then the 309e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 310e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 311e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 312e909fb83SCyril Bur * checkpointed structure. 313e909fb83SCyril Bur */ 314e909fb83SCyril Bur if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 315e909fb83SCyril Bur return; 316a0e72cf1SAnton Blanchard __giveup_altivec(current); 317b86fd2bdSAnton Blanchard } 318d64d02ceSAnton Blanchard } 31914cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_altivec); 32014cf11afSPaul Mackerras 32114cf11afSPaul Mackerras /* 32214cf11afSPaul Mackerras * Make sure the VMX/Altivec register state in the 32314cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 32414cf11afSPaul Mackerras */ 32514cf11afSPaul Mackerras void flush_altivec_to_thread(struct task_struct *tsk) 32614cf11afSPaul Mackerras { 32714cf11afSPaul Mackerras if (tsk->thread.regs) { 32814cf11afSPaul Mackerras preempt_disable(); 32914cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_VEC) { 33014cf11afSPaul Mackerras BUG_ON(tsk != current); 331b86fd2bdSAnton Blanchard giveup_altivec(tsk); 33214cf11afSPaul Mackerras } 33314cf11afSPaul Mackerras preempt_enable(); 33414cf11afSPaul Mackerras } 33514cf11afSPaul Mackerras } 336de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 33770fe3d98SCyril Bur 33870fe3d98SCyril Bur static int restore_altivec(struct task_struct *tsk) 33970fe3d98SCyril Bur { 340dc16b553SCyril Bur if (cpu_has_feature(CPU_FTR_ALTIVEC) && 341a7771176SCyril Bur (tsk->thread.load_vec || tm_active_with_altivec(tsk))) { 34270fe3d98SCyril Bur load_vr_state(&tsk->thread.vr_state); 34370fe3d98SCyril Bur tsk->thread.used_vr = 1; 34470fe3d98SCyril Bur tsk->thread.load_vec++; 34570fe3d98SCyril Bur 34670fe3d98SCyril Bur return 1; 34770fe3d98SCyril Bur } 34870fe3d98SCyril Bur return 0; 34970fe3d98SCyril Bur } 35070fe3d98SCyril Bur #else 35170fe3d98SCyril Bur #define loadvec(thr) 0 35270fe3d98SCyril Bur static inline int restore_altivec(struct task_struct *tsk) { return 0; } 35314cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 35414cf11afSPaul Mackerras 355ce48b210SMichael Neuling #ifdef CONFIG_VSX 356bf6a4d5bSCyril Bur static void __giveup_vsx(struct task_struct *tsk) 357a7d623d4SAnton Blanchard { 358dc801081SBenjamin Herrenschmidt unsigned long msr = tsk->thread.regs->msr; 359dc801081SBenjamin Herrenschmidt 360dc801081SBenjamin Herrenschmidt /* 361dc801081SBenjamin Herrenschmidt * We should never be ssetting MSR_VSX without also setting 362dc801081SBenjamin Herrenschmidt * MSR_FP and MSR_VEC 363dc801081SBenjamin Herrenschmidt */ 364dc801081SBenjamin Herrenschmidt WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); 365dc801081SBenjamin Herrenschmidt 366dc801081SBenjamin Herrenschmidt /* __giveup_fpu will clear MSR_VSX */ 367dc801081SBenjamin Herrenschmidt if (msr & MSR_FP) 368a7d623d4SAnton Blanchard __giveup_fpu(tsk); 369dc801081SBenjamin Herrenschmidt if (msr & MSR_VEC) 370a7d623d4SAnton Blanchard __giveup_altivec(tsk); 371bf6a4d5bSCyril Bur } 372bf6a4d5bSCyril Bur 373bf6a4d5bSCyril Bur static void giveup_vsx(struct task_struct *tsk) 374bf6a4d5bSCyril Bur { 375bf6a4d5bSCyril Bur check_if_tm_restore_required(tsk); 376bf6a4d5bSCyril Bur 377bf6a4d5bSCyril Bur msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 378a7d623d4SAnton Blanchard __giveup_vsx(tsk); 379a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 380a7d623d4SAnton Blanchard } 381bf6a4d5bSCyril Bur 382ce48b210SMichael Neuling void enable_kernel_vsx(void) 383ce48b210SMichael Neuling { 384e909fb83SCyril Bur unsigned long cpumsr; 385e909fb83SCyril Bur 386ce48b210SMichael Neuling WARN_ON(preemptible()); 387ce48b210SMichael Neuling 388e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 389611b0e5cSAnton Blanchard 3905a69aec9SBenjamin Herrenschmidt if (current->thread.regs && 3915a69aec9SBenjamin Herrenschmidt (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { 392d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 393e909fb83SCyril Bur /* 394e909fb83SCyril Bur * If a thread has already been reclaimed then the 395e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 396e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 397e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 398e909fb83SCyril Bur * checkpointed structure. 399e909fb83SCyril Bur */ 400e909fb83SCyril Bur if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 401e909fb83SCyril Bur return; 402a0e72cf1SAnton Blanchard __giveup_vsx(current); 403611b0e5cSAnton Blanchard } 404ce48b210SMichael Neuling } 405ce48b210SMichael Neuling EXPORT_SYMBOL(enable_kernel_vsx); 406ce48b210SMichael Neuling 407ce48b210SMichael Neuling void flush_vsx_to_thread(struct task_struct *tsk) 408ce48b210SMichael Neuling { 409ce48b210SMichael Neuling if (tsk->thread.regs) { 410ce48b210SMichael Neuling preempt_disable(); 4115a69aec9SBenjamin Herrenschmidt if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { 412ce48b210SMichael Neuling BUG_ON(tsk != current); 413ce48b210SMichael Neuling giveup_vsx(tsk); 414ce48b210SMichael Neuling } 415ce48b210SMichael Neuling preempt_enable(); 416ce48b210SMichael Neuling } 417ce48b210SMichael Neuling } 418de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 41970fe3d98SCyril Bur 42070fe3d98SCyril Bur static int restore_vsx(struct task_struct *tsk) 42170fe3d98SCyril Bur { 42270fe3d98SCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) { 42370fe3d98SCyril Bur tsk->thread.used_vsr = 1; 42470fe3d98SCyril Bur return 1; 42570fe3d98SCyril Bur } 42670fe3d98SCyril Bur 42770fe3d98SCyril Bur return 0; 42870fe3d98SCyril Bur } 42970fe3d98SCyril Bur #else 43070fe3d98SCyril Bur static inline int restore_vsx(struct task_struct *tsk) { return 0; } 431ce48b210SMichael Neuling #endif /* CONFIG_VSX */ 432ce48b210SMichael Neuling 43314cf11afSPaul Mackerras #ifdef CONFIG_SPE 43498da581eSAnton Blanchard void giveup_spe(struct task_struct *tsk) 43598da581eSAnton Blanchard { 43698da581eSAnton Blanchard check_if_tm_restore_required(tsk); 43798da581eSAnton Blanchard 438a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 43998da581eSAnton Blanchard __giveup_spe(tsk); 440a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_SPE); 44198da581eSAnton Blanchard } 44298da581eSAnton Blanchard EXPORT_SYMBOL(giveup_spe); 44314cf11afSPaul Mackerras 44414cf11afSPaul Mackerras void enable_kernel_spe(void) 44514cf11afSPaul Mackerras { 44614cf11afSPaul Mackerras WARN_ON(preemptible()); 44714cf11afSPaul Mackerras 448a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 449611b0e5cSAnton Blanchard 450d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 451d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 452a0e72cf1SAnton Blanchard __giveup_spe(current); 45314cf11afSPaul Mackerras } 454d64d02ceSAnton Blanchard } 45514cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_spe); 45614cf11afSPaul Mackerras 45714cf11afSPaul Mackerras void flush_spe_to_thread(struct task_struct *tsk) 45814cf11afSPaul Mackerras { 45914cf11afSPaul Mackerras if (tsk->thread.regs) { 46014cf11afSPaul Mackerras preempt_disable(); 46114cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_SPE) { 46214cf11afSPaul Mackerras BUG_ON(tsk != current); 463685659eeSyu liu tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 4640ee6c15eSKumar Gala giveup_spe(tsk); 46514cf11afSPaul Mackerras } 46614cf11afSPaul Mackerras preempt_enable(); 46714cf11afSPaul Mackerras } 46814cf11afSPaul Mackerras } 46914cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 47014cf11afSPaul Mackerras 471c2085059SAnton Blanchard static unsigned long msr_all_available; 472c2085059SAnton Blanchard 473c2085059SAnton Blanchard static int __init init_msr_all_available(void) 474c2085059SAnton Blanchard { 475c2085059SAnton Blanchard #ifdef CONFIG_PPC_FPU 476c2085059SAnton Blanchard msr_all_available |= MSR_FP; 477c2085059SAnton Blanchard #endif 478c2085059SAnton Blanchard #ifdef CONFIG_ALTIVEC 479c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC)) 480c2085059SAnton Blanchard msr_all_available |= MSR_VEC; 481c2085059SAnton Blanchard #endif 482c2085059SAnton Blanchard #ifdef CONFIG_VSX 483c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX)) 484c2085059SAnton Blanchard msr_all_available |= MSR_VSX; 485c2085059SAnton Blanchard #endif 486c2085059SAnton Blanchard #ifdef CONFIG_SPE 487c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_SPE)) 488c2085059SAnton Blanchard msr_all_available |= MSR_SPE; 489c2085059SAnton Blanchard #endif 490c2085059SAnton Blanchard 491c2085059SAnton Blanchard return 0; 492c2085059SAnton Blanchard } 493c2085059SAnton Blanchard early_initcall(init_msr_all_available); 494c2085059SAnton Blanchard 495c2085059SAnton Blanchard void giveup_all(struct task_struct *tsk) 496c2085059SAnton Blanchard { 497c2085059SAnton Blanchard unsigned long usermsr; 498c2085059SAnton Blanchard 499c2085059SAnton Blanchard if (!tsk->thread.regs) 500c2085059SAnton Blanchard return; 501c2085059SAnton Blanchard 502c2085059SAnton Blanchard usermsr = tsk->thread.regs->msr; 503c2085059SAnton Blanchard 504c2085059SAnton Blanchard if ((usermsr & msr_all_available) == 0) 505c2085059SAnton Blanchard return; 506c2085059SAnton Blanchard 507c2085059SAnton Blanchard msr_check_and_set(msr_all_available); 508b0f16b46SCyril Bur check_if_tm_restore_required(tsk); 509c2085059SAnton Blanchard 51096c79b6bSBenjamin Herrenschmidt WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 51196c79b6bSBenjamin Herrenschmidt 512c2085059SAnton Blanchard #ifdef CONFIG_PPC_FPU 513c2085059SAnton Blanchard if (usermsr & MSR_FP) 514c2085059SAnton Blanchard __giveup_fpu(tsk); 515c2085059SAnton Blanchard #endif 516c2085059SAnton Blanchard #ifdef CONFIG_ALTIVEC 517c2085059SAnton Blanchard if (usermsr & MSR_VEC) 518c2085059SAnton Blanchard __giveup_altivec(tsk); 519c2085059SAnton Blanchard #endif 520c2085059SAnton Blanchard #ifdef CONFIG_SPE 521c2085059SAnton Blanchard if (usermsr & MSR_SPE) 522c2085059SAnton Blanchard __giveup_spe(tsk); 523c2085059SAnton Blanchard #endif 524c2085059SAnton Blanchard 525c2085059SAnton Blanchard msr_check_and_clear(msr_all_available); 526c2085059SAnton Blanchard } 527c2085059SAnton Blanchard EXPORT_SYMBOL(giveup_all); 528c2085059SAnton Blanchard 52970fe3d98SCyril Bur void restore_math(struct pt_regs *regs) 53070fe3d98SCyril Bur { 53170fe3d98SCyril Bur unsigned long msr; 53270fe3d98SCyril Bur 533dc16b553SCyril Bur if (!msr_tm_active(regs->msr) && 534dc16b553SCyril Bur !current->thread.load_fp && !loadvec(current->thread)) 53570fe3d98SCyril Bur return; 53670fe3d98SCyril Bur 53770fe3d98SCyril Bur msr = regs->msr; 53870fe3d98SCyril Bur msr_check_and_set(msr_all_available); 53970fe3d98SCyril Bur 54070fe3d98SCyril Bur /* 54170fe3d98SCyril Bur * Only reload if the bit is not set in the user MSR, the bit BEING set 54270fe3d98SCyril Bur * indicates that the registers are hot 54370fe3d98SCyril Bur */ 54470fe3d98SCyril Bur if ((!(msr & MSR_FP)) && restore_fp(current)) 54570fe3d98SCyril Bur msr |= MSR_FP | current->thread.fpexc_mode; 54670fe3d98SCyril Bur 54770fe3d98SCyril Bur if ((!(msr & MSR_VEC)) && restore_altivec(current)) 54870fe3d98SCyril Bur msr |= MSR_VEC; 54970fe3d98SCyril Bur 55070fe3d98SCyril Bur if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && 55170fe3d98SCyril Bur restore_vsx(current)) { 55270fe3d98SCyril Bur msr |= MSR_VSX; 55370fe3d98SCyril Bur } 55470fe3d98SCyril Bur 55570fe3d98SCyril Bur msr_check_and_clear(msr_all_available); 55670fe3d98SCyril Bur 55770fe3d98SCyril Bur regs->msr = msr; 55870fe3d98SCyril Bur } 55970fe3d98SCyril Bur 5601cdf039bSMathieu Malaterre static void save_all(struct task_struct *tsk) 561de2a20aaSCyril Bur { 562de2a20aaSCyril Bur unsigned long usermsr; 563de2a20aaSCyril Bur 564de2a20aaSCyril Bur if (!tsk->thread.regs) 565de2a20aaSCyril Bur return; 566de2a20aaSCyril Bur 567de2a20aaSCyril Bur usermsr = tsk->thread.regs->msr; 568de2a20aaSCyril Bur 569de2a20aaSCyril Bur if ((usermsr & msr_all_available) == 0) 570de2a20aaSCyril Bur return; 571de2a20aaSCyril Bur 572de2a20aaSCyril Bur msr_check_and_set(msr_all_available); 573de2a20aaSCyril Bur 57496c79b6bSBenjamin Herrenschmidt WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 57596c79b6bSBenjamin Herrenschmidt 576de2a20aaSCyril Bur if (usermsr & MSR_FP) 5778792468dSCyril Bur save_fpu(tsk); 578de2a20aaSCyril Bur 579de2a20aaSCyril Bur if (usermsr & MSR_VEC) 5806f515d84SCyril Bur save_altivec(tsk); 581de2a20aaSCyril Bur 582de2a20aaSCyril Bur if (usermsr & MSR_SPE) 583de2a20aaSCyril Bur __giveup_spe(tsk); 584de2a20aaSCyril Bur 585de2a20aaSCyril Bur msr_check_and_clear(msr_all_available); 586de2a20aaSCyril Bur } 587de2a20aaSCyril Bur 588579e633eSAnton Blanchard void flush_all_to_thread(struct task_struct *tsk) 589579e633eSAnton Blanchard { 590579e633eSAnton Blanchard if (tsk->thread.regs) { 591579e633eSAnton Blanchard preempt_disable(); 592579e633eSAnton Blanchard BUG_ON(tsk != current); 593de2a20aaSCyril Bur save_all(tsk); 594579e633eSAnton Blanchard 595579e633eSAnton Blanchard #ifdef CONFIG_SPE 596579e633eSAnton Blanchard if (tsk->thread.regs->msr & MSR_SPE) 597579e633eSAnton Blanchard tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 598579e633eSAnton Blanchard #endif 599579e633eSAnton Blanchard 600579e633eSAnton Blanchard preempt_enable(); 601579e633eSAnton Blanchard } 602579e633eSAnton Blanchard } 603579e633eSAnton Blanchard EXPORT_SYMBOL(flush_all_to_thread); 604579e633eSAnton Blanchard 6053bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6063bffb652SDave Kleikamp void do_send_trap(struct pt_regs *regs, unsigned long address, 60747355040SEric W. Biederman unsigned long error_code, int breakpt) 6083bffb652SDave Kleikamp { 60947355040SEric W. Biederman current->thread.trap_nr = TRAP_HWBKPT; 6103bffb652SDave Kleikamp if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 6113bffb652SDave Kleikamp 11, SIGSEGV) == NOTIFY_STOP) 6123bffb652SDave Kleikamp return; 6133bffb652SDave Kleikamp 6143bffb652SDave Kleikamp /* Deliver the signal to userspace */ 615f71dd7dcSEric W. Biederman force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ 616f71dd7dcSEric W. Biederman (void __user *)address); 6173bffb652SDave Kleikamp } 6183bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 6199422de3eSMichael Neuling void do_break (struct pt_regs *regs, unsigned long address, 620d6a61bfcSLuis Machado unsigned long error_code) 621d6a61bfcSLuis Machado { 622d6a61bfcSLuis Machado siginfo_t info; 623d6a61bfcSLuis Machado 62441ab5266SAnanth N Mavinakayanahalli current->thread.trap_nr = TRAP_HWBKPT; 625d6a61bfcSLuis Machado if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 626d6a61bfcSLuis Machado 11, SIGSEGV) == NOTIFY_STOP) 627d6a61bfcSLuis Machado return; 628d6a61bfcSLuis Machado 6299422de3eSMichael Neuling if (debugger_break_match(regs)) 630d6a61bfcSLuis Machado return; 631d6a61bfcSLuis Machado 6329422de3eSMichael Neuling /* Clear the breakpoint */ 6339422de3eSMichael Neuling hw_breakpoint_disable(); 634d6a61bfcSLuis Machado 635d6a61bfcSLuis Machado /* Deliver the signal to userspace */ 636d6a61bfcSLuis Machado info.si_signo = SIGTRAP; 637d6a61bfcSLuis Machado info.si_errno = 0; 638d6a61bfcSLuis Machado info.si_code = TRAP_HWBKPT; 639d6a61bfcSLuis Machado info.si_addr = (void __user *)address; 640d6a61bfcSLuis Machado force_sig_info(SIGTRAP, &info, current); 641d6a61bfcSLuis Machado } 6423bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 643d6a61bfcSLuis Machado 6449422de3eSMichael Neuling static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 645a2ceff5eSMichael Ellerman 6463bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6473bffb652SDave Kleikamp /* 6483bffb652SDave Kleikamp * Set the debug registers back to their default "safe" values. 6493bffb652SDave Kleikamp */ 6503bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 6513bffb652SDave Kleikamp { 65251ae8d4aSBharat Bhushan thread->debug.iac1 = thread->debug.iac2 = 0; 6533bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 65451ae8d4aSBharat Bhushan thread->debug.iac3 = thread->debug.iac4 = 0; 6553bffb652SDave Kleikamp #endif 65651ae8d4aSBharat Bhushan thread->debug.dac1 = thread->debug.dac2 = 0; 6573bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 65851ae8d4aSBharat Bhushan thread->debug.dvc1 = thread->debug.dvc2 = 0; 6593bffb652SDave Kleikamp #endif 66051ae8d4aSBharat Bhushan thread->debug.dbcr0 = 0; 6613bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 6623bffb652SDave Kleikamp /* 6633bffb652SDave Kleikamp * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 6643bffb652SDave Kleikamp */ 66551ae8d4aSBharat Bhushan thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 6663bffb652SDave Kleikamp DBCR1_IAC3US | DBCR1_IAC4US; 6673bffb652SDave Kleikamp /* 6683bffb652SDave Kleikamp * Force Data Address Compare User/Supervisor bits to be User-only 6693bffb652SDave Kleikamp * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 6703bffb652SDave Kleikamp */ 67151ae8d4aSBharat Bhushan thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 6723bffb652SDave Kleikamp #else 67351ae8d4aSBharat Bhushan thread->debug.dbcr1 = 0; 6743bffb652SDave Kleikamp #endif 6753bffb652SDave Kleikamp } 6763bffb652SDave Kleikamp 677f5f97210SScott Wood static void prime_debug_regs(struct debug_reg *debug) 6783bffb652SDave Kleikamp { 6796cecf76bSScott Wood /* 6806cecf76bSScott Wood * We could have inherited MSR_DE from userspace, since 6816cecf76bSScott Wood * it doesn't get cleared on exception entry. Make sure 6826cecf76bSScott Wood * MSR_DE is clear before we enable any debug events. 6836cecf76bSScott Wood */ 6846cecf76bSScott Wood mtmsr(mfmsr() & ~MSR_DE); 6856cecf76bSScott Wood 686f5f97210SScott Wood mtspr(SPRN_IAC1, debug->iac1); 687f5f97210SScott Wood mtspr(SPRN_IAC2, debug->iac2); 6883bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 689f5f97210SScott Wood mtspr(SPRN_IAC3, debug->iac3); 690f5f97210SScott Wood mtspr(SPRN_IAC4, debug->iac4); 6913bffb652SDave Kleikamp #endif 692f5f97210SScott Wood mtspr(SPRN_DAC1, debug->dac1); 693f5f97210SScott Wood mtspr(SPRN_DAC2, debug->dac2); 6943bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 695f5f97210SScott Wood mtspr(SPRN_DVC1, debug->dvc1); 696f5f97210SScott Wood mtspr(SPRN_DVC2, debug->dvc2); 6973bffb652SDave Kleikamp #endif 698f5f97210SScott Wood mtspr(SPRN_DBCR0, debug->dbcr0); 699f5f97210SScott Wood mtspr(SPRN_DBCR1, debug->dbcr1); 7003bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 701f5f97210SScott Wood mtspr(SPRN_DBCR2, debug->dbcr2); 7023bffb652SDave Kleikamp #endif 7033bffb652SDave Kleikamp } 7043bffb652SDave Kleikamp /* 7053bffb652SDave Kleikamp * Unless neither the old or new thread are making use of the 7063bffb652SDave Kleikamp * debug registers, set the debug registers from the values 7073bffb652SDave Kleikamp * stored in the new thread. 7083bffb652SDave Kleikamp */ 709f5f97210SScott Wood void switch_booke_debug_regs(struct debug_reg *new_debug) 7103bffb652SDave Kleikamp { 71151ae8d4aSBharat Bhushan if ((current->thread.debug.dbcr0 & DBCR0_IDM) 712f5f97210SScott Wood || (new_debug->dbcr0 & DBCR0_IDM)) 713f5f97210SScott Wood prime_debug_regs(new_debug); 7143bffb652SDave Kleikamp } 7153743c9b8SBharat Bhushan EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 7163bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 717e0780b72SK.Prasad #ifndef CONFIG_HAVE_HW_BREAKPOINT 7183bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 7193bffb652SDave Kleikamp { 7209422de3eSMichael Neuling thread->hw_brk.address = 0; 7219422de3eSMichael Neuling thread->hw_brk.type = 0; 722252988cbSNicholas Piggin if (ppc_breakpoint_available()) 723b9818c33SMichael Neuling set_breakpoint(&thread->hw_brk); 7243bffb652SDave Kleikamp } 725e0780b72SK.Prasad #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 7263bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 7273bffb652SDave Kleikamp 728172ae2e7SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 7299422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7309422de3eSMichael Neuling { 731c6c9eaceSBenjamin Herrenschmidt mtspr(SPRN_DAC1, dabr); 732221c185dSDave Kleikamp #ifdef CONFIG_PPC_47x 733221c185dSDave Kleikamp isync(); 734221c185dSDave Kleikamp #endif 7359422de3eSMichael Neuling return 0; 7369422de3eSMichael Neuling } 737c6c9eaceSBenjamin Herrenschmidt #elif defined(CONFIG_PPC_BOOK3S) 7389422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7399422de3eSMichael Neuling { 740cab0af98SMichael Ellerman mtspr(SPRN_DABR, dabr); 74182a9f16aSMichael Neuling if (cpu_has_feature(CPU_FTR_DABRX)) 7424474ef05SMichael Neuling mtspr(SPRN_DABRX, dabrx); 743cab0af98SMichael Ellerman return 0; 74414cf11afSPaul Mackerras } 7454ad8622dSChristophe Leroy #elif defined(CONFIG_PPC_8xx) 7464ad8622dSChristophe Leroy static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7474ad8622dSChristophe Leroy { 7484ad8622dSChristophe Leroy unsigned long addr = dabr & ~HW_BRK_TYPE_DABR; 7494ad8622dSChristophe Leroy unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */ 7504ad8622dSChristophe Leroy unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */ 7514ad8622dSChristophe Leroy 7524ad8622dSChristophe Leroy if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) 7534ad8622dSChristophe Leroy lctrl1 |= 0xa0000; 7544ad8622dSChristophe Leroy else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) 7554ad8622dSChristophe Leroy lctrl1 |= 0xf0000; 7564ad8622dSChristophe Leroy else if ((dabr & HW_BRK_TYPE_RDWR) == 0) 7574ad8622dSChristophe Leroy lctrl2 = 0; 7584ad8622dSChristophe Leroy 7594ad8622dSChristophe Leroy mtspr(SPRN_LCTRL2, 0); 7604ad8622dSChristophe Leroy mtspr(SPRN_CMPE, addr); 7614ad8622dSChristophe Leroy mtspr(SPRN_CMPF, addr + 4); 7624ad8622dSChristophe Leroy mtspr(SPRN_LCTRL1, lctrl1); 7634ad8622dSChristophe Leroy mtspr(SPRN_LCTRL2, lctrl2); 7644ad8622dSChristophe Leroy 7654ad8622dSChristophe Leroy return 0; 7664ad8622dSChristophe Leroy } 7679422de3eSMichael Neuling #else 7689422de3eSMichael Neuling static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 7699422de3eSMichael Neuling { 7709422de3eSMichael Neuling return -EINVAL; 7719422de3eSMichael Neuling } 7729422de3eSMichael Neuling #endif 7739422de3eSMichael Neuling 7749422de3eSMichael Neuling static inline int set_dabr(struct arch_hw_breakpoint *brk) 7759422de3eSMichael Neuling { 7769422de3eSMichael Neuling unsigned long dabr, dabrx; 7779422de3eSMichael Neuling 7789422de3eSMichael Neuling dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 7799422de3eSMichael Neuling dabrx = ((brk->type >> 3) & 0x7); 7809422de3eSMichael Neuling 7819422de3eSMichael Neuling if (ppc_md.set_dabr) 7829422de3eSMichael Neuling return ppc_md.set_dabr(dabr, dabrx); 7839422de3eSMichael Neuling 7849422de3eSMichael Neuling return __set_dabr(dabr, dabrx); 7859422de3eSMichael Neuling } 7869422de3eSMichael Neuling 787bf99de36SMichael Neuling static inline int set_dawr(struct arch_hw_breakpoint *brk) 788bf99de36SMichael Neuling { 78905d694eaSMichael Neuling unsigned long dawr, dawrx, mrd; 790bf99de36SMichael Neuling 791bf99de36SMichael Neuling dawr = brk->address; 792bf99de36SMichael Neuling 793bf99de36SMichael Neuling dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 794bf99de36SMichael Neuling << (63 - 58); //* read/write bits */ 795bf99de36SMichael Neuling dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 796bf99de36SMichael Neuling << (63 - 59); //* translate */ 797bf99de36SMichael Neuling dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 798bf99de36SMichael Neuling >> 3; //* PRIM bits */ 79905d694eaSMichael Neuling /* dawr length is stored in field MDR bits 48:53. Matches range in 80005d694eaSMichael Neuling doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 80105d694eaSMichael Neuling 0b111111=64DW. 80205d694eaSMichael Neuling brk->len is in bytes. 80305d694eaSMichael Neuling This aligns up to double word size, shifts and does the bias. 80405d694eaSMichael Neuling */ 80505d694eaSMichael Neuling mrd = ((brk->len + 7) >> 3) - 1; 80605d694eaSMichael Neuling dawrx |= (mrd & 0x3f) << (63 - 53); 807bf99de36SMichael Neuling 808bf99de36SMichael Neuling if (ppc_md.set_dawr) 809bf99de36SMichael Neuling return ppc_md.set_dawr(dawr, dawrx); 810bf99de36SMichael Neuling mtspr(SPRN_DAWR, dawr); 811bf99de36SMichael Neuling mtspr(SPRN_DAWRX, dawrx); 812bf99de36SMichael Neuling return 0; 813bf99de36SMichael Neuling } 814bf99de36SMichael Neuling 81521f58507SPaul Gortmaker void __set_breakpoint(struct arch_hw_breakpoint *brk) 8169422de3eSMichael Neuling { 81769111bacSChristoph Lameter memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); 8189422de3eSMichael Neuling 819bf99de36SMichael Neuling if (cpu_has_feature(CPU_FTR_DAWR)) 820252988cbSNicholas Piggin // Power8 or later 82104c32a51SPaul Gortmaker set_dawr(brk); 822252988cbSNicholas Piggin else if (!cpu_has_feature(CPU_FTR_ARCH_207S)) 823252988cbSNicholas Piggin // Power7 or earlier 82404c32a51SPaul Gortmaker set_dabr(brk); 825252988cbSNicholas Piggin else 826252988cbSNicholas Piggin // Shouldn't happen due to higher level checks 827252988cbSNicholas Piggin WARN_ON_ONCE(1); 8289422de3eSMichael Neuling } 82914cf11afSPaul Mackerras 83021f58507SPaul Gortmaker void set_breakpoint(struct arch_hw_breakpoint *brk) 83121f58507SPaul Gortmaker { 83221f58507SPaul Gortmaker preempt_disable(); 83321f58507SPaul Gortmaker __set_breakpoint(brk); 83421f58507SPaul Gortmaker preempt_enable(); 83521f58507SPaul Gortmaker } 83621f58507SPaul Gortmaker 837404b27d6SMichael Neuling /* Check if we have DAWR or DABR hardware */ 838404b27d6SMichael Neuling bool ppc_breakpoint_available(void) 839404b27d6SMichael Neuling { 840404b27d6SMichael Neuling if (cpu_has_feature(CPU_FTR_DAWR)) 841404b27d6SMichael Neuling return true; /* POWER8 DAWR */ 842404b27d6SMichael Neuling if (cpu_has_feature(CPU_FTR_ARCH_207S)) 843404b27d6SMichael Neuling return false; /* POWER9 with DAWR disabled */ 844404b27d6SMichael Neuling /* DABR: Everything but POWER8 and POWER9 */ 845404b27d6SMichael Neuling return true; 846404b27d6SMichael Neuling } 847404b27d6SMichael Neuling EXPORT_SYMBOL_GPL(ppc_breakpoint_available); 848404b27d6SMichael Neuling 8499422de3eSMichael Neuling static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 8509422de3eSMichael Neuling struct arch_hw_breakpoint *b) 8519422de3eSMichael Neuling { 8529422de3eSMichael Neuling if (a->address != b->address) 8539422de3eSMichael Neuling return false; 8549422de3eSMichael Neuling if (a->type != b->type) 8559422de3eSMichael Neuling return false; 8569422de3eSMichael Neuling if (a->len != b->len) 8579422de3eSMichael Neuling return false; 8589422de3eSMichael Neuling return true; 8599422de3eSMichael Neuling } 860d31626f7SPaul Mackerras 861fb09692eSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 8625d176f75SCyril Bur 8635d176f75SCyril Bur static inline bool tm_enabled(struct task_struct *tsk) 8645d176f75SCyril Bur { 8655d176f75SCyril Bur return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); 8665d176f75SCyril Bur } 8675d176f75SCyril Bur 868d31626f7SPaul Mackerras static void tm_reclaim_thread(struct thread_struct *thr, 869d31626f7SPaul Mackerras struct thread_info *ti, uint8_t cause) 870d31626f7SPaul Mackerras { 8717f821fc9SMichael Neuling /* 8727f821fc9SMichael Neuling * Use the current MSR TM suspended bit to track if we have 8737f821fc9SMichael Neuling * checkpointed state outstanding. 8747f821fc9SMichael Neuling * On signal delivery, we'd normally reclaim the checkpointed 8757f821fc9SMichael Neuling * state to obtain stack pointer (see:get_tm_stackpointer()). 8767f821fc9SMichael Neuling * This will then directly return to userspace without going 8777f821fc9SMichael Neuling * through __switch_to(). However, if the stack frame is bad, 8787f821fc9SMichael Neuling * we need to exit this thread which calls __switch_to() which 8797f821fc9SMichael Neuling * will again attempt to reclaim the already saved tm state. 8807f821fc9SMichael Neuling * Hence we need to check that we've not already reclaimed 8817f821fc9SMichael Neuling * this state. 8827f821fc9SMichael Neuling * We do this using the current MSR, rather tracking it in 8837f821fc9SMichael Neuling * some specific thread_struct bit, as it has the additional 884027dfac6SMichael Ellerman * benefit of checking for a potential TM bad thing exception. 8857f821fc9SMichael Neuling */ 8867f821fc9SMichael Neuling if (!MSR_TM_SUSPENDED(mfmsr())) 8877f821fc9SMichael Neuling return; 8887f821fc9SMichael Neuling 88991381b9cSCyril Bur giveup_all(container_of(thr, struct task_struct, thread)); 89091381b9cSCyril Bur 891eb5c3f1cSCyril Bur tm_reclaim(thr, cause); 892eb5c3f1cSCyril Bur 893f48e91e8SMichael Neuling /* 894f48e91e8SMichael Neuling * If we are in a transaction and FP is off then we can't have 895f48e91e8SMichael Neuling * used FP inside that transaction. Hence the checkpointed 896f48e91e8SMichael Neuling * state is the same as the live state. We need to copy the 897f48e91e8SMichael Neuling * live state to the checkpointed state so that when the 898f48e91e8SMichael Neuling * transaction is restored, the checkpointed state is correct 899f48e91e8SMichael Neuling * and the aborted transaction sees the correct state. We use 900f48e91e8SMichael Neuling * ckpt_regs.msr here as that's what tm_reclaim will use to 901f48e91e8SMichael Neuling * determine if it's going to write the checkpointed state or 902f48e91e8SMichael Neuling * not. So either this will write the checkpointed registers, 903f48e91e8SMichael Neuling * or reclaim will. Similarly for VMX. 904f48e91e8SMichael Neuling */ 905f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_FP) == 0) 906f48e91e8SMichael Neuling memcpy(&thr->ckfp_state, &thr->fp_state, 907f48e91e8SMichael Neuling sizeof(struct thread_fp_state)); 908f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_VEC) == 0) 909f48e91e8SMichael Neuling memcpy(&thr->ckvr_state, &thr->vr_state, 910f48e91e8SMichael Neuling sizeof(struct thread_vr_state)); 911d31626f7SPaul Mackerras } 912d31626f7SPaul Mackerras 913d31626f7SPaul Mackerras void tm_reclaim_current(uint8_t cause) 914d31626f7SPaul Mackerras { 915d31626f7SPaul Mackerras tm_enable(); 916d31626f7SPaul Mackerras tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 917d31626f7SPaul Mackerras } 918d31626f7SPaul Mackerras 919fb09692eSMichael Neuling static inline void tm_reclaim_task(struct task_struct *tsk) 920fb09692eSMichael Neuling { 921fb09692eSMichael Neuling /* We have to work out if we're switching from/to a task that's in the 922fb09692eSMichael Neuling * middle of a transaction. 923fb09692eSMichael Neuling * 924fb09692eSMichael Neuling * In switching we need to maintain a 2nd register state as 925fb09692eSMichael Neuling * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 926000ec280SCyril Bur * checkpointed (tbegin) state in ckpt_regs, ckfp_state and 927000ec280SCyril Bur * ckvr_state 928fb09692eSMichael Neuling * 929fb09692eSMichael Neuling * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 930fb09692eSMichael Neuling */ 931fb09692eSMichael Neuling struct thread_struct *thr = &tsk->thread; 932fb09692eSMichael Neuling 933fb09692eSMichael Neuling if (!thr->regs) 934fb09692eSMichael Neuling return; 935fb09692eSMichael Neuling 936fb09692eSMichael Neuling if (!MSR_TM_ACTIVE(thr->regs->msr)) 937fb09692eSMichael Neuling goto out_and_saveregs; 938fb09692eSMichael Neuling 93992fb8690SMichael Neuling WARN_ON(tm_suspend_disabled); 94092fb8690SMichael Neuling 941fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 942fb09692eSMichael Neuling "ccr=%lx, msr=%lx, trap=%lx)\n", 943fb09692eSMichael Neuling tsk->pid, thr->regs->nip, 944fb09692eSMichael Neuling thr->regs->ccr, thr->regs->msr, 945fb09692eSMichael Neuling thr->regs->trap); 946fb09692eSMichael Neuling 947d31626f7SPaul Mackerras tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 948fb09692eSMichael Neuling 949fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d complete\n", 950fb09692eSMichael Neuling tsk->pid); 951fb09692eSMichael Neuling 952fb09692eSMichael Neuling out_and_saveregs: 953fb09692eSMichael Neuling /* Always save the regs here, even if a transaction's not active. 954fb09692eSMichael Neuling * This context-switches a thread's TM info SPRs. We do it here to 955fb09692eSMichael Neuling * be consistent with the restore path (in recheckpoint) which 956fb09692eSMichael Neuling * cannot happen later in _switch(). 957fb09692eSMichael Neuling */ 958fb09692eSMichael Neuling tm_save_sprs(thr); 959fb09692eSMichael Neuling } 960fb09692eSMichael Neuling 961eb5c3f1cSCyril Bur extern void __tm_recheckpoint(struct thread_struct *thread); 962e6b8fd02SMichael Neuling 963eb5c3f1cSCyril Bur void tm_recheckpoint(struct thread_struct *thread) 964e6b8fd02SMichael Neuling { 965e6b8fd02SMichael Neuling unsigned long flags; 966e6b8fd02SMichael Neuling 9675d176f75SCyril Bur if (!(thread->regs->msr & MSR_TM)) 9685d176f75SCyril Bur return; 9695d176f75SCyril Bur 970e6b8fd02SMichael Neuling /* We really can't be interrupted here as the TEXASR registers can't 971e6b8fd02SMichael Neuling * change and later in the trecheckpoint code, we have a userspace R1. 972e6b8fd02SMichael Neuling * So let's hard disable over this region. 973e6b8fd02SMichael Neuling */ 974e6b8fd02SMichael Neuling local_irq_save(flags); 975e6b8fd02SMichael Neuling hard_irq_disable(); 976e6b8fd02SMichael Neuling 977e6b8fd02SMichael Neuling /* The TM SPRs are restored here, so that TEXASR.FS can be set 978e6b8fd02SMichael Neuling * before the trecheckpoint and no explosion occurs. 979e6b8fd02SMichael Neuling */ 980e6b8fd02SMichael Neuling tm_restore_sprs(thread); 981e6b8fd02SMichael Neuling 982eb5c3f1cSCyril Bur __tm_recheckpoint(thread); 983e6b8fd02SMichael Neuling 984e6b8fd02SMichael Neuling local_irq_restore(flags); 985e6b8fd02SMichael Neuling } 986e6b8fd02SMichael Neuling 987bc2a9408SMichael Neuling static inline void tm_recheckpoint_new_task(struct task_struct *new) 988fb09692eSMichael Neuling { 989fb09692eSMichael Neuling if (!cpu_has_feature(CPU_FTR_TM)) 990fb09692eSMichael Neuling return; 991fb09692eSMichael Neuling 992fb09692eSMichael Neuling /* Recheckpoint the registers of the thread we're about to switch to. 993fb09692eSMichael Neuling * 994fb09692eSMichael Neuling * If the task was using FP, we non-lazily reload both the original and 995fb09692eSMichael Neuling * the speculative FP register states. This is because the kernel 996fb09692eSMichael Neuling * doesn't see if/when a TM rollback occurs, so if we take an FP 997dc310669SCyril Bur * unavailable later, we are unable to determine which set of FP regs 998fb09692eSMichael Neuling * need to be restored. 999fb09692eSMichael Neuling */ 10005d176f75SCyril Bur if (!tm_enabled(new)) 1001fb09692eSMichael Neuling return; 1002fb09692eSMichael Neuling 1003e6b8fd02SMichael Neuling if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 1004fb09692eSMichael Neuling tm_restore_sprs(&new->thread); 1005fb09692eSMichael Neuling return; 1006e6b8fd02SMichael Neuling } 1007fb09692eSMichael Neuling /* Recheckpoint to restore original checkpointed register state. */ 1008eb5c3f1cSCyril Bur TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", 1009eb5c3f1cSCyril Bur new->pid, new->thread.regs->msr); 1010fb09692eSMichael Neuling 1011eb5c3f1cSCyril Bur tm_recheckpoint(&new->thread); 1012fb09692eSMichael Neuling 1013dc310669SCyril Bur /* 1014dc310669SCyril Bur * The checkpointed state has been restored but the live state has 1015dc310669SCyril Bur * not, ensure all the math functionality is turned off to trigger 1016dc310669SCyril Bur * restore_math() to reload. 1017dc310669SCyril Bur */ 1018dc310669SCyril Bur new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); 1019fb09692eSMichael Neuling 1020fb09692eSMichael Neuling TM_DEBUG("*** tm_recheckpoint of pid %d complete " 1021fb09692eSMichael Neuling "(kernel msr 0x%lx)\n", 1022fb09692eSMichael Neuling new->pid, mfmsr()); 1023fb09692eSMichael Neuling } 1024fb09692eSMichael Neuling 1025dc310669SCyril Bur static inline void __switch_to_tm(struct task_struct *prev, 1026dc310669SCyril Bur struct task_struct *new) 1027fb09692eSMichael Neuling { 1028fb09692eSMichael Neuling if (cpu_has_feature(CPU_FTR_TM)) { 10295d176f75SCyril Bur if (tm_enabled(prev) || tm_enabled(new)) 1030fb09692eSMichael Neuling tm_enable(); 10315d176f75SCyril Bur 10325d176f75SCyril Bur if (tm_enabled(prev)) { 10335d176f75SCyril Bur prev->thread.load_tm++; 1034fb09692eSMichael Neuling tm_reclaim_task(prev); 10355d176f75SCyril Bur if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) 10365d176f75SCyril Bur prev->thread.regs->msr &= ~MSR_TM; 10375d176f75SCyril Bur } 10385d176f75SCyril Bur 1039dc310669SCyril Bur tm_recheckpoint_new_task(new); 1040fb09692eSMichael Neuling } 1041fb09692eSMichael Neuling } 1042d31626f7SPaul Mackerras 1043d31626f7SPaul Mackerras /* 1044d31626f7SPaul Mackerras * This is called if we are on the way out to userspace and the 1045d31626f7SPaul Mackerras * TIF_RESTORE_TM flag is set. It checks if we need to reload 1046d31626f7SPaul Mackerras * FP and/or vector state and does so if necessary. 1047d31626f7SPaul Mackerras * If userspace is inside a transaction (whether active or 1048d31626f7SPaul Mackerras * suspended) and FP/VMX/VSX instructions have ever been enabled 1049d31626f7SPaul Mackerras * inside that transaction, then we have to keep them enabled 1050d31626f7SPaul Mackerras * and keep the FP/VMX/VSX state loaded while ever the transaction 1051d31626f7SPaul Mackerras * continues. The reason is that if we didn't, and subsequently 1052d31626f7SPaul Mackerras * got a FP/VMX/VSX unavailable interrupt inside a transaction, 1053d31626f7SPaul Mackerras * we don't know whether it's the same transaction, and thus we 1054d31626f7SPaul Mackerras * don't know which of the checkpointed state and the transactional 1055d31626f7SPaul Mackerras * state to use. 1056d31626f7SPaul Mackerras */ 1057d31626f7SPaul Mackerras void restore_tm_state(struct pt_regs *regs) 1058d31626f7SPaul Mackerras { 1059d31626f7SPaul Mackerras unsigned long msr_diff; 1060d31626f7SPaul Mackerras 1061dc310669SCyril Bur /* 1062dc310669SCyril Bur * This is the only moment we should clear TIF_RESTORE_TM as 1063dc310669SCyril Bur * it is here that ckpt_regs.msr and pt_regs.msr become the same 1064dc310669SCyril Bur * again, anything else could lead to an incorrect ckpt_msr being 1065dc310669SCyril Bur * saved and therefore incorrect signal contexts. 1066dc310669SCyril Bur */ 1067d31626f7SPaul Mackerras clear_thread_flag(TIF_RESTORE_TM); 1068d31626f7SPaul Mackerras if (!MSR_TM_ACTIVE(regs->msr)) 1069d31626f7SPaul Mackerras return; 1070d31626f7SPaul Mackerras 1071829023dfSAnshuman Khandual msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 1072d31626f7SPaul Mackerras msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 107370fe3d98SCyril Bur 1074dc16b553SCyril Bur /* Ensure that restore_math() will restore */ 1075dc16b553SCyril Bur if (msr_diff & MSR_FP) 1076dc16b553SCyril Bur current->thread.load_fp = 1; 107739715bf9SValentin Rothberg #ifdef CONFIG_ALTIVEC 1078dc16b553SCyril Bur if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) 1079dc16b553SCyril Bur current->thread.load_vec = 1; 1080dc16b553SCyril Bur #endif 108170fe3d98SCyril Bur restore_math(regs); 108270fe3d98SCyril Bur 1083d31626f7SPaul Mackerras regs->msr |= msr_diff; 1084d31626f7SPaul Mackerras } 1085d31626f7SPaul Mackerras 1086fb09692eSMichael Neuling #else 1087fb09692eSMichael Neuling #define tm_recheckpoint_new_task(new) 1088dc310669SCyril Bur #define __switch_to_tm(prev, new) 1089fb09692eSMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 10909422de3eSMichael Neuling 1091152d523eSAnton Blanchard static inline void save_sprs(struct thread_struct *t) 1092152d523eSAnton Blanchard { 1093152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 109401d7c2a2SOliver O'Halloran if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1095152d523eSAnton Blanchard t->vrsave = mfspr(SPRN_VRSAVE); 1096152d523eSAnton Blanchard #endif 1097152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1098152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) 1099152d523eSAnton Blanchard t->dscr = mfspr(SPRN_DSCR); 1100152d523eSAnton Blanchard 1101152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1102152d523eSAnton Blanchard t->bescr = mfspr(SPRN_BESCR); 1103152d523eSAnton Blanchard t->ebbhr = mfspr(SPRN_EBBHR); 1104152d523eSAnton Blanchard t->ebbrr = mfspr(SPRN_EBBRR); 1105152d523eSAnton Blanchard 1106152d523eSAnton Blanchard t->fscr = mfspr(SPRN_FSCR); 1107152d523eSAnton Blanchard 1108152d523eSAnton Blanchard /* 1109152d523eSAnton Blanchard * Note that the TAR is not available for use in the kernel. 1110152d523eSAnton Blanchard * (To provide this, the TAR should be backed up/restored on 1111152d523eSAnton Blanchard * exception entry/exit instead, and be in pt_regs. FIXME, 1112152d523eSAnton Blanchard * this should be in pt_regs anyway (for debug).) 1113152d523eSAnton Blanchard */ 1114152d523eSAnton Blanchard t->tar = mfspr(SPRN_TAR); 1115152d523eSAnton Blanchard } 1116152d523eSAnton Blanchard #endif 111706bb53b3SRam Pai 111806bb53b3SRam Pai thread_pkey_regs_save(t); 1119152d523eSAnton Blanchard } 1120152d523eSAnton Blanchard 1121152d523eSAnton Blanchard static inline void restore_sprs(struct thread_struct *old_thread, 1122152d523eSAnton Blanchard struct thread_struct *new_thread) 1123152d523eSAnton Blanchard { 1124152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 1125152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC) && 1126152d523eSAnton Blanchard old_thread->vrsave != new_thread->vrsave) 1127152d523eSAnton Blanchard mtspr(SPRN_VRSAVE, new_thread->vrsave); 1128152d523eSAnton Blanchard #endif 1129152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1130152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) { 1131152d523eSAnton Blanchard u64 dscr = get_paca()->dscr_default; 1132b57bd2deSMichael Neuling if (new_thread->dscr_inherit) 1133152d523eSAnton Blanchard dscr = new_thread->dscr; 1134152d523eSAnton Blanchard 1135152d523eSAnton Blanchard if (old_thread->dscr != dscr) 1136152d523eSAnton Blanchard mtspr(SPRN_DSCR, dscr); 1137152d523eSAnton Blanchard } 1138152d523eSAnton Blanchard 1139152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1140152d523eSAnton Blanchard if (old_thread->bescr != new_thread->bescr) 1141152d523eSAnton Blanchard mtspr(SPRN_BESCR, new_thread->bescr); 1142152d523eSAnton Blanchard if (old_thread->ebbhr != new_thread->ebbhr) 1143152d523eSAnton Blanchard mtspr(SPRN_EBBHR, new_thread->ebbhr); 1144152d523eSAnton Blanchard if (old_thread->ebbrr != new_thread->ebbrr) 1145152d523eSAnton Blanchard mtspr(SPRN_EBBRR, new_thread->ebbrr); 1146152d523eSAnton Blanchard 1147b57bd2deSMichael Neuling if (old_thread->fscr != new_thread->fscr) 1148b57bd2deSMichael Neuling mtspr(SPRN_FSCR, new_thread->fscr); 1149b57bd2deSMichael Neuling 1150152d523eSAnton Blanchard if (old_thread->tar != new_thread->tar) 1151152d523eSAnton Blanchard mtspr(SPRN_TAR, new_thread->tar); 1152152d523eSAnton Blanchard } 1153ec233edeSSukadev Bhattiprolu 11543449f191SAlastair D'Silva if (cpu_has_feature(CPU_FTR_P9_TIDR) && 1155ec233edeSSukadev Bhattiprolu old_thread->tidr != new_thread->tidr) 1156ec233edeSSukadev Bhattiprolu mtspr(SPRN_TIDR, new_thread->tidr); 1157152d523eSAnton Blanchard #endif 115806bb53b3SRam Pai 115906bb53b3SRam Pai thread_pkey_regs_restore(new_thread, old_thread); 1160152d523eSAnton Blanchard } 1161152d523eSAnton Blanchard 116207d2a628SNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 116307d2a628SNicholas Piggin #define CP_SIZE 128 116407d2a628SNicholas Piggin static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE))); 116507d2a628SNicholas Piggin #endif 116607d2a628SNicholas Piggin 116714cf11afSPaul Mackerras struct task_struct *__switch_to(struct task_struct *prev, 116814cf11afSPaul Mackerras struct task_struct *new) 116914cf11afSPaul Mackerras { 117014cf11afSPaul Mackerras struct thread_struct *new_thread, *old_thread; 117114cf11afSPaul Mackerras struct task_struct *last; 1172d6bf29b4SPeter Zijlstra #ifdef CONFIG_PPC_BOOK3S_64 1173d6bf29b4SPeter Zijlstra struct ppc64_tlb_batch *batch; 1174d6bf29b4SPeter Zijlstra #endif 117514cf11afSPaul Mackerras 1176152d523eSAnton Blanchard new_thread = &new->thread; 1177152d523eSAnton Blanchard old_thread = ¤t->thread; 1178152d523eSAnton Blanchard 11797ba5fef7SMichael Neuling WARN_ON(!irqs_disabled()); 11807ba5fef7SMichael Neuling 11814e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 118269111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1183d6bf29b4SPeter Zijlstra if (batch->active) { 1184d6bf29b4SPeter Zijlstra current_thread_info()->local_flags |= _TLF_LAZY_MMU; 1185d6bf29b4SPeter Zijlstra if (batch->index) 1186d6bf29b4SPeter Zijlstra __flush_tlb_pending(batch); 1187d6bf29b4SPeter Zijlstra batch->active = 0; 1188d6bf29b4SPeter Zijlstra } 11894e003747SMichael Ellerman #endif /* CONFIG_PPC_BOOK3S_64 */ 119006d67d54SPaul Mackerras 1191f3d885ccSAnton Blanchard #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1192f3d885ccSAnton Blanchard switch_booke_debug_regs(&new->thread.debug); 1193f3d885ccSAnton Blanchard #else 1194f3d885ccSAnton Blanchard /* 1195f3d885ccSAnton Blanchard * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 1196f3d885ccSAnton Blanchard * schedule DABR 1197f3d885ccSAnton Blanchard */ 1198f3d885ccSAnton Blanchard #ifndef CONFIG_HAVE_HW_BREAKPOINT 1199f3d885ccSAnton Blanchard if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) 1200f3d885ccSAnton Blanchard __set_breakpoint(&new->thread.hw_brk); 1201f3d885ccSAnton Blanchard #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1202f3d885ccSAnton Blanchard #endif 1203f3d885ccSAnton Blanchard 1204f3d885ccSAnton Blanchard /* 1205f3d885ccSAnton Blanchard * We need to save SPRs before treclaim/trecheckpoint as these will 1206f3d885ccSAnton Blanchard * change a number of them. 1207f3d885ccSAnton Blanchard */ 1208f3d885ccSAnton Blanchard save_sprs(&prev->thread); 1209f3d885ccSAnton Blanchard 1210f3d885ccSAnton Blanchard /* Save FPU, Altivec, VSX and SPE state */ 1211f3d885ccSAnton Blanchard giveup_all(prev); 1212f3d885ccSAnton Blanchard 1213dc310669SCyril Bur __switch_to_tm(prev, new); 1214dc310669SCyril Bur 1215e4c0fc5fSNicholas Piggin if (!radix_enabled()) { 121644387e9fSAnton Blanchard /* 1217e4c0fc5fSNicholas Piggin * We can't take a PMU exception inside _switch() since there 1218e4c0fc5fSNicholas Piggin * is a window where the kernel stack SLB and the kernel stack 1219e4c0fc5fSNicholas Piggin * are out of sync. Hard disable here. 122044387e9fSAnton Blanchard */ 122144387e9fSAnton Blanchard hard_irq_disable(); 1222e4c0fc5fSNicholas Piggin } 1223bc2a9408SMichael Neuling 122420dbe670SAnton Blanchard /* 122520dbe670SAnton Blanchard * Call restore_sprs() before calling _switch(). If we move it after 122620dbe670SAnton Blanchard * _switch() then we miss out on calling it for new tasks. The reason 122720dbe670SAnton Blanchard * for this is we manually create a stack frame for new tasks that 122820dbe670SAnton Blanchard * directly returns through ret_from_fork() or 122920dbe670SAnton Blanchard * ret_from_kernel_thread(). See copy_thread() for details. 123020dbe670SAnton Blanchard */ 1231f3d885ccSAnton Blanchard restore_sprs(old_thread, new_thread); 1232f3d885ccSAnton Blanchard 123320dbe670SAnton Blanchard last = _switch(old_thread, new_thread); 123420dbe670SAnton Blanchard 12354e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 1236d6bf29b4SPeter Zijlstra if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1237d6bf29b4SPeter Zijlstra current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 123869111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1239d6bf29b4SPeter Zijlstra batch->active = 1; 1240d6bf29b4SPeter Zijlstra } 124170fe3d98SCyril Bur 124207d2a628SNicholas Piggin if (current_thread_info()->task->thread.regs) { 124370fe3d98SCyril Bur restore_math(current_thread_info()->task->thread.regs); 124407d2a628SNicholas Piggin 124507d2a628SNicholas Piggin /* 124607d2a628SNicholas Piggin * The copy-paste buffer can only store into foreign real 124707d2a628SNicholas Piggin * addresses, so unprivileged processes can not see the 124807d2a628SNicholas Piggin * data or use it in any way unless they have foreign real 12499d2a4d71SSukadev Bhattiprolu * mappings. If the new process has the foreign real address 12509d2a4d71SSukadev Bhattiprolu * mappings, we must issue a cp_abort to clear any state and 12519d2a4d71SSukadev Bhattiprolu * prevent snooping, corruption or a covert channel. 125207d2a628SNicholas Piggin * 12539d2a4d71SSukadev Bhattiprolu * DD1 allows paste into normal system memory so we do an 12549d2a4d71SSukadev Bhattiprolu * unpaired copy, rather than cp_abort, to clear the buffer, 12559d2a4d71SSukadev Bhattiprolu * since cp_abort is quite expensive. 125607d2a628SNicholas Piggin */ 12579d2a4d71SSukadev Bhattiprolu if (current_thread_info()->task->thread.used_vas) { 12589d2a4d71SSukadev Bhattiprolu asm volatile(PPC_CP_ABORT); 12599d2a4d71SSukadev Bhattiprolu } else if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 126007d2a628SNicholas Piggin asm volatile(PPC_COPY(%0, %1) 126107d2a628SNicholas Piggin : : "r"(dummy_copy_buffer), "r"(0)); 126207d2a628SNicholas Piggin } 126307d2a628SNicholas Piggin } 12644e003747SMichael Ellerman #endif /* CONFIG_PPC_BOOK3S_64 */ 1265d6bf29b4SPeter Zijlstra 126614cf11afSPaul Mackerras return last; 126714cf11afSPaul Mackerras } 126814cf11afSPaul Mackerras 126906d67d54SPaul Mackerras static int instructions_to_print = 16; 127006d67d54SPaul Mackerras 127106d67d54SPaul Mackerras static void show_instructions(struct pt_regs *regs) 127206d67d54SPaul Mackerras { 127306d67d54SPaul Mackerras int i; 127406d67d54SPaul Mackerras unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 127506d67d54SPaul Mackerras sizeof(int)); 127606d67d54SPaul Mackerras 127706d67d54SPaul Mackerras printk("Instruction dump:"); 127806d67d54SPaul Mackerras 127906d67d54SPaul Mackerras for (i = 0; i < instructions_to_print; i++) { 128006d67d54SPaul Mackerras int instr; 128106d67d54SPaul Mackerras 128206d67d54SPaul Mackerras if (!(i % 8)) 12832ffd04deSAndrew Donnellan pr_cont("\n"); 128406d67d54SPaul Mackerras 12850de2d820SScott Wood #if !defined(CONFIG_BOOKE) 12860de2d820SScott Wood /* If executing with the IMMU off, adjust pc rather 12870de2d820SScott Wood * than print XXXXXXXX. 12880de2d820SScott Wood */ 12890de2d820SScott Wood if (!(regs->msr & MSR_IR)) 12900de2d820SScott Wood pc = (unsigned long)phys_to_virt(pc); 12910de2d820SScott Wood #endif 12920de2d820SScott Wood 129300ae36deSAnton Blanchard if (!__kernel_text_address(pc) || 12947b051f66SAnton Blanchard probe_kernel_address((unsigned int __user *)pc, instr)) { 12952ffd04deSAndrew Donnellan pr_cont("XXXXXXXX "); 129606d67d54SPaul Mackerras } else { 129706d67d54SPaul Mackerras if (regs->nip == pc) 12982ffd04deSAndrew Donnellan pr_cont("<%08x> ", instr); 129906d67d54SPaul Mackerras else 13002ffd04deSAndrew Donnellan pr_cont("%08x ", instr); 130106d67d54SPaul Mackerras } 130206d67d54SPaul Mackerras 130306d67d54SPaul Mackerras pc += sizeof(int); 130406d67d54SPaul Mackerras } 130506d67d54SPaul Mackerras 13062ffd04deSAndrew Donnellan pr_cont("\n"); 130706d67d54SPaul Mackerras } 130806d67d54SPaul Mackerras 1309801c0b2cSMichael Neuling struct regbit { 131006d67d54SPaul Mackerras unsigned long bit; 131106d67d54SPaul Mackerras const char *name; 1312801c0b2cSMichael Neuling }; 1313801c0b2cSMichael Neuling 1314801c0b2cSMichael Neuling static struct regbit msr_bits[] = { 13153bfd0c9cSAnton Blanchard #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 13163bfd0c9cSAnton Blanchard {MSR_SF, "SF"}, 13173bfd0c9cSAnton Blanchard {MSR_HV, "HV"}, 13183bfd0c9cSAnton Blanchard #endif 13193bfd0c9cSAnton Blanchard {MSR_VEC, "VEC"}, 13203bfd0c9cSAnton Blanchard {MSR_VSX, "VSX"}, 13213bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13223bfd0c9cSAnton Blanchard {MSR_CE, "CE"}, 13233bfd0c9cSAnton Blanchard #endif 132406d67d54SPaul Mackerras {MSR_EE, "EE"}, 132506d67d54SPaul Mackerras {MSR_PR, "PR"}, 132606d67d54SPaul Mackerras {MSR_FP, "FP"}, 132706d67d54SPaul Mackerras {MSR_ME, "ME"}, 13283bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13291b98326bSKumar Gala {MSR_DE, "DE"}, 13303bfd0c9cSAnton Blanchard #else 13313bfd0c9cSAnton Blanchard {MSR_SE, "SE"}, 13323bfd0c9cSAnton Blanchard {MSR_BE, "BE"}, 13333bfd0c9cSAnton Blanchard #endif 133406d67d54SPaul Mackerras {MSR_IR, "IR"}, 133506d67d54SPaul Mackerras {MSR_DR, "DR"}, 13363bfd0c9cSAnton Blanchard {MSR_PMM, "PMM"}, 13373bfd0c9cSAnton Blanchard #ifndef CONFIG_BOOKE 13383bfd0c9cSAnton Blanchard {MSR_RI, "RI"}, 13393bfd0c9cSAnton Blanchard {MSR_LE, "LE"}, 13403bfd0c9cSAnton Blanchard #endif 134106d67d54SPaul Mackerras {0, NULL} 134206d67d54SPaul Mackerras }; 134306d67d54SPaul Mackerras 1344801c0b2cSMichael Neuling static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 134506d67d54SPaul Mackerras { 1346801c0b2cSMichael Neuling const char *s = ""; 134706d67d54SPaul Mackerras 134806d67d54SPaul Mackerras for (; bits->bit; ++bits) 134906d67d54SPaul Mackerras if (val & bits->bit) { 1350db5ba5aeSMichael Ellerman pr_cont("%s%s", s, bits->name); 1351801c0b2cSMichael Neuling s = sep; 135206d67d54SPaul Mackerras } 1353801c0b2cSMichael Neuling } 1354801c0b2cSMichael Neuling 1355801c0b2cSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1356801c0b2cSMichael Neuling static struct regbit msr_tm_bits[] = { 1357801c0b2cSMichael Neuling {MSR_TS_T, "T"}, 1358801c0b2cSMichael Neuling {MSR_TS_S, "S"}, 1359801c0b2cSMichael Neuling {MSR_TM, "E"}, 1360801c0b2cSMichael Neuling {0, NULL} 1361801c0b2cSMichael Neuling }; 1362801c0b2cSMichael Neuling 1363801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) 1364801c0b2cSMichael Neuling { 1365801c0b2cSMichael Neuling /* 1366801c0b2cSMichael Neuling * This only prints something if at least one of the TM bit is set. 1367801c0b2cSMichael Neuling * Inside the TM[], the output means: 1368801c0b2cSMichael Neuling * E: Enabled (bit 32) 1369801c0b2cSMichael Neuling * S: Suspended (bit 33) 1370801c0b2cSMichael Neuling * T: Transactional (bit 34) 1371801c0b2cSMichael Neuling */ 1372801c0b2cSMichael Neuling if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1373db5ba5aeSMichael Ellerman pr_cont(",TM["); 1374801c0b2cSMichael Neuling print_bits(val, msr_tm_bits, ""); 1375db5ba5aeSMichael Ellerman pr_cont("]"); 1376801c0b2cSMichael Neuling } 1377801c0b2cSMichael Neuling } 1378801c0b2cSMichael Neuling #else 1379801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) {} 1380801c0b2cSMichael Neuling #endif 1381801c0b2cSMichael Neuling 1382801c0b2cSMichael Neuling static void print_msr_bits(unsigned long val) 1383801c0b2cSMichael Neuling { 1384db5ba5aeSMichael Ellerman pr_cont("<"); 1385801c0b2cSMichael Neuling print_bits(val, msr_bits, ","); 1386801c0b2cSMichael Neuling print_tm_bits(val); 1387db5ba5aeSMichael Ellerman pr_cont(">"); 138806d67d54SPaul Mackerras } 138906d67d54SPaul Mackerras 139006d67d54SPaul Mackerras #ifdef CONFIG_PPC64 1391f6f7dde3Santon@samba.org #define REG "%016lx" 139206d67d54SPaul Mackerras #define REGS_PER_LINE 4 139306d67d54SPaul Mackerras #define LAST_VOLATILE 13 139406d67d54SPaul Mackerras #else 1395f6f7dde3Santon@samba.org #define REG "%08lx" 139606d67d54SPaul Mackerras #define REGS_PER_LINE 8 139706d67d54SPaul Mackerras #define LAST_VOLATILE 12 139806d67d54SPaul Mackerras #endif 139906d67d54SPaul Mackerras 140014cf11afSPaul Mackerras void show_regs(struct pt_regs * regs) 140114cf11afSPaul Mackerras { 140214cf11afSPaul Mackerras int i, trap; 140314cf11afSPaul Mackerras 1404a43cb95dSTejun Heo show_regs_print_info(KERN_DEFAULT); 1405a43cb95dSTejun Heo 140606d67d54SPaul Mackerras printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 140706d67d54SPaul Mackerras regs->nip, regs->link, regs->ctr); 1408182dc9c7SMichael Ellerman printk("REGS: %px TRAP: %04lx %s (%s)\n", 140996b644bdSSerge E. Hallyn regs, regs->trap, print_tainted(), init_utsname()->release); 141006d67d54SPaul Mackerras printk("MSR: "REG" ", regs->msr); 1411801c0b2cSMichael Neuling print_msr_bits(regs->msr); 1412f6fc73fbSMichael Ellerman pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 141314cf11afSPaul Mackerras trap = TRAP(regs); 14142271db20SBenjamin Herrenschmidt if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 14157dae865fSMichael Ellerman pr_cont("CFAR: "REG" ", regs->orig_gpr3); 1416c5400649SAnton Blanchard if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1417ba28c9aaSKumar Gala #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 14187dae865fSMichael Ellerman pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 141914170789SKumar Gala #else 14207dae865fSMichael Ellerman pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 14219db8bcfdSAnton Blanchard #endif 14229db8bcfdSAnton Blanchard #ifdef CONFIG_PPC64 14233130a7bbSNicholas Piggin pr_cont("IRQMASK: %lx ", regs->softe); 14249db8bcfdSAnton Blanchard #endif 14259db8bcfdSAnton Blanchard #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 14266d888d1aSAnton Blanchard if (MSR_TM_ACTIVE(regs->msr)) 14277dae865fSMichael Ellerman pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 142814170789SKumar Gala #endif 142914cf11afSPaul Mackerras 143014cf11afSPaul Mackerras for (i = 0; i < 32; i++) { 143106d67d54SPaul Mackerras if ((i % REGS_PER_LINE) == 0) 14327dae865fSMichael Ellerman pr_cont("\nGPR%02d: ", i); 14337dae865fSMichael Ellerman pr_cont(REG " ", regs->gpr[i]); 143406d67d54SPaul Mackerras if (i == LAST_VOLATILE && !FULL_REGS(regs)) 143514cf11afSPaul Mackerras break; 143614cf11afSPaul Mackerras } 14377dae865fSMichael Ellerman pr_cont("\n"); 143814cf11afSPaul Mackerras #ifdef CONFIG_KALLSYMS 143914cf11afSPaul Mackerras /* 144014cf11afSPaul Mackerras * Lookup NIP late so we have the best change of getting the 144114cf11afSPaul Mackerras * above info out without failing 144214cf11afSPaul Mackerras */ 1443058c78f4SBenjamin Herrenschmidt printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1444058c78f4SBenjamin Herrenschmidt printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 144514cf11afSPaul Mackerras #endif 144614cf11afSPaul Mackerras show_stack(current, (unsigned long *) regs->gpr[1]); 144706d67d54SPaul Mackerras if (!user_mode(regs)) 144806d67d54SPaul Mackerras show_instructions(regs); 144914cf11afSPaul Mackerras } 145014cf11afSPaul Mackerras 145114cf11afSPaul Mackerras void flush_thread(void) 145214cf11afSPaul Mackerras { 1453e0780b72SK.Prasad #ifdef CONFIG_HAVE_HW_BREAKPOINT 14545aae8a53SK.Prasad flush_ptrace_hw_breakpoint(current); 1455e0780b72SK.Prasad #else /* CONFIG_HAVE_HW_BREAKPOINT */ 14563bffb652SDave Kleikamp set_debug_reg_defaults(¤t->thread); 1457e0780b72SK.Prasad #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 145814cf11afSPaul Mackerras } 145914cf11afSPaul Mackerras 14609d2a4d71SSukadev Bhattiprolu int set_thread_uses_vas(void) 14619d2a4d71SSukadev Bhattiprolu { 14629d2a4d71SSukadev Bhattiprolu #ifdef CONFIG_PPC_BOOK3S_64 14639d2a4d71SSukadev Bhattiprolu if (!cpu_has_feature(CPU_FTR_ARCH_300)) 14649d2a4d71SSukadev Bhattiprolu return -EINVAL; 14659d2a4d71SSukadev Bhattiprolu 14669d2a4d71SSukadev Bhattiprolu current->thread.used_vas = 1; 14679d2a4d71SSukadev Bhattiprolu 14689d2a4d71SSukadev Bhattiprolu /* 14699d2a4d71SSukadev Bhattiprolu * Even a process that has no foreign real address mapping can use 14709d2a4d71SSukadev Bhattiprolu * an unpaired COPY instruction (to no real effect). Issue CP_ABORT 14719d2a4d71SSukadev Bhattiprolu * to clear any pending COPY and prevent a covert channel. 14729d2a4d71SSukadev Bhattiprolu * 14739d2a4d71SSukadev Bhattiprolu * __switch_to() will issue CP_ABORT on future context switches. 14749d2a4d71SSukadev Bhattiprolu */ 14759d2a4d71SSukadev Bhattiprolu asm volatile(PPC_CP_ABORT); 14769d2a4d71SSukadev Bhattiprolu 14779d2a4d71SSukadev Bhattiprolu #endif /* CONFIG_PPC_BOOK3S_64 */ 14789d2a4d71SSukadev Bhattiprolu return 0; 14799d2a4d71SSukadev Bhattiprolu } 14809d2a4d71SSukadev Bhattiprolu 1481ec233edeSSukadev Bhattiprolu #ifdef CONFIG_PPC64 1482*71cc64a8SAlastair D'Silva /** 1483*71cc64a8SAlastair D'Silva * Assign a TIDR (thread ID) for task @t and set it in the thread 1484ec233edeSSukadev Bhattiprolu * structure. For now, we only support setting TIDR for 'current' task. 1485*71cc64a8SAlastair D'Silva * 1486*71cc64a8SAlastair D'Silva * Since the TID value is a truncated form of it PID, it is possible 1487*71cc64a8SAlastair D'Silva * (but unlikely) for 2 threads to have the same TID. In the unlikely event 1488*71cc64a8SAlastair D'Silva * that 2 threads share the same TID and are waiting, one of the following 1489*71cc64a8SAlastair D'Silva * cases will happen: 1490*71cc64a8SAlastair D'Silva * 1491*71cc64a8SAlastair D'Silva * 1. The correct thread is running, the wrong thread is not 1492*71cc64a8SAlastair D'Silva * In this situation, the correct thread is woken and proceeds to pass it's 1493*71cc64a8SAlastair D'Silva * condition check. 1494*71cc64a8SAlastair D'Silva * 1495*71cc64a8SAlastair D'Silva * 2. Neither threads are running 1496*71cc64a8SAlastair D'Silva * In this situation, neither thread will be woken. When scheduled, the waiting 1497*71cc64a8SAlastair D'Silva * threads will execute either a wait, which will return immediately, followed 1498*71cc64a8SAlastair D'Silva * by a condition check, which will pass for the correct thread and fail 1499*71cc64a8SAlastair D'Silva * for the wrong thread, or they will execute the condition check immediately. 1500*71cc64a8SAlastair D'Silva * 1501*71cc64a8SAlastair D'Silva * 3. The wrong thread is running, the correct thread is not 1502*71cc64a8SAlastair D'Silva * The wrong thread will be woken, but will fail it's condition check and 1503*71cc64a8SAlastair D'Silva * re-execute wait. The correct thread, when scheduled, will execute either 1504*71cc64a8SAlastair D'Silva * it's condition check (which will pass), or wait, which returns immediately 1505*71cc64a8SAlastair D'Silva * when called the first time after the thread is scheduled, followed by it's 1506*71cc64a8SAlastair D'Silva * condition check (which will pass). 1507*71cc64a8SAlastair D'Silva * 1508*71cc64a8SAlastair D'Silva * 4. Both threads are running 1509*71cc64a8SAlastair D'Silva * Both threads will be woken. The wrong thread will fail it's condition check 1510*71cc64a8SAlastair D'Silva * and execute another wait, while the correct thread will pass it's condition 1511*71cc64a8SAlastair D'Silva * check. 1512*71cc64a8SAlastair D'Silva * 1513*71cc64a8SAlastair D'Silva * @t: the task to set the thread ID for 1514ec233edeSSukadev Bhattiprolu */ 1515ec233edeSSukadev Bhattiprolu int set_thread_tidr(struct task_struct *t) 1516ec233edeSSukadev Bhattiprolu { 15173449f191SAlastair D'Silva if (!cpu_has_feature(CPU_FTR_P9_TIDR)) 1518ec233edeSSukadev Bhattiprolu return -EINVAL; 1519ec233edeSSukadev Bhattiprolu 1520ec233edeSSukadev Bhattiprolu if (t != current) 1521ec233edeSSukadev Bhattiprolu return -EINVAL; 1522ec233edeSSukadev Bhattiprolu 15237e4d4233SVaibhav Jain if (t->thread.tidr) 15247e4d4233SVaibhav Jain return 0; 15257e4d4233SVaibhav Jain 1526*71cc64a8SAlastair D'Silva t->thread.tidr = (u16)task_pid_nr(t); 1527ec233edeSSukadev Bhattiprolu mtspr(SPRN_TIDR, t->thread.tidr); 1528ec233edeSSukadev Bhattiprolu 1529ec233edeSSukadev Bhattiprolu return 0; 1530ec233edeSSukadev Bhattiprolu } 1531b1db5513SChristophe Lombard EXPORT_SYMBOL_GPL(set_thread_tidr); 1532ec233edeSSukadev Bhattiprolu 1533ec233edeSSukadev Bhattiprolu #endif /* CONFIG_PPC64 */ 1534ec233edeSSukadev Bhattiprolu 153514cf11afSPaul Mackerras void 153614cf11afSPaul Mackerras release_thread(struct task_struct *t) 153714cf11afSPaul Mackerras { 153814cf11afSPaul Mackerras } 153914cf11afSPaul Mackerras 154014cf11afSPaul Mackerras /* 154155ccf3feSSuresh Siddha * this gets called so that we can store coprocessor state into memory and 154255ccf3feSSuresh Siddha * copy the current task into the new thread. 154314cf11afSPaul Mackerras */ 154455ccf3feSSuresh Siddha int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 154514cf11afSPaul Mackerras { 1546579e633eSAnton Blanchard flush_all_to_thread(src); 1547621b5060SMichael Neuling /* 1548621b5060SMichael Neuling * Flush TM state out so we can copy it. __switch_to_tm() does this 1549621b5060SMichael Neuling * flush but it removes the checkpointed state from the current CPU and 1550621b5060SMichael Neuling * transitions the CPU out of TM mode. Hence we need to call 1551621b5060SMichael Neuling * tm_recheckpoint_new_task() (on the same task) to restore the 1552621b5060SMichael Neuling * checkpointed state back and the TM mode. 15535d176f75SCyril Bur * 15545d176f75SCyril Bur * Can't pass dst because it isn't ready. Doesn't matter, passing 15555d176f75SCyril Bur * dst is only important for __switch_to() 1556621b5060SMichael Neuling */ 1557dc310669SCyril Bur __switch_to_tm(src, src); 1558330a1eb7SMichael Ellerman 155955ccf3feSSuresh Siddha *dst = *src; 1560330a1eb7SMichael Ellerman 1561330a1eb7SMichael Ellerman clear_task_ebb(dst); 1562330a1eb7SMichael Ellerman 156355ccf3feSSuresh Siddha return 0; 156414cf11afSPaul Mackerras } 156514cf11afSPaul Mackerras 1566cec15488SMichael Ellerman static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1567cec15488SMichael Ellerman { 15684e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 1569cec15488SMichael Ellerman unsigned long sp_vsid; 1570cec15488SMichael Ellerman unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1571cec15488SMichael Ellerman 1572caca285eSAneesh Kumar K.V if (radix_enabled()) 1573caca285eSAneesh Kumar K.V return; 1574caca285eSAneesh Kumar K.V 1575cec15488SMichael Ellerman if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1576cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1577cec15488SMichael Ellerman << SLB_VSID_SHIFT_1T; 1578cec15488SMichael Ellerman else 1579cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1580cec15488SMichael Ellerman << SLB_VSID_SHIFT; 1581cec15488SMichael Ellerman sp_vsid |= SLB_VSID_KERNEL | llp; 1582cec15488SMichael Ellerman p->thread.ksp_vsid = sp_vsid; 1583cec15488SMichael Ellerman #endif 1584cec15488SMichael Ellerman } 1585cec15488SMichael Ellerman 158614cf11afSPaul Mackerras /* 158714cf11afSPaul Mackerras * Copy a thread.. 158814cf11afSPaul Mackerras */ 1589efcac658SAlexey Kardashevskiy 15906eca8933SAlex Dowad /* 15916eca8933SAlex Dowad * Copy architecture-specific thread state 15926eca8933SAlex Dowad */ 15936f2c55b8SAlexey Dobriyan int copy_thread(unsigned long clone_flags, unsigned long usp, 15946eca8933SAlex Dowad unsigned long kthread_arg, struct task_struct *p) 159514cf11afSPaul Mackerras { 159614cf11afSPaul Mackerras struct pt_regs *childregs, *kregs; 159714cf11afSPaul Mackerras extern void ret_from_fork(void); 159858254e10SAl Viro extern void ret_from_kernel_thread(void); 159958254e10SAl Viro void (*f)(void); 16000cec6fd1SAl Viro unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 16015d31a96eSMichael Ellerman struct thread_info *ti = task_thread_info(p); 16025d31a96eSMichael Ellerman 16035d31a96eSMichael Ellerman klp_init_thread_info(ti); 160414cf11afSPaul Mackerras 160514cf11afSPaul Mackerras /* Copy registers */ 160614cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 160714cf11afSPaul Mackerras childregs = (struct pt_regs *) sp; 1608ab75819dSAl Viro if (unlikely(p->flags & PF_KTHREAD)) { 16096eca8933SAlex Dowad /* kernel thread */ 161058254e10SAl Viro memset(childregs, 0, sizeof(struct pt_regs)); 161114cf11afSPaul Mackerras childregs->gpr[1] = sp + sizeof(struct pt_regs); 16127cedd601SAnton Blanchard /* function */ 16137cedd601SAnton Blanchard if (usp) 16147cedd601SAnton Blanchard childregs->gpr[14] = ppc_function_entry((void *)usp); 161558254e10SAl Viro #ifdef CONFIG_PPC64 1616b5e2fc1cSAl Viro clear_tsk_thread_flag(p, TIF_32BIT); 1617c2e480baSMadhavan Srinivasan childregs->softe = IRQS_ENABLED; 161806d67d54SPaul Mackerras #endif 16196eca8933SAlex Dowad childregs->gpr[15] = kthread_arg; 162014cf11afSPaul Mackerras p->thread.regs = NULL; /* no user register state */ 1621138d1ce8SAl Viro ti->flags |= _TIF_RESTOREALL; 162258254e10SAl Viro f = ret_from_kernel_thread; 162314cf11afSPaul Mackerras } else { 16246eca8933SAlex Dowad /* user thread */ 1625afa86fc4SAl Viro struct pt_regs *regs = current_pt_regs(); 162658254e10SAl Viro CHECK_FULL_REGS(regs); 162758254e10SAl Viro *childregs = *regs; 1628ea516b11SAl Viro if (usp) 162914cf11afSPaul Mackerras childregs->gpr[1] = usp; 163014cf11afSPaul Mackerras p->thread.regs = childregs; 163158254e10SAl Viro childregs->gpr[3] = 0; /* Result from fork() */ 163206d67d54SPaul Mackerras if (clone_flags & CLONE_SETTLS) { 163306d67d54SPaul Mackerras #ifdef CONFIG_PPC64 16349904b005SDenis Kirjanov if (!is_32bit_task()) 163506d67d54SPaul Mackerras childregs->gpr[13] = childregs->gpr[6]; 163606d67d54SPaul Mackerras else 163706d67d54SPaul Mackerras #endif 163814cf11afSPaul Mackerras childregs->gpr[2] = childregs->gpr[6]; 163914cf11afSPaul Mackerras } 164058254e10SAl Viro 164158254e10SAl Viro f = ret_from_fork; 164206d67d54SPaul Mackerras } 1643d272f667SCyril Bur childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); 164414cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 164514cf11afSPaul Mackerras 164614cf11afSPaul Mackerras /* 164714cf11afSPaul Mackerras * The way this works is that at some point in the future 164814cf11afSPaul Mackerras * some task will call _switch to switch to the new task. 164914cf11afSPaul Mackerras * That will pop off the stack frame created below and start 165014cf11afSPaul Mackerras * the new task running at ret_from_fork. The new task will 165114cf11afSPaul Mackerras * do some house keeping and then return from the fork or clone 165214cf11afSPaul Mackerras * system call, using the stack frame created above. 165314cf11afSPaul Mackerras */ 1654af945cf4SLi Zhong ((unsigned long *)sp)[0] = 0; 165514cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 165614cf11afSPaul Mackerras kregs = (struct pt_regs *) sp; 165714cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 165814cf11afSPaul Mackerras p->thread.ksp = sp; 1659cbc9565eSBenjamin Herrenschmidt #ifdef CONFIG_PPC32 166085218827SKumar Gala p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 166185218827SKumar Gala _ALIGN_UP(sizeof(struct thread_info), 16); 1662cbc9565eSBenjamin Herrenschmidt #endif 166328d170abSOleg Nesterov #ifdef CONFIG_HAVE_HW_BREAKPOINT 166428d170abSOleg Nesterov p->thread.ptrace_bps[0] = NULL; 166528d170abSOleg Nesterov #endif 166628d170abSOleg Nesterov 166718461960SPaul Mackerras p->thread.fp_save_area = NULL; 166818461960SPaul Mackerras #ifdef CONFIG_ALTIVEC 166918461960SPaul Mackerras p->thread.vr_save_area = NULL; 167018461960SPaul Mackerras #endif 167118461960SPaul Mackerras 1672cec15488SMichael Ellerman setup_ksp_vsid(p, sp); 167306d67d54SPaul Mackerras 1674efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64 1675efcac658SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_DSCR)) { 16761021cb26SAnton Blanchard p->thread.dscr_inherit = current->thread.dscr_inherit; 1677db1231dcSAnton Blanchard p->thread.dscr = mfspr(SPRN_DSCR); 1678efcac658SAlexey Kardashevskiy } 167992779245SHaren Myneni if (cpu_has_feature(CPU_FTR_HAS_PPR)) 168092779245SHaren Myneni p->thread.ppr = INIT_PPR; 1681ec233edeSSukadev Bhattiprolu 1682ec233edeSSukadev Bhattiprolu p->thread.tidr = 0; 1683efcac658SAlexey Kardashevskiy #endif 16847cedd601SAnton Blanchard kregs->nip = ppc_function_entry(f); 168514cf11afSPaul Mackerras return 0; 168614cf11afSPaul Mackerras } 168714cf11afSPaul Mackerras 168814cf11afSPaul Mackerras /* 168914cf11afSPaul Mackerras * Set up a thread for executing a new program 169014cf11afSPaul Mackerras */ 169106d67d54SPaul Mackerras void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 169214cf11afSPaul Mackerras { 169390eac727SMichael Ellerman #ifdef CONFIG_PPC64 169490eac727SMichael Ellerman unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 169590eac727SMichael Ellerman #endif 169690eac727SMichael Ellerman 169706d67d54SPaul Mackerras /* 169806d67d54SPaul Mackerras * If we exec out of a kernel thread then thread.regs will not be 169906d67d54SPaul Mackerras * set. Do it now. 170006d67d54SPaul Mackerras */ 170106d67d54SPaul Mackerras if (!current->thread.regs) { 17020cec6fd1SAl Viro struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 17030cec6fd1SAl Viro current->thread.regs = regs - 1; 170406d67d54SPaul Mackerras } 170506d67d54SPaul Mackerras 17068e96a87cSCyril Bur #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 17078e96a87cSCyril Bur /* 17088e96a87cSCyril Bur * Clear any transactional state, we're exec()ing. The cause is 17098e96a87cSCyril Bur * not important as there will never be a recheckpoint so it's not 17108e96a87cSCyril Bur * user visible. 17118e96a87cSCyril Bur */ 17128e96a87cSCyril Bur if (MSR_TM_SUSPENDED(mfmsr())) 17138e96a87cSCyril Bur tm_reclaim_current(0); 17148e96a87cSCyril Bur #endif 17158e96a87cSCyril Bur 171614cf11afSPaul Mackerras memset(regs->gpr, 0, sizeof(regs->gpr)); 171714cf11afSPaul Mackerras regs->ctr = 0; 171814cf11afSPaul Mackerras regs->link = 0; 171914cf11afSPaul Mackerras regs->xer = 0; 172014cf11afSPaul Mackerras regs->ccr = 0; 172114cf11afSPaul Mackerras regs->gpr[1] = sp; 172206d67d54SPaul Mackerras 1723474f8196SRoland McGrath /* 1724474f8196SRoland McGrath * We have just cleared all the nonvolatile GPRs, so make 1725474f8196SRoland McGrath * FULL_REGS(regs) return true. This is necessary to allow 1726474f8196SRoland McGrath * ptrace to examine the thread immediately after exec. 1727474f8196SRoland McGrath */ 1728474f8196SRoland McGrath regs->trap &= ~1UL; 1729474f8196SRoland McGrath 173006d67d54SPaul Mackerras #ifdef CONFIG_PPC32 173106d67d54SPaul Mackerras regs->mq = 0; 173206d67d54SPaul Mackerras regs->nip = start; 173314cf11afSPaul Mackerras regs->msr = MSR_USER; 173406d67d54SPaul Mackerras #else 17359904b005SDenis Kirjanov if (!is_32bit_task()) { 173694af3abfSRusty Russell unsigned long entry; 173706d67d54SPaul Mackerras 173894af3abfSRusty Russell if (is_elf2_task()) { 173994af3abfSRusty Russell /* Look ma, no function descriptors! */ 174094af3abfSRusty Russell entry = start; 174194af3abfSRusty Russell 174294af3abfSRusty Russell /* 174394af3abfSRusty Russell * Ulrich says: 174494af3abfSRusty Russell * The latest iteration of the ABI requires that when 174594af3abfSRusty Russell * calling a function (at its global entry point), 174694af3abfSRusty Russell * the caller must ensure r12 holds the entry point 174794af3abfSRusty Russell * address (so that the function can quickly 174894af3abfSRusty Russell * establish addressability). 174994af3abfSRusty Russell */ 175094af3abfSRusty Russell regs->gpr[12] = start; 175194af3abfSRusty Russell /* Make sure that's restored on entry to userspace. */ 175294af3abfSRusty Russell set_thread_flag(TIF_RESTOREALL); 175394af3abfSRusty Russell } else { 175494af3abfSRusty Russell unsigned long toc; 175594af3abfSRusty Russell 175694af3abfSRusty Russell /* start is a relocated pointer to the function 175794af3abfSRusty Russell * descriptor for the elf _start routine. The first 175894af3abfSRusty Russell * entry in the function descriptor is the entry 175994af3abfSRusty Russell * address of _start and the second entry is the TOC 176094af3abfSRusty Russell * value we need to use. 176106d67d54SPaul Mackerras */ 176206d67d54SPaul Mackerras __get_user(entry, (unsigned long __user *)start); 176306d67d54SPaul Mackerras __get_user(toc, (unsigned long __user *)start+1); 176406d67d54SPaul Mackerras 176506d67d54SPaul Mackerras /* Check whether the e_entry function descriptor entries 176606d67d54SPaul Mackerras * need to be relocated before we can use them. 176706d67d54SPaul Mackerras */ 176806d67d54SPaul Mackerras if (load_addr != 0) { 176906d67d54SPaul Mackerras entry += load_addr; 177006d67d54SPaul Mackerras toc += load_addr; 177106d67d54SPaul Mackerras } 177206d67d54SPaul Mackerras regs->gpr[2] = toc; 177394af3abfSRusty Russell } 177494af3abfSRusty Russell regs->nip = entry; 177506d67d54SPaul Mackerras regs->msr = MSR_USER64; 1776d4bf9a78SStephen Rothwell } else { 1777d4bf9a78SStephen Rothwell regs->nip = start; 1778d4bf9a78SStephen Rothwell regs->gpr[2] = 0; 1779d4bf9a78SStephen Rothwell regs->msr = MSR_USER32; 178006d67d54SPaul Mackerras } 178106d67d54SPaul Mackerras #endif 1782ce48b210SMichael Neuling #ifdef CONFIG_VSX 1783ce48b210SMichael Neuling current->thread.used_vsr = 0; 1784ce48b210SMichael Neuling #endif 17851195892cSBreno Leitao current->thread.load_fp = 0; 1786de79f7b9SPaul Mackerras memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 178718461960SPaul Mackerras current->thread.fp_save_area = NULL; 178814cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 1789de79f7b9SPaul Mackerras memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1790de79f7b9SPaul Mackerras current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 179118461960SPaul Mackerras current->thread.vr_save_area = NULL; 179214cf11afSPaul Mackerras current->thread.vrsave = 0; 179314cf11afSPaul Mackerras current->thread.used_vr = 0; 17941195892cSBreno Leitao current->thread.load_vec = 0; 179514cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 179614cf11afSPaul Mackerras #ifdef CONFIG_SPE 179714cf11afSPaul Mackerras memset(current->thread.evr, 0, sizeof(current->thread.evr)); 179814cf11afSPaul Mackerras current->thread.acc = 0; 179914cf11afSPaul Mackerras current->thread.spefscr = 0; 180014cf11afSPaul Mackerras current->thread.used_spe = 0; 180114cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 1802bc2a9408SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1803bc2a9408SMichael Neuling current->thread.tm_tfhar = 0; 1804bc2a9408SMichael Neuling current->thread.tm_texasr = 0; 1805bc2a9408SMichael Neuling current->thread.tm_tfiar = 0; 18067f22ced4SBreno Leitao current->thread.load_tm = 0; 1807bc2a9408SMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 180806bb53b3SRam Pai 180906bb53b3SRam Pai thread_pkey_regs_init(¤t->thread); 181014cf11afSPaul Mackerras } 1811e1802b06SAnton Blanchard EXPORT_SYMBOL(start_thread); 181214cf11afSPaul Mackerras 181314cf11afSPaul Mackerras #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 181414cf11afSPaul Mackerras | PR_FP_EXC_RES | PR_FP_EXC_INV) 181514cf11afSPaul Mackerras 181614cf11afSPaul Mackerras int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 181714cf11afSPaul Mackerras { 181814cf11afSPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 181914cf11afSPaul Mackerras 182014cf11afSPaul Mackerras /* This is a bit hairy. If we are an SPE enabled processor 182114cf11afSPaul Mackerras * (have embedded fp) we store the IEEE exception enable flags in 182214cf11afSPaul Mackerras * fpexc_mode. fpexc_mode is also used for setting FP exception 182314cf11afSPaul Mackerras * mode (asyn, precise, disabled) for 'Classic' FP. */ 182414cf11afSPaul Mackerras if (val & PR_FP_EXC_SW_ENABLE) { 182514cf11afSPaul Mackerras #ifdef CONFIG_SPE 18265e14d21eSKumar Gala if (cpu_has_feature(CPU_FTR_SPE)) { 1827640e9225SJoseph Myers /* 1828640e9225SJoseph Myers * When the sticky exception bits are set 1829640e9225SJoseph Myers * directly by userspace, it must call prctl 1830640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1831640e9225SJoseph Myers * in the existing prctl settings) or 1832640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1833640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1834640e9225SJoseph Myers * saving and restoring the whole 1835640e9225SJoseph Myers * floating-point environment need to do so 1836640e9225SJoseph Myers * anyway to restore the prctl settings from 1837640e9225SJoseph Myers * the saved environment. 1838640e9225SJoseph Myers */ 1839640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 184014cf11afSPaul Mackerras tsk->thread.fpexc_mode = val & 184114cf11afSPaul Mackerras (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 184206d67d54SPaul Mackerras return 0; 18435e14d21eSKumar Gala } else { 18445e14d21eSKumar Gala return -EINVAL; 18455e14d21eSKumar Gala } 184614cf11afSPaul Mackerras #else 184714cf11afSPaul Mackerras return -EINVAL; 184814cf11afSPaul Mackerras #endif 184906d67d54SPaul Mackerras } 185006d67d54SPaul Mackerras 185114cf11afSPaul Mackerras /* on a CONFIG_SPE this does not hurt us. The bits that 185214cf11afSPaul Mackerras * __pack_fe01 use do not overlap with bits used for 185314cf11afSPaul Mackerras * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 185414cf11afSPaul Mackerras * on CONFIG_SPE implementations are reserved so writing to 185514cf11afSPaul Mackerras * them does not change anything */ 185614cf11afSPaul Mackerras if (val > PR_FP_EXC_PRECISE) 185714cf11afSPaul Mackerras return -EINVAL; 185814cf11afSPaul Mackerras tsk->thread.fpexc_mode = __pack_fe01(val); 185914cf11afSPaul Mackerras if (regs != NULL && (regs->msr & MSR_FP) != 0) 186014cf11afSPaul Mackerras regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 186114cf11afSPaul Mackerras | tsk->thread.fpexc_mode; 186214cf11afSPaul Mackerras return 0; 186314cf11afSPaul Mackerras } 186414cf11afSPaul Mackerras 186514cf11afSPaul Mackerras int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 186614cf11afSPaul Mackerras { 186714cf11afSPaul Mackerras unsigned int val; 186814cf11afSPaul Mackerras 186914cf11afSPaul Mackerras if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 187014cf11afSPaul Mackerras #ifdef CONFIG_SPE 1871640e9225SJoseph Myers if (cpu_has_feature(CPU_FTR_SPE)) { 1872640e9225SJoseph Myers /* 1873640e9225SJoseph Myers * When the sticky exception bits are set 1874640e9225SJoseph Myers * directly by userspace, it must call prctl 1875640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1876640e9225SJoseph Myers * in the existing prctl settings) or 1877640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1878640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1879640e9225SJoseph Myers * saving and restoring the whole 1880640e9225SJoseph Myers * floating-point environment need to do so 1881640e9225SJoseph Myers * anyway to restore the prctl settings from 1882640e9225SJoseph Myers * the saved environment. 1883640e9225SJoseph Myers */ 1884640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 188514cf11afSPaul Mackerras val = tsk->thread.fpexc_mode; 1886640e9225SJoseph Myers } else 18875e14d21eSKumar Gala return -EINVAL; 188814cf11afSPaul Mackerras #else 188914cf11afSPaul Mackerras return -EINVAL; 189014cf11afSPaul Mackerras #endif 189114cf11afSPaul Mackerras else 189214cf11afSPaul Mackerras val = __unpack_fe01(tsk->thread.fpexc_mode); 189314cf11afSPaul Mackerras return put_user(val, (unsigned int __user *) adr); 189414cf11afSPaul Mackerras } 189514cf11afSPaul Mackerras 1896fab5db97SPaul Mackerras int set_endian(struct task_struct *tsk, unsigned int val) 1897fab5db97SPaul Mackerras { 1898fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1899fab5db97SPaul Mackerras 1900fab5db97SPaul Mackerras if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1901fab5db97SPaul Mackerras (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1902fab5db97SPaul Mackerras return -EINVAL; 1903fab5db97SPaul Mackerras 1904fab5db97SPaul Mackerras if (regs == NULL) 1905fab5db97SPaul Mackerras return -EINVAL; 1906fab5db97SPaul Mackerras 1907fab5db97SPaul Mackerras if (val == PR_ENDIAN_BIG) 1908fab5db97SPaul Mackerras regs->msr &= ~MSR_LE; 1909fab5db97SPaul Mackerras else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1910fab5db97SPaul Mackerras regs->msr |= MSR_LE; 1911fab5db97SPaul Mackerras else 1912fab5db97SPaul Mackerras return -EINVAL; 1913fab5db97SPaul Mackerras 1914fab5db97SPaul Mackerras return 0; 1915fab5db97SPaul Mackerras } 1916fab5db97SPaul Mackerras 1917fab5db97SPaul Mackerras int get_endian(struct task_struct *tsk, unsigned long adr) 1918fab5db97SPaul Mackerras { 1919fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1920fab5db97SPaul Mackerras unsigned int val; 1921fab5db97SPaul Mackerras 1922fab5db97SPaul Mackerras if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1923fab5db97SPaul Mackerras !cpu_has_feature(CPU_FTR_REAL_LE)) 1924fab5db97SPaul Mackerras return -EINVAL; 1925fab5db97SPaul Mackerras 1926fab5db97SPaul Mackerras if (regs == NULL) 1927fab5db97SPaul Mackerras return -EINVAL; 1928fab5db97SPaul Mackerras 1929fab5db97SPaul Mackerras if (regs->msr & MSR_LE) { 1930fab5db97SPaul Mackerras if (cpu_has_feature(CPU_FTR_REAL_LE)) 1931fab5db97SPaul Mackerras val = PR_ENDIAN_LITTLE; 1932fab5db97SPaul Mackerras else 1933fab5db97SPaul Mackerras val = PR_ENDIAN_PPC_LITTLE; 1934fab5db97SPaul Mackerras } else 1935fab5db97SPaul Mackerras val = PR_ENDIAN_BIG; 1936fab5db97SPaul Mackerras 1937fab5db97SPaul Mackerras return put_user(val, (unsigned int __user *)adr); 1938fab5db97SPaul Mackerras } 1939fab5db97SPaul Mackerras 1940e9370ae1SPaul Mackerras int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1941e9370ae1SPaul Mackerras { 1942e9370ae1SPaul Mackerras tsk->thread.align_ctl = val; 1943e9370ae1SPaul Mackerras return 0; 1944e9370ae1SPaul Mackerras } 1945e9370ae1SPaul Mackerras 1946e9370ae1SPaul Mackerras int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1947e9370ae1SPaul Mackerras { 1948e9370ae1SPaul Mackerras return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1949e9370ae1SPaul Mackerras } 1950e9370ae1SPaul Mackerras 1951bb72c481SPaul Mackerras static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1952bb72c481SPaul Mackerras unsigned long nbytes) 1953bb72c481SPaul Mackerras { 1954bb72c481SPaul Mackerras unsigned long stack_page; 1955bb72c481SPaul Mackerras unsigned long cpu = task_cpu(p); 1956bb72c481SPaul Mackerras 1957bb72c481SPaul Mackerras /* 1958bb72c481SPaul Mackerras * Avoid crashing if the stack has overflowed and corrupted 1959bb72c481SPaul Mackerras * task_cpu(p), which is in the thread_info struct. 1960bb72c481SPaul Mackerras */ 1961bb72c481SPaul Mackerras if (cpu < NR_CPUS && cpu_possible(cpu)) { 1962bb72c481SPaul Mackerras stack_page = (unsigned long) hardirq_ctx[cpu]; 1963bb72c481SPaul Mackerras if (sp >= stack_page + sizeof(struct thread_struct) 1964bb72c481SPaul Mackerras && sp <= stack_page + THREAD_SIZE - nbytes) 1965bb72c481SPaul Mackerras return 1; 1966bb72c481SPaul Mackerras 1967bb72c481SPaul Mackerras stack_page = (unsigned long) softirq_ctx[cpu]; 1968bb72c481SPaul Mackerras if (sp >= stack_page + sizeof(struct thread_struct) 1969bb72c481SPaul Mackerras && sp <= stack_page + THREAD_SIZE - nbytes) 1970bb72c481SPaul Mackerras return 1; 1971bb72c481SPaul Mackerras } 1972bb72c481SPaul Mackerras return 0; 1973bb72c481SPaul Mackerras } 1974bb72c481SPaul Mackerras 19752f25194dSAnton Blanchard int validate_sp(unsigned long sp, struct task_struct *p, 197614cf11afSPaul Mackerras unsigned long nbytes) 197714cf11afSPaul Mackerras { 19780cec6fd1SAl Viro unsigned long stack_page = (unsigned long)task_stack_page(p); 197914cf11afSPaul Mackerras 198014cf11afSPaul Mackerras if (sp >= stack_page + sizeof(struct thread_struct) 198114cf11afSPaul Mackerras && sp <= stack_page + THREAD_SIZE - nbytes) 198214cf11afSPaul Mackerras return 1; 198314cf11afSPaul Mackerras 1984bb72c481SPaul Mackerras return valid_irq_stack(sp, p, nbytes); 198514cf11afSPaul Mackerras } 198614cf11afSPaul Mackerras 19872f25194dSAnton Blanchard EXPORT_SYMBOL(validate_sp); 19882f25194dSAnton Blanchard 198906d67d54SPaul Mackerras unsigned long get_wchan(struct task_struct *p) 199006d67d54SPaul Mackerras { 199106d67d54SPaul Mackerras unsigned long ip, sp; 199206d67d54SPaul Mackerras int count = 0; 199306d67d54SPaul Mackerras 199406d67d54SPaul Mackerras if (!p || p == current || p->state == TASK_RUNNING) 199506d67d54SPaul Mackerras return 0; 199606d67d54SPaul Mackerras 199706d67d54SPaul Mackerras sp = p->thread.ksp; 1998ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 199906d67d54SPaul Mackerras return 0; 200006d67d54SPaul Mackerras 200106d67d54SPaul Mackerras do { 200206d67d54SPaul Mackerras sp = *(unsigned long *)sp; 20034ca360f3SKautuk Consul if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) || 20044ca360f3SKautuk Consul p->state == TASK_RUNNING) 200506d67d54SPaul Mackerras return 0; 200606d67d54SPaul Mackerras if (count > 0) { 2007ec2b36b9SBenjamin Herrenschmidt ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 200806d67d54SPaul Mackerras if (!in_sched_functions(ip)) 200906d67d54SPaul Mackerras return ip; 201006d67d54SPaul Mackerras } 201106d67d54SPaul Mackerras } while (count++ < 16); 201206d67d54SPaul Mackerras return 0; 201306d67d54SPaul Mackerras } 201406d67d54SPaul Mackerras 2015c4d04be1SJohannes Berg static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 201614cf11afSPaul Mackerras 201714cf11afSPaul Mackerras void show_stack(struct task_struct *tsk, unsigned long *stack) 201814cf11afSPaul Mackerras { 201906d67d54SPaul Mackerras unsigned long sp, ip, lr, newsp; 202014cf11afSPaul Mackerras int count = 0; 202106d67d54SPaul Mackerras int firstframe = 1; 20226794c782SSteven Rostedt #ifdef CONFIG_FUNCTION_GRAPH_TRACER 20236794c782SSteven Rostedt int curr_frame = current->curr_ret_stack; 20246794c782SSteven Rostedt extern void return_to_handler(void); 20259135c3ccSSteven Rostedt unsigned long rth = (unsigned long)return_to_handler; 20266794c782SSteven Rostedt #endif 202714cf11afSPaul Mackerras 202814cf11afSPaul Mackerras sp = (unsigned long) stack; 202914cf11afSPaul Mackerras if (tsk == NULL) 203014cf11afSPaul Mackerras tsk = current; 203114cf11afSPaul Mackerras if (sp == 0) { 203214cf11afSPaul Mackerras if (tsk == current) 2033acf620ecSAnton Blanchard sp = current_stack_pointer(); 203414cf11afSPaul Mackerras else 203514cf11afSPaul Mackerras sp = tsk->thread.ksp; 203614cf11afSPaul Mackerras } 203714cf11afSPaul Mackerras 203806d67d54SPaul Mackerras lr = 0; 203906d67d54SPaul Mackerras printk("Call Trace:\n"); 204014cf11afSPaul Mackerras do { 2041ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 204206d67d54SPaul Mackerras return; 204306d67d54SPaul Mackerras 204406d67d54SPaul Mackerras stack = (unsigned long *) sp; 204506d67d54SPaul Mackerras newsp = stack[0]; 2046ec2b36b9SBenjamin Herrenschmidt ip = stack[STACK_FRAME_LR_SAVE]; 204706d67d54SPaul Mackerras if (!firstframe || ip != lr) { 2048058c78f4SBenjamin Herrenschmidt printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 20496794c782SSteven Rostedt #ifdef CONFIG_FUNCTION_GRAPH_TRACER 20507d56c65aSAnton Blanchard if ((ip == rth) && curr_frame >= 0) { 20519a1f490fSMichael Ellerman pr_cont(" (%pS)", 20526794c782SSteven Rostedt (void *)current->ret_stack[curr_frame].ret); 20536794c782SSteven Rostedt curr_frame--; 20546794c782SSteven Rostedt } 20556794c782SSteven Rostedt #endif 205606d67d54SPaul Mackerras if (firstframe) 20579a1f490fSMichael Ellerman pr_cont(" (unreliable)"); 20589a1f490fSMichael Ellerman pr_cont("\n"); 205914cf11afSPaul Mackerras } 206006d67d54SPaul Mackerras firstframe = 0; 206106d67d54SPaul Mackerras 206206d67d54SPaul Mackerras /* 206306d67d54SPaul Mackerras * See if this is an exception frame. 206406d67d54SPaul Mackerras * We look for the "regshere" marker in the current frame. 206506d67d54SPaul Mackerras */ 2066ec2b36b9SBenjamin Herrenschmidt if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 2067ec2b36b9SBenjamin Herrenschmidt && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 206806d67d54SPaul Mackerras struct pt_regs *regs = (struct pt_regs *) 206906d67d54SPaul Mackerras (sp + STACK_FRAME_OVERHEAD); 207006d67d54SPaul Mackerras lr = regs->link; 20719be9be2eSPaul Mackerras printk("--- interrupt: %lx at %pS\n LR = %pS\n", 2072058c78f4SBenjamin Herrenschmidt regs->trap, (void *)regs->nip, (void *)lr); 207306d67d54SPaul Mackerras firstframe = 1; 207414cf11afSPaul Mackerras } 207506d67d54SPaul Mackerras 207606d67d54SPaul Mackerras sp = newsp; 207706d67d54SPaul Mackerras } while (count++ < kstack_depth_to_print); 207806d67d54SPaul Mackerras } 207906d67d54SPaul Mackerras 2080cb2c9b27SAnton Blanchard #ifdef CONFIG_PPC64 2081fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 20820e37739bSMichael Ellerman void notrace __ppc64_runlatch_on(void) 2083cb2c9b27SAnton Blanchard { 2084fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2085d1d0d5ffSNicholas Piggin 2086d1d0d5ffSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2087d1d0d5ffSNicholas Piggin /* 2088d1d0d5ffSNicholas Piggin * Least significant bit (RUN) is the only writable bit of 2089d1d0d5ffSNicholas Piggin * the CTRL register, so we can avoid mfspr. 2.06 is not the 2090d1d0d5ffSNicholas Piggin * earliest ISA where this is the case, but it's convenient. 2091d1d0d5ffSNicholas Piggin */ 2092d1d0d5ffSNicholas Piggin mtspr(SPRN_CTRLT, CTRL_RUNLATCH); 2093d1d0d5ffSNicholas Piggin } else { 2094cb2c9b27SAnton Blanchard unsigned long ctrl; 2095cb2c9b27SAnton Blanchard 2096d1d0d5ffSNicholas Piggin /* 2097d1d0d5ffSNicholas Piggin * Some architectures (e.g., Cell) have writable fields other 2098d1d0d5ffSNicholas Piggin * than RUN, so do the read-modify-write. 2099d1d0d5ffSNicholas Piggin */ 2100cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2101cb2c9b27SAnton Blanchard ctrl |= CTRL_RUNLATCH; 2102cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2103d1d0d5ffSNicholas Piggin } 2104cb2c9b27SAnton Blanchard 2105fae2e0fbSBenjamin Herrenschmidt ti->local_flags |= _TLF_RUNLATCH; 2106cb2c9b27SAnton Blanchard } 2107cb2c9b27SAnton Blanchard 2108fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 21090e37739bSMichael Ellerman void notrace __ppc64_runlatch_off(void) 2110cb2c9b27SAnton Blanchard { 2111fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2112cb2c9b27SAnton Blanchard 2113fae2e0fbSBenjamin Herrenschmidt ti->local_flags &= ~_TLF_RUNLATCH; 2114cb2c9b27SAnton Blanchard 2115d1d0d5ffSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2116d1d0d5ffSNicholas Piggin mtspr(SPRN_CTRLT, 0); 2117d1d0d5ffSNicholas Piggin } else { 2118d1d0d5ffSNicholas Piggin unsigned long ctrl; 2119d1d0d5ffSNicholas Piggin 2120cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2121cb2c9b27SAnton Blanchard ctrl &= ~CTRL_RUNLATCH; 2122cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2123cb2c9b27SAnton Blanchard } 2124d1d0d5ffSNicholas Piggin } 2125fe1952fcSBenjamin Herrenschmidt #endif /* CONFIG_PPC64 */ 2126f6a61680SBenjamin Herrenschmidt 2127d839088cSAnton Blanchard unsigned long arch_align_stack(unsigned long sp) 2128d839088cSAnton Blanchard { 2129d839088cSAnton Blanchard if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 2130d839088cSAnton Blanchard sp -= get_random_int() & ~PAGE_MASK; 2131d839088cSAnton Blanchard return sp & ~0xf; 2132d839088cSAnton Blanchard } 2133912f9ee2SAnton Blanchard 2134912f9ee2SAnton Blanchard static inline unsigned long brk_rnd(void) 2135912f9ee2SAnton Blanchard { 2136912f9ee2SAnton Blanchard unsigned long rnd = 0; 2137912f9ee2SAnton Blanchard 2138912f9ee2SAnton Blanchard /* 8MB for 32bit, 1GB for 64bit */ 2139912f9ee2SAnton Blanchard if (is_32bit_task()) 21405ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 2141912f9ee2SAnton Blanchard else 21425ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 2143912f9ee2SAnton Blanchard 2144912f9ee2SAnton Blanchard return rnd << PAGE_SHIFT; 2145912f9ee2SAnton Blanchard } 2146912f9ee2SAnton Blanchard 2147912f9ee2SAnton Blanchard unsigned long arch_randomize_brk(struct mm_struct *mm) 2148912f9ee2SAnton Blanchard { 21498bbde7a7SAnton Blanchard unsigned long base = mm->brk; 21508bbde7a7SAnton Blanchard unsigned long ret; 21518bbde7a7SAnton Blanchard 21524e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 21538bbde7a7SAnton Blanchard /* 21548bbde7a7SAnton Blanchard * If we are using 1TB segments and we are allowed to randomise 21558bbde7a7SAnton Blanchard * the heap, we can put it above 1TB so it is backed by a 1TB 21568bbde7a7SAnton Blanchard * segment. Otherwise the heap will be in the bottom 1TB 21578bbde7a7SAnton Blanchard * which always uses 256MB segments and this may result in a 2158caca285eSAneesh Kumar K.V * performance penalty. We don't need to worry about radix. For 2159caca285eSAneesh Kumar K.V * radix, mmu_highuser_ssize remains unchanged from 256MB. 21608bbde7a7SAnton Blanchard */ 21618bbde7a7SAnton Blanchard if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 21628bbde7a7SAnton Blanchard base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 21638bbde7a7SAnton Blanchard #endif 21648bbde7a7SAnton Blanchard 21658bbde7a7SAnton Blanchard ret = PAGE_ALIGN(base + brk_rnd()); 2166912f9ee2SAnton Blanchard 2167912f9ee2SAnton Blanchard if (ret < mm->brk) 2168912f9ee2SAnton Blanchard return mm->brk; 2169912f9ee2SAnton Blanchard 2170912f9ee2SAnton Blanchard return ret; 2171912f9ee2SAnton Blanchard } 2172501cb16dSAnton Blanchard 2173