12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 214cf11afSPaul Mackerras /* 314cf11afSPaul Mackerras * Derived from "arch/i386/kernel/process.c" 414cf11afSPaul Mackerras * Copyright (C) 1995 Linus Torvalds 514cf11afSPaul Mackerras * 614cf11afSPaul Mackerras * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 714cf11afSPaul Mackerras * Paul Mackerras (paulus@cs.anu.edu.au) 814cf11afSPaul Mackerras * 914cf11afSPaul Mackerras * PowerPC version 1014cf11afSPaul Mackerras * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 1114cf11afSPaul Mackerras */ 1214cf11afSPaul Mackerras 1314cf11afSPaul Mackerras #include <linux/errno.h> 1414cf11afSPaul Mackerras #include <linux/sched.h> 15b17b0153SIngo Molnar #include <linux/sched/debug.h> 1629930025SIngo Molnar #include <linux/sched/task.h> 1768db0cf1SIngo Molnar #include <linux/sched/task_stack.h> 1814cf11afSPaul Mackerras #include <linux/kernel.h> 1914cf11afSPaul Mackerras #include <linux/mm.h> 2014cf11afSPaul Mackerras #include <linux/smp.h> 2114cf11afSPaul Mackerras #include <linux/stddef.h> 2214cf11afSPaul Mackerras #include <linux/unistd.h> 2314cf11afSPaul Mackerras #include <linux/ptrace.h> 2414cf11afSPaul Mackerras #include <linux/slab.h> 2514cf11afSPaul Mackerras #include <linux/user.h> 2614cf11afSPaul Mackerras #include <linux/elf.h> 2714cf11afSPaul Mackerras #include <linux/prctl.h> 2814cf11afSPaul Mackerras #include <linux/init_task.h> 294b16f8e2SPaul Gortmaker #include <linux/export.h> 3014cf11afSPaul Mackerras #include <linux/kallsyms.h> 3114cf11afSPaul Mackerras #include <linux/mqueue.h> 3214cf11afSPaul Mackerras #include <linux/hardirq.h> 3306d67d54SPaul Mackerras #include <linux/utsname.h> 346794c782SSteven Rostedt #include <linux/ftrace.h> 3579741dd3SMartin Schwidefsky #include <linux/kernel_stat.h> 36d839088cSAnton Blanchard #include <linux/personality.h> 37d839088cSAnton Blanchard #include <linux/random.h> 385aae8a53SK.Prasad #include <linux/hw_breakpoint.h> 397b051f66SAnton Blanchard #include <linux/uaccess.h> 407f92bc56SDaniel Axtens #include <linux/elf-randomize.h> 4106bb53b3SRam Pai #include <linux/pkeys.h> 42fb2d9505SChristophe Leroy #include <linux/seq_buf.h> 4314cf11afSPaul Mackerras 44*3a96570fSNicholas Piggin #include <asm/interrupt.h> 4514cf11afSPaul Mackerras #include <asm/io.h> 4614cf11afSPaul Mackerras #include <asm/processor.h> 4714cf11afSPaul Mackerras #include <asm/mmu.h> 4814cf11afSPaul Mackerras #include <asm/prom.h> 4976032de8SMichael Ellerman #include <asm/machdep.h> 50c6622f63SPaul Mackerras #include <asm/time.h> 51ae3a197eSDavid Howells #include <asm/runlatch.h> 52a7f31841SArnd Bergmann #include <asm/syscalls.h> 53ae3a197eSDavid Howells #include <asm/switch_to.h> 54fb09692eSMichael Neuling #include <asm/tm.h> 55ae3a197eSDavid Howells #include <asm/debug.h> 5606d67d54SPaul Mackerras #ifdef CONFIG_PPC64 5706d67d54SPaul Mackerras #include <asm/firmware.h> 58c2e480baSMadhavan Srinivasan #include <asm/hw_irq.h> 5906d67d54SPaul Mackerras #endif 607cedd601SAnton Blanchard #include <asm/code-patching.h> 617f92bc56SDaniel Axtens #include <asm/exec.h> 625d31a96eSMichael Ellerman #include <asm/livepatch.h> 63b92a226eSKevin Hao #include <asm/cpu_has_feature.h> 640545d543SDaniel Axtens #include <asm/asm-prototypes.h> 65c9386bfdSChristophe Leroy #include <asm/stacktrace.h> 66c1fe190cSMichael Neuling #include <asm/hw_breakpoint.h> 675d31a96eSMichael Ellerman 68d6a61bfcSLuis Machado #include <linux/kprobes.h> 69d6a61bfcSLuis Machado #include <linux/kdebug.h> 7014cf11afSPaul Mackerras 718b3c34cfSMichael Neuling /* Transactional Memory debug */ 728b3c34cfSMichael Neuling #ifdef TM_DEBUG_SW 738b3c34cfSMichael Neuling #define TM_DEBUG(x...) printk(KERN_INFO x) 748b3c34cfSMichael Neuling #else 758b3c34cfSMichael Neuling #define TM_DEBUG(x...) do { } while(0) 768b3c34cfSMichael Neuling #endif 778b3c34cfSMichael Neuling 7814cf11afSPaul Mackerras extern unsigned long _get_SP(void); 7914cf11afSPaul Mackerras 80d31626f7SPaul Mackerras #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 8154820530SMichael Ellerman /* 8254820530SMichael Ellerman * Are we running in "Suspend disabled" mode? If so we have to block any 8354820530SMichael Ellerman * sigreturn that would get us into suspended state, and we also warn in some 8454820530SMichael Ellerman * other paths that we should never reach with suspend disabled. 8554820530SMichael Ellerman */ 8654820530SMichael Ellerman bool tm_suspend_disabled __ro_after_init = false; 8754820530SMichael Ellerman 88b86fd2bdSAnton Blanchard static void check_if_tm_restore_required(struct task_struct *tsk) 89d31626f7SPaul Mackerras { 90d31626f7SPaul Mackerras /* 91d31626f7SPaul Mackerras * If we are saving the current thread's registers, and the 92d31626f7SPaul Mackerras * thread is in a transactional state, set the TIF_RESTORE_TM 93d31626f7SPaul Mackerras * bit so that we know to restore the registers before 94d31626f7SPaul Mackerras * returning to userspace. 95d31626f7SPaul Mackerras */ 96d31626f7SPaul Mackerras if (tsk == current && tsk->thread.regs && 97d31626f7SPaul Mackerras MSR_TM_ACTIVE(tsk->thread.regs->msr) && 98d31626f7SPaul Mackerras !test_thread_flag(TIF_RESTORE_TM)) { 99829023dfSAnshuman Khandual tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 100d31626f7SPaul Mackerras set_thread_flag(TIF_RESTORE_TM); 101d31626f7SPaul Mackerras } 102d31626f7SPaul Mackerras } 103dc16b553SCyril Bur 104d31626f7SPaul Mackerras #else 105b86fd2bdSAnton Blanchard static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 106d31626f7SPaul Mackerras #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 107d31626f7SPaul Mackerras 1083eb5d588SAnton Blanchard bool strict_msr_control; 1093eb5d588SAnton Blanchard EXPORT_SYMBOL(strict_msr_control); 1103eb5d588SAnton Blanchard 1113eb5d588SAnton Blanchard static int __init enable_strict_msr_control(char *str) 1123eb5d588SAnton Blanchard { 1133eb5d588SAnton Blanchard strict_msr_control = true; 1143eb5d588SAnton Blanchard pr_info("Enabling strict facility control\n"); 1153eb5d588SAnton Blanchard 1163eb5d588SAnton Blanchard return 0; 1173eb5d588SAnton Blanchard } 1183eb5d588SAnton Blanchard early_param("ppc_strict_facility_enable", enable_strict_msr_control); 1193eb5d588SAnton Blanchard 120e2b36d59SNicholas Piggin /* notrace because it's called by restore_math */ 121e2b36d59SNicholas Piggin unsigned long notrace msr_check_and_set(unsigned long bits) 122a0e72cf1SAnton Blanchard { 123a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 124a0e72cf1SAnton Blanchard unsigned long newmsr; 125a0e72cf1SAnton Blanchard 126a0e72cf1SAnton Blanchard newmsr = oldmsr | bits; 127a0e72cf1SAnton Blanchard 128a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 129a0e72cf1SAnton Blanchard newmsr |= MSR_VSX; 130a0e72cf1SAnton Blanchard 131a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 132a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 1333cee070aSCyril Bur 1343cee070aSCyril Bur return newmsr; 135a0e72cf1SAnton Blanchard } 136d1c72112SSimon Guo EXPORT_SYMBOL_GPL(msr_check_and_set); 137a0e72cf1SAnton Blanchard 138e2b36d59SNicholas Piggin /* notrace because it's called by restore_math */ 139e2b36d59SNicholas Piggin void notrace __msr_check_and_clear(unsigned long bits) 140a0e72cf1SAnton Blanchard { 141a0e72cf1SAnton Blanchard unsigned long oldmsr = mfmsr(); 142a0e72cf1SAnton Blanchard unsigned long newmsr; 143a0e72cf1SAnton Blanchard 144a0e72cf1SAnton Blanchard newmsr = oldmsr & ~bits; 145a0e72cf1SAnton Blanchard 146a0e72cf1SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 147a0e72cf1SAnton Blanchard newmsr &= ~MSR_VSX; 148a0e72cf1SAnton Blanchard 149a0e72cf1SAnton Blanchard if (oldmsr != newmsr) 150a0e72cf1SAnton Blanchard mtmsr_isync(newmsr); 151a0e72cf1SAnton Blanchard } 1523eb5d588SAnton Blanchard EXPORT_SYMBOL(__msr_check_and_clear); 153a0e72cf1SAnton Blanchard 154037f0eedSKevin Hao #ifdef CONFIG_PPC_FPU 1551cdf039bSMathieu Malaterre static void __giveup_fpu(struct task_struct *tsk) 1568792468dSCyril Bur { 1578eb98037SAnton Blanchard unsigned long msr; 1588eb98037SAnton Blanchard 1598792468dSCyril Bur save_fpu(tsk); 1608eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 161fe1ef6bcSMark Cave-Ayland msr &= ~(MSR_FP|MSR_FE0|MSR_FE1); 1628792468dSCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 1638eb98037SAnton Blanchard msr &= ~MSR_VSX; 1648eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 1658792468dSCyril Bur } 1668792468dSCyril Bur 16798da581eSAnton Blanchard void giveup_fpu(struct task_struct *tsk) 16898da581eSAnton Blanchard { 16998da581eSAnton Blanchard check_if_tm_restore_required(tsk); 17098da581eSAnton Blanchard 171a0e72cf1SAnton Blanchard msr_check_and_set(MSR_FP); 17298da581eSAnton Blanchard __giveup_fpu(tsk); 173a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP); 17498da581eSAnton Blanchard } 17598da581eSAnton Blanchard EXPORT_SYMBOL(giveup_fpu); 17698da581eSAnton Blanchard 17714cf11afSPaul Mackerras /* 17814cf11afSPaul Mackerras * Make sure the floating-point register state in the 17914cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 18014cf11afSPaul Mackerras */ 18114cf11afSPaul Mackerras void flush_fp_to_thread(struct task_struct *tsk) 18214cf11afSPaul Mackerras { 18314cf11afSPaul Mackerras if (tsk->thread.regs) { 18414cf11afSPaul Mackerras /* 18514cf11afSPaul Mackerras * We need to disable preemption here because if we didn't, 18614cf11afSPaul Mackerras * another process could get scheduled after the regs->msr 18714cf11afSPaul Mackerras * test but before we have finished saving the FP registers 18814cf11afSPaul Mackerras * to the thread_struct. That process could take over the 18914cf11afSPaul Mackerras * FPU, and then when we get scheduled again we would store 19014cf11afSPaul Mackerras * bogus values for the remaining FP registers. 19114cf11afSPaul Mackerras */ 19214cf11afSPaul Mackerras preempt_disable(); 19314cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_FP) { 19414cf11afSPaul Mackerras /* 19514cf11afSPaul Mackerras * This should only ever be called for current or 19614cf11afSPaul Mackerras * for a stopped child process. Since we save away 197af1bbc3dSAnton Blanchard * the FP register state on context switch, 19814cf11afSPaul Mackerras * there is something wrong if a stopped child appears 19914cf11afSPaul Mackerras * to still have its FP state in the CPU registers. 20014cf11afSPaul Mackerras */ 20114cf11afSPaul Mackerras BUG_ON(tsk != current); 202b86fd2bdSAnton Blanchard giveup_fpu(tsk); 20314cf11afSPaul Mackerras } 20414cf11afSPaul Mackerras preempt_enable(); 20514cf11afSPaul Mackerras } 20614cf11afSPaul Mackerras } 207de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_fp_to_thread); 20814cf11afSPaul Mackerras 20914cf11afSPaul Mackerras void enable_kernel_fp(void) 21014cf11afSPaul Mackerras { 211e909fb83SCyril Bur unsigned long cpumsr; 212e909fb83SCyril Bur 21314cf11afSPaul Mackerras WARN_ON(preemptible()); 21414cf11afSPaul Mackerras 215e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP); 216611b0e5cSAnton Blanchard 217d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 218d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 219e909fb83SCyril Bur /* 220e909fb83SCyril Bur * If a thread has already been reclaimed then the 221e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 222e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 223e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 224e909fb83SCyril Bur * checkpointed structure. 225e909fb83SCyril Bur */ 2265c784c84SBreno Leitao if (!MSR_TM_ACTIVE(cpumsr) && 2275c784c84SBreno Leitao MSR_TM_ACTIVE(current->thread.regs->msr)) 228e909fb83SCyril Bur return; 229a0e72cf1SAnton Blanchard __giveup_fpu(current); 230b86fd2bdSAnton Blanchard } 231d64d02ceSAnton Blanchard } 23214cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_fp); 233c83c192aSChristophe Leroy #else 234c83c192aSChristophe Leroy static inline void __giveup_fpu(struct task_struct *tsk) { } 235d1e1cf2eSAnton Blanchard #endif /* CONFIG_PPC_FPU */ 23614cf11afSPaul Mackerras 23714cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 2386f515d84SCyril Bur static void __giveup_altivec(struct task_struct *tsk) 2396f515d84SCyril Bur { 2408eb98037SAnton Blanchard unsigned long msr; 2418eb98037SAnton Blanchard 2426f515d84SCyril Bur save_altivec(tsk); 2438eb98037SAnton Blanchard msr = tsk->thread.regs->msr; 2448eb98037SAnton Blanchard msr &= ~MSR_VEC; 2456f515d84SCyril Bur if (cpu_has_feature(CPU_FTR_VSX)) 2468eb98037SAnton Blanchard msr &= ~MSR_VSX; 2478eb98037SAnton Blanchard tsk->thread.regs->msr = msr; 2486f515d84SCyril Bur } 2496f515d84SCyril Bur 25098da581eSAnton Blanchard void giveup_altivec(struct task_struct *tsk) 25198da581eSAnton Blanchard { 25298da581eSAnton Blanchard check_if_tm_restore_required(tsk); 25398da581eSAnton Blanchard 254a0e72cf1SAnton Blanchard msr_check_and_set(MSR_VEC); 25598da581eSAnton Blanchard __giveup_altivec(tsk); 256a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_VEC); 25798da581eSAnton Blanchard } 25898da581eSAnton Blanchard EXPORT_SYMBOL(giveup_altivec); 25998da581eSAnton Blanchard 26014cf11afSPaul Mackerras void enable_kernel_altivec(void) 26114cf11afSPaul Mackerras { 262e909fb83SCyril Bur unsigned long cpumsr; 263e909fb83SCyril Bur 26414cf11afSPaul Mackerras WARN_ON(preemptible()); 26514cf11afSPaul Mackerras 266e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_VEC); 267611b0e5cSAnton Blanchard 268d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 269d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 270e909fb83SCyril Bur /* 271e909fb83SCyril Bur * If a thread has already been reclaimed then the 272e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 273e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 274e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 275e909fb83SCyril Bur * checkpointed structure. 276e909fb83SCyril Bur */ 2775c784c84SBreno Leitao if (!MSR_TM_ACTIVE(cpumsr) && 2785c784c84SBreno Leitao MSR_TM_ACTIVE(current->thread.regs->msr)) 279e909fb83SCyril Bur return; 280a0e72cf1SAnton Blanchard __giveup_altivec(current); 281b86fd2bdSAnton Blanchard } 282d64d02ceSAnton Blanchard } 28314cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_altivec); 28414cf11afSPaul Mackerras 28514cf11afSPaul Mackerras /* 28614cf11afSPaul Mackerras * Make sure the VMX/Altivec register state in the 28714cf11afSPaul Mackerras * the thread_struct is up to date for task tsk. 28814cf11afSPaul Mackerras */ 28914cf11afSPaul Mackerras void flush_altivec_to_thread(struct task_struct *tsk) 29014cf11afSPaul Mackerras { 29114cf11afSPaul Mackerras if (tsk->thread.regs) { 29214cf11afSPaul Mackerras preempt_disable(); 29314cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_VEC) { 29414cf11afSPaul Mackerras BUG_ON(tsk != current); 295b86fd2bdSAnton Blanchard giveup_altivec(tsk); 29614cf11afSPaul Mackerras } 29714cf11afSPaul Mackerras preempt_enable(); 29814cf11afSPaul Mackerras } 29914cf11afSPaul Mackerras } 300de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 30114cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 30214cf11afSPaul Mackerras 303ce48b210SMichael Neuling #ifdef CONFIG_VSX 304bf6a4d5bSCyril Bur static void __giveup_vsx(struct task_struct *tsk) 305a7d623d4SAnton Blanchard { 306dc801081SBenjamin Herrenschmidt unsigned long msr = tsk->thread.regs->msr; 307dc801081SBenjamin Herrenschmidt 308dc801081SBenjamin Herrenschmidt /* 309dc801081SBenjamin Herrenschmidt * We should never be ssetting MSR_VSX without also setting 310dc801081SBenjamin Herrenschmidt * MSR_FP and MSR_VEC 311dc801081SBenjamin Herrenschmidt */ 312dc801081SBenjamin Herrenschmidt WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); 313dc801081SBenjamin Herrenschmidt 314dc801081SBenjamin Herrenschmidt /* __giveup_fpu will clear MSR_VSX */ 315dc801081SBenjamin Herrenschmidt if (msr & MSR_FP) 316a7d623d4SAnton Blanchard __giveup_fpu(tsk); 317dc801081SBenjamin Herrenschmidt if (msr & MSR_VEC) 318a7d623d4SAnton Blanchard __giveup_altivec(tsk); 319bf6a4d5bSCyril Bur } 320bf6a4d5bSCyril Bur 321bf6a4d5bSCyril Bur static void giveup_vsx(struct task_struct *tsk) 322bf6a4d5bSCyril Bur { 323bf6a4d5bSCyril Bur check_if_tm_restore_required(tsk); 324bf6a4d5bSCyril Bur 325bf6a4d5bSCyril Bur msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 326a7d623d4SAnton Blanchard __giveup_vsx(tsk); 327a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 328a7d623d4SAnton Blanchard } 329bf6a4d5bSCyril Bur 330ce48b210SMichael Neuling void enable_kernel_vsx(void) 331ce48b210SMichael Neuling { 332e909fb83SCyril Bur unsigned long cpumsr; 333e909fb83SCyril Bur 334ce48b210SMichael Neuling WARN_ON(preemptible()); 335ce48b210SMichael Neuling 336e909fb83SCyril Bur cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 337611b0e5cSAnton Blanchard 3385a69aec9SBenjamin Herrenschmidt if (current->thread.regs && 3395a69aec9SBenjamin Herrenschmidt (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { 340d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 341e909fb83SCyril Bur /* 342e909fb83SCyril Bur * If a thread has already been reclaimed then the 343e909fb83SCyril Bur * checkpointed registers are on the CPU but have definitely 344e909fb83SCyril Bur * been saved by the reclaim code. Don't need to and *cannot* 345e909fb83SCyril Bur * giveup as this would save to the 'live' structure not the 346e909fb83SCyril Bur * checkpointed structure. 347e909fb83SCyril Bur */ 3485c784c84SBreno Leitao if (!MSR_TM_ACTIVE(cpumsr) && 3495c784c84SBreno Leitao MSR_TM_ACTIVE(current->thread.regs->msr)) 350e909fb83SCyril Bur return; 351a0e72cf1SAnton Blanchard __giveup_vsx(current); 352611b0e5cSAnton Blanchard } 353ce48b210SMichael Neuling } 354ce48b210SMichael Neuling EXPORT_SYMBOL(enable_kernel_vsx); 355ce48b210SMichael Neuling 356ce48b210SMichael Neuling void flush_vsx_to_thread(struct task_struct *tsk) 357ce48b210SMichael Neuling { 358ce48b210SMichael Neuling if (tsk->thread.regs) { 359ce48b210SMichael Neuling preempt_disable(); 3605a69aec9SBenjamin Herrenschmidt if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { 361ce48b210SMichael Neuling BUG_ON(tsk != current); 362ce48b210SMichael Neuling giveup_vsx(tsk); 363ce48b210SMichael Neuling } 364ce48b210SMichael Neuling preempt_enable(); 365ce48b210SMichael Neuling } 366ce48b210SMichael Neuling } 367de56a948SPaul Mackerras EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 368ce48b210SMichael Neuling #endif /* CONFIG_VSX */ 369ce48b210SMichael Neuling 37014cf11afSPaul Mackerras #ifdef CONFIG_SPE 37198da581eSAnton Blanchard void giveup_spe(struct task_struct *tsk) 37298da581eSAnton Blanchard { 37398da581eSAnton Blanchard check_if_tm_restore_required(tsk); 37498da581eSAnton Blanchard 375a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 37698da581eSAnton Blanchard __giveup_spe(tsk); 377a0e72cf1SAnton Blanchard msr_check_and_clear(MSR_SPE); 37898da581eSAnton Blanchard } 37998da581eSAnton Blanchard EXPORT_SYMBOL(giveup_spe); 38014cf11afSPaul Mackerras 38114cf11afSPaul Mackerras void enable_kernel_spe(void) 38214cf11afSPaul Mackerras { 38314cf11afSPaul Mackerras WARN_ON(preemptible()); 38414cf11afSPaul Mackerras 385a0e72cf1SAnton Blanchard msr_check_and_set(MSR_SPE); 386611b0e5cSAnton Blanchard 387d64d02ceSAnton Blanchard if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 388d64d02ceSAnton Blanchard check_if_tm_restore_required(current); 389a0e72cf1SAnton Blanchard __giveup_spe(current); 39014cf11afSPaul Mackerras } 391d64d02ceSAnton Blanchard } 39214cf11afSPaul Mackerras EXPORT_SYMBOL(enable_kernel_spe); 39314cf11afSPaul Mackerras 39414cf11afSPaul Mackerras void flush_spe_to_thread(struct task_struct *tsk) 39514cf11afSPaul Mackerras { 39614cf11afSPaul Mackerras if (tsk->thread.regs) { 39714cf11afSPaul Mackerras preempt_disable(); 39814cf11afSPaul Mackerras if (tsk->thread.regs->msr & MSR_SPE) { 39914cf11afSPaul Mackerras BUG_ON(tsk != current); 400685659eeSyu liu tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 4010ee6c15eSKumar Gala giveup_spe(tsk); 40214cf11afSPaul Mackerras } 40314cf11afSPaul Mackerras preempt_enable(); 40414cf11afSPaul Mackerras } 40514cf11afSPaul Mackerras } 40614cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 40714cf11afSPaul Mackerras 408c2085059SAnton Blanchard static unsigned long msr_all_available; 409c2085059SAnton Blanchard 410c2085059SAnton Blanchard static int __init init_msr_all_available(void) 411c2085059SAnton Blanchard { 412c83c192aSChristophe Leroy if (IS_ENABLED(CONFIG_PPC_FPU)) 413c2085059SAnton Blanchard msr_all_available |= MSR_FP; 414c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC)) 415c2085059SAnton Blanchard msr_all_available |= MSR_VEC; 416c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_VSX)) 417c2085059SAnton Blanchard msr_all_available |= MSR_VSX; 418c2085059SAnton Blanchard if (cpu_has_feature(CPU_FTR_SPE)) 419c2085059SAnton Blanchard msr_all_available |= MSR_SPE; 420c2085059SAnton Blanchard 421c2085059SAnton Blanchard return 0; 422c2085059SAnton Blanchard } 423c2085059SAnton Blanchard early_initcall(init_msr_all_available); 424c2085059SAnton Blanchard 425c2085059SAnton Blanchard void giveup_all(struct task_struct *tsk) 426c2085059SAnton Blanchard { 427c2085059SAnton Blanchard unsigned long usermsr; 428c2085059SAnton Blanchard 429c2085059SAnton Blanchard if (!tsk->thread.regs) 430c2085059SAnton Blanchard return; 431c2085059SAnton Blanchard 4328205d5d9SGustavo Romero check_if_tm_restore_required(tsk); 4338205d5d9SGustavo Romero 434c2085059SAnton Blanchard usermsr = tsk->thread.regs->msr; 435c2085059SAnton Blanchard 436c2085059SAnton Blanchard if ((usermsr & msr_all_available) == 0) 437c2085059SAnton Blanchard return; 438c2085059SAnton Blanchard 439c2085059SAnton Blanchard msr_check_and_set(msr_all_available); 440c2085059SAnton Blanchard 44196c79b6bSBenjamin Herrenschmidt WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 44296c79b6bSBenjamin Herrenschmidt 443c2085059SAnton Blanchard if (usermsr & MSR_FP) 444c2085059SAnton Blanchard __giveup_fpu(tsk); 445c2085059SAnton Blanchard if (usermsr & MSR_VEC) 446c2085059SAnton Blanchard __giveup_altivec(tsk); 447c2085059SAnton Blanchard if (usermsr & MSR_SPE) 448c2085059SAnton Blanchard __giveup_spe(tsk); 449c2085059SAnton Blanchard 450c2085059SAnton Blanchard msr_check_and_clear(msr_all_available); 451c2085059SAnton Blanchard } 452c2085059SAnton Blanchard EXPORT_SYMBOL(giveup_all); 453c2085059SAnton Blanchard 4546cc0c16dSNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64 4556cc0c16dSNicholas Piggin #ifdef CONFIG_PPC_FPU 45601eb0187SNicholas Piggin static bool should_restore_fp(void) 4576cc0c16dSNicholas Piggin { 45801eb0187SNicholas Piggin if (current->thread.load_fp) { 4596cc0c16dSNicholas Piggin current->thread.load_fp++; 46001eb0187SNicholas Piggin return true; 4616cc0c16dSNicholas Piggin } 46201eb0187SNicholas Piggin return false; 46301eb0187SNicholas Piggin } 46401eb0187SNicholas Piggin 46501eb0187SNicholas Piggin static void do_restore_fp(void) 46601eb0187SNicholas Piggin { 46701eb0187SNicholas Piggin load_fp_state(¤t->thread.fp_state); 4686cc0c16dSNicholas Piggin } 4696cc0c16dSNicholas Piggin #else 47001eb0187SNicholas Piggin static bool should_restore_fp(void) { return false; } 47101eb0187SNicholas Piggin static void do_restore_fp(void) { } 4726cc0c16dSNicholas Piggin #endif /* CONFIG_PPC_FPU */ 4736cc0c16dSNicholas Piggin 4746cc0c16dSNicholas Piggin #ifdef CONFIG_ALTIVEC 47501eb0187SNicholas Piggin static bool should_restore_altivec(void) 4766cc0c16dSNicholas Piggin { 47701eb0187SNicholas Piggin if (cpu_has_feature(CPU_FTR_ALTIVEC) && (current->thread.load_vec)) { 47801eb0187SNicholas Piggin current->thread.load_vec++; 47901eb0187SNicholas Piggin return true; 4806cc0c16dSNicholas Piggin } 48101eb0187SNicholas Piggin return false; 48201eb0187SNicholas Piggin } 48301eb0187SNicholas Piggin 48401eb0187SNicholas Piggin static void do_restore_altivec(void) 48501eb0187SNicholas Piggin { 48601eb0187SNicholas Piggin load_vr_state(¤t->thread.vr_state); 48701eb0187SNicholas Piggin current->thread.used_vr = 1; 4886cc0c16dSNicholas Piggin } 4896cc0c16dSNicholas Piggin #else 49001eb0187SNicholas Piggin static bool should_restore_altivec(void) { return false; } 49101eb0187SNicholas Piggin static void do_restore_altivec(void) { } 4926cc0c16dSNicholas Piggin #endif /* CONFIG_ALTIVEC */ 4936cc0c16dSNicholas Piggin 49401eb0187SNicholas Piggin static bool should_restore_vsx(void) 4956cc0c16dSNicholas Piggin { 49601eb0187SNicholas Piggin if (cpu_has_feature(CPU_FTR_VSX)) 49701eb0187SNicholas Piggin return true; 49801eb0187SNicholas Piggin return false; 4996cc0c16dSNicholas Piggin } 50080739c2bSChristophe Leroy #ifdef CONFIG_VSX 50101eb0187SNicholas Piggin static void do_restore_vsx(void) 50201eb0187SNicholas Piggin { 50301eb0187SNicholas Piggin current->thread.used_vsr = 1; 5046cc0c16dSNicholas Piggin } 5056cc0c16dSNicholas Piggin #else 50601eb0187SNicholas Piggin static void do_restore_vsx(void) { } 5076cc0c16dSNicholas Piggin #endif /* CONFIG_VSX */ 5086cc0c16dSNicholas Piggin 509e2b36d59SNicholas Piggin /* 510e2b36d59SNicholas Piggin * The exception exit path calls restore_math() with interrupts hard disabled 511e2b36d59SNicholas Piggin * but the soft irq state not "reconciled". ftrace code that calls 512e2b36d59SNicholas Piggin * local_irq_save/restore causes warnings. 513e2b36d59SNicholas Piggin * 514e2b36d59SNicholas Piggin * Rather than complicate the exit path, just don't trace restore_math. This 515e2b36d59SNicholas Piggin * could be done by having ftrace entry code check for this un-reconciled 516e2b36d59SNicholas Piggin * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and 517e2b36d59SNicholas Piggin * temporarily fix it up for the duration of the ftrace call. 518e2b36d59SNicholas Piggin */ 519e2b36d59SNicholas Piggin void notrace restore_math(struct pt_regs *regs) 52070fe3d98SCyril Bur { 52170fe3d98SCyril Bur unsigned long msr; 52201eb0187SNicholas Piggin unsigned long new_msr = 0; 52370fe3d98SCyril Bur 52470fe3d98SCyril Bur msr = regs->msr; 52570fe3d98SCyril Bur 52670fe3d98SCyril Bur /* 52701eb0187SNicholas Piggin * new_msr tracks the facilities that are to be restored. Only reload 52801eb0187SNicholas Piggin * if the bit is not set in the user MSR (if it is set, the registers 52901eb0187SNicholas Piggin * are live for the user thread). 53070fe3d98SCyril Bur */ 53101eb0187SNicholas Piggin if ((!(msr & MSR_FP)) && should_restore_fp()) 532b91eb518SMichael Ellerman new_msr |= MSR_FP; 53370fe3d98SCyril Bur 53401eb0187SNicholas Piggin if ((!(msr & MSR_VEC)) && should_restore_altivec()) 53501eb0187SNicholas Piggin new_msr |= MSR_VEC; 53670fe3d98SCyril Bur 53701eb0187SNicholas Piggin if ((!(msr & MSR_VSX)) && should_restore_vsx()) { 53801eb0187SNicholas Piggin if (((msr | new_msr) & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) 53901eb0187SNicholas Piggin new_msr |= MSR_VSX; 54070fe3d98SCyril Bur } 54170fe3d98SCyril Bur 54201eb0187SNicholas Piggin if (new_msr) { 543b91eb518SMichael Ellerman unsigned long fpexc_mode = 0; 544b91eb518SMichael Ellerman 54501eb0187SNicholas Piggin msr_check_and_set(new_msr); 54670fe3d98SCyril Bur 547b91eb518SMichael Ellerman if (new_msr & MSR_FP) { 54801eb0187SNicholas Piggin do_restore_fp(); 54901eb0187SNicholas Piggin 550b91eb518SMichael Ellerman // This also covers VSX, because VSX implies FP 551b91eb518SMichael Ellerman fpexc_mode = current->thread.fpexc_mode; 552b91eb518SMichael Ellerman } 553b91eb518SMichael Ellerman 55401eb0187SNicholas Piggin if (new_msr & MSR_VEC) 55501eb0187SNicholas Piggin do_restore_altivec(); 55601eb0187SNicholas Piggin 55701eb0187SNicholas Piggin if (new_msr & MSR_VSX) 55801eb0187SNicholas Piggin do_restore_vsx(); 55901eb0187SNicholas Piggin 56001eb0187SNicholas Piggin msr_check_and_clear(new_msr); 56101eb0187SNicholas Piggin 562b91eb518SMichael Ellerman regs->msr |= new_msr | fpexc_mode; 56301eb0187SNicholas Piggin } 56470fe3d98SCyril Bur } 56560d62bfdSChristophe Leroy #endif /* CONFIG_PPC_BOOK3S_64 */ 56670fe3d98SCyril Bur 5671cdf039bSMathieu Malaterre static void save_all(struct task_struct *tsk) 568de2a20aaSCyril Bur { 569de2a20aaSCyril Bur unsigned long usermsr; 570de2a20aaSCyril Bur 571de2a20aaSCyril Bur if (!tsk->thread.regs) 572de2a20aaSCyril Bur return; 573de2a20aaSCyril Bur 574de2a20aaSCyril Bur usermsr = tsk->thread.regs->msr; 575de2a20aaSCyril Bur 576de2a20aaSCyril Bur if ((usermsr & msr_all_available) == 0) 577de2a20aaSCyril Bur return; 578de2a20aaSCyril Bur 579de2a20aaSCyril Bur msr_check_and_set(msr_all_available); 580de2a20aaSCyril Bur 58196c79b6bSBenjamin Herrenschmidt WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 58296c79b6bSBenjamin Herrenschmidt 583de2a20aaSCyril Bur if (usermsr & MSR_FP) 5848792468dSCyril Bur save_fpu(tsk); 585de2a20aaSCyril Bur 586de2a20aaSCyril Bur if (usermsr & MSR_VEC) 5876f515d84SCyril Bur save_altivec(tsk); 588de2a20aaSCyril Bur 589de2a20aaSCyril Bur if (usermsr & MSR_SPE) 590de2a20aaSCyril Bur __giveup_spe(tsk); 591de2a20aaSCyril Bur 592de2a20aaSCyril Bur msr_check_and_clear(msr_all_available); 593de2a20aaSCyril Bur } 594de2a20aaSCyril Bur 595579e633eSAnton Blanchard void flush_all_to_thread(struct task_struct *tsk) 596579e633eSAnton Blanchard { 597579e633eSAnton Blanchard if (tsk->thread.regs) { 598579e633eSAnton Blanchard preempt_disable(); 599579e633eSAnton Blanchard BUG_ON(tsk != current); 600579e633eSAnton Blanchard #ifdef CONFIG_SPE 601579e633eSAnton Blanchard if (tsk->thread.regs->msr & MSR_SPE) 602579e633eSAnton Blanchard tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 603579e633eSAnton Blanchard #endif 604e9013785SFelipe Rechia save_all(tsk); 605579e633eSAnton Blanchard 606579e633eSAnton Blanchard preempt_enable(); 607579e633eSAnton Blanchard } 608579e633eSAnton Blanchard } 609579e633eSAnton Blanchard EXPORT_SYMBOL(flush_all_to_thread); 610579e633eSAnton Blanchard 6113bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6123bffb652SDave Kleikamp void do_send_trap(struct pt_regs *regs, unsigned long address, 61347355040SEric W. Biederman unsigned long error_code, int breakpt) 6143bffb652SDave Kleikamp { 61547355040SEric W. Biederman current->thread.trap_nr = TRAP_HWBKPT; 6163bffb652SDave Kleikamp if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 6173bffb652SDave Kleikamp 11, SIGSEGV) == NOTIFY_STOP) 6183bffb652SDave Kleikamp return; 6193bffb652SDave Kleikamp 6203bffb652SDave Kleikamp /* Deliver the signal to userspace */ 621f71dd7dcSEric W. Biederman force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ 622f71dd7dcSEric W. Biederman (void __user *)address); 6233bffb652SDave Kleikamp } 6243bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 6255b905d77SRavi Bangoria 6265b905d77SRavi Bangoria static void do_break_handler(struct pt_regs *regs) 6275b905d77SRavi Bangoria { 6285b905d77SRavi Bangoria struct arch_hw_breakpoint null_brk = {0}; 6295b905d77SRavi Bangoria struct arch_hw_breakpoint *info; 6305b905d77SRavi Bangoria struct ppc_inst instr = ppc_inst(0); 6315b905d77SRavi Bangoria int type = 0; 6325b905d77SRavi Bangoria int size = 0; 6335b905d77SRavi Bangoria unsigned long ea; 6345b905d77SRavi Bangoria int i; 6355b905d77SRavi Bangoria 6365b905d77SRavi Bangoria /* 6375b905d77SRavi Bangoria * If underneath hw supports only one watchpoint, we know it 6385b905d77SRavi Bangoria * caused exception. 8xx also falls into this category. 6395b905d77SRavi Bangoria */ 6405b905d77SRavi Bangoria if (nr_wp_slots() == 1) { 6415b905d77SRavi Bangoria __set_breakpoint(0, &null_brk); 6425b905d77SRavi Bangoria current->thread.hw_brk[0] = null_brk; 6435b905d77SRavi Bangoria current->thread.hw_brk[0].flags |= HW_BRK_FLAG_DISABLED; 6445b905d77SRavi Bangoria return; 6455b905d77SRavi Bangoria } 6465b905d77SRavi Bangoria 6475b905d77SRavi Bangoria /* Otherwise findout which DAWR caused exception and disable it. */ 6485b905d77SRavi Bangoria wp_get_instr_detail(regs, &instr, &type, &size, &ea); 6495b905d77SRavi Bangoria 6505b905d77SRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) { 6515b905d77SRavi Bangoria info = ¤t->thread.hw_brk[i]; 6525b905d77SRavi Bangoria if (!info->address) 6535b905d77SRavi Bangoria continue; 6545b905d77SRavi Bangoria 6555b905d77SRavi Bangoria if (wp_check_constraints(regs, instr, ea, type, size, info)) { 6565b905d77SRavi Bangoria __set_breakpoint(i, &null_brk); 6575b905d77SRavi Bangoria current->thread.hw_brk[i] = null_brk; 6585b905d77SRavi Bangoria current->thread.hw_brk[i].flags |= HW_BRK_FLAG_DISABLED; 6595b905d77SRavi Bangoria } 6605b905d77SRavi Bangoria } 6615b905d77SRavi Bangoria } 6625b905d77SRavi Bangoria 663*3a96570fSNicholas Piggin DEFINE_INTERRUPT_HANDLER(do_break) 664d6a61bfcSLuis Machado { 66541ab5266SAnanth N Mavinakayanahalli current->thread.trap_nr = TRAP_HWBKPT; 66618722ecfSNicholas Piggin if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, regs->dsisr, 667d6a61bfcSLuis Machado 11, SIGSEGV) == NOTIFY_STOP) 668d6a61bfcSLuis Machado return; 669d6a61bfcSLuis Machado 6709422de3eSMichael Neuling if (debugger_break_match(regs)) 671d6a61bfcSLuis Machado return; 672d6a61bfcSLuis Machado 6735b905d77SRavi Bangoria /* 6745b905d77SRavi Bangoria * We reach here only when watchpoint exception is generated by ptrace 6755b905d77SRavi Bangoria * event (or hw is buggy!). Now if CONFIG_HAVE_HW_BREAKPOINT is set, 6765b905d77SRavi Bangoria * watchpoint is already handled by hw_breakpoint_handler() so we don't 6775b905d77SRavi Bangoria * have to do anything. But when CONFIG_HAVE_HW_BREAKPOINT is not set, 6785b905d77SRavi Bangoria * we need to manually handle the watchpoint here. 6795b905d77SRavi Bangoria */ 6805b905d77SRavi Bangoria if (!IS_ENABLED(CONFIG_HAVE_HW_BREAKPOINT)) 6815b905d77SRavi Bangoria do_break_handler(regs); 6825b905d77SRavi Bangoria 683d6a61bfcSLuis Machado /* Deliver the signal to userspace */ 68418722ecfSNicholas Piggin force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)regs->dar); 685d6a61bfcSLuis Machado } 6863bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 687d6a61bfcSLuis Machado 6884a8a9379SRavi Bangoria static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]); 689a2ceff5eSMichael Ellerman 6903bffb652SDave Kleikamp #ifdef CONFIG_PPC_ADV_DEBUG_REGS 6913bffb652SDave Kleikamp /* 6923bffb652SDave Kleikamp * Set the debug registers back to their default "safe" values. 6933bffb652SDave Kleikamp */ 6943bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 6953bffb652SDave Kleikamp { 69651ae8d4aSBharat Bhushan thread->debug.iac1 = thread->debug.iac2 = 0; 6973bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 69851ae8d4aSBharat Bhushan thread->debug.iac3 = thread->debug.iac4 = 0; 6993bffb652SDave Kleikamp #endif 70051ae8d4aSBharat Bhushan thread->debug.dac1 = thread->debug.dac2 = 0; 7013bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 70251ae8d4aSBharat Bhushan thread->debug.dvc1 = thread->debug.dvc2 = 0; 7033bffb652SDave Kleikamp #endif 70451ae8d4aSBharat Bhushan thread->debug.dbcr0 = 0; 7053bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 7063bffb652SDave Kleikamp /* 7073bffb652SDave Kleikamp * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 7083bffb652SDave Kleikamp */ 70951ae8d4aSBharat Bhushan thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 7103bffb652SDave Kleikamp DBCR1_IAC3US | DBCR1_IAC4US; 7113bffb652SDave Kleikamp /* 7123bffb652SDave Kleikamp * Force Data Address Compare User/Supervisor bits to be User-only 7133bffb652SDave Kleikamp * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 7143bffb652SDave Kleikamp */ 71551ae8d4aSBharat Bhushan thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 7163bffb652SDave Kleikamp #else 71751ae8d4aSBharat Bhushan thread->debug.dbcr1 = 0; 7183bffb652SDave Kleikamp #endif 7193bffb652SDave Kleikamp } 7203bffb652SDave Kleikamp 721f5f97210SScott Wood static void prime_debug_regs(struct debug_reg *debug) 7223bffb652SDave Kleikamp { 7236cecf76bSScott Wood /* 7246cecf76bSScott Wood * We could have inherited MSR_DE from userspace, since 7256cecf76bSScott Wood * it doesn't get cleared on exception entry. Make sure 7266cecf76bSScott Wood * MSR_DE is clear before we enable any debug events. 7276cecf76bSScott Wood */ 7286cecf76bSScott Wood mtmsr(mfmsr() & ~MSR_DE); 7296cecf76bSScott Wood 730f5f97210SScott Wood mtspr(SPRN_IAC1, debug->iac1); 731f5f97210SScott Wood mtspr(SPRN_IAC2, debug->iac2); 7323bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_IACS > 2 733f5f97210SScott Wood mtspr(SPRN_IAC3, debug->iac3); 734f5f97210SScott Wood mtspr(SPRN_IAC4, debug->iac4); 7353bffb652SDave Kleikamp #endif 736f5f97210SScott Wood mtspr(SPRN_DAC1, debug->dac1); 737f5f97210SScott Wood mtspr(SPRN_DAC2, debug->dac2); 7383bffb652SDave Kleikamp #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 739f5f97210SScott Wood mtspr(SPRN_DVC1, debug->dvc1); 740f5f97210SScott Wood mtspr(SPRN_DVC2, debug->dvc2); 7413bffb652SDave Kleikamp #endif 742f5f97210SScott Wood mtspr(SPRN_DBCR0, debug->dbcr0); 743f5f97210SScott Wood mtspr(SPRN_DBCR1, debug->dbcr1); 7443bffb652SDave Kleikamp #ifdef CONFIG_BOOKE 745f5f97210SScott Wood mtspr(SPRN_DBCR2, debug->dbcr2); 7463bffb652SDave Kleikamp #endif 7473bffb652SDave Kleikamp } 7483bffb652SDave Kleikamp /* 7493bffb652SDave Kleikamp * Unless neither the old or new thread are making use of the 7503bffb652SDave Kleikamp * debug registers, set the debug registers from the values 7513bffb652SDave Kleikamp * stored in the new thread. 7523bffb652SDave Kleikamp */ 753f5f97210SScott Wood void switch_booke_debug_regs(struct debug_reg *new_debug) 7543bffb652SDave Kleikamp { 75551ae8d4aSBharat Bhushan if ((current->thread.debug.dbcr0 & DBCR0_IDM) 756f5f97210SScott Wood || (new_debug->dbcr0 & DBCR0_IDM)) 757f5f97210SScott Wood prime_debug_regs(new_debug); 7583bffb652SDave Kleikamp } 7593743c9b8SBharat Bhushan EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 7603bffb652SDave Kleikamp #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 761e0780b72SK.Prasad #ifndef CONFIG_HAVE_HW_BREAKPOINT 762303e6a9dSRavi Bangoria static void set_breakpoint(int i, struct arch_hw_breakpoint *brk) 763b5ac51d7SChristophe Leroy { 764b5ac51d7SChristophe Leroy preempt_disable(); 765303e6a9dSRavi Bangoria __set_breakpoint(i, brk); 766b5ac51d7SChristophe Leroy preempt_enable(); 767b5ac51d7SChristophe Leroy } 768b5ac51d7SChristophe Leroy 7693bffb652SDave Kleikamp static void set_debug_reg_defaults(struct thread_struct *thread) 7703bffb652SDave Kleikamp { 771303e6a9dSRavi Bangoria int i; 772303e6a9dSRavi Bangoria struct arch_hw_breakpoint null_brk = {0}; 773303e6a9dSRavi Bangoria 774303e6a9dSRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) { 775303e6a9dSRavi Bangoria thread->hw_brk[i] = null_brk; 776252988cbSNicholas Piggin if (ppc_breakpoint_available()) 777303e6a9dSRavi Bangoria set_breakpoint(i, &thread->hw_brk[i]); 778303e6a9dSRavi Bangoria } 779303e6a9dSRavi Bangoria } 780303e6a9dSRavi Bangoria 781303e6a9dSRavi Bangoria static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 782303e6a9dSRavi Bangoria struct arch_hw_breakpoint *b) 783303e6a9dSRavi Bangoria { 784303e6a9dSRavi Bangoria if (a->address != b->address) 785303e6a9dSRavi Bangoria return false; 786303e6a9dSRavi Bangoria if (a->type != b->type) 787303e6a9dSRavi Bangoria return false; 788303e6a9dSRavi Bangoria if (a->len != b->len) 789303e6a9dSRavi Bangoria return false; 790303e6a9dSRavi Bangoria /* no need to check hw_len. it's calculated from address and len */ 791303e6a9dSRavi Bangoria return true; 792303e6a9dSRavi Bangoria } 793303e6a9dSRavi Bangoria 794303e6a9dSRavi Bangoria static void switch_hw_breakpoint(struct task_struct *new) 795303e6a9dSRavi Bangoria { 796303e6a9dSRavi Bangoria int i; 797303e6a9dSRavi Bangoria 798303e6a9dSRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) { 799303e6a9dSRavi Bangoria if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]), 800303e6a9dSRavi Bangoria &new->thread.hw_brk[i]))) 801303e6a9dSRavi Bangoria continue; 802303e6a9dSRavi Bangoria 803303e6a9dSRavi Bangoria __set_breakpoint(i, &new->thread.hw_brk[i]); 804303e6a9dSRavi Bangoria } 8053bffb652SDave Kleikamp } 806e0780b72SK.Prasad #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 8073bffb652SDave Kleikamp #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 8083bffb652SDave Kleikamp 8099422de3eSMichael Neuling static inline int set_dabr(struct arch_hw_breakpoint *brk) 8109422de3eSMichael Neuling { 8119422de3eSMichael Neuling unsigned long dabr, dabrx; 8129422de3eSMichael Neuling 8139422de3eSMichael Neuling dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 8149422de3eSMichael Neuling dabrx = ((brk->type >> 3) & 0x7); 8159422de3eSMichael Neuling 8169422de3eSMichael Neuling if (ppc_md.set_dabr) 8179422de3eSMichael Neuling return ppc_md.set_dabr(dabr, dabrx); 8189422de3eSMichael Neuling 819ad3ed15cSChristophe Leroy if (IS_ENABLED(CONFIG_PPC_ADV_DEBUG_REGS)) { 820ad3ed15cSChristophe Leroy mtspr(SPRN_DAC1, dabr); 821ad3ed15cSChristophe Leroy if (IS_ENABLED(CONFIG_PPC_47x)) 822ad3ed15cSChristophe Leroy isync(); 823ad3ed15cSChristophe Leroy return 0; 824ad3ed15cSChristophe Leroy } else if (IS_ENABLED(CONFIG_PPC_BOOK3S)) { 825ad3ed15cSChristophe Leroy mtspr(SPRN_DABR, dabr); 826ad3ed15cSChristophe Leroy if (cpu_has_feature(CPU_FTR_DABRX)) 827ad3ed15cSChristophe Leroy mtspr(SPRN_DABRX, dabrx); 828ad3ed15cSChristophe Leroy return 0; 829ad3ed15cSChristophe Leroy } else { 830ad3ed15cSChristophe Leroy return -EINVAL; 831ad3ed15cSChristophe Leroy } 8329422de3eSMichael Neuling } 8339422de3eSMichael Neuling 83439413ae0SChristophe Leroy static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk) 83539413ae0SChristophe Leroy { 83639413ae0SChristophe Leroy unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW | 83739413ae0SChristophe Leroy LCTRL1_CRWF_RW; 83839413ae0SChristophe Leroy unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN; 839e68ef121SRavi Bangoria unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE); 840e68ef121SRavi Bangoria unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE); 84139413ae0SChristophe Leroy 84239413ae0SChristophe Leroy if (start_addr == 0) 84339413ae0SChristophe Leroy lctrl2 |= LCTRL2_LW0LA_F; 844e68ef121SRavi Bangoria else if (end_addr == 0) 84539413ae0SChristophe Leroy lctrl2 |= LCTRL2_LW0LA_E; 84639413ae0SChristophe Leroy else 84739413ae0SChristophe Leroy lctrl2 |= LCTRL2_LW0LA_EandF; 84839413ae0SChristophe Leroy 84939413ae0SChristophe Leroy mtspr(SPRN_LCTRL2, 0); 85039413ae0SChristophe Leroy 85139413ae0SChristophe Leroy if ((brk->type & HW_BRK_TYPE_RDWR) == 0) 85239413ae0SChristophe Leroy return 0; 85339413ae0SChristophe Leroy 85439413ae0SChristophe Leroy if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) 85539413ae0SChristophe Leroy lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO; 85639413ae0SChristophe Leroy if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) 85739413ae0SChristophe Leroy lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO; 85839413ae0SChristophe Leroy 85939413ae0SChristophe Leroy mtspr(SPRN_CMPE, start_addr - 1); 860e68ef121SRavi Bangoria mtspr(SPRN_CMPF, end_addr); 86139413ae0SChristophe Leroy mtspr(SPRN_LCTRL1, lctrl1); 86239413ae0SChristophe Leroy mtspr(SPRN_LCTRL2, lctrl2); 86339413ae0SChristophe Leroy 86439413ae0SChristophe Leroy return 0; 86539413ae0SChristophe Leroy } 86639413ae0SChristophe Leroy 8674a8a9379SRavi Bangoria void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk) 8689422de3eSMichael Neuling { 8694a8a9379SRavi Bangoria memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk)); 8709422de3eSMichael Neuling 871c1fe190cSMichael Neuling if (dawr_enabled()) 872252988cbSNicholas Piggin // Power8 or later 8734a8a9379SRavi Bangoria set_dawr(nr, brk); 87439413ae0SChristophe Leroy else if (IS_ENABLED(CONFIG_PPC_8xx)) 87539413ae0SChristophe Leroy set_breakpoint_8xx(brk); 876252988cbSNicholas Piggin else if (!cpu_has_feature(CPU_FTR_ARCH_207S)) 877252988cbSNicholas Piggin // Power7 or earlier 87804c32a51SPaul Gortmaker set_dabr(brk); 879252988cbSNicholas Piggin else 880252988cbSNicholas Piggin // Shouldn't happen due to higher level checks 881252988cbSNicholas Piggin WARN_ON_ONCE(1); 8829422de3eSMichael Neuling } 88314cf11afSPaul Mackerras 884404b27d6SMichael Neuling /* Check if we have DAWR or DABR hardware */ 885404b27d6SMichael Neuling bool ppc_breakpoint_available(void) 886404b27d6SMichael Neuling { 887c1fe190cSMichael Neuling if (dawr_enabled()) 888c1fe190cSMichael Neuling return true; /* POWER8 DAWR or POWER9 forced DAWR */ 889404b27d6SMichael Neuling if (cpu_has_feature(CPU_FTR_ARCH_207S)) 890404b27d6SMichael Neuling return false; /* POWER9 with DAWR disabled */ 891404b27d6SMichael Neuling /* DABR: Everything but POWER8 and POWER9 */ 892404b27d6SMichael Neuling return true; 893404b27d6SMichael Neuling } 894404b27d6SMichael Neuling EXPORT_SYMBOL_GPL(ppc_breakpoint_available); 895404b27d6SMichael Neuling 896fb09692eSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 8975d176f75SCyril Bur 8985d176f75SCyril Bur static inline bool tm_enabled(struct task_struct *tsk) 8995d176f75SCyril Bur { 9005d176f75SCyril Bur return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); 9015d176f75SCyril Bur } 9025d176f75SCyril Bur 903edd00b83SCyril Bur static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause) 904d31626f7SPaul Mackerras { 9057f821fc9SMichael Neuling /* 9067f821fc9SMichael Neuling * Use the current MSR TM suspended bit to track if we have 9077f821fc9SMichael Neuling * checkpointed state outstanding. 9087f821fc9SMichael Neuling * On signal delivery, we'd normally reclaim the checkpointed 9097f821fc9SMichael Neuling * state to obtain stack pointer (see:get_tm_stackpointer()). 9107f821fc9SMichael Neuling * This will then directly return to userspace without going 9117f821fc9SMichael Neuling * through __switch_to(). However, if the stack frame is bad, 9127f821fc9SMichael Neuling * we need to exit this thread which calls __switch_to() which 9137f821fc9SMichael Neuling * will again attempt to reclaim the already saved tm state. 9147f821fc9SMichael Neuling * Hence we need to check that we've not already reclaimed 9157f821fc9SMichael Neuling * this state. 9167f821fc9SMichael Neuling * We do this using the current MSR, rather tracking it in 9177f821fc9SMichael Neuling * some specific thread_struct bit, as it has the additional 918027dfac6SMichael Ellerman * benefit of checking for a potential TM bad thing exception. 9197f821fc9SMichael Neuling */ 9207f821fc9SMichael Neuling if (!MSR_TM_SUSPENDED(mfmsr())) 9217f821fc9SMichael Neuling return; 9227f821fc9SMichael Neuling 92391381b9cSCyril Bur giveup_all(container_of(thr, struct task_struct, thread)); 92491381b9cSCyril Bur 925eb5c3f1cSCyril Bur tm_reclaim(thr, cause); 926eb5c3f1cSCyril Bur 927f48e91e8SMichael Neuling /* 928f48e91e8SMichael Neuling * If we are in a transaction and FP is off then we can't have 929f48e91e8SMichael Neuling * used FP inside that transaction. Hence the checkpointed 930f48e91e8SMichael Neuling * state is the same as the live state. We need to copy the 931f48e91e8SMichael Neuling * live state to the checkpointed state so that when the 932f48e91e8SMichael Neuling * transaction is restored, the checkpointed state is correct 933f48e91e8SMichael Neuling * and the aborted transaction sees the correct state. We use 934f48e91e8SMichael Neuling * ckpt_regs.msr here as that's what tm_reclaim will use to 935f48e91e8SMichael Neuling * determine if it's going to write the checkpointed state or 936f48e91e8SMichael Neuling * not. So either this will write the checkpointed registers, 937f48e91e8SMichael Neuling * or reclaim will. Similarly for VMX. 938f48e91e8SMichael Neuling */ 939f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_FP) == 0) 940f48e91e8SMichael Neuling memcpy(&thr->ckfp_state, &thr->fp_state, 941f48e91e8SMichael Neuling sizeof(struct thread_fp_state)); 942f48e91e8SMichael Neuling if ((thr->ckpt_regs.msr & MSR_VEC) == 0) 943f48e91e8SMichael Neuling memcpy(&thr->ckvr_state, &thr->vr_state, 944f48e91e8SMichael Neuling sizeof(struct thread_vr_state)); 945d31626f7SPaul Mackerras } 946d31626f7SPaul Mackerras 947d31626f7SPaul Mackerras void tm_reclaim_current(uint8_t cause) 948d31626f7SPaul Mackerras { 949d31626f7SPaul Mackerras tm_enable(); 950edd00b83SCyril Bur tm_reclaim_thread(¤t->thread, cause); 951d31626f7SPaul Mackerras } 952d31626f7SPaul Mackerras 953fb09692eSMichael Neuling static inline void tm_reclaim_task(struct task_struct *tsk) 954fb09692eSMichael Neuling { 955fb09692eSMichael Neuling /* We have to work out if we're switching from/to a task that's in the 956fb09692eSMichael Neuling * middle of a transaction. 957fb09692eSMichael Neuling * 958fb09692eSMichael Neuling * In switching we need to maintain a 2nd register state as 959fb09692eSMichael Neuling * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 960000ec280SCyril Bur * checkpointed (tbegin) state in ckpt_regs, ckfp_state and 961000ec280SCyril Bur * ckvr_state 962fb09692eSMichael Neuling * 963fb09692eSMichael Neuling * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 964fb09692eSMichael Neuling */ 965fb09692eSMichael Neuling struct thread_struct *thr = &tsk->thread; 966fb09692eSMichael Neuling 967fb09692eSMichael Neuling if (!thr->regs) 968fb09692eSMichael Neuling return; 969fb09692eSMichael Neuling 970fb09692eSMichael Neuling if (!MSR_TM_ACTIVE(thr->regs->msr)) 971fb09692eSMichael Neuling goto out_and_saveregs; 972fb09692eSMichael Neuling 97392fb8690SMichael Neuling WARN_ON(tm_suspend_disabled); 97492fb8690SMichael Neuling 975fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 976fb09692eSMichael Neuling "ccr=%lx, msr=%lx, trap=%lx)\n", 977fb09692eSMichael Neuling tsk->pid, thr->regs->nip, 978fb09692eSMichael Neuling thr->regs->ccr, thr->regs->msr, 979fb09692eSMichael Neuling thr->regs->trap); 980fb09692eSMichael Neuling 981edd00b83SCyril Bur tm_reclaim_thread(thr, TM_CAUSE_RESCHED); 982fb09692eSMichael Neuling 983fb09692eSMichael Neuling TM_DEBUG("--- tm_reclaim on pid %d complete\n", 984fb09692eSMichael Neuling tsk->pid); 985fb09692eSMichael Neuling 986fb09692eSMichael Neuling out_and_saveregs: 987fb09692eSMichael Neuling /* Always save the regs here, even if a transaction's not active. 988fb09692eSMichael Neuling * This context-switches a thread's TM info SPRs. We do it here to 989fb09692eSMichael Neuling * be consistent with the restore path (in recheckpoint) which 990fb09692eSMichael Neuling * cannot happen later in _switch(). 991fb09692eSMichael Neuling */ 992fb09692eSMichael Neuling tm_save_sprs(thr); 993fb09692eSMichael Neuling } 994fb09692eSMichael Neuling 995eb5c3f1cSCyril Bur extern void __tm_recheckpoint(struct thread_struct *thread); 996e6b8fd02SMichael Neuling 997eb5c3f1cSCyril Bur void tm_recheckpoint(struct thread_struct *thread) 998e6b8fd02SMichael Neuling { 999e6b8fd02SMichael Neuling unsigned long flags; 1000e6b8fd02SMichael Neuling 10015d176f75SCyril Bur if (!(thread->regs->msr & MSR_TM)) 10025d176f75SCyril Bur return; 10035d176f75SCyril Bur 1004e6b8fd02SMichael Neuling /* We really can't be interrupted here as the TEXASR registers can't 1005e6b8fd02SMichael Neuling * change and later in the trecheckpoint code, we have a userspace R1. 1006e6b8fd02SMichael Neuling * So let's hard disable over this region. 1007e6b8fd02SMichael Neuling */ 1008e6b8fd02SMichael Neuling local_irq_save(flags); 1009e6b8fd02SMichael Neuling hard_irq_disable(); 1010e6b8fd02SMichael Neuling 1011e6b8fd02SMichael Neuling /* The TM SPRs are restored here, so that TEXASR.FS can be set 1012e6b8fd02SMichael Neuling * before the trecheckpoint and no explosion occurs. 1013e6b8fd02SMichael Neuling */ 1014e6b8fd02SMichael Neuling tm_restore_sprs(thread); 1015e6b8fd02SMichael Neuling 1016eb5c3f1cSCyril Bur __tm_recheckpoint(thread); 1017e6b8fd02SMichael Neuling 1018e6b8fd02SMichael Neuling local_irq_restore(flags); 1019e6b8fd02SMichael Neuling } 1020e6b8fd02SMichael Neuling 1021bc2a9408SMichael Neuling static inline void tm_recheckpoint_new_task(struct task_struct *new) 1022fb09692eSMichael Neuling { 1023fb09692eSMichael Neuling if (!cpu_has_feature(CPU_FTR_TM)) 1024fb09692eSMichael Neuling return; 1025fb09692eSMichael Neuling 1026fb09692eSMichael Neuling /* Recheckpoint the registers of the thread we're about to switch to. 1027fb09692eSMichael Neuling * 1028fb09692eSMichael Neuling * If the task was using FP, we non-lazily reload both the original and 1029fb09692eSMichael Neuling * the speculative FP register states. This is because the kernel 1030fb09692eSMichael Neuling * doesn't see if/when a TM rollback occurs, so if we take an FP 1031dc310669SCyril Bur * unavailable later, we are unable to determine which set of FP regs 1032fb09692eSMichael Neuling * need to be restored. 1033fb09692eSMichael Neuling */ 10345d176f75SCyril Bur if (!tm_enabled(new)) 1035fb09692eSMichael Neuling return; 1036fb09692eSMichael Neuling 1037e6b8fd02SMichael Neuling if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 1038fb09692eSMichael Neuling tm_restore_sprs(&new->thread); 1039fb09692eSMichael Neuling return; 1040e6b8fd02SMichael Neuling } 1041fb09692eSMichael Neuling /* Recheckpoint to restore original checkpointed register state. */ 1042eb5c3f1cSCyril Bur TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", 1043eb5c3f1cSCyril Bur new->pid, new->thread.regs->msr); 1044fb09692eSMichael Neuling 1045eb5c3f1cSCyril Bur tm_recheckpoint(&new->thread); 1046fb09692eSMichael Neuling 1047dc310669SCyril Bur /* 1048dc310669SCyril Bur * The checkpointed state has been restored but the live state has 1049dc310669SCyril Bur * not, ensure all the math functionality is turned off to trigger 1050dc310669SCyril Bur * restore_math() to reload. 1051dc310669SCyril Bur */ 1052dc310669SCyril Bur new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); 1053fb09692eSMichael Neuling 1054fb09692eSMichael Neuling TM_DEBUG("*** tm_recheckpoint of pid %d complete " 1055fb09692eSMichael Neuling "(kernel msr 0x%lx)\n", 1056fb09692eSMichael Neuling new->pid, mfmsr()); 1057fb09692eSMichael Neuling } 1058fb09692eSMichael Neuling 1059dc310669SCyril Bur static inline void __switch_to_tm(struct task_struct *prev, 1060dc310669SCyril Bur struct task_struct *new) 1061fb09692eSMichael Neuling { 1062fb09692eSMichael Neuling if (cpu_has_feature(CPU_FTR_TM)) { 10635d176f75SCyril Bur if (tm_enabled(prev) || tm_enabled(new)) 1064fb09692eSMichael Neuling tm_enable(); 10655d176f75SCyril Bur 10665d176f75SCyril Bur if (tm_enabled(prev)) { 10675d176f75SCyril Bur prev->thread.load_tm++; 1068fb09692eSMichael Neuling tm_reclaim_task(prev); 10695d176f75SCyril Bur if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) 10705d176f75SCyril Bur prev->thread.regs->msr &= ~MSR_TM; 10715d176f75SCyril Bur } 10725d176f75SCyril Bur 1073dc310669SCyril Bur tm_recheckpoint_new_task(new); 1074fb09692eSMichael Neuling } 1075fb09692eSMichael Neuling } 1076d31626f7SPaul Mackerras 1077d31626f7SPaul Mackerras /* 1078d31626f7SPaul Mackerras * This is called if we are on the way out to userspace and the 1079d31626f7SPaul Mackerras * TIF_RESTORE_TM flag is set. It checks if we need to reload 1080d31626f7SPaul Mackerras * FP and/or vector state and does so if necessary. 1081d31626f7SPaul Mackerras * If userspace is inside a transaction (whether active or 1082d31626f7SPaul Mackerras * suspended) and FP/VMX/VSX instructions have ever been enabled 1083d31626f7SPaul Mackerras * inside that transaction, then we have to keep them enabled 1084d31626f7SPaul Mackerras * and keep the FP/VMX/VSX state loaded while ever the transaction 1085d31626f7SPaul Mackerras * continues. The reason is that if we didn't, and subsequently 1086d31626f7SPaul Mackerras * got a FP/VMX/VSX unavailable interrupt inside a transaction, 1087d31626f7SPaul Mackerras * we don't know whether it's the same transaction, and thus we 1088d31626f7SPaul Mackerras * don't know which of the checkpointed state and the transactional 1089d31626f7SPaul Mackerras * state to use. 1090d31626f7SPaul Mackerras */ 1091d31626f7SPaul Mackerras void restore_tm_state(struct pt_regs *regs) 1092d31626f7SPaul Mackerras { 1093d31626f7SPaul Mackerras unsigned long msr_diff; 1094d31626f7SPaul Mackerras 1095dc310669SCyril Bur /* 1096dc310669SCyril Bur * This is the only moment we should clear TIF_RESTORE_TM as 1097dc310669SCyril Bur * it is here that ckpt_regs.msr and pt_regs.msr become the same 1098dc310669SCyril Bur * again, anything else could lead to an incorrect ckpt_msr being 1099dc310669SCyril Bur * saved and therefore incorrect signal contexts. 1100dc310669SCyril Bur */ 1101d31626f7SPaul Mackerras clear_thread_flag(TIF_RESTORE_TM); 1102d31626f7SPaul Mackerras if (!MSR_TM_ACTIVE(regs->msr)) 1103d31626f7SPaul Mackerras return; 1104d31626f7SPaul Mackerras 1105829023dfSAnshuman Khandual msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 1106d31626f7SPaul Mackerras msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 110770fe3d98SCyril Bur 1108dc16b553SCyril Bur /* Ensure that restore_math() will restore */ 1109dc16b553SCyril Bur if (msr_diff & MSR_FP) 1110dc16b553SCyril Bur current->thread.load_fp = 1; 111139715bf9SValentin Rothberg #ifdef CONFIG_ALTIVEC 1112dc16b553SCyril Bur if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) 1113dc16b553SCyril Bur current->thread.load_vec = 1; 1114dc16b553SCyril Bur #endif 111570fe3d98SCyril Bur restore_math(regs); 111670fe3d98SCyril Bur 1117d31626f7SPaul Mackerras regs->msr |= msr_diff; 1118d31626f7SPaul Mackerras } 1119d31626f7SPaul Mackerras 1120fb09692eSMichael Neuling #else 1121fb09692eSMichael Neuling #define tm_recheckpoint_new_task(new) 1122dc310669SCyril Bur #define __switch_to_tm(prev, new) 1123fb09692eSMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 11249422de3eSMichael Neuling 1125152d523eSAnton Blanchard static inline void save_sprs(struct thread_struct *t) 1126152d523eSAnton Blanchard { 1127152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 112801d7c2a2SOliver O'Halloran if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1129152d523eSAnton Blanchard t->vrsave = mfspr(SPRN_VRSAVE); 1130152d523eSAnton Blanchard #endif 1131152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1132152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) 1133152d523eSAnton Blanchard t->dscr = mfspr(SPRN_DSCR); 1134152d523eSAnton Blanchard 1135152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1136152d523eSAnton Blanchard t->bescr = mfspr(SPRN_BESCR); 1137152d523eSAnton Blanchard t->ebbhr = mfspr(SPRN_EBBHR); 1138152d523eSAnton Blanchard t->ebbrr = mfspr(SPRN_EBBRR); 1139152d523eSAnton Blanchard 1140152d523eSAnton Blanchard t->fscr = mfspr(SPRN_FSCR); 1141152d523eSAnton Blanchard 1142152d523eSAnton Blanchard /* 1143152d523eSAnton Blanchard * Note that the TAR is not available for use in the kernel. 1144152d523eSAnton Blanchard * (To provide this, the TAR should be backed up/restored on 1145152d523eSAnton Blanchard * exception entry/exit instead, and be in pt_regs. FIXME, 1146152d523eSAnton Blanchard * this should be in pt_regs anyway (for debug).) 1147152d523eSAnton Blanchard */ 1148152d523eSAnton Blanchard t->tar = mfspr(SPRN_TAR); 1149152d523eSAnton Blanchard } 1150152d523eSAnton Blanchard #endif 1151152d523eSAnton Blanchard } 1152152d523eSAnton Blanchard 1153152d523eSAnton Blanchard static inline void restore_sprs(struct thread_struct *old_thread, 1154152d523eSAnton Blanchard struct thread_struct *new_thread) 1155152d523eSAnton Blanchard { 1156152d523eSAnton Blanchard #ifdef CONFIG_ALTIVEC 1157152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ALTIVEC) && 1158152d523eSAnton Blanchard old_thread->vrsave != new_thread->vrsave) 1159152d523eSAnton Blanchard mtspr(SPRN_VRSAVE, new_thread->vrsave); 1160152d523eSAnton Blanchard #endif 1161152d523eSAnton Blanchard #ifdef CONFIG_PPC_BOOK3S_64 1162152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_DSCR)) { 1163152d523eSAnton Blanchard u64 dscr = get_paca()->dscr_default; 1164b57bd2deSMichael Neuling if (new_thread->dscr_inherit) 1165152d523eSAnton Blanchard dscr = new_thread->dscr; 1166152d523eSAnton Blanchard 1167152d523eSAnton Blanchard if (old_thread->dscr != dscr) 1168152d523eSAnton Blanchard mtspr(SPRN_DSCR, dscr); 1169152d523eSAnton Blanchard } 1170152d523eSAnton Blanchard 1171152d523eSAnton Blanchard if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1172152d523eSAnton Blanchard if (old_thread->bescr != new_thread->bescr) 1173152d523eSAnton Blanchard mtspr(SPRN_BESCR, new_thread->bescr); 1174152d523eSAnton Blanchard if (old_thread->ebbhr != new_thread->ebbhr) 1175152d523eSAnton Blanchard mtspr(SPRN_EBBHR, new_thread->ebbhr); 1176152d523eSAnton Blanchard if (old_thread->ebbrr != new_thread->ebbrr) 1177152d523eSAnton Blanchard mtspr(SPRN_EBBRR, new_thread->ebbrr); 1178152d523eSAnton Blanchard 1179b57bd2deSMichael Neuling if (old_thread->fscr != new_thread->fscr) 1180b57bd2deSMichael Neuling mtspr(SPRN_FSCR, new_thread->fscr); 1181b57bd2deSMichael Neuling 1182152d523eSAnton Blanchard if (old_thread->tar != new_thread->tar) 1183152d523eSAnton Blanchard mtspr(SPRN_TAR, new_thread->tar); 1184152d523eSAnton Blanchard } 1185ec233edeSSukadev Bhattiprolu 11863449f191SAlastair D'Silva if (cpu_has_feature(CPU_FTR_P9_TIDR) && 1187ec233edeSSukadev Bhattiprolu old_thread->tidr != new_thread->tidr) 1188ec233edeSSukadev Bhattiprolu mtspr(SPRN_TIDR, new_thread->tidr); 1189152d523eSAnton Blanchard #endif 119006bb53b3SRam Pai 1191152d523eSAnton Blanchard } 1192152d523eSAnton Blanchard 119314cf11afSPaul Mackerras struct task_struct *__switch_to(struct task_struct *prev, 119414cf11afSPaul Mackerras struct task_struct *new) 119514cf11afSPaul Mackerras { 119614cf11afSPaul Mackerras struct thread_struct *new_thread, *old_thread; 119714cf11afSPaul Mackerras struct task_struct *last; 1198d6bf29b4SPeter Zijlstra #ifdef CONFIG_PPC_BOOK3S_64 1199d6bf29b4SPeter Zijlstra struct ppc64_tlb_batch *batch; 1200d6bf29b4SPeter Zijlstra #endif 120114cf11afSPaul Mackerras 1202152d523eSAnton Blanchard new_thread = &new->thread; 1203152d523eSAnton Blanchard old_thread = ¤t->thread; 1204152d523eSAnton Blanchard 12057ba5fef7SMichael Neuling WARN_ON(!irqs_disabled()); 12067ba5fef7SMichael Neuling 12074e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 120869111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1209d6bf29b4SPeter Zijlstra if (batch->active) { 1210d6bf29b4SPeter Zijlstra current_thread_info()->local_flags |= _TLF_LAZY_MMU; 1211d6bf29b4SPeter Zijlstra if (batch->index) 1212d6bf29b4SPeter Zijlstra __flush_tlb_pending(batch); 1213d6bf29b4SPeter Zijlstra batch->active = 0; 1214d6bf29b4SPeter Zijlstra } 12154e003747SMichael Ellerman #endif /* CONFIG_PPC_BOOK3S_64 */ 121606d67d54SPaul Mackerras 1217f3d885ccSAnton Blanchard #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1218f3d885ccSAnton Blanchard switch_booke_debug_regs(&new->thread.debug); 1219f3d885ccSAnton Blanchard #else 1220f3d885ccSAnton Blanchard /* 1221f3d885ccSAnton Blanchard * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 1222f3d885ccSAnton Blanchard * schedule DABR 1223f3d885ccSAnton Blanchard */ 1224f3d885ccSAnton Blanchard #ifndef CONFIG_HAVE_HW_BREAKPOINT 1225303e6a9dSRavi Bangoria switch_hw_breakpoint(new); 1226f3d885ccSAnton Blanchard #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1227f3d885ccSAnton Blanchard #endif 1228f3d885ccSAnton Blanchard 1229f3d885ccSAnton Blanchard /* 1230f3d885ccSAnton Blanchard * We need to save SPRs before treclaim/trecheckpoint as these will 1231f3d885ccSAnton Blanchard * change a number of them. 1232f3d885ccSAnton Blanchard */ 1233f3d885ccSAnton Blanchard save_sprs(&prev->thread); 1234f3d885ccSAnton Blanchard 1235f3d885ccSAnton Blanchard /* Save FPU, Altivec, VSX and SPE state */ 1236f3d885ccSAnton Blanchard giveup_all(prev); 1237f3d885ccSAnton Blanchard 1238dc310669SCyril Bur __switch_to_tm(prev, new); 1239dc310669SCyril Bur 1240e4c0fc5fSNicholas Piggin if (!radix_enabled()) { 124144387e9fSAnton Blanchard /* 1242e4c0fc5fSNicholas Piggin * We can't take a PMU exception inside _switch() since there 1243e4c0fc5fSNicholas Piggin * is a window where the kernel stack SLB and the kernel stack 1244e4c0fc5fSNicholas Piggin * are out of sync. Hard disable here. 124544387e9fSAnton Blanchard */ 124644387e9fSAnton Blanchard hard_irq_disable(); 1247e4c0fc5fSNicholas Piggin } 1248bc2a9408SMichael Neuling 124920dbe670SAnton Blanchard /* 125020dbe670SAnton Blanchard * Call restore_sprs() before calling _switch(). If we move it after 125120dbe670SAnton Blanchard * _switch() then we miss out on calling it for new tasks. The reason 125220dbe670SAnton Blanchard * for this is we manually create a stack frame for new tasks that 125320dbe670SAnton Blanchard * directly returns through ret_from_fork() or 125420dbe670SAnton Blanchard * ret_from_kernel_thread(). See copy_thread() for details. 125520dbe670SAnton Blanchard */ 1256f3d885ccSAnton Blanchard restore_sprs(old_thread, new_thread); 1257f3d885ccSAnton Blanchard 125820dbe670SAnton Blanchard last = _switch(old_thread, new_thread); 125920dbe670SAnton Blanchard 12604e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 1261d6bf29b4SPeter Zijlstra if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1262d6bf29b4SPeter Zijlstra current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 126369111bacSChristoph Lameter batch = this_cpu_ptr(&ppc64_tlb_batch); 1264d6bf29b4SPeter Zijlstra batch->active = 1; 1265d6bf29b4SPeter Zijlstra } 126670fe3d98SCyril Bur 126705b98791SChristophe Leroy if (current->thread.regs) { 126805b98791SChristophe Leroy restore_math(current->thread.regs); 126907d2a628SNicholas Piggin 127007d2a628SNicholas Piggin /* 1271dc462267SNicholas Piggin * On POWER9 the copy-paste buffer can only paste into 1272dc462267SNicholas Piggin * foreign real addresses, so unprivileged processes can not 1273dc462267SNicholas Piggin * see the data or use it in any way unless they have 1274dc462267SNicholas Piggin * foreign real mappings. If the new process has the foreign 1275dc462267SNicholas Piggin * real address mappings, we must issue a cp_abort to clear 1276dc462267SNicholas Piggin * any state and prevent snooping, corruption or a covert 1277dc462267SNicholas Piggin * channel. ISA v3.1 supports paste into local memory. 127807d2a628SNicholas Piggin */ 1279c420644cSHaren Myneni if (current->mm && 1280dc462267SNicholas Piggin (cpu_has_feature(CPU_FTR_ARCH_31) || 1281dc462267SNicholas Piggin atomic_read(¤t->mm->context.vas_windows))) 12829d2a4d71SSukadev Bhattiprolu asm volatile(PPC_CP_ABORT); 128307d2a628SNicholas Piggin } 12844e003747SMichael Ellerman #endif /* CONFIG_PPC_BOOK3S_64 */ 1285d6bf29b4SPeter Zijlstra 128614cf11afSPaul Mackerras return last; 128714cf11afSPaul Mackerras } 128814cf11afSPaul Mackerras 1289df13102fSChristophe Leroy #define NR_INSN_TO_PRINT 16 129006d67d54SPaul Mackerras 129106d67d54SPaul Mackerras static void show_instructions(struct pt_regs *regs) 129206d67d54SPaul Mackerras { 129306d67d54SPaul Mackerras int i; 1294a6e2c226SAneesh Kumar K.V unsigned long nip = regs->nip; 1295df13102fSChristophe Leroy unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); 129606d67d54SPaul Mackerras 129706d67d54SPaul Mackerras printk("Instruction dump:"); 129806d67d54SPaul Mackerras 1299a6e2c226SAneesh Kumar K.V /* 1300a6e2c226SAneesh Kumar K.V * If we were executing with the MMU off for instructions, adjust pc 1301a6e2c226SAneesh Kumar K.V * rather than printing XXXXXXXX. 1302a6e2c226SAneesh Kumar K.V */ 1303a6e2c226SAneesh Kumar K.V if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) { 1304a6e2c226SAneesh Kumar K.V pc = (unsigned long)phys_to_virt(pc); 1305a6e2c226SAneesh Kumar K.V nip = (unsigned long)phys_to_virt(regs->nip); 1306a6e2c226SAneesh Kumar K.V } 1307a6e2c226SAneesh Kumar K.V 1308df13102fSChristophe Leroy for (i = 0; i < NR_INSN_TO_PRINT; i++) { 130906d67d54SPaul Mackerras int instr; 131006d67d54SPaul Mackerras 131106d67d54SPaul Mackerras if (!(i % 8)) 13122ffd04deSAndrew Donnellan pr_cont("\n"); 131306d67d54SPaul Mackerras 131400ae36deSAnton Blanchard if (!__kernel_text_address(pc) || 131525f12ae4SChristoph Hellwig get_kernel_nofault(instr, (const void *)pc)) { 13162ffd04deSAndrew Donnellan pr_cont("XXXXXXXX "); 131706d67d54SPaul Mackerras } else { 1318a6e2c226SAneesh Kumar K.V if (nip == pc) 13192ffd04deSAndrew Donnellan pr_cont("<%08x> ", instr); 132006d67d54SPaul Mackerras else 13212ffd04deSAndrew Donnellan pr_cont("%08x ", instr); 132206d67d54SPaul Mackerras } 132306d67d54SPaul Mackerras 132406d67d54SPaul Mackerras pc += sizeof(int); 132506d67d54SPaul Mackerras } 132606d67d54SPaul Mackerras 13272ffd04deSAndrew Donnellan pr_cont("\n"); 132806d67d54SPaul Mackerras } 132906d67d54SPaul Mackerras 133088b0fe17SMurilo Opsfelder Araujo void show_user_instructions(struct pt_regs *regs) 133188b0fe17SMurilo Opsfelder Araujo { 133288b0fe17SMurilo Opsfelder Araujo unsigned long pc; 1333df13102fSChristophe Leroy int n = NR_INSN_TO_PRINT; 1334fb2d9505SChristophe Leroy struct seq_buf s; 1335fb2d9505SChristophe Leroy char buf[96]; /* enough for 8 times 9 + 2 chars */ 133688b0fe17SMurilo Opsfelder Araujo 1337df13102fSChristophe Leroy pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); 133888b0fe17SMurilo Opsfelder Araujo 1339fb2d9505SChristophe Leroy seq_buf_init(&s, buf, sizeof(buf)); 134088b0fe17SMurilo Opsfelder Araujo 1341fb2d9505SChristophe Leroy while (n) { 1342fb2d9505SChristophe Leroy int i; 1343fb2d9505SChristophe Leroy 1344fb2d9505SChristophe Leroy seq_buf_clear(&s); 1345fb2d9505SChristophe Leroy 1346fb2d9505SChristophe Leroy for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) { 134788b0fe17SMurilo Opsfelder Araujo int instr; 134888b0fe17SMurilo Opsfelder Araujo 1349c0ee37e8SChristoph Hellwig if (copy_from_user_nofault(&instr, (void __user *)pc, 1350c0ee37e8SChristoph Hellwig sizeof(instr))) { 1351fb2d9505SChristophe Leroy seq_buf_printf(&s, "XXXXXXXX "); 1352fb2d9505SChristophe Leroy continue; 1353fb2d9505SChristophe Leroy } 1354fb2d9505SChristophe Leroy seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr); 135588b0fe17SMurilo Opsfelder Araujo } 135688b0fe17SMurilo Opsfelder Araujo 1357fb2d9505SChristophe Leroy if (!seq_buf_has_overflowed(&s)) 1358fb2d9505SChristophe Leroy pr_info("%s[%d]: code: %s\n", current->comm, 1359fb2d9505SChristophe Leroy current->pid, s.buffer); 136088b0fe17SMurilo Opsfelder Araujo } 136188b0fe17SMurilo Opsfelder Araujo } 136288b0fe17SMurilo Opsfelder Araujo 1363801c0b2cSMichael Neuling struct regbit { 136406d67d54SPaul Mackerras unsigned long bit; 136506d67d54SPaul Mackerras const char *name; 1366801c0b2cSMichael Neuling }; 1367801c0b2cSMichael Neuling 1368801c0b2cSMichael Neuling static struct regbit msr_bits[] = { 13693bfd0c9cSAnton Blanchard #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 13703bfd0c9cSAnton Blanchard {MSR_SF, "SF"}, 13713bfd0c9cSAnton Blanchard {MSR_HV, "HV"}, 13723bfd0c9cSAnton Blanchard #endif 13733bfd0c9cSAnton Blanchard {MSR_VEC, "VEC"}, 13743bfd0c9cSAnton Blanchard {MSR_VSX, "VSX"}, 13753bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13763bfd0c9cSAnton Blanchard {MSR_CE, "CE"}, 13773bfd0c9cSAnton Blanchard #endif 137806d67d54SPaul Mackerras {MSR_EE, "EE"}, 137906d67d54SPaul Mackerras {MSR_PR, "PR"}, 138006d67d54SPaul Mackerras {MSR_FP, "FP"}, 138106d67d54SPaul Mackerras {MSR_ME, "ME"}, 13823bfd0c9cSAnton Blanchard #ifdef CONFIG_BOOKE 13831b98326bSKumar Gala {MSR_DE, "DE"}, 13843bfd0c9cSAnton Blanchard #else 13853bfd0c9cSAnton Blanchard {MSR_SE, "SE"}, 13863bfd0c9cSAnton Blanchard {MSR_BE, "BE"}, 13873bfd0c9cSAnton Blanchard #endif 138806d67d54SPaul Mackerras {MSR_IR, "IR"}, 138906d67d54SPaul Mackerras {MSR_DR, "DR"}, 13903bfd0c9cSAnton Blanchard {MSR_PMM, "PMM"}, 13913bfd0c9cSAnton Blanchard #ifndef CONFIG_BOOKE 13923bfd0c9cSAnton Blanchard {MSR_RI, "RI"}, 13933bfd0c9cSAnton Blanchard {MSR_LE, "LE"}, 13943bfd0c9cSAnton Blanchard #endif 139506d67d54SPaul Mackerras {0, NULL} 139606d67d54SPaul Mackerras }; 139706d67d54SPaul Mackerras 1398801c0b2cSMichael Neuling static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 139906d67d54SPaul Mackerras { 1400801c0b2cSMichael Neuling const char *s = ""; 140106d67d54SPaul Mackerras 140206d67d54SPaul Mackerras for (; bits->bit; ++bits) 140306d67d54SPaul Mackerras if (val & bits->bit) { 1404db5ba5aeSMichael Ellerman pr_cont("%s%s", s, bits->name); 1405801c0b2cSMichael Neuling s = sep; 140606d67d54SPaul Mackerras } 1407801c0b2cSMichael Neuling } 1408801c0b2cSMichael Neuling 1409801c0b2cSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1410801c0b2cSMichael Neuling static struct regbit msr_tm_bits[] = { 1411801c0b2cSMichael Neuling {MSR_TS_T, "T"}, 1412801c0b2cSMichael Neuling {MSR_TS_S, "S"}, 1413801c0b2cSMichael Neuling {MSR_TM, "E"}, 1414801c0b2cSMichael Neuling {0, NULL} 1415801c0b2cSMichael Neuling }; 1416801c0b2cSMichael Neuling 1417801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) 1418801c0b2cSMichael Neuling { 1419801c0b2cSMichael Neuling /* 1420801c0b2cSMichael Neuling * This only prints something if at least one of the TM bit is set. 1421801c0b2cSMichael Neuling * Inside the TM[], the output means: 1422801c0b2cSMichael Neuling * E: Enabled (bit 32) 1423801c0b2cSMichael Neuling * S: Suspended (bit 33) 1424801c0b2cSMichael Neuling * T: Transactional (bit 34) 1425801c0b2cSMichael Neuling */ 1426801c0b2cSMichael Neuling if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1427db5ba5aeSMichael Ellerman pr_cont(",TM["); 1428801c0b2cSMichael Neuling print_bits(val, msr_tm_bits, ""); 1429db5ba5aeSMichael Ellerman pr_cont("]"); 1430801c0b2cSMichael Neuling } 1431801c0b2cSMichael Neuling } 1432801c0b2cSMichael Neuling #else 1433801c0b2cSMichael Neuling static void print_tm_bits(unsigned long val) {} 1434801c0b2cSMichael Neuling #endif 1435801c0b2cSMichael Neuling 1436801c0b2cSMichael Neuling static void print_msr_bits(unsigned long val) 1437801c0b2cSMichael Neuling { 1438db5ba5aeSMichael Ellerman pr_cont("<"); 1439801c0b2cSMichael Neuling print_bits(val, msr_bits, ","); 1440801c0b2cSMichael Neuling print_tm_bits(val); 1441db5ba5aeSMichael Ellerman pr_cont(">"); 144206d67d54SPaul Mackerras } 144306d67d54SPaul Mackerras 144406d67d54SPaul Mackerras #ifdef CONFIG_PPC64 1445f6f7dde3Santon@samba.org #define REG "%016lx" 144606d67d54SPaul Mackerras #define REGS_PER_LINE 4 144706d67d54SPaul Mackerras #define LAST_VOLATILE 13 144806d67d54SPaul Mackerras #else 1449f6f7dde3Santon@samba.org #define REG "%08lx" 145006d67d54SPaul Mackerras #define REGS_PER_LINE 8 145106d67d54SPaul Mackerras #define LAST_VOLATILE 12 145206d67d54SPaul Mackerras #endif 145306d67d54SPaul Mackerras 1454bf13718bSNicholas Piggin static void __show_regs(struct pt_regs *regs) 145514cf11afSPaul Mackerras { 145614cf11afSPaul Mackerras int i, trap; 145714cf11afSPaul Mackerras 145806d67d54SPaul Mackerras printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 145906d67d54SPaul Mackerras regs->nip, regs->link, regs->ctr); 1460182dc9c7SMichael Ellerman printk("REGS: %px TRAP: %04lx %s (%s)\n", 146196b644bdSSerge E. Hallyn regs, regs->trap, print_tainted(), init_utsname()->release); 146206d67d54SPaul Mackerras printk("MSR: "REG" ", regs->msr); 1463801c0b2cSMichael Neuling print_msr_bits(regs->msr); 1464f6fc73fbSMichael Ellerman pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 146514cf11afSPaul Mackerras trap = TRAP(regs); 1466912237eaSNicholas Piggin if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR)) 14677dae865fSMichael Ellerman pr_cont("CFAR: "REG" ", regs->orig_gpr3); 14682ec42996SChristophe Leroy if (trap == 0x200 || trap == 0x300 || trap == 0x600) { 14692ec42996SChristophe Leroy if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE)) 14707dae865fSMichael Ellerman pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 14712ec42996SChristophe Leroy else 14727dae865fSMichael Ellerman pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 14732ec42996SChristophe Leroy } 14742ec42996SChristophe Leroy 14759db8bcfdSAnton Blanchard #ifdef CONFIG_PPC64 14763130a7bbSNicholas Piggin pr_cont("IRQMASK: %lx ", regs->softe); 14779db8bcfdSAnton Blanchard #endif 14789db8bcfdSAnton Blanchard #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 14796d888d1aSAnton Blanchard if (MSR_TM_ACTIVE(regs->msr)) 14807dae865fSMichael Ellerman pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 148114170789SKumar Gala #endif 148214cf11afSPaul Mackerras 148314cf11afSPaul Mackerras for (i = 0; i < 32; i++) { 148406d67d54SPaul Mackerras if ((i % REGS_PER_LINE) == 0) 14857dae865fSMichael Ellerman pr_cont("\nGPR%02d: ", i); 14867dae865fSMichael Ellerman pr_cont(REG " ", regs->gpr[i]); 148706d67d54SPaul Mackerras if (i == LAST_VOLATILE && !FULL_REGS(regs)) 148814cf11afSPaul Mackerras break; 148914cf11afSPaul Mackerras } 14907dae865fSMichael Ellerman pr_cont("\n"); 149114cf11afSPaul Mackerras /* 149214cf11afSPaul Mackerras * Lookup NIP late so we have the best change of getting the 149314cf11afSPaul Mackerras * above info out without failing 149414cf11afSPaul Mackerras */ 14958f020c7cSChristophe Leroy if (IS_ENABLED(CONFIG_KALLSYMS)) { 1496058c78f4SBenjamin Herrenschmidt printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1497058c78f4SBenjamin Herrenschmidt printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 14988f020c7cSChristophe Leroy } 1499bf13718bSNicholas Piggin } 1500bf13718bSNicholas Piggin 1501bf13718bSNicholas Piggin void show_regs(struct pt_regs *regs) 1502bf13718bSNicholas Piggin { 1503bf13718bSNicholas Piggin show_regs_print_info(KERN_DEFAULT); 1504bf13718bSNicholas Piggin __show_regs(regs); 15059cb8f069SDmitry Safonov show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT); 150606d67d54SPaul Mackerras if (!user_mode(regs)) 150706d67d54SPaul Mackerras show_instructions(regs); 150814cf11afSPaul Mackerras } 150914cf11afSPaul Mackerras 151014cf11afSPaul Mackerras void flush_thread(void) 151114cf11afSPaul Mackerras { 1512e0780b72SK.Prasad #ifdef CONFIG_HAVE_HW_BREAKPOINT 15135aae8a53SK.Prasad flush_ptrace_hw_breakpoint(current); 1514e0780b72SK.Prasad #else /* CONFIG_HAVE_HW_BREAKPOINT */ 15153bffb652SDave Kleikamp set_debug_reg_defaults(¤t->thread); 1516e0780b72SK.Prasad #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 151714cf11afSPaul Mackerras } 151814cf11afSPaul Mackerras 1519425d3314SNicholas Piggin void arch_setup_new_exec(void) 1520425d3314SNicholas Piggin { 1521d7df77e8SAneesh Kumar K.V 1522d7df77e8SAneesh Kumar K.V #ifdef CONFIG_PPC_BOOK3S_64 1523d7df77e8SAneesh Kumar K.V if (!radix_enabled()) 1524425d3314SNicholas Piggin hash__setup_new_exec(); 1525425d3314SNicholas Piggin #endif 1526d7df77e8SAneesh Kumar K.V /* 1527d7df77e8SAneesh Kumar K.V * If we exec out of a kernel thread then thread.regs will not be 1528d7df77e8SAneesh Kumar K.V * set. Do it now. 1529d7df77e8SAneesh Kumar K.V */ 1530d7df77e8SAneesh Kumar K.V if (!current->thread.regs) { 1531d7df77e8SAneesh Kumar K.V struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1532d7df77e8SAneesh Kumar K.V current->thread.regs = regs - 1; 1533d7df77e8SAneesh Kumar K.V } 1534d5fa30e6SAneesh Kumar K.V 1535d5fa30e6SAneesh Kumar K.V #ifdef CONFIG_PPC_MEM_KEYS 1536d5fa30e6SAneesh Kumar K.V current->thread.regs->amr = default_amr; 1537d5fa30e6SAneesh Kumar K.V current->thread.regs->iamr = default_iamr; 1538d5fa30e6SAneesh Kumar K.V #endif 1539d7df77e8SAneesh Kumar K.V } 1540425d3314SNicholas Piggin 1541ec233edeSSukadev Bhattiprolu #ifdef CONFIG_PPC64 154271cc64a8SAlastair D'Silva /** 154371cc64a8SAlastair D'Silva * Assign a TIDR (thread ID) for task @t and set it in the thread 1544ec233edeSSukadev Bhattiprolu * structure. For now, we only support setting TIDR for 'current' task. 154571cc64a8SAlastair D'Silva * 154671cc64a8SAlastair D'Silva * Since the TID value is a truncated form of it PID, it is possible 154771cc64a8SAlastair D'Silva * (but unlikely) for 2 threads to have the same TID. In the unlikely event 154871cc64a8SAlastair D'Silva * that 2 threads share the same TID and are waiting, one of the following 154971cc64a8SAlastair D'Silva * cases will happen: 155071cc64a8SAlastair D'Silva * 155171cc64a8SAlastair D'Silva * 1. The correct thread is running, the wrong thread is not 155271cc64a8SAlastair D'Silva * In this situation, the correct thread is woken and proceeds to pass it's 155371cc64a8SAlastair D'Silva * condition check. 155471cc64a8SAlastair D'Silva * 155571cc64a8SAlastair D'Silva * 2. Neither threads are running 155671cc64a8SAlastair D'Silva * In this situation, neither thread will be woken. When scheduled, the waiting 155771cc64a8SAlastair D'Silva * threads will execute either a wait, which will return immediately, followed 155871cc64a8SAlastair D'Silva * by a condition check, which will pass for the correct thread and fail 155971cc64a8SAlastair D'Silva * for the wrong thread, or they will execute the condition check immediately. 156071cc64a8SAlastair D'Silva * 156171cc64a8SAlastair D'Silva * 3. The wrong thread is running, the correct thread is not 156271cc64a8SAlastair D'Silva * The wrong thread will be woken, but will fail it's condition check and 156371cc64a8SAlastair D'Silva * re-execute wait. The correct thread, when scheduled, will execute either 156471cc64a8SAlastair D'Silva * it's condition check (which will pass), or wait, which returns immediately 156571cc64a8SAlastair D'Silva * when called the first time after the thread is scheduled, followed by it's 156671cc64a8SAlastair D'Silva * condition check (which will pass). 156771cc64a8SAlastair D'Silva * 156871cc64a8SAlastair D'Silva * 4. Both threads are running 156971cc64a8SAlastair D'Silva * Both threads will be woken. The wrong thread will fail it's condition check 157071cc64a8SAlastair D'Silva * and execute another wait, while the correct thread will pass it's condition 157171cc64a8SAlastair D'Silva * check. 157271cc64a8SAlastair D'Silva * 157371cc64a8SAlastair D'Silva * @t: the task to set the thread ID for 1574ec233edeSSukadev Bhattiprolu */ 1575ec233edeSSukadev Bhattiprolu int set_thread_tidr(struct task_struct *t) 1576ec233edeSSukadev Bhattiprolu { 15773449f191SAlastair D'Silva if (!cpu_has_feature(CPU_FTR_P9_TIDR)) 1578ec233edeSSukadev Bhattiprolu return -EINVAL; 1579ec233edeSSukadev Bhattiprolu 1580ec233edeSSukadev Bhattiprolu if (t != current) 1581ec233edeSSukadev Bhattiprolu return -EINVAL; 1582ec233edeSSukadev Bhattiprolu 15837e4d4233SVaibhav Jain if (t->thread.tidr) 15847e4d4233SVaibhav Jain return 0; 15857e4d4233SVaibhav Jain 158671cc64a8SAlastair D'Silva t->thread.tidr = (u16)task_pid_nr(t); 1587ec233edeSSukadev Bhattiprolu mtspr(SPRN_TIDR, t->thread.tidr); 1588ec233edeSSukadev Bhattiprolu 1589ec233edeSSukadev Bhattiprolu return 0; 1590ec233edeSSukadev Bhattiprolu } 1591b1db5513SChristophe Lombard EXPORT_SYMBOL_GPL(set_thread_tidr); 1592ec233edeSSukadev Bhattiprolu 1593ec233edeSSukadev Bhattiprolu #endif /* CONFIG_PPC64 */ 1594ec233edeSSukadev Bhattiprolu 159514cf11afSPaul Mackerras void 159614cf11afSPaul Mackerras release_thread(struct task_struct *t) 159714cf11afSPaul Mackerras { 159814cf11afSPaul Mackerras } 159914cf11afSPaul Mackerras 160014cf11afSPaul Mackerras /* 160155ccf3feSSuresh Siddha * this gets called so that we can store coprocessor state into memory and 160255ccf3feSSuresh Siddha * copy the current task into the new thread. 160314cf11afSPaul Mackerras */ 160455ccf3feSSuresh Siddha int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 160514cf11afSPaul Mackerras { 1606579e633eSAnton Blanchard flush_all_to_thread(src); 1607621b5060SMichael Neuling /* 1608621b5060SMichael Neuling * Flush TM state out so we can copy it. __switch_to_tm() does this 1609621b5060SMichael Neuling * flush but it removes the checkpointed state from the current CPU and 1610621b5060SMichael Neuling * transitions the CPU out of TM mode. Hence we need to call 1611621b5060SMichael Neuling * tm_recheckpoint_new_task() (on the same task) to restore the 1612621b5060SMichael Neuling * checkpointed state back and the TM mode. 16135d176f75SCyril Bur * 16145d176f75SCyril Bur * Can't pass dst because it isn't ready. Doesn't matter, passing 16155d176f75SCyril Bur * dst is only important for __switch_to() 1616621b5060SMichael Neuling */ 1617dc310669SCyril Bur __switch_to_tm(src, src); 1618330a1eb7SMichael Ellerman 161955ccf3feSSuresh Siddha *dst = *src; 1620330a1eb7SMichael Ellerman 1621330a1eb7SMichael Ellerman clear_task_ebb(dst); 1622330a1eb7SMichael Ellerman 162355ccf3feSSuresh Siddha return 0; 162414cf11afSPaul Mackerras } 162514cf11afSPaul Mackerras 1626cec15488SMichael Ellerman static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1627cec15488SMichael Ellerman { 16284e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 1629cec15488SMichael Ellerman unsigned long sp_vsid; 1630cec15488SMichael Ellerman unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1631cec15488SMichael Ellerman 1632caca285eSAneesh Kumar K.V if (radix_enabled()) 1633caca285eSAneesh Kumar K.V return; 1634caca285eSAneesh Kumar K.V 1635cec15488SMichael Ellerman if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1636cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1637cec15488SMichael Ellerman << SLB_VSID_SHIFT_1T; 1638cec15488SMichael Ellerman else 1639cec15488SMichael Ellerman sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1640cec15488SMichael Ellerman << SLB_VSID_SHIFT; 1641cec15488SMichael Ellerman sp_vsid |= SLB_VSID_KERNEL | llp; 1642cec15488SMichael Ellerman p->thread.ksp_vsid = sp_vsid; 1643cec15488SMichael Ellerman #endif 1644cec15488SMichael Ellerman } 1645cec15488SMichael Ellerman 164614cf11afSPaul Mackerras /* 164714cf11afSPaul Mackerras * Copy a thread.. 164814cf11afSPaul Mackerras */ 1649efcac658SAlexey Kardashevskiy 16506eca8933SAlex Dowad /* 16516eca8933SAlex Dowad * Copy architecture-specific thread state 16526eca8933SAlex Dowad */ 1653714acdbdSChristian Brauner int copy_thread(unsigned long clone_flags, unsigned long usp, 1654facd04a9SNicholas Piggin unsigned long kthread_arg, struct task_struct *p, 1655facd04a9SNicholas Piggin unsigned long tls) 165614cf11afSPaul Mackerras { 165714cf11afSPaul Mackerras struct pt_regs *childregs, *kregs; 165814cf11afSPaul Mackerras extern void ret_from_fork(void); 16597fa95f9aSNicholas Piggin extern void ret_from_fork_scv(void); 166058254e10SAl Viro extern void ret_from_kernel_thread(void); 166158254e10SAl Viro void (*f)(void); 16620cec6fd1SAl Viro unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 16635d31a96eSMichael Ellerman struct thread_info *ti = task_thread_info(p); 16646b424efaSRavi Bangoria #ifdef CONFIG_HAVE_HW_BREAKPOINT 16656b424efaSRavi Bangoria int i; 16666b424efaSRavi Bangoria #endif 16675d31a96eSMichael Ellerman 1668ed1cd6deSChristophe Leroy klp_init_thread_info(p); 166914cf11afSPaul Mackerras 167014cf11afSPaul Mackerras /* Copy registers */ 167114cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 167214cf11afSPaul Mackerras childregs = (struct pt_regs *) sp; 1673ab75819dSAl Viro if (unlikely(p->flags & PF_KTHREAD)) { 16746eca8933SAlex Dowad /* kernel thread */ 167558254e10SAl Viro memset(childregs, 0, sizeof(struct pt_regs)); 167614cf11afSPaul Mackerras childregs->gpr[1] = sp + sizeof(struct pt_regs); 16777cedd601SAnton Blanchard /* function */ 16787cedd601SAnton Blanchard if (usp) 16797cedd601SAnton Blanchard childregs->gpr[14] = ppc_function_entry((void *)usp); 168058254e10SAl Viro #ifdef CONFIG_PPC64 1681b5e2fc1cSAl Viro clear_tsk_thread_flag(p, TIF_32BIT); 1682c2e480baSMadhavan Srinivasan childregs->softe = IRQS_ENABLED; 168306d67d54SPaul Mackerras #endif 16846eca8933SAlex Dowad childregs->gpr[15] = kthread_arg; 168514cf11afSPaul Mackerras p->thread.regs = NULL; /* no user register state */ 1686138d1ce8SAl Viro ti->flags |= _TIF_RESTOREALL; 168758254e10SAl Viro f = ret_from_kernel_thread; 168814cf11afSPaul Mackerras } else { 16896eca8933SAlex Dowad /* user thread */ 1690afa86fc4SAl Viro struct pt_regs *regs = current_pt_regs(); 169158254e10SAl Viro CHECK_FULL_REGS(regs); 169258254e10SAl Viro *childregs = *regs; 1693ea516b11SAl Viro if (usp) 169414cf11afSPaul Mackerras childregs->gpr[1] = usp; 169514cf11afSPaul Mackerras p->thread.regs = childregs; 16967fa95f9aSNicholas Piggin /* 64s sets this in ret_from_fork */ 16977fa95f9aSNicholas Piggin if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64)) 169858254e10SAl Viro childregs->gpr[3] = 0; /* Result from fork() */ 169906d67d54SPaul Mackerras if (clone_flags & CLONE_SETTLS) { 17009904b005SDenis Kirjanov if (!is_32bit_task()) 1701facd04a9SNicholas Piggin childregs->gpr[13] = tls; 170206d67d54SPaul Mackerras else 1703facd04a9SNicholas Piggin childregs->gpr[2] = tls; 170414cf11afSPaul Mackerras } 170558254e10SAl Viro 17067fa95f9aSNicholas Piggin if (trap_is_scv(regs)) 17077fa95f9aSNicholas Piggin f = ret_from_fork_scv; 17087fa95f9aSNicholas Piggin else 170958254e10SAl Viro f = ret_from_fork; 171006d67d54SPaul Mackerras } 1711d272f667SCyril Bur childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); 171214cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 171314cf11afSPaul Mackerras 171414cf11afSPaul Mackerras /* 171514cf11afSPaul Mackerras * The way this works is that at some point in the future 171614cf11afSPaul Mackerras * some task will call _switch to switch to the new task. 171714cf11afSPaul Mackerras * That will pop off the stack frame created below and start 171814cf11afSPaul Mackerras * the new task running at ret_from_fork. The new task will 171914cf11afSPaul Mackerras * do some house keeping and then return from the fork or clone 172014cf11afSPaul Mackerras * system call, using the stack frame created above. 172114cf11afSPaul Mackerras */ 1722af945cf4SLi Zhong ((unsigned long *)sp)[0] = 0; 172314cf11afSPaul Mackerras sp -= sizeof(struct pt_regs); 172414cf11afSPaul Mackerras kregs = (struct pt_regs *) sp; 172514cf11afSPaul Mackerras sp -= STACK_FRAME_OVERHEAD; 172614cf11afSPaul Mackerras p->thread.ksp = sp; 1727cbc9565eSBenjamin Herrenschmidt #ifdef CONFIG_PPC32 1728a7916a1dSChristophe Leroy p->thread.ksp_limit = (unsigned long)end_of_stack(p); 1729cbc9565eSBenjamin Herrenschmidt #endif 173028d170abSOleg Nesterov #ifdef CONFIG_HAVE_HW_BREAKPOINT 17316b424efaSRavi Bangoria for (i = 0; i < nr_wp_slots(); i++) 17326b424efaSRavi Bangoria p->thread.ptrace_bps[i] = NULL; 173328d170abSOleg Nesterov #endif 173428d170abSOleg Nesterov 1735b6254cedSChristophe Leroy #ifdef CONFIG_PPC_FPU_REGS 173618461960SPaul Mackerras p->thread.fp_save_area = NULL; 1737b6254cedSChristophe Leroy #endif 173818461960SPaul Mackerras #ifdef CONFIG_ALTIVEC 173918461960SPaul Mackerras p->thread.vr_save_area = NULL; 174018461960SPaul Mackerras #endif 174118461960SPaul Mackerras 1742cec15488SMichael Ellerman setup_ksp_vsid(p, sp); 174306d67d54SPaul Mackerras 1744efcac658SAlexey Kardashevskiy #ifdef CONFIG_PPC64 1745efcac658SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_DSCR)) { 17461021cb26SAnton Blanchard p->thread.dscr_inherit = current->thread.dscr_inherit; 1747db1231dcSAnton Blanchard p->thread.dscr = mfspr(SPRN_DSCR); 1748efcac658SAlexey Kardashevskiy } 174992779245SHaren Myneni if (cpu_has_feature(CPU_FTR_HAS_PPR)) 17504c2de74cSNicholas Piggin childregs->ppr = DEFAULT_PPR; 1751ec233edeSSukadev Bhattiprolu 1752ec233edeSSukadev Bhattiprolu p->thread.tidr = 0; 1753efcac658SAlexey Kardashevskiy #endif 1754f643fcabSAneesh Kumar K.V /* 1755f643fcabSAneesh Kumar K.V * Run with the current AMR value of the kernel 1756f643fcabSAneesh Kumar K.V */ 1757f643fcabSAneesh Kumar K.V #ifdef CONFIG_PPC_PKEY 1758f643fcabSAneesh Kumar K.V if (mmu_has_feature(MMU_FTR_BOOK3S_KUAP)) 1759f643fcabSAneesh Kumar K.V kregs->amr = AMR_KUAP_BLOCKED; 1760f643fcabSAneesh Kumar K.V 1761f643fcabSAneesh Kumar K.V if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) 1762f643fcabSAneesh Kumar K.V kregs->iamr = AMR_KUEP_BLOCKED; 1763f643fcabSAneesh Kumar K.V #endif 17647cedd601SAnton Blanchard kregs->nip = ppc_function_entry(f); 176514cf11afSPaul Mackerras return 0; 176614cf11afSPaul Mackerras } 176714cf11afSPaul Mackerras 17685434ae74SNicholas Piggin void preload_new_slb_context(unsigned long start, unsigned long sp); 17695434ae74SNicholas Piggin 177014cf11afSPaul Mackerras /* 177114cf11afSPaul Mackerras * Set up a thread for executing a new program 177214cf11afSPaul Mackerras */ 177306d67d54SPaul Mackerras void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 177414cf11afSPaul Mackerras { 177590eac727SMichael Ellerman #ifdef CONFIG_PPC64 177690eac727SMichael Ellerman unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 17775434ae74SNicholas Piggin 1778bfac2799SChristophe Leroy if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !radix_enabled()) 17795434ae74SNicholas Piggin preload_new_slb_context(start, sp); 17805434ae74SNicholas Piggin #endif 178190eac727SMichael Ellerman 17828e96a87cSCyril Bur #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 17838e96a87cSCyril Bur /* 17848e96a87cSCyril Bur * Clear any transactional state, we're exec()ing. The cause is 17858e96a87cSCyril Bur * not important as there will never be a recheckpoint so it's not 17868e96a87cSCyril Bur * user visible. 17878e96a87cSCyril Bur */ 17888e96a87cSCyril Bur if (MSR_TM_SUSPENDED(mfmsr())) 17898e96a87cSCyril Bur tm_reclaim_current(0); 17908e96a87cSCyril Bur #endif 17918e96a87cSCyril Bur 179214cf11afSPaul Mackerras memset(regs->gpr, 0, sizeof(regs->gpr)); 179314cf11afSPaul Mackerras regs->ctr = 0; 179414cf11afSPaul Mackerras regs->link = 0; 179514cf11afSPaul Mackerras regs->xer = 0; 179614cf11afSPaul Mackerras regs->ccr = 0; 179714cf11afSPaul Mackerras regs->gpr[1] = sp; 179806d67d54SPaul Mackerras 1799474f8196SRoland McGrath /* 1800474f8196SRoland McGrath * We have just cleared all the nonvolatile GPRs, so make 1801474f8196SRoland McGrath * FULL_REGS(regs) return true. This is necessary to allow 1802474f8196SRoland McGrath * ptrace to examine the thread immediately after exec. 1803474f8196SRoland McGrath */ 1804feb9df34SNicholas Piggin SET_FULL_REGS(regs); 1805474f8196SRoland McGrath 180606d67d54SPaul Mackerras #ifdef CONFIG_PPC32 180706d67d54SPaul Mackerras regs->mq = 0; 180806d67d54SPaul Mackerras regs->nip = start; 180914cf11afSPaul Mackerras regs->msr = MSR_USER; 181006d67d54SPaul Mackerras #else 18119904b005SDenis Kirjanov if (!is_32bit_task()) { 181294af3abfSRusty Russell unsigned long entry; 181306d67d54SPaul Mackerras 181494af3abfSRusty Russell if (is_elf2_task()) { 181594af3abfSRusty Russell /* Look ma, no function descriptors! */ 181694af3abfSRusty Russell entry = start; 181794af3abfSRusty Russell 181894af3abfSRusty Russell /* 181994af3abfSRusty Russell * Ulrich says: 182094af3abfSRusty Russell * The latest iteration of the ABI requires that when 182194af3abfSRusty Russell * calling a function (at its global entry point), 182294af3abfSRusty Russell * the caller must ensure r12 holds the entry point 182394af3abfSRusty Russell * address (so that the function can quickly 182494af3abfSRusty Russell * establish addressability). 182594af3abfSRusty Russell */ 182694af3abfSRusty Russell regs->gpr[12] = start; 182794af3abfSRusty Russell /* Make sure that's restored on entry to userspace. */ 182894af3abfSRusty Russell set_thread_flag(TIF_RESTOREALL); 182994af3abfSRusty Russell } else { 183094af3abfSRusty Russell unsigned long toc; 183194af3abfSRusty Russell 183294af3abfSRusty Russell /* start is a relocated pointer to the function 183394af3abfSRusty Russell * descriptor for the elf _start routine. The first 183494af3abfSRusty Russell * entry in the function descriptor is the entry 183594af3abfSRusty Russell * address of _start and the second entry is the TOC 183694af3abfSRusty Russell * value we need to use. 183706d67d54SPaul Mackerras */ 183806d67d54SPaul Mackerras __get_user(entry, (unsigned long __user *)start); 183906d67d54SPaul Mackerras __get_user(toc, (unsigned long __user *)start+1); 184006d67d54SPaul Mackerras 184106d67d54SPaul Mackerras /* Check whether the e_entry function descriptor entries 184206d67d54SPaul Mackerras * need to be relocated before we can use them. 184306d67d54SPaul Mackerras */ 184406d67d54SPaul Mackerras if (load_addr != 0) { 184506d67d54SPaul Mackerras entry += load_addr; 184606d67d54SPaul Mackerras toc += load_addr; 184706d67d54SPaul Mackerras } 184806d67d54SPaul Mackerras regs->gpr[2] = toc; 184994af3abfSRusty Russell } 185094af3abfSRusty Russell regs->nip = entry; 185106d67d54SPaul Mackerras regs->msr = MSR_USER64; 1852d4bf9a78SStephen Rothwell } else { 1853d4bf9a78SStephen Rothwell regs->nip = start; 1854d4bf9a78SStephen Rothwell regs->gpr[2] = 0; 1855d4bf9a78SStephen Rothwell regs->msr = MSR_USER32; 185606d67d54SPaul Mackerras } 185706d67d54SPaul Mackerras #endif 1858ce48b210SMichael Neuling #ifdef CONFIG_VSX 1859ce48b210SMichael Neuling current->thread.used_vsr = 0; 1860ce48b210SMichael Neuling #endif 18615434ae74SNicholas Piggin current->thread.load_slb = 0; 18621195892cSBreno Leitao current->thread.load_fp = 0; 1863b6254cedSChristophe Leroy #ifdef CONFIG_PPC_FPU_REGS 1864de79f7b9SPaul Mackerras memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 186518461960SPaul Mackerras current->thread.fp_save_area = NULL; 1866b6254cedSChristophe Leroy #endif 186714cf11afSPaul Mackerras #ifdef CONFIG_ALTIVEC 1868de79f7b9SPaul Mackerras memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1869de79f7b9SPaul Mackerras current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 187018461960SPaul Mackerras current->thread.vr_save_area = NULL; 187114cf11afSPaul Mackerras current->thread.vrsave = 0; 187214cf11afSPaul Mackerras current->thread.used_vr = 0; 18731195892cSBreno Leitao current->thread.load_vec = 0; 187414cf11afSPaul Mackerras #endif /* CONFIG_ALTIVEC */ 187514cf11afSPaul Mackerras #ifdef CONFIG_SPE 187614cf11afSPaul Mackerras memset(current->thread.evr, 0, sizeof(current->thread.evr)); 187714cf11afSPaul Mackerras current->thread.acc = 0; 187814cf11afSPaul Mackerras current->thread.spefscr = 0; 187914cf11afSPaul Mackerras current->thread.used_spe = 0; 188014cf11afSPaul Mackerras #endif /* CONFIG_SPE */ 1881bc2a9408SMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1882bc2a9408SMichael Neuling current->thread.tm_tfhar = 0; 1883bc2a9408SMichael Neuling current->thread.tm_texasr = 0; 1884bc2a9408SMichael Neuling current->thread.tm_tfiar = 0; 18857f22ced4SBreno Leitao current->thread.load_tm = 0; 1886bc2a9408SMichael Neuling #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 188706bb53b3SRam Pai 188814cf11afSPaul Mackerras } 1889e1802b06SAnton Blanchard EXPORT_SYMBOL(start_thread); 189014cf11afSPaul Mackerras 189114cf11afSPaul Mackerras #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 189214cf11afSPaul Mackerras | PR_FP_EXC_RES | PR_FP_EXC_INV) 189314cf11afSPaul Mackerras 189414cf11afSPaul Mackerras int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 189514cf11afSPaul Mackerras { 189614cf11afSPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 189714cf11afSPaul Mackerras 189814cf11afSPaul Mackerras /* This is a bit hairy. If we are an SPE enabled processor 189914cf11afSPaul Mackerras * (have embedded fp) we store the IEEE exception enable flags in 190014cf11afSPaul Mackerras * fpexc_mode. fpexc_mode is also used for setting FP exception 190114cf11afSPaul Mackerras * mode (asyn, precise, disabled) for 'Classic' FP. */ 190214cf11afSPaul Mackerras if (val & PR_FP_EXC_SW_ENABLE) { 19035e14d21eSKumar Gala if (cpu_has_feature(CPU_FTR_SPE)) { 1904640e9225SJoseph Myers /* 1905640e9225SJoseph Myers * When the sticky exception bits are set 1906640e9225SJoseph Myers * directly by userspace, it must call prctl 1907640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1908640e9225SJoseph Myers * in the existing prctl settings) or 1909640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1910640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1911640e9225SJoseph Myers * saving and restoring the whole 1912640e9225SJoseph Myers * floating-point environment need to do so 1913640e9225SJoseph Myers * anyway to restore the prctl settings from 1914640e9225SJoseph Myers * the saved environment. 1915640e9225SJoseph Myers */ 1916532ed190SChristophe Leroy #ifdef CONFIG_SPE 1917640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 191814cf11afSPaul Mackerras tsk->thread.fpexc_mode = val & 191914cf11afSPaul Mackerras (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1920532ed190SChristophe Leroy #endif 192106d67d54SPaul Mackerras return 0; 19225e14d21eSKumar Gala } else { 19235e14d21eSKumar Gala return -EINVAL; 19245e14d21eSKumar Gala } 192506d67d54SPaul Mackerras } 192606d67d54SPaul Mackerras 192714cf11afSPaul Mackerras /* on a CONFIG_SPE this does not hurt us. The bits that 192814cf11afSPaul Mackerras * __pack_fe01 use do not overlap with bits used for 192914cf11afSPaul Mackerras * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 193014cf11afSPaul Mackerras * on CONFIG_SPE implementations are reserved so writing to 193114cf11afSPaul Mackerras * them does not change anything */ 193214cf11afSPaul Mackerras if (val > PR_FP_EXC_PRECISE) 193314cf11afSPaul Mackerras return -EINVAL; 193414cf11afSPaul Mackerras tsk->thread.fpexc_mode = __pack_fe01(val); 193514cf11afSPaul Mackerras if (regs != NULL && (regs->msr & MSR_FP) != 0) 193614cf11afSPaul Mackerras regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 193714cf11afSPaul Mackerras | tsk->thread.fpexc_mode; 193814cf11afSPaul Mackerras return 0; 193914cf11afSPaul Mackerras } 194014cf11afSPaul Mackerras 194114cf11afSPaul Mackerras int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 194214cf11afSPaul Mackerras { 1943d208e13cSMichael Ellerman unsigned int val = 0; 194414cf11afSPaul Mackerras 1945532ed190SChristophe Leroy if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) { 1946640e9225SJoseph Myers if (cpu_has_feature(CPU_FTR_SPE)) { 1947640e9225SJoseph Myers /* 1948640e9225SJoseph Myers * When the sticky exception bits are set 1949640e9225SJoseph Myers * directly by userspace, it must call prctl 1950640e9225SJoseph Myers * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1951640e9225SJoseph Myers * in the existing prctl settings) or 1952640e9225SJoseph Myers * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1953640e9225SJoseph Myers * the bits being set). <fenv.h> functions 1954640e9225SJoseph Myers * saving and restoring the whole 1955640e9225SJoseph Myers * floating-point environment need to do so 1956640e9225SJoseph Myers * anyway to restore the prctl settings from 1957640e9225SJoseph Myers * the saved environment. 1958640e9225SJoseph Myers */ 1959532ed190SChristophe Leroy #ifdef CONFIG_SPE 1960640e9225SJoseph Myers tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 196114cf11afSPaul Mackerras val = tsk->thread.fpexc_mode; 1962532ed190SChristophe Leroy #endif 1963640e9225SJoseph Myers } else 19645e14d21eSKumar Gala return -EINVAL; 1965532ed190SChristophe Leroy } else { 196614cf11afSPaul Mackerras val = __unpack_fe01(tsk->thread.fpexc_mode); 1967532ed190SChristophe Leroy } 196814cf11afSPaul Mackerras return put_user(val, (unsigned int __user *) adr); 196914cf11afSPaul Mackerras } 197014cf11afSPaul Mackerras 1971fab5db97SPaul Mackerras int set_endian(struct task_struct *tsk, unsigned int val) 1972fab5db97SPaul Mackerras { 1973fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1974fab5db97SPaul Mackerras 1975fab5db97SPaul Mackerras if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1976fab5db97SPaul Mackerras (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1977fab5db97SPaul Mackerras return -EINVAL; 1978fab5db97SPaul Mackerras 1979fab5db97SPaul Mackerras if (regs == NULL) 1980fab5db97SPaul Mackerras return -EINVAL; 1981fab5db97SPaul Mackerras 1982fab5db97SPaul Mackerras if (val == PR_ENDIAN_BIG) 1983fab5db97SPaul Mackerras regs->msr &= ~MSR_LE; 1984fab5db97SPaul Mackerras else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1985fab5db97SPaul Mackerras regs->msr |= MSR_LE; 1986fab5db97SPaul Mackerras else 1987fab5db97SPaul Mackerras return -EINVAL; 1988fab5db97SPaul Mackerras 1989fab5db97SPaul Mackerras return 0; 1990fab5db97SPaul Mackerras } 1991fab5db97SPaul Mackerras 1992fab5db97SPaul Mackerras int get_endian(struct task_struct *tsk, unsigned long adr) 1993fab5db97SPaul Mackerras { 1994fab5db97SPaul Mackerras struct pt_regs *regs = tsk->thread.regs; 1995fab5db97SPaul Mackerras unsigned int val; 1996fab5db97SPaul Mackerras 1997fab5db97SPaul Mackerras if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1998fab5db97SPaul Mackerras !cpu_has_feature(CPU_FTR_REAL_LE)) 1999fab5db97SPaul Mackerras return -EINVAL; 2000fab5db97SPaul Mackerras 2001fab5db97SPaul Mackerras if (regs == NULL) 2002fab5db97SPaul Mackerras return -EINVAL; 2003fab5db97SPaul Mackerras 2004fab5db97SPaul Mackerras if (regs->msr & MSR_LE) { 2005fab5db97SPaul Mackerras if (cpu_has_feature(CPU_FTR_REAL_LE)) 2006fab5db97SPaul Mackerras val = PR_ENDIAN_LITTLE; 2007fab5db97SPaul Mackerras else 2008fab5db97SPaul Mackerras val = PR_ENDIAN_PPC_LITTLE; 2009fab5db97SPaul Mackerras } else 2010fab5db97SPaul Mackerras val = PR_ENDIAN_BIG; 2011fab5db97SPaul Mackerras 2012fab5db97SPaul Mackerras return put_user(val, (unsigned int __user *)adr); 2013fab5db97SPaul Mackerras } 2014fab5db97SPaul Mackerras 2015e9370ae1SPaul Mackerras int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 2016e9370ae1SPaul Mackerras { 2017e9370ae1SPaul Mackerras tsk->thread.align_ctl = val; 2018e9370ae1SPaul Mackerras return 0; 2019e9370ae1SPaul Mackerras } 2020e9370ae1SPaul Mackerras 2021e9370ae1SPaul Mackerras int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 2022e9370ae1SPaul Mackerras { 2023e9370ae1SPaul Mackerras return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 2024e9370ae1SPaul Mackerras } 2025e9370ae1SPaul Mackerras 2026bb72c481SPaul Mackerras static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 2027bb72c481SPaul Mackerras unsigned long nbytes) 2028bb72c481SPaul Mackerras { 2029bb72c481SPaul Mackerras unsigned long stack_page; 2030bb72c481SPaul Mackerras unsigned long cpu = task_cpu(p); 2031bb72c481SPaul Mackerras 2032bb72c481SPaul Mackerras stack_page = (unsigned long)hardirq_ctx[cpu]; 2033a7916a1dSChristophe Leroy if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2034bb72c481SPaul Mackerras return 1; 2035bb72c481SPaul Mackerras 2036bb72c481SPaul Mackerras stack_page = (unsigned long)softirq_ctx[cpu]; 2037a7916a1dSChristophe Leroy if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2038bb72c481SPaul Mackerras return 1; 2039a7916a1dSChristophe Leroy 2040bb72c481SPaul Mackerras return 0; 2041bb72c481SPaul Mackerras } 2042bb72c481SPaul Mackerras 2043a2e36683SNicholas Piggin static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p, 2044a2e36683SNicholas Piggin unsigned long nbytes) 2045a2e36683SNicholas Piggin { 2046a2e36683SNicholas Piggin #ifdef CONFIG_PPC64 2047a2e36683SNicholas Piggin unsigned long stack_page; 2048a2e36683SNicholas Piggin unsigned long cpu = task_cpu(p); 2049a2e36683SNicholas Piggin 2050a2e36683SNicholas Piggin stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE; 2051a2e36683SNicholas Piggin if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2052a2e36683SNicholas Piggin return 1; 2053a2e36683SNicholas Piggin 2054a2e36683SNicholas Piggin # ifdef CONFIG_PPC_BOOK3S_64 2055a2e36683SNicholas Piggin stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE; 2056a2e36683SNicholas Piggin if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2057a2e36683SNicholas Piggin return 1; 2058a2e36683SNicholas Piggin 2059a2e36683SNicholas Piggin stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE; 2060a2e36683SNicholas Piggin if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2061a2e36683SNicholas Piggin return 1; 2062a2e36683SNicholas Piggin # endif 2063a2e36683SNicholas Piggin #endif 2064a2e36683SNicholas Piggin 2065a2e36683SNicholas Piggin return 0; 2066a2e36683SNicholas Piggin } 2067a2e36683SNicholas Piggin 2068a2e36683SNicholas Piggin 20692f25194dSAnton Blanchard int validate_sp(unsigned long sp, struct task_struct *p, 207014cf11afSPaul Mackerras unsigned long nbytes) 207114cf11afSPaul Mackerras { 20720cec6fd1SAl Viro unsigned long stack_page = (unsigned long)task_stack_page(p); 207314cf11afSPaul Mackerras 2074a7916a1dSChristophe Leroy if (sp < THREAD_SIZE) 2075a7916a1dSChristophe Leroy return 0; 2076a7916a1dSChristophe Leroy 2077a7916a1dSChristophe Leroy if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 207814cf11afSPaul Mackerras return 1; 207914cf11afSPaul Mackerras 2080a2e36683SNicholas Piggin if (valid_irq_stack(sp, p, nbytes)) 2081a2e36683SNicholas Piggin return 1; 2082a2e36683SNicholas Piggin 2083a2e36683SNicholas Piggin return valid_emergency_stack(sp, p, nbytes); 208414cf11afSPaul Mackerras } 208514cf11afSPaul Mackerras 20862f25194dSAnton Blanchard EXPORT_SYMBOL(validate_sp); 20872f25194dSAnton Blanchard 2088018cce33SChristophe Leroy static unsigned long __get_wchan(struct task_struct *p) 208906d67d54SPaul Mackerras { 209006d67d54SPaul Mackerras unsigned long ip, sp; 209106d67d54SPaul Mackerras int count = 0; 209206d67d54SPaul Mackerras 209306d67d54SPaul Mackerras if (!p || p == current || p->state == TASK_RUNNING) 209406d67d54SPaul Mackerras return 0; 209506d67d54SPaul Mackerras 209606d67d54SPaul Mackerras sp = p->thread.ksp; 2097ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 209806d67d54SPaul Mackerras return 0; 209906d67d54SPaul Mackerras 210006d67d54SPaul Mackerras do { 210106d67d54SPaul Mackerras sp = *(unsigned long *)sp; 21024ca360f3SKautuk Consul if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) || 21034ca360f3SKautuk Consul p->state == TASK_RUNNING) 210406d67d54SPaul Mackerras return 0; 210506d67d54SPaul Mackerras if (count > 0) { 2106ec2b36b9SBenjamin Herrenschmidt ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 210706d67d54SPaul Mackerras if (!in_sched_functions(ip)) 210806d67d54SPaul Mackerras return ip; 210906d67d54SPaul Mackerras } 211006d67d54SPaul Mackerras } while (count++ < 16); 211106d67d54SPaul Mackerras return 0; 211206d67d54SPaul Mackerras } 211306d67d54SPaul Mackerras 2114018cce33SChristophe Leroy unsigned long get_wchan(struct task_struct *p) 2115018cce33SChristophe Leroy { 2116018cce33SChristophe Leroy unsigned long ret; 2117018cce33SChristophe Leroy 2118018cce33SChristophe Leroy if (!try_get_task_stack(p)) 2119018cce33SChristophe Leroy return 0; 2120018cce33SChristophe Leroy 2121018cce33SChristophe Leroy ret = __get_wchan(p); 2122018cce33SChristophe Leroy 2123018cce33SChristophe Leroy put_task_stack(p); 2124018cce33SChristophe Leroy 2125018cce33SChristophe Leroy return ret; 2126018cce33SChristophe Leroy } 2127018cce33SChristophe Leroy 2128c4d04be1SJohannes Berg static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 212914cf11afSPaul Mackerras 21309cb8f069SDmitry Safonov void show_stack(struct task_struct *tsk, unsigned long *stack, 2131b9677a8cSDmitry Safonov const char *loglvl) 213214cf11afSPaul Mackerras { 213306d67d54SPaul Mackerras unsigned long sp, ip, lr, newsp; 213414cf11afSPaul Mackerras int count = 0; 213506d67d54SPaul Mackerras int firstframe = 1; 21367c1bb6bbSNaveen N. Rao unsigned long ret_addr; 21377c1bb6bbSNaveen N. Rao int ftrace_idx = 0; 213814cf11afSPaul Mackerras 213914cf11afSPaul Mackerras if (tsk == NULL) 214014cf11afSPaul Mackerras tsk = current; 2141018cce33SChristophe Leroy 2142018cce33SChristophe Leroy if (!try_get_task_stack(tsk)) 2143018cce33SChristophe Leroy return; 2144018cce33SChristophe Leroy 2145018cce33SChristophe Leroy sp = (unsigned long) stack; 214614cf11afSPaul Mackerras if (sp == 0) { 214714cf11afSPaul Mackerras if (tsk == current) 21483d13e839SMichael Ellerman sp = current_stack_frame(); 214914cf11afSPaul Mackerras else 215014cf11afSPaul Mackerras sp = tsk->thread.ksp; 215114cf11afSPaul Mackerras } 215214cf11afSPaul Mackerras 215306d67d54SPaul Mackerras lr = 0; 2154b9677a8cSDmitry Safonov printk("%sCall Trace:\n", loglvl); 215514cf11afSPaul Mackerras do { 2156ec2b36b9SBenjamin Herrenschmidt if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 2157018cce33SChristophe Leroy break; 215806d67d54SPaul Mackerras 215906d67d54SPaul Mackerras stack = (unsigned long *) sp; 216006d67d54SPaul Mackerras newsp = stack[0]; 2161ec2b36b9SBenjamin Herrenschmidt ip = stack[STACK_FRAME_LR_SAVE]; 216206d67d54SPaul Mackerras if (!firstframe || ip != lr) { 2163b9677a8cSDmitry Safonov printk("%s["REG"] ["REG"] %pS", 2164b9677a8cSDmitry Safonov loglvl, sp, ip, (void *)ip); 21657c1bb6bbSNaveen N. Rao ret_addr = ftrace_graph_ret_addr(current, 21667c1bb6bbSNaveen N. Rao &ftrace_idx, ip, stack); 21677c1bb6bbSNaveen N. Rao if (ret_addr != ip) 21687c1bb6bbSNaveen N. Rao pr_cont(" (%pS)", (void *)ret_addr); 216906d67d54SPaul Mackerras if (firstframe) 21709a1f490fSMichael Ellerman pr_cont(" (unreliable)"); 21719a1f490fSMichael Ellerman pr_cont("\n"); 217214cf11afSPaul Mackerras } 217306d67d54SPaul Mackerras firstframe = 0; 217406d67d54SPaul Mackerras 217506d67d54SPaul Mackerras /* 217606d67d54SPaul Mackerras * See if this is an exception frame. 217706d67d54SPaul Mackerras * We look for the "regshere" marker in the current frame. 217806d67d54SPaul Mackerras */ 2179ec2b36b9SBenjamin Herrenschmidt if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 2180ec2b36b9SBenjamin Herrenschmidt && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 218106d67d54SPaul Mackerras struct pt_regs *regs = (struct pt_regs *) 218206d67d54SPaul Mackerras (sp + STACK_FRAME_OVERHEAD); 2183bf13718bSNicholas Piggin 218406d67d54SPaul Mackerras lr = regs->link; 2185bf13718bSNicholas Piggin printk("%s--- interrupt: %lx at %pS\n", 2186bf13718bSNicholas Piggin loglvl, regs->trap, (void *)regs->nip); 2187bf13718bSNicholas Piggin __show_regs(regs); 2188bf13718bSNicholas Piggin printk("%s--- interrupt: %lx\n", 2189bf13718bSNicholas Piggin loglvl, regs->trap); 2190bf13718bSNicholas Piggin 219106d67d54SPaul Mackerras firstframe = 1; 219214cf11afSPaul Mackerras } 219306d67d54SPaul Mackerras 219406d67d54SPaul Mackerras sp = newsp; 219506d67d54SPaul Mackerras } while (count++ < kstack_depth_to_print); 2196018cce33SChristophe Leroy 2197018cce33SChristophe Leroy put_task_stack(tsk); 219806d67d54SPaul Mackerras } 219906d67d54SPaul Mackerras 2200cb2c9b27SAnton Blanchard #ifdef CONFIG_PPC64 2201fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 22020e37739bSMichael Ellerman void notrace __ppc64_runlatch_on(void) 2203cb2c9b27SAnton Blanchard { 2204fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2205d1d0d5ffSNicholas Piggin 2206d1d0d5ffSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2207d1d0d5ffSNicholas Piggin /* 2208d1d0d5ffSNicholas Piggin * Least significant bit (RUN) is the only writable bit of 2209d1d0d5ffSNicholas Piggin * the CTRL register, so we can avoid mfspr. 2.06 is not the 2210d1d0d5ffSNicholas Piggin * earliest ISA where this is the case, but it's convenient. 2211d1d0d5ffSNicholas Piggin */ 2212d1d0d5ffSNicholas Piggin mtspr(SPRN_CTRLT, CTRL_RUNLATCH); 2213d1d0d5ffSNicholas Piggin } else { 2214cb2c9b27SAnton Blanchard unsigned long ctrl; 2215cb2c9b27SAnton Blanchard 2216d1d0d5ffSNicholas Piggin /* 2217d1d0d5ffSNicholas Piggin * Some architectures (e.g., Cell) have writable fields other 2218d1d0d5ffSNicholas Piggin * than RUN, so do the read-modify-write. 2219d1d0d5ffSNicholas Piggin */ 2220cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2221cb2c9b27SAnton Blanchard ctrl |= CTRL_RUNLATCH; 2222cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2223d1d0d5ffSNicholas Piggin } 2224cb2c9b27SAnton Blanchard 2225fae2e0fbSBenjamin Herrenschmidt ti->local_flags |= _TLF_RUNLATCH; 2226cb2c9b27SAnton Blanchard } 2227cb2c9b27SAnton Blanchard 2228fe1952fcSBenjamin Herrenschmidt /* Called with hard IRQs off */ 22290e37739bSMichael Ellerman void notrace __ppc64_runlatch_off(void) 2230cb2c9b27SAnton Blanchard { 2231fe1952fcSBenjamin Herrenschmidt struct thread_info *ti = current_thread_info(); 2232cb2c9b27SAnton Blanchard 2233fae2e0fbSBenjamin Herrenschmidt ti->local_flags &= ~_TLF_RUNLATCH; 2234cb2c9b27SAnton Blanchard 2235d1d0d5ffSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2236d1d0d5ffSNicholas Piggin mtspr(SPRN_CTRLT, 0); 2237d1d0d5ffSNicholas Piggin } else { 2238d1d0d5ffSNicholas Piggin unsigned long ctrl; 2239d1d0d5ffSNicholas Piggin 2240cb2c9b27SAnton Blanchard ctrl = mfspr(SPRN_CTRLF); 2241cb2c9b27SAnton Blanchard ctrl &= ~CTRL_RUNLATCH; 2242cb2c9b27SAnton Blanchard mtspr(SPRN_CTRLT, ctrl); 2243cb2c9b27SAnton Blanchard } 2244d1d0d5ffSNicholas Piggin } 2245fe1952fcSBenjamin Herrenschmidt #endif /* CONFIG_PPC64 */ 2246f6a61680SBenjamin Herrenschmidt 2247d839088cSAnton Blanchard unsigned long arch_align_stack(unsigned long sp) 2248d839088cSAnton Blanchard { 2249d839088cSAnton Blanchard if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 2250d839088cSAnton Blanchard sp -= get_random_int() & ~PAGE_MASK; 2251d839088cSAnton Blanchard return sp & ~0xf; 2252d839088cSAnton Blanchard } 2253912f9ee2SAnton Blanchard 2254912f9ee2SAnton Blanchard static inline unsigned long brk_rnd(void) 2255912f9ee2SAnton Blanchard { 2256912f9ee2SAnton Blanchard unsigned long rnd = 0; 2257912f9ee2SAnton Blanchard 2258912f9ee2SAnton Blanchard /* 8MB for 32bit, 1GB for 64bit */ 2259912f9ee2SAnton Blanchard if (is_32bit_task()) 22605ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 2261912f9ee2SAnton Blanchard else 22625ef11c35SDaniel Cashman rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 2263912f9ee2SAnton Blanchard 2264912f9ee2SAnton Blanchard return rnd << PAGE_SHIFT; 2265912f9ee2SAnton Blanchard } 2266912f9ee2SAnton Blanchard 2267912f9ee2SAnton Blanchard unsigned long arch_randomize_brk(struct mm_struct *mm) 2268912f9ee2SAnton Blanchard { 22698bbde7a7SAnton Blanchard unsigned long base = mm->brk; 22708bbde7a7SAnton Blanchard unsigned long ret; 22718bbde7a7SAnton Blanchard 22724e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 22738bbde7a7SAnton Blanchard /* 22748bbde7a7SAnton Blanchard * If we are using 1TB segments and we are allowed to randomise 22758bbde7a7SAnton Blanchard * the heap, we can put it above 1TB so it is backed by a 1TB 22768bbde7a7SAnton Blanchard * segment. Otherwise the heap will be in the bottom 1TB 22778bbde7a7SAnton Blanchard * which always uses 256MB segments and this may result in a 2278caca285eSAneesh Kumar K.V * performance penalty. We don't need to worry about radix. For 2279caca285eSAneesh Kumar K.V * radix, mmu_highuser_ssize remains unchanged from 256MB. 22808bbde7a7SAnton Blanchard */ 22818bbde7a7SAnton Blanchard if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 22828bbde7a7SAnton Blanchard base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 22838bbde7a7SAnton Blanchard #endif 22848bbde7a7SAnton Blanchard 22858bbde7a7SAnton Blanchard ret = PAGE_ALIGN(base + brk_rnd()); 2286912f9ee2SAnton Blanchard 2287912f9ee2SAnton Blanchard if (ret < mm->brk) 2288912f9ee2SAnton Blanchard return mm->brk; 2289912f9ee2SAnton Blanchard 2290912f9ee2SAnton Blanchard return ret; 2291912f9ee2SAnton Blanchard } 2292501cb16dSAnton Blanchard 2293