1 /* 2 * Port for PPC64 David Engebretsen, IBM Corp. 3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 4 * 5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 6 * Rework, based on alpha PCI code. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #undef DEBUG 15 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/string.h> 19 #include <linux/init.h> 20 #include <linux/bootmem.h> 21 #include <linux/export.h> 22 #include <linux/mm.h> 23 #include <linux/list.h> 24 #include <linux/syscalls.h> 25 #include <linux/irq.h> 26 #include <linux/vmalloc.h> 27 28 #include <asm/processor.h> 29 #include <asm/io.h> 30 #include <asm/prom.h> 31 #include <asm/pci-bridge.h> 32 #include <asm/byteorder.h> 33 #include <asm/machdep.h> 34 #include <asm/ppc-pci.h> 35 36 unsigned long pci_probe_only = 1; 37 38 /* pci_io_base -- the base address from which io bars are offsets. 39 * This is the lowest I/O base address (so bar values are always positive), 40 * and it *must* be the start of ISA space if an ISA bus exists because 41 * ISA drivers use hard coded offsets. If no ISA bus exists nothing 42 * is mapped on the first 64K of IO space 43 */ 44 unsigned long pci_io_base = ISA_IO_BASE; 45 EXPORT_SYMBOL(pci_io_base); 46 47 static int __init pcibios_init(void) 48 { 49 struct pci_controller *hose, *tmp; 50 51 printk(KERN_INFO "PCI: Probing PCI hardware\n"); 52 53 /* For now, override phys_mem_access_prot. If we need it,g 54 * later, we may move that initialization to each ppc_md 55 */ 56 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 57 58 if (pci_probe_only) 59 pci_add_flags(PCI_PROBE_ONLY); 60 61 /* On ppc64, we always enable PCI domains and we keep domain 0 62 * backward compatible in /proc for video cards 63 */ 64 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); 65 66 /* Scan all of the recorded PCI controllers. */ 67 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 68 pcibios_scan_phb(hose); 69 pci_bus_add_devices(hose->bus); 70 } 71 72 /* Call common code to handle resource allocation */ 73 pcibios_resource_survey(); 74 75 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); 76 77 return 0; 78 } 79 80 subsys_initcall(pcibios_init); 81 82 #ifdef CONFIG_HOTPLUG 83 84 int pcibios_unmap_io_space(struct pci_bus *bus) 85 { 86 struct pci_controller *hose; 87 88 WARN_ON(bus == NULL); 89 90 /* If this is not a PHB, we only flush the hash table over 91 * the area mapped by this bridge. We don't play with the PTE 92 * mappings since we might have to deal with sub-page alignemnts 93 * so flushing the hash table is the only sane way to make sure 94 * that no hash entries are covering that removed bridge area 95 * while still allowing other busses overlapping those pages 96 * 97 * Note: If we ever support P2P hotplug on Book3E, we'll have 98 * to do an appropriate TLB flush here too 99 */ 100 if (bus->self) { 101 #ifdef CONFIG_PPC_STD_MMU_64 102 struct resource *res = bus->resource[0]; 103 #endif 104 105 pr_debug("IO unmapping for PCI-PCI bridge %s\n", 106 pci_name(bus->self)); 107 108 #ifdef CONFIG_PPC_STD_MMU_64 109 __flush_hash_table_range(&init_mm, res->start + _IO_BASE, 110 res->end + _IO_BASE + 1); 111 #endif 112 return 0; 113 } 114 115 /* Get the host bridge */ 116 hose = pci_bus_to_host(bus); 117 118 /* Check if we have IOs allocated */ 119 if (hose->io_base_alloc == 0) 120 return 0; 121 122 pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name); 123 pr_debug(" alloc=0x%p\n", hose->io_base_alloc); 124 125 /* This is a PHB, we fully unmap the IO area */ 126 vunmap(hose->io_base_alloc); 127 128 return 0; 129 } 130 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space); 131 132 #endif /* CONFIG_HOTPLUG */ 133 134 int __devinit pcibios_map_io_space(struct pci_bus *bus) 135 { 136 struct vm_struct *area; 137 unsigned long phys_page; 138 unsigned long size_page; 139 unsigned long io_virt_offset; 140 struct pci_controller *hose; 141 142 WARN_ON(bus == NULL); 143 144 /* If this not a PHB, nothing to do, page tables still exist and 145 * thus HPTEs will be faulted in when needed 146 */ 147 if (bus->self) { 148 pr_debug("IO mapping for PCI-PCI bridge %s\n", 149 pci_name(bus->self)); 150 pr_debug(" virt=0x%016llx...0x%016llx\n", 151 bus->resource[0]->start + _IO_BASE, 152 bus->resource[0]->end + _IO_BASE); 153 return 0; 154 } 155 156 /* Get the host bridge */ 157 hose = pci_bus_to_host(bus); 158 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); 159 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); 160 161 /* Make sure IO area address is clear */ 162 hose->io_base_alloc = NULL; 163 164 /* If there's no IO to map on that bus, get away too */ 165 if (hose->pci_io_size == 0 || hose->io_base_phys == 0) 166 return 0; 167 168 /* Let's allocate some IO space for that guy. We don't pass 169 * VM_IOREMAP because we don't care about alignment tricks that 170 * the core does in that case. Maybe we should due to stupid card 171 * with incomplete address decoding but I'd rather not deal with 172 * those outside of the reserved 64K legacy region. 173 */ 174 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END); 175 if (area == NULL) 176 return -ENOMEM; 177 hose->io_base_alloc = area->addr; 178 hose->io_base_virt = (void __iomem *)(area->addr + 179 hose->io_base_phys - phys_page); 180 181 pr_debug("IO mapping for PHB %s\n", hose->dn->full_name); 182 pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n", 183 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); 184 pr_debug(" size=0x%016llx (alloc=0x%016lx)\n", 185 hose->pci_io_size, size_page); 186 187 /* Establish the mapping */ 188 if (__ioremap_at(phys_page, area->addr, size_page, 189 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL) 190 return -ENOMEM; 191 192 /* Fixup hose IO resource */ 193 io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 194 hose->io_resource.start += io_virt_offset; 195 hose->io_resource.end += io_virt_offset; 196 197 pr_debug(" hose->io_resource=%pR\n", &hose->io_resource); 198 199 return 0; 200 } 201 EXPORT_SYMBOL_GPL(pcibios_map_io_space); 202 203 void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose) 204 { 205 pcibios_map_io_space(hose->bus); 206 } 207 208 #define IOBASE_BRIDGE_NUMBER 0 209 #define IOBASE_MEMORY 1 210 #define IOBASE_IO 2 211 #define IOBASE_ISA_IO 3 212 #define IOBASE_ISA_MEM 4 213 214 long sys_pciconfig_iobase(long which, unsigned long in_bus, 215 unsigned long in_devfn) 216 { 217 struct pci_controller* hose; 218 struct list_head *ln; 219 struct pci_bus *bus = NULL; 220 struct device_node *hose_node; 221 222 /* Argh ! Please forgive me for that hack, but that's the 223 * simplest way to get existing XFree to not lockup on some 224 * G5 machines... So when something asks for bus 0 io base 225 * (bus 0 is HT root), we return the AGP one instead. 226 */ 227 if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) { 228 struct device_node *agp; 229 230 agp = of_find_compatible_node(NULL, NULL, "u3-agp"); 231 if (agp) 232 in_bus = 0xf0; 233 of_node_put(agp); 234 } 235 236 /* That syscall isn't quite compatible with PCI domains, but it's 237 * used on pre-domains setup. We return the first match 238 */ 239 240 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { 241 bus = pci_bus_b(ln); 242 if (in_bus >= bus->number && in_bus <= bus->subordinate) 243 break; 244 bus = NULL; 245 } 246 if (bus == NULL || bus->dev.of_node == NULL) 247 return -ENODEV; 248 249 hose_node = bus->dev.of_node; 250 hose = PCI_DN(hose_node)->phb; 251 252 switch (which) { 253 case IOBASE_BRIDGE_NUMBER: 254 return (long)hose->first_busno; 255 case IOBASE_MEMORY: 256 return (long)hose->pci_mem_offset; 257 case IOBASE_IO: 258 return (long)hose->io_base_phys; 259 case IOBASE_ISA_IO: 260 return (long)isa_io_base; 261 case IOBASE_ISA_MEM: 262 return -EINVAL; 263 } 264 265 return -EOPNOTSUPP; 266 } 267 268 #ifdef CONFIG_NUMA 269 int pcibus_to_node(struct pci_bus *bus) 270 { 271 struct pci_controller *phb = pci_bus_to_host(bus); 272 return phb->node; 273 } 274 EXPORT_SYMBOL(pcibus_to_node); 275 #endif 276