12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 27568cb4eSPaul Mackerras /* 37568cb4eSPaul Mackerras * Port for PPC64 David Engebretsen, IBM Corp. 47568cb4eSPaul Mackerras * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 57568cb4eSPaul Mackerras * 67568cb4eSPaul Mackerras * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 77568cb4eSPaul Mackerras * Rework, based on alpha PCI code. 87568cb4eSPaul Mackerras */ 97568cb4eSPaul Mackerras 107568cb4eSPaul Mackerras #undef DEBUG 117568cb4eSPaul Mackerras 127568cb4eSPaul Mackerras #include <linux/kernel.h> 137568cb4eSPaul Mackerras #include <linux/pci.h> 147568cb4eSPaul Mackerras #include <linux/string.h> 157568cb4eSPaul Mackerras #include <linux/init.h> 1666b15db6SPaul Gortmaker #include <linux/export.h> 177568cb4eSPaul Mackerras #include <linux/mm.h> 187568cb4eSPaul Mackerras #include <linux/list.h> 197568cb4eSPaul Mackerras #include <linux/syscalls.h> 206e99e458SBenjamin Herrenschmidt #include <linux/irq.h> 213d5134eeSBenjamin Herrenschmidt #include <linux/vmalloc.h> 227568cb4eSPaul Mackerras 237568cb4eSPaul Mackerras #include <asm/processor.h> 247568cb4eSPaul Mackerras #include <asm/io.h> 257568cb4eSPaul Mackerras #include <asm/prom.h> 267568cb4eSPaul Mackerras #include <asm/pci-bridge.h> 277568cb4eSPaul Mackerras #include <asm/byteorder.h> 287568cb4eSPaul Mackerras #include <asm/machdep.h> 297568cb4eSPaul Mackerras #include <asm/ppc-pci.h> 307568cb4eSPaul Mackerras 317568cb4eSPaul Mackerras /* pci_io_base -- the base address from which io bars are offsets. 327568cb4eSPaul Mackerras * This is the lowest I/O base address (so bar values are always positive), 337568cb4eSPaul Mackerras * and it *must* be the start of ISA space if an ISA bus exists because 343d5134eeSBenjamin Herrenschmidt * ISA drivers use hard coded offsets. If no ISA bus exists nothing 353d5134eeSBenjamin Herrenschmidt * is mapped on the first 64K of IO space 367568cb4eSPaul Mackerras */ 37d6a9996eSAneesh Kumar K.V unsigned long pci_io_base; 387568cb4eSPaul Mackerras EXPORT_SYMBOL(pci_io_base); 397568cb4eSPaul Mackerras 407568cb4eSPaul Mackerras static int __init pcibios_init(void) 417568cb4eSPaul Mackerras { 427568cb4eSPaul Mackerras struct pci_controller *hose, *tmp; 437568cb4eSPaul Mackerras 443fd94c6bSBenjamin Herrenschmidt printk(KERN_INFO "PCI: Probing PCI hardware\n"); 453fd94c6bSBenjamin Herrenschmidt 4653280323SBenjamin Herrenschmidt /* For now, override phys_mem_access_prot. If we need it,g 477568cb4eSPaul Mackerras * later, we may move that initialization to each ppc_md 487568cb4eSPaul Mackerras */ 497568cb4eSPaul Mackerras ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 507568cb4eSPaul Mackerras 511fd0f525SBenjamin Herrenschmidt /* On ppc64, we always enable PCI domains and we keep domain 0 521fd0f525SBenjamin Herrenschmidt * backward compatible in /proc for video cards 531fd0f525SBenjamin Herrenschmidt */ 540e47ff1cSRob Herring pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); 551fd0f525SBenjamin Herrenschmidt 567568cb4eSPaul Mackerras /* Scan all of the recorded PCI controllers. */ 573f068aaeSSam Bobroff list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 58b5d937deSGrant Likely pcibios_scan_phb(hose); 597568cb4eSPaul Mackerras 603fd94c6bSBenjamin Herrenschmidt /* Call common code to handle resource allocation */ 613fd94c6bSBenjamin Herrenschmidt pcibios_resource_survey(); 627568cb4eSPaul Mackerras 633f068aaeSSam Bobroff /* Add devices. */ 643f068aaeSSam Bobroff list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 653f068aaeSSam Bobroff pci_bus_add_devices(hose->bus); 663f068aaeSSam Bobroff 673f068aaeSSam Bobroff /* Call machine dependent fixup */ 683f068aaeSSam Bobroff if (ppc_md.pcibios_fixup) 693f068aaeSSam Bobroff ppc_md.pcibios_fixup(); 703f068aaeSSam Bobroff 71e884e9c5SOlof Johansson printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); 727568cb4eSPaul Mackerras 737568cb4eSPaul Mackerras return 0; 747568cb4eSPaul Mackerras } 757568cb4eSPaul Mackerras 767568cb4eSPaul Mackerras subsys_initcall(pcibios_init); 777568cb4eSPaul Mackerras 783d5134eeSBenjamin Herrenschmidt int pcibios_unmap_io_space(struct pci_bus *bus) 797568cb4eSPaul Mackerras { 803d5134eeSBenjamin Herrenschmidt struct pci_controller *hose; 817568cb4eSPaul Mackerras 823d5134eeSBenjamin Herrenschmidt WARN_ON(bus == NULL); 83de821204SBenjamin Herrenschmidt 843d5134eeSBenjamin Herrenschmidt /* If this is not a PHB, we only flush the hash table over 853d5134eeSBenjamin Herrenschmidt * the area mapped by this bridge. We don't play with the PTE 86027dfac6SMichael Ellerman * mappings since we might have to deal with sub-page alignments 873d5134eeSBenjamin Herrenschmidt * so flushing the hash table is the only sane way to make sure 883d5134eeSBenjamin Herrenschmidt * that no hash entries are covering that removed bridge area 893d5134eeSBenjamin Herrenschmidt * while still allowing other busses overlapping those pages 9094491685SBenjamin Herrenschmidt * 9194491685SBenjamin Herrenschmidt * Note: If we ever support P2P hotplug on Book3E, we'll have 9294491685SBenjamin Herrenschmidt * to do an appropriate TLB flush here too 93de821204SBenjamin Herrenschmidt */ 943d5134eeSBenjamin Herrenschmidt if (bus->self) { 954e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 963d5134eeSBenjamin Herrenschmidt struct resource *res = bus->resource[0]; 97ce7a35c7SKumar Gala #endif 983d5134eeSBenjamin Herrenschmidt 99b0494bc8SBenjamin Herrenschmidt pr_debug("IO unmapping for PCI-PCI bridge %s\n", 1003d5134eeSBenjamin Herrenschmidt pci_name(bus->self)); 1013d5134eeSBenjamin Herrenschmidt 1024e003747SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_64 1033d5134eeSBenjamin Herrenschmidt __flush_hash_table_range(&init_mm, res->start + _IO_BASE, 104b30115eaSBenjamin Herrenschmidt res->end + _IO_BASE + 1); 10594491685SBenjamin Herrenschmidt #endif 1063d5134eeSBenjamin Herrenschmidt return 0; 1077568cb4eSPaul Mackerras } 1087568cb4eSPaul Mackerras 1093d5134eeSBenjamin Herrenschmidt /* Get the host bridge */ 1103d5134eeSBenjamin Herrenschmidt hose = pci_bus_to_host(bus); 1113d5134eeSBenjamin Herrenschmidt 112b7c670d6SRob Herring pr_debug("IO unmapping for PHB %pOF\n", hose->dn); 113b0494bc8SBenjamin Herrenschmidt pr_debug(" alloc=0x%p\n", hose->io_base_alloc); 1143d5134eeSBenjamin Herrenschmidt 115*b274014cSChristoph Hellwig iounmap(hose->io_base_alloc); 1163d5134eeSBenjamin Herrenschmidt return 0; 1173d5134eeSBenjamin Herrenschmidt } 1183d5134eeSBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(pcibios_unmap_io_space); 1193d5134eeSBenjamin Herrenschmidt 120*b274014cSChristoph Hellwig void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size) 1217568cb4eSPaul Mackerras { 1223d5134eeSBenjamin Herrenschmidt struct vm_struct *area; 123*b274014cSChristoph Hellwig unsigned long addr; 124*b274014cSChristoph Hellwig 125*b274014cSChristoph Hellwig WARN_ON_ONCE(paddr & ~PAGE_MASK); 126*b274014cSChristoph Hellwig WARN_ON_ONCE(size & ~PAGE_MASK); 127*b274014cSChristoph Hellwig 128*b274014cSChristoph Hellwig /* 129*b274014cSChristoph Hellwig * Let's allocate some IO space for that guy. We don't pass VM_IOREMAP 130*b274014cSChristoph Hellwig * because we don't care about alignment tricks that the core does in 131*b274014cSChristoph Hellwig * that case. Maybe we should due to stupid card with incomplete 132*b274014cSChristoph Hellwig * address decoding but I'd rather not deal with those outside of the 133*b274014cSChristoph Hellwig * reserved 64K legacy region. 134*b274014cSChristoph Hellwig */ 135*b274014cSChristoph Hellwig area = __get_vm_area(size, 0, PHB_IO_BASE, PHB_IO_END); 136*b274014cSChristoph Hellwig if (!area) 137*b274014cSChristoph Hellwig return NULL; 138*b274014cSChristoph Hellwig 139*b274014cSChristoph Hellwig addr = (unsigned long)area->addr; 140*b274014cSChristoph Hellwig if (ioremap_page_range(addr, addr + size, paddr, 141*b274014cSChristoph Hellwig pgprot_noncached(PAGE_KERNEL))) { 142*b274014cSChristoph Hellwig unmap_kernel_range(addr, size); 143*b274014cSChristoph Hellwig return NULL; 144*b274014cSChristoph Hellwig } 145*b274014cSChristoph Hellwig 146*b274014cSChristoph Hellwig return (void __iomem *)addr; 147*b274014cSChristoph Hellwig } 148*b274014cSChristoph Hellwig EXPORT_SYMBOL_GPL(ioremap_phb); 149*b274014cSChristoph Hellwig 150*b274014cSChristoph Hellwig static int pcibios_map_phb_io_space(struct pci_controller *hose) 151*b274014cSChristoph Hellwig { 1523d5134eeSBenjamin Herrenschmidt unsigned long phys_page; 1533d5134eeSBenjamin Herrenschmidt unsigned long size_page; 1547568cb4eSPaul Mackerras unsigned long io_virt_offset; 1557568cb4eSPaul Mackerras 1563d5134eeSBenjamin Herrenschmidt phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); 1573d5134eeSBenjamin Herrenschmidt size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); 1587568cb4eSPaul Mackerras 1593d5134eeSBenjamin Herrenschmidt /* Make sure IO area address is clear */ 1603d5134eeSBenjamin Herrenschmidt hose->io_base_alloc = NULL; 1617568cb4eSPaul Mackerras 1623d5134eeSBenjamin Herrenschmidt /* If there's no IO to map on that bus, get away too */ 1633d5134eeSBenjamin Herrenschmidt if (hose->pci_io_size == 0 || hose->io_base_phys == 0) 1643d5134eeSBenjamin Herrenschmidt return 0; 1653d5134eeSBenjamin Herrenschmidt 1663d5134eeSBenjamin Herrenschmidt /* Let's allocate some IO space for that guy. We don't pass 1673d5134eeSBenjamin Herrenschmidt * VM_IOREMAP because we don't care about alignment tricks that 1683d5134eeSBenjamin Herrenschmidt * the core does in that case. Maybe we should due to stupid card 1693d5134eeSBenjamin Herrenschmidt * with incomplete address decoding but I'd rather not deal with 1703d5134eeSBenjamin Herrenschmidt * those outside of the reserved 64K legacy region. 1713d5134eeSBenjamin Herrenschmidt */ 172*b274014cSChristoph Hellwig hose->io_base_alloc = ioremap_phb(phys_page, size_page); 173*b274014cSChristoph Hellwig if (!hose->io_base_alloc) 1743d5134eeSBenjamin Herrenschmidt return -ENOMEM; 175*b274014cSChristoph Hellwig hose->io_base_virt = hose->io_base_alloc + 176*b274014cSChristoph Hellwig hose->io_base_phys - phys_page; 1773d5134eeSBenjamin Herrenschmidt 178b7c670d6SRob Herring pr_debug("IO mapping for PHB %pOF\n", hose->dn); 1799477e455SStephen Rothwell pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n", 1803d5134eeSBenjamin Herrenschmidt hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); 181bcba0778SStephen Rothwell pr_debug(" size=0x%016llx (alloc=0x%016lx)\n", 1823d5134eeSBenjamin Herrenschmidt hose->pci_io_size, size_page); 1833d5134eeSBenjamin Herrenschmidt 1843d5134eeSBenjamin Herrenschmidt /* Fixup hose IO resource */ 18538973ba7SBjorn Helgaas io_virt_offset = pcibios_io_space_offset(hose); 1863d5134eeSBenjamin Herrenschmidt hose->io_resource.start += io_virt_offset; 1873d5134eeSBenjamin Herrenschmidt hose->io_resource.end += io_virt_offset; 1883d5134eeSBenjamin Herrenschmidt 189518fdae2SJoe Perches pr_debug(" hose->io_resource=%pR\n", &hose->io_resource); 1907568cb4eSPaul Mackerras 1917568cb4eSPaul Mackerras return 0; 1927568cb4eSPaul Mackerras } 19349a6cba4SBjorn Helgaas 194cad5cef6SGreg Kroah-Hartman int pcibios_map_io_space(struct pci_bus *bus) 19549a6cba4SBjorn Helgaas { 19649a6cba4SBjorn Helgaas WARN_ON(bus == NULL); 19749a6cba4SBjorn Helgaas 19849a6cba4SBjorn Helgaas /* If this not a PHB, nothing to do, page tables still exist and 19949a6cba4SBjorn Helgaas * thus HPTEs will be faulted in when needed 20049a6cba4SBjorn Helgaas */ 20149a6cba4SBjorn Helgaas if (bus->self) { 20249a6cba4SBjorn Helgaas pr_debug("IO mapping for PCI-PCI bridge %s\n", 20349a6cba4SBjorn Helgaas pci_name(bus->self)); 20449a6cba4SBjorn Helgaas pr_debug(" virt=0x%016llx...0x%016llx\n", 20549a6cba4SBjorn Helgaas bus->resource[0]->start + _IO_BASE, 20649a6cba4SBjorn Helgaas bus->resource[0]->end + _IO_BASE); 20749a6cba4SBjorn Helgaas return 0; 20849a6cba4SBjorn Helgaas } 20949a6cba4SBjorn Helgaas 21049a6cba4SBjorn Helgaas return pcibios_map_phb_io_space(pci_bus_to_host(bus)); 21149a6cba4SBjorn Helgaas } 2123d5134eeSBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(pcibios_map_io_space); 2137568cb4eSPaul Mackerras 214cad5cef6SGreg Kroah-Hartman void pcibios_setup_phb_io_space(struct pci_controller *hose) 2150ed2c722SGrant Likely { 21649a6cba4SBjorn Helgaas pcibios_map_phb_io_space(hose); 2170ed2c722SGrant Likely } 2180ed2c722SGrant Likely 2197568cb4eSPaul Mackerras #define IOBASE_BRIDGE_NUMBER 0 2207568cb4eSPaul Mackerras #define IOBASE_MEMORY 1 2217568cb4eSPaul Mackerras #define IOBASE_IO 2 2227568cb4eSPaul Mackerras #define IOBASE_ISA_IO 3 2237568cb4eSPaul Mackerras #define IOBASE_ISA_MEM 4 2247568cb4eSPaul Mackerras 2253691d614SAl Viro SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, in_bus, 2263691d614SAl Viro unsigned long, in_devfn) 2277568cb4eSPaul Mackerras { 2287568cb4eSPaul Mackerras struct pci_controller* hose; 229140ab645SMike Qiu struct pci_bus *tmp_bus, *bus = NULL; 2307568cb4eSPaul Mackerras struct device_node *hose_node; 2317568cb4eSPaul Mackerras 2327568cb4eSPaul Mackerras /* Argh ! Please forgive me for that hack, but that's the 2337568cb4eSPaul Mackerras * simplest way to get existing XFree to not lockup on some 2347568cb4eSPaul Mackerras * G5 machines... So when something asks for bus 0 io base 2357568cb4eSPaul Mackerras * (bus 0 is HT root), we return the AGP one instead. 2367568cb4eSPaul Mackerras */ 23771a157e8SGrant Likely if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) { 23816124f10SPaul Mackerras struct device_node *agp; 23916124f10SPaul Mackerras 24016124f10SPaul Mackerras agp = of_find_compatible_node(NULL, NULL, "u3-agp"); 24116124f10SPaul Mackerras if (agp) 2427568cb4eSPaul Mackerras in_bus = 0xf0; 24316124f10SPaul Mackerras of_node_put(agp); 24416124f10SPaul Mackerras } 2457568cb4eSPaul Mackerras 2467568cb4eSPaul Mackerras /* That syscall isn't quite compatible with PCI domains, but it's 2477568cb4eSPaul Mackerras * used on pre-domains setup. We return the first match 2487568cb4eSPaul Mackerras */ 2497568cb4eSPaul Mackerras 250140ab645SMike Qiu list_for_each_entry(tmp_bus, &pci_root_buses, node) { 251140ab645SMike Qiu if (in_bus >= tmp_bus->number && 252140ab645SMike Qiu in_bus <= tmp_bus->busn_res.end) { 253140ab645SMike Qiu bus = tmp_bus; 2547568cb4eSPaul Mackerras break; 255140ab645SMike Qiu } 2567568cb4eSPaul Mackerras } 257b5d937deSGrant Likely if (bus == NULL || bus->dev.of_node == NULL) 2587568cb4eSPaul Mackerras return -ENODEV; 2597568cb4eSPaul Mackerras 260b5d937deSGrant Likely hose_node = bus->dev.of_node; 2617568cb4eSPaul Mackerras hose = PCI_DN(hose_node)->phb; 2627568cb4eSPaul Mackerras 2637568cb4eSPaul Mackerras switch (which) { 2647568cb4eSPaul Mackerras case IOBASE_BRIDGE_NUMBER: 2657568cb4eSPaul Mackerras return (long)hose->first_busno; 2667568cb4eSPaul Mackerras case IOBASE_MEMORY: 2673fd47f06SBenjamin Herrenschmidt return (long)hose->mem_offset[0]; 2687568cb4eSPaul Mackerras case IOBASE_IO: 2697568cb4eSPaul Mackerras return (long)hose->io_base_phys; 2707568cb4eSPaul Mackerras case IOBASE_ISA_IO: 2717568cb4eSPaul Mackerras return (long)isa_io_base; 2727568cb4eSPaul Mackerras case IOBASE_ISA_MEM: 2737568cb4eSPaul Mackerras return -EINVAL; 2747568cb4eSPaul Mackerras } 2757568cb4eSPaul Mackerras 2767568cb4eSPaul Mackerras return -EOPNOTSUPP; 2777568cb4eSPaul Mackerras } 278357518faSAnton Blanchard 279357518faSAnton Blanchard #ifdef CONFIG_NUMA 280357518faSAnton Blanchard int pcibus_to_node(struct pci_bus *bus) 281357518faSAnton Blanchard { 282357518faSAnton Blanchard struct pci_controller *phb = pci_bus_to_host(bus); 283357518faSAnton Blanchard return phb->node; 284357518faSAnton Blanchard } 285357518faSAnton Blanchard EXPORT_SYMBOL(pcibus_to_node); 286357518faSAnton Blanchard #endif 287