1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/export.h> 25 #include <linux/of_address.h> 26 #include <linux/of_pci.h> 27 #include <linux/mm.h> 28 #include <linux/list.h> 29 #include <linux/syscalls.h> 30 #include <linux/irq.h> 31 #include <linux/vmalloc.h> 32 #include <linux/slab.h> 33 34 #include <asm/processor.h> 35 #include <asm/io.h> 36 #include <asm/prom.h> 37 #include <asm/pci-bridge.h> 38 #include <asm/byteorder.h> 39 #include <asm/machdep.h> 40 #include <asm/ppc-pci.h> 41 #include <asm/firmware.h> 42 #include <asm/eeh.h> 43 44 static DEFINE_SPINLOCK(hose_spinlock); 45 LIST_HEAD(hose_list); 46 47 /* XXX kill that some day ... */ 48 static int global_phb_number; /* Global phb counter */ 49 50 /* ISA Memory physical address */ 51 resource_size_t isa_mem_base; 52 53 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */ 54 unsigned int pci_flags = 0; 55 56 57 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 58 59 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 60 { 61 pci_dma_ops = dma_ops; 62 } 63 64 struct dma_map_ops *get_pci_dma_ops(void) 65 { 66 return pci_dma_ops; 67 } 68 EXPORT_SYMBOL(get_pci_dma_ops); 69 70 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 71 { 72 struct pci_controller *phb; 73 74 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 75 if (phb == NULL) 76 return NULL; 77 spin_lock(&hose_spinlock); 78 phb->global_number = global_phb_number++; 79 list_add_tail(&phb->list_node, &hose_list); 80 spin_unlock(&hose_spinlock); 81 phb->dn = dev; 82 phb->is_dynamic = mem_init_done; 83 #ifdef CONFIG_PPC64 84 if (dev) { 85 int nid = of_node_to_nid(dev); 86 87 if (nid < 0 || !node_online(nid)) 88 nid = -1; 89 90 PHB_SET_NODE(phb, nid); 91 } 92 #endif 93 return phb; 94 } 95 96 void pcibios_free_controller(struct pci_controller *phb) 97 { 98 spin_lock(&hose_spinlock); 99 list_del(&phb->list_node); 100 spin_unlock(&hose_spinlock); 101 102 if (phb->is_dynamic) 103 kfree(phb); 104 } 105 106 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 107 { 108 #ifdef CONFIG_PPC64 109 return hose->pci_io_size; 110 #else 111 return resource_size(&hose->io_resource); 112 #endif 113 } 114 115 int pcibios_vaddr_is_ioport(void __iomem *address) 116 { 117 int ret = 0; 118 struct pci_controller *hose; 119 resource_size_t size; 120 121 spin_lock(&hose_spinlock); 122 list_for_each_entry(hose, &hose_list, list_node) { 123 size = pcibios_io_size(hose); 124 if (address >= hose->io_base_virt && 125 address < (hose->io_base_virt + size)) { 126 ret = 1; 127 break; 128 } 129 } 130 spin_unlock(&hose_spinlock); 131 return ret; 132 } 133 134 unsigned long pci_address_to_pio(phys_addr_t address) 135 { 136 struct pci_controller *hose; 137 resource_size_t size; 138 unsigned long ret = ~0; 139 140 spin_lock(&hose_spinlock); 141 list_for_each_entry(hose, &hose_list, list_node) { 142 size = pcibios_io_size(hose); 143 if (address >= hose->io_base_phys && 144 address < (hose->io_base_phys + size)) { 145 unsigned long base = 146 (unsigned long)hose->io_base_virt - _IO_BASE; 147 ret = base + (address - hose->io_base_phys); 148 break; 149 } 150 } 151 spin_unlock(&hose_spinlock); 152 153 return ret; 154 } 155 EXPORT_SYMBOL_GPL(pci_address_to_pio); 156 157 /* 158 * Return the domain number for this bus. 159 */ 160 int pci_domain_nr(struct pci_bus *bus) 161 { 162 struct pci_controller *hose = pci_bus_to_host(bus); 163 164 return hose->global_number; 165 } 166 EXPORT_SYMBOL(pci_domain_nr); 167 168 /* This routine is meant to be used early during boot, when the 169 * PCI bus numbers have not yet been assigned, and you need to 170 * issue PCI config cycles to an OF device. 171 * It could also be used to "fix" RTAS config cycles if you want 172 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 173 * config cycles. 174 */ 175 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 176 { 177 while(node) { 178 struct pci_controller *hose, *tmp; 179 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 180 if (hose->dn == node) 181 return hose; 182 node = node->parent; 183 } 184 return NULL; 185 } 186 187 static ssize_t pci_show_devspec(struct device *dev, 188 struct device_attribute *attr, char *buf) 189 { 190 struct pci_dev *pdev; 191 struct device_node *np; 192 193 pdev = to_pci_dev (dev); 194 np = pci_device_to_OF_node(pdev); 195 if (np == NULL || np->full_name == NULL) 196 return 0; 197 return sprintf(buf, "%s", np->full_name); 198 } 199 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 200 201 /* Add sysfs properties */ 202 int pcibios_add_platform_entries(struct pci_dev *pdev) 203 { 204 return device_create_file(&pdev->dev, &dev_attr_devspec); 205 } 206 207 char __devinit *pcibios_setup(char *str) 208 { 209 return str; 210 } 211 212 /* 213 * Reads the interrupt pin to determine if interrupt is use by card. 214 * If the interrupt is used, then gets the interrupt line from the 215 * openfirmware and sets it in the pci_dev and pci_config line. 216 */ 217 int pci_read_irq_line(struct pci_dev *pci_dev) 218 { 219 struct of_irq oirq; 220 unsigned int virq; 221 222 /* The current device-tree that iSeries generates from the HV 223 * PCI informations doesn't contain proper interrupt routing, 224 * and all the fallback would do is print out crap, so we 225 * don't attempt to resolve the interrupts here at all, some 226 * iSeries specific fixup does it. 227 * 228 * In the long run, we will hopefully fix the generated device-tree 229 * instead. 230 */ 231 #ifdef CONFIG_PPC_ISERIES 232 if (firmware_has_feature(FW_FEATURE_ISERIES)) 233 return -1; 234 #endif 235 236 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 237 238 #ifdef DEBUG 239 memset(&oirq, 0xff, sizeof(oirq)); 240 #endif 241 /* Try to get a mapping from the device-tree */ 242 if (of_irq_map_pci(pci_dev, &oirq)) { 243 u8 line, pin; 244 245 /* If that fails, lets fallback to what is in the config 246 * space and map that through the default controller. We 247 * also set the type to level low since that's what PCI 248 * interrupts are. If your platform does differently, then 249 * either provide a proper interrupt tree or don't use this 250 * function. 251 */ 252 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 253 return -1; 254 if (pin == 0) 255 return -1; 256 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 257 line == 0xff || line == 0) { 258 return -1; 259 } 260 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 261 line, pin); 262 263 virq = irq_create_mapping(NULL, line); 264 if (virq != NO_IRQ) 265 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 266 } else { 267 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 268 oirq.size, oirq.specifier[0], oirq.specifier[1], 269 oirq.controller ? oirq.controller->full_name : 270 "<default>"); 271 272 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 273 oirq.size); 274 } 275 if(virq == NO_IRQ) { 276 pr_debug(" Failed to map !\n"); 277 return -1; 278 } 279 280 pr_debug(" Mapped to linux irq %d\n", virq); 281 282 pci_dev->irq = virq; 283 284 return 0; 285 } 286 EXPORT_SYMBOL(pci_read_irq_line); 287 288 /* 289 * Platform support for /proc/bus/pci/X/Y mmap()s, 290 * modelled on the sparc64 implementation by Dave Miller. 291 * -- paulus. 292 */ 293 294 /* 295 * Adjust vm_pgoff of VMA such that it is the physical page offset 296 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 297 * 298 * Basically, the user finds the base address for his device which he wishes 299 * to mmap. They read the 32-bit value from the config space base register, 300 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 301 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 302 * 303 * Returns negative error code on failure, zero on success. 304 */ 305 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 306 resource_size_t *offset, 307 enum pci_mmap_state mmap_state) 308 { 309 struct pci_controller *hose = pci_bus_to_host(dev->bus); 310 unsigned long io_offset = 0; 311 int i, res_bit; 312 313 if (hose == 0) 314 return NULL; /* should never happen */ 315 316 /* If memory, add on the PCI bridge address offset */ 317 if (mmap_state == pci_mmap_mem) { 318 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 319 *offset += hose->pci_mem_offset; 320 #endif 321 res_bit = IORESOURCE_MEM; 322 } else { 323 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 324 *offset += io_offset; 325 res_bit = IORESOURCE_IO; 326 } 327 328 /* 329 * Check that the offset requested corresponds to one of the 330 * resources of the device. 331 */ 332 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 333 struct resource *rp = &dev->resource[i]; 334 int flags = rp->flags; 335 336 /* treat ROM as memory (should be already) */ 337 if (i == PCI_ROM_RESOURCE) 338 flags |= IORESOURCE_MEM; 339 340 /* Active and same type? */ 341 if ((flags & res_bit) == 0) 342 continue; 343 344 /* In the range of this resource? */ 345 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 346 continue; 347 348 /* found it! construct the final physical address */ 349 if (mmap_state == pci_mmap_io) 350 *offset += hose->io_base_phys - io_offset; 351 return rp; 352 } 353 354 return NULL; 355 } 356 357 /* 358 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 359 * device mapping. 360 */ 361 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 362 pgprot_t protection, 363 enum pci_mmap_state mmap_state, 364 int write_combine) 365 { 366 unsigned long prot = pgprot_val(protection); 367 368 /* Write combine is always 0 on non-memory space mappings. On 369 * memory space, if the user didn't pass 1, we check for a 370 * "prefetchable" resource. This is a bit hackish, but we use 371 * this to workaround the inability of /sysfs to provide a write 372 * combine bit 373 */ 374 if (mmap_state != pci_mmap_mem) 375 write_combine = 0; 376 else if (write_combine == 0) { 377 if (rp->flags & IORESOURCE_PREFETCH) 378 write_combine = 1; 379 } 380 381 /* XXX would be nice to have a way to ask for write-through */ 382 if (write_combine) 383 return pgprot_noncached_wc(prot); 384 else 385 return pgprot_noncached(prot); 386 } 387 388 /* 389 * This one is used by /dev/mem and fbdev who have no clue about the 390 * PCI device, it tries to find the PCI device first and calls the 391 * above routine 392 */ 393 pgprot_t pci_phys_mem_access_prot(struct file *file, 394 unsigned long pfn, 395 unsigned long size, 396 pgprot_t prot) 397 { 398 struct pci_dev *pdev = NULL; 399 struct resource *found = NULL; 400 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 401 int i; 402 403 if (page_is_ram(pfn)) 404 return prot; 405 406 prot = pgprot_noncached(prot); 407 for_each_pci_dev(pdev) { 408 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 409 struct resource *rp = &pdev->resource[i]; 410 int flags = rp->flags; 411 412 /* Active and same type? */ 413 if ((flags & IORESOURCE_MEM) == 0) 414 continue; 415 /* In the range of this resource? */ 416 if (offset < (rp->start & PAGE_MASK) || 417 offset > rp->end) 418 continue; 419 found = rp; 420 break; 421 } 422 if (found) 423 break; 424 } 425 if (found) { 426 if (found->flags & IORESOURCE_PREFETCH) 427 prot = pgprot_noncached_wc(prot); 428 pci_dev_put(pdev); 429 } 430 431 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 432 (unsigned long long)offset, pgprot_val(prot)); 433 434 return prot; 435 } 436 437 438 /* 439 * Perform the actual remap of the pages for a PCI device mapping, as 440 * appropriate for this architecture. The region in the process to map 441 * is described by vm_start and vm_end members of VMA, the base physical 442 * address is found in vm_pgoff. 443 * The pci device structure is provided so that architectures may make mapping 444 * decisions on a per-device or per-bus basis. 445 * 446 * Returns a negative error code on failure, zero on success. 447 */ 448 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 449 enum pci_mmap_state mmap_state, int write_combine) 450 { 451 resource_size_t offset = 452 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 453 struct resource *rp; 454 int ret; 455 456 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 457 if (rp == NULL) 458 return -EINVAL; 459 460 vma->vm_pgoff = offset >> PAGE_SHIFT; 461 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 462 vma->vm_page_prot, 463 mmap_state, write_combine); 464 465 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 466 vma->vm_end - vma->vm_start, vma->vm_page_prot); 467 468 return ret; 469 } 470 471 /* This provides legacy IO read access on a bus */ 472 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 473 { 474 unsigned long offset; 475 struct pci_controller *hose = pci_bus_to_host(bus); 476 struct resource *rp = &hose->io_resource; 477 void __iomem *addr; 478 479 /* Check if port can be supported by that bus. We only check 480 * the ranges of the PHB though, not the bus itself as the rules 481 * for forwarding legacy cycles down bridges are not our problem 482 * here. So if the host bridge supports it, we do it. 483 */ 484 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 485 offset += port; 486 487 if (!(rp->flags & IORESOURCE_IO)) 488 return -ENXIO; 489 if (offset < rp->start || (offset + size) > rp->end) 490 return -ENXIO; 491 addr = hose->io_base_virt + port; 492 493 switch(size) { 494 case 1: 495 *((u8 *)val) = in_8(addr); 496 return 1; 497 case 2: 498 if (port & 1) 499 return -EINVAL; 500 *((u16 *)val) = in_le16(addr); 501 return 2; 502 case 4: 503 if (port & 3) 504 return -EINVAL; 505 *((u32 *)val) = in_le32(addr); 506 return 4; 507 } 508 return -EINVAL; 509 } 510 511 /* This provides legacy IO write access on a bus */ 512 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 513 { 514 unsigned long offset; 515 struct pci_controller *hose = pci_bus_to_host(bus); 516 struct resource *rp = &hose->io_resource; 517 void __iomem *addr; 518 519 /* Check if port can be supported by that bus. We only check 520 * the ranges of the PHB though, not the bus itself as the rules 521 * for forwarding legacy cycles down bridges are not our problem 522 * here. So if the host bridge supports it, we do it. 523 */ 524 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 525 offset += port; 526 527 if (!(rp->flags & IORESOURCE_IO)) 528 return -ENXIO; 529 if (offset < rp->start || (offset + size) > rp->end) 530 return -ENXIO; 531 addr = hose->io_base_virt + port; 532 533 /* WARNING: The generic code is idiotic. It gets passed a pointer 534 * to what can be a 1, 2 or 4 byte quantity and always reads that 535 * as a u32, which means that we have to correct the location of 536 * the data read within those 32 bits for size 1 and 2 537 */ 538 switch(size) { 539 case 1: 540 out_8(addr, val >> 24); 541 return 1; 542 case 2: 543 if (port & 1) 544 return -EINVAL; 545 out_le16(addr, val >> 16); 546 return 2; 547 case 4: 548 if (port & 3) 549 return -EINVAL; 550 out_le32(addr, val); 551 return 4; 552 } 553 return -EINVAL; 554 } 555 556 /* This provides legacy IO or memory mmap access on a bus */ 557 int pci_mmap_legacy_page_range(struct pci_bus *bus, 558 struct vm_area_struct *vma, 559 enum pci_mmap_state mmap_state) 560 { 561 struct pci_controller *hose = pci_bus_to_host(bus); 562 resource_size_t offset = 563 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 564 resource_size_t size = vma->vm_end - vma->vm_start; 565 struct resource *rp; 566 567 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 568 pci_domain_nr(bus), bus->number, 569 mmap_state == pci_mmap_mem ? "MEM" : "IO", 570 (unsigned long long)offset, 571 (unsigned long long)(offset + size - 1)); 572 573 if (mmap_state == pci_mmap_mem) { 574 /* Hack alert ! 575 * 576 * Because X is lame and can fail starting if it gets an error trying 577 * to mmap legacy_mem (instead of just moving on without legacy memory 578 * access) we fake it here by giving it anonymous memory, effectively 579 * behaving just like /dev/zero 580 */ 581 if ((offset + size) > hose->isa_mem_size) { 582 printk(KERN_DEBUG 583 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 584 current->comm, current->pid, pci_domain_nr(bus), bus->number); 585 if (vma->vm_flags & VM_SHARED) 586 return shmem_zero_setup(vma); 587 return 0; 588 } 589 offset += hose->isa_mem_phys; 590 } else { 591 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 592 unsigned long roffset = offset + io_offset; 593 rp = &hose->io_resource; 594 if (!(rp->flags & IORESOURCE_IO)) 595 return -ENXIO; 596 if (roffset < rp->start || (roffset + size) > rp->end) 597 return -ENXIO; 598 offset += hose->io_base_phys; 599 } 600 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 601 602 vma->vm_pgoff = offset >> PAGE_SHIFT; 603 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 604 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 605 vma->vm_end - vma->vm_start, 606 vma->vm_page_prot); 607 } 608 609 void pci_resource_to_user(const struct pci_dev *dev, int bar, 610 const struct resource *rsrc, 611 resource_size_t *start, resource_size_t *end) 612 { 613 struct pci_controller *hose = pci_bus_to_host(dev->bus); 614 resource_size_t offset = 0; 615 616 if (hose == NULL) 617 return; 618 619 if (rsrc->flags & IORESOURCE_IO) 620 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 621 622 /* We pass a fully fixed up address to userland for MMIO instead of 623 * a BAR value because X is lame and expects to be able to use that 624 * to pass to /dev/mem ! 625 * 626 * That means that we'll have potentially 64 bits values where some 627 * userland apps only expect 32 (like X itself since it thinks only 628 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 629 * 32 bits CHRPs :-( 630 * 631 * Hopefully, the sysfs insterface is immune to that gunk. Once X 632 * has been fixed (and the fix spread enough), we can re-enable the 633 * 2 lines below and pass down a BAR value to userland. In that case 634 * we'll also have to re-enable the matching code in 635 * __pci_mmap_make_offset(). 636 * 637 * BenH. 638 */ 639 #if 0 640 else if (rsrc->flags & IORESOURCE_MEM) 641 offset = hose->pci_mem_offset; 642 #endif 643 644 *start = rsrc->start - offset; 645 *end = rsrc->end - offset; 646 } 647 648 /** 649 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 650 * @hose: newly allocated pci_controller to be setup 651 * @dev: device node of the host bridge 652 * @primary: set if primary bus (32 bits only, soon to be deprecated) 653 * 654 * This function will parse the "ranges" property of a PCI host bridge device 655 * node and setup the resource mapping of a pci controller based on its 656 * content. 657 * 658 * Life would be boring if it wasn't for a few issues that we have to deal 659 * with here: 660 * 661 * - We can only cope with one IO space range and up to 3 Memory space 662 * ranges. However, some machines (thanks Apple !) tend to split their 663 * space into lots of small contiguous ranges. So we have to coalesce. 664 * 665 * - We can only cope with all memory ranges having the same offset 666 * between CPU addresses and PCI addresses. Unfortunately, some bridges 667 * are setup for a large 1:1 mapping along with a small "window" which 668 * maps PCI address 0 to some arbitrary high address of the CPU space in 669 * order to give access to the ISA memory hole. 670 * The way out of here that I've chosen for now is to always set the 671 * offset based on the first resource found, then override it if we 672 * have a different offset and the previous was set by an ISA hole. 673 * 674 * - Some busses have IO space not starting at 0, which causes trouble with 675 * the way we do our IO resource renumbering. The code somewhat deals with 676 * it for 64 bits but I would expect problems on 32 bits. 677 * 678 * - Some 32 bits platforms such as 4xx can have physical space larger than 679 * 32 bits so we need to use 64 bits values for the parsing 680 */ 681 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, 682 struct device_node *dev, 683 int primary) 684 { 685 const u32 *ranges; 686 int rlen; 687 int pna = of_n_addr_cells(dev); 688 int np = pna + 5; 689 int memno = 0, isa_hole = -1; 690 u32 pci_space; 691 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 692 unsigned long long isa_mb = 0; 693 struct resource *res; 694 695 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 696 dev->full_name, primary ? "(primary)" : ""); 697 698 /* Get ranges property */ 699 ranges = of_get_property(dev, "ranges", &rlen); 700 if (ranges == NULL) 701 return; 702 703 /* Parse it */ 704 while ((rlen -= np * 4) >= 0) { 705 /* Read next ranges element */ 706 pci_space = ranges[0]; 707 pci_addr = of_read_number(ranges + 1, 2); 708 cpu_addr = of_translate_address(dev, ranges + 3); 709 size = of_read_number(ranges + pna + 3, 2); 710 ranges += np; 711 712 /* If we failed translation or got a zero-sized region 713 * (some FW try to feed us with non sensical zero sized regions 714 * such as power3 which look like some kind of attempt at exposing 715 * the VGA memory hole) 716 */ 717 if (cpu_addr == OF_BAD_ADDR || size == 0) 718 continue; 719 720 /* Now consume following elements while they are contiguous */ 721 for (; rlen >= np * sizeof(u32); 722 ranges += np, rlen -= np * 4) { 723 if (ranges[0] != pci_space) 724 break; 725 pci_next = of_read_number(ranges + 1, 2); 726 cpu_next = of_translate_address(dev, ranges + 3); 727 if (pci_next != pci_addr + size || 728 cpu_next != cpu_addr + size) 729 break; 730 size += of_read_number(ranges + pna + 3, 2); 731 } 732 733 /* Act based on address space type */ 734 res = NULL; 735 switch ((pci_space >> 24) & 0x3) { 736 case 1: /* PCI IO space */ 737 printk(KERN_INFO 738 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 739 cpu_addr, cpu_addr + size - 1, pci_addr); 740 741 /* We support only one IO range */ 742 if (hose->pci_io_size) { 743 printk(KERN_INFO 744 " \\--> Skipped (too many) !\n"); 745 continue; 746 } 747 #ifdef CONFIG_PPC32 748 /* On 32 bits, limit I/O space to 16MB */ 749 if (size > 0x01000000) 750 size = 0x01000000; 751 752 /* 32 bits needs to map IOs here */ 753 hose->io_base_virt = ioremap(cpu_addr, size); 754 755 /* Expect trouble if pci_addr is not 0 */ 756 if (primary) 757 isa_io_base = 758 (unsigned long)hose->io_base_virt; 759 #endif /* CONFIG_PPC32 */ 760 /* pci_io_size and io_base_phys always represent IO 761 * space starting at 0 so we factor in pci_addr 762 */ 763 hose->pci_io_size = pci_addr + size; 764 hose->io_base_phys = cpu_addr - pci_addr; 765 766 /* Build resource */ 767 res = &hose->io_resource; 768 res->flags = IORESOURCE_IO; 769 res->start = pci_addr; 770 break; 771 case 2: /* PCI Memory space */ 772 case 3: /* PCI 64 bits Memory space */ 773 printk(KERN_INFO 774 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 775 cpu_addr, cpu_addr + size - 1, pci_addr, 776 (pci_space & 0x40000000) ? "Prefetch" : ""); 777 778 /* We support only 3 memory ranges */ 779 if (memno >= 3) { 780 printk(KERN_INFO 781 " \\--> Skipped (too many) !\n"); 782 continue; 783 } 784 /* Handles ISA memory hole space here */ 785 if (pci_addr == 0) { 786 isa_mb = cpu_addr; 787 isa_hole = memno; 788 if (primary || isa_mem_base == 0) 789 isa_mem_base = cpu_addr; 790 hose->isa_mem_phys = cpu_addr; 791 hose->isa_mem_size = size; 792 } 793 794 /* We get the PCI/Mem offset from the first range or 795 * the, current one if the offset came from an ISA 796 * hole. If they don't match, bugger. 797 */ 798 if (memno == 0 || 799 (isa_hole >= 0 && pci_addr != 0 && 800 hose->pci_mem_offset == isa_mb)) 801 hose->pci_mem_offset = cpu_addr - pci_addr; 802 else if (pci_addr != 0 && 803 hose->pci_mem_offset != cpu_addr - pci_addr) { 804 printk(KERN_INFO 805 " \\--> Skipped (offset mismatch) !\n"); 806 continue; 807 } 808 809 /* Build resource */ 810 res = &hose->mem_resources[memno++]; 811 res->flags = IORESOURCE_MEM; 812 if (pci_space & 0x40000000) 813 res->flags |= IORESOURCE_PREFETCH; 814 res->start = cpu_addr; 815 break; 816 } 817 if (res != NULL) { 818 res->name = dev->full_name; 819 res->end = res->start + size - 1; 820 res->parent = NULL; 821 res->sibling = NULL; 822 res->child = NULL; 823 } 824 } 825 826 /* If there's an ISA hole and the pci_mem_offset is -not- matching 827 * the ISA hole offset, then we need to remove the ISA hole from 828 * the resource list for that brige 829 */ 830 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { 831 unsigned int next = isa_hole + 1; 832 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); 833 if (next < memno) 834 memmove(&hose->mem_resources[isa_hole], 835 &hose->mem_resources[next], 836 sizeof(struct resource) * (memno - next)); 837 hose->mem_resources[--memno].flags = 0; 838 } 839 } 840 841 /* Decide whether to display the domain number in /proc */ 842 int pci_proc_domain(struct pci_bus *bus) 843 { 844 struct pci_controller *hose = pci_bus_to_host(bus); 845 846 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 847 return 0; 848 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 849 return hose->global_number != 0; 850 return 1; 851 } 852 853 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 854 struct resource *res) 855 { 856 resource_size_t offset = 0, mask = (resource_size_t)-1; 857 struct pci_controller *hose = pci_bus_to_host(dev->bus); 858 859 if (!hose) 860 return; 861 if (res->flags & IORESOURCE_IO) { 862 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 863 mask = 0xffffffffu; 864 } else if (res->flags & IORESOURCE_MEM) 865 offset = hose->pci_mem_offset; 866 867 region->start = (res->start - offset) & mask; 868 region->end = (res->end - offset) & mask; 869 } 870 EXPORT_SYMBOL(pcibios_resource_to_bus); 871 872 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 873 struct pci_bus_region *region) 874 { 875 resource_size_t offset = 0, mask = (resource_size_t)-1; 876 struct pci_controller *hose = pci_bus_to_host(dev->bus); 877 878 if (!hose) 879 return; 880 if (res->flags & IORESOURCE_IO) { 881 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 882 mask = 0xffffffffu; 883 } else if (res->flags & IORESOURCE_MEM) 884 offset = hose->pci_mem_offset; 885 res->start = (region->start + offset) & mask; 886 res->end = (region->end + offset) & mask; 887 } 888 EXPORT_SYMBOL(pcibios_bus_to_resource); 889 890 /* Fixup a bus resource into a linux resource */ 891 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) 892 { 893 struct pci_controller *hose = pci_bus_to_host(dev->bus); 894 resource_size_t offset = 0, mask = (resource_size_t)-1; 895 896 if (res->flags & IORESOURCE_IO) { 897 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 898 mask = 0xffffffffu; 899 } else if (res->flags & IORESOURCE_MEM) 900 offset = hose->pci_mem_offset; 901 902 res->start = (res->start + offset) & mask; 903 res->end = (res->end + offset) & mask; 904 } 905 906 907 /* This header fixup will do the resource fixup for all devices as they are 908 * probed, but not for bridge ranges 909 */ 910 static void __devinit pcibios_fixup_resources(struct pci_dev *dev) 911 { 912 struct pci_controller *hose = pci_bus_to_host(dev->bus); 913 int i; 914 915 if (!hose) { 916 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 917 pci_name(dev)); 918 return; 919 } 920 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 921 struct resource *res = dev->resource + i; 922 if (!res->flags) 923 continue; 924 /* On platforms that have PCI_PROBE_ONLY set, we don't 925 * consider 0 as an unassigned BAR value. It's technically 926 * a valid value, but linux doesn't like it... so when we can 927 * re-assign things, we do so, but if we can't, we keep it 928 * around and hope for the best... 929 */ 930 if (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY)) { 931 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", 932 pci_name(dev), i, 933 (unsigned long long)res->start, 934 (unsigned long long)res->end, 935 (unsigned int)res->flags); 936 res->end -= res->start; 937 res->start = 0; 938 res->flags |= IORESOURCE_UNSET; 939 continue; 940 } 941 942 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", 943 pci_name(dev), i, 944 (unsigned long long)res->start,\ 945 (unsigned long long)res->end, 946 (unsigned int)res->flags); 947 948 fixup_resource(res, dev); 949 950 pr_debug("PCI:%s %016llx-%016llx\n", 951 pci_name(dev), 952 (unsigned long long)res->start, 953 (unsigned long long)res->end); 954 } 955 956 /* Call machine specific resource fixup */ 957 if (ppc_md.pcibios_fixup_resources) 958 ppc_md.pcibios_fixup_resources(dev); 959 } 960 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 961 962 /* This function tries to figure out if a bridge resource has been initialized 963 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 964 * things go more smoothly when it gets it right. It should covers cases such 965 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 966 */ 967 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 968 struct resource *res) 969 { 970 struct pci_controller *hose = pci_bus_to_host(bus); 971 struct pci_dev *dev = bus->self; 972 resource_size_t offset; 973 u16 command; 974 int i; 975 976 /* We don't do anything if PCI_PROBE_ONLY is set */ 977 if (pci_has_flag(PCI_PROBE_ONLY)) 978 return 0; 979 980 /* Job is a bit different between memory and IO */ 981 if (res->flags & IORESOURCE_MEM) { 982 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been 983 * initialized by somebody 984 */ 985 if (res->start != hose->pci_mem_offset) 986 return 0; 987 988 /* The BAR is 0, let's check if memory decoding is enabled on 989 * the bridge. If not, we consider it unassigned 990 */ 991 pci_read_config_word(dev, PCI_COMMAND, &command); 992 if ((command & PCI_COMMAND_MEMORY) == 0) 993 return 1; 994 995 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 996 * resources covers that starting address (0 then it's good enough for 997 * us for memory 998 */ 999 for (i = 0; i < 3; i++) { 1000 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 1001 hose->mem_resources[i].start == hose->pci_mem_offset) 1002 return 0; 1003 } 1004 1005 /* Well, it starts at 0 and we know it will collide so we may as 1006 * well consider it as unassigned. That covers the Apple case. 1007 */ 1008 return 1; 1009 } else { 1010 /* If the BAR is non-0, then we consider it assigned */ 1011 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1012 if (((res->start - offset) & 0xfffffffful) != 0) 1013 return 0; 1014 1015 /* Here, we are a bit different than memory as typically IO space 1016 * starting at low addresses -is- valid. What we do instead if that 1017 * we consider as unassigned anything that doesn't have IO enabled 1018 * in the PCI command register, and that's it. 1019 */ 1020 pci_read_config_word(dev, PCI_COMMAND, &command); 1021 if (command & PCI_COMMAND_IO) 1022 return 0; 1023 1024 /* It's starting at 0 and IO is disabled in the bridge, consider 1025 * it unassigned 1026 */ 1027 return 1; 1028 } 1029 } 1030 1031 /* Fixup resources of a PCI<->PCI bridge */ 1032 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus) 1033 { 1034 struct resource *res; 1035 int i; 1036 1037 struct pci_dev *dev = bus->self; 1038 1039 pci_bus_for_each_resource(bus, res, i) { 1040 if (!res || !res->flags) 1041 continue; 1042 if (i >= 3 && bus->self->transparent) 1043 continue; 1044 1045 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", 1046 pci_name(dev), i, 1047 (unsigned long long)res->start,\ 1048 (unsigned long long)res->end, 1049 (unsigned int)res->flags); 1050 1051 /* Perform fixup */ 1052 fixup_resource(res, dev); 1053 1054 /* Try to detect uninitialized P2P bridge resources, 1055 * and clear them out so they get re-assigned later 1056 */ 1057 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1058 res->flags = 0; 1059 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1060 } else { 1061 1062 pr_debug("PCI:%s %016llx-%016llx\n", 1063 pci_name(dev), 1064 (unsigned long long)res->start, 1065 (unsigned long long)res->end); 1066 } 1067 } 1068 } 1069 1070 void __devinit pcibios_setup_bus_self(struct pci_bus *bus) 1071 { 1072 /* Fix up the bus resources for P2P bridges */ 1073 if (bus->self != NULL) 1074 pcibios_fixup_bridge(bus); 1075 1076 /* Platform specific bus fixups. This is currently only used 1077 * by fsl_pci and I'm hoping to get rid of it at some point 1078 */ 1079 if (ppc_md.pcibios_fixup_bus) 1080 ppc_md.pcibios_fixup_bus(bus); 1081 1082 /* Setup bus DMA mappings */ 1083 if (ppc_md.pci_dma_bus_setup) 1084 ppc_md.pci_dma_bus_setup(bus); 1085 } 1086 1087 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus) 1088 { 1089 struct pci_dev *dev; 1090 1091 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1092 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1093 1094 list_for_each_entry(dev, &bus->devices, bus_list) { 1095 /* Cardbus can call us to add new devices to a bus, so ignore 1096 * those who are already fully discovered 1097 */ 1098 if (dev->is_added) 1099 continue; 1100 1101 /* Fixup NUMA node as it may not be setup yet by the generic 1102 * code and is needed by the DMA init 1103 */ 1104 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1105 1106 /* Hook up default DMA ops */ 1107 set_dma_ops(&dev->dev, pci_dma_ops); 1108 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1109 1110 /* Additional platform DMA/iommu setup */ 1111 if (ppc_md.pci_dma_dev_setup) 1112 ppc_md.pci_dma_dev_setup(dev); 1113 1114 /* Read default IRQs and fixup if necessary */ 1115 pci_read_irq_line(dev); 1116 if (ppc_md.pci_irq_fixup) 1117 ppc_md.pci_irq_fixup(dev); 1118 } 1119 } 1120 1121 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 1122 { 1123 /* When called from the generic PCI probe, read PCI<->PCI bridge 1124 * bases. This is -not- called when generating the PCI tree from 1125 * the OF device-tree. 1126 */ 1127 if (bus->self != NULL) 1128 pci_read_bridge_bases(bus); 1129 1130 /* Now fixup the bus bus */ 1131 pcibios_setup_bus_self(bus); 1132 1133 /* Now fixup devices on that bus */ 1134 pcibios_setup_bus_devices(bus); 1135 } 1136 EXPORT_SYMBOL(pcibios_fixup_bus); 1137 1138 void __devinit pci_fixup_cardbus(struct pci_bus *bus) 1139 { 1140 /* Now fixup devices on that bus */ 1141 pcibios_setup_bus_devices(bus); 1142 } 1143 1144 1145 static int skip_isa_ioresource_align(struct pci_dev *dev) 1146 { 1147 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1148 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1149 return 1; 1150 return 0; 1151 } 1152 1153 /* 1154 * We need to avoid collisions with `mirrored' VGA ports 1155 * and other strange ISA hardware, so we always want the 1156 * addresses to be allocated in the 0x000-0x0ff region 1157 * modulo 0x400. 1158 * 1159 * Why? Because some silly external IO cards only decode 1160 * the low 10 bits of the IO address. The 0x00-0xff region 1161 * is reserved for motherboard devices that decode all 16 1162 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1163 * but we want to try to avoid allocating at 0x2900-0x2bff 1164 * which might have be mirrored at 0x0100-0x03ff.. 1165 */ 1166 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1167 resource_size_t size, resource_size_t align) 1168 { 1169 struct pci_dev *dev = data; 1170 resource_size_t start = res->start; 1171 1172 if (res->flags & IORESOURCE_IO) { 1173 if (skip_isa_ioresource_align(dev)) 1174 return start; 1175 if (start & 0x300) 1176 start = (start + 0x3ff) & ~0x3ff; 1177 } 1178 1179 return start; 1180 } 1181 EXPORT_SYMBOL(pcibios_align_resource); 1182 1183 /* 1184 * Reparent resource children of pr that conflict with res 1185 * under res, and make res replace those children. 1186 */ 1187 static int reparent_resources(struct resource *parent, 1188 struct resource *res) 1189 { 1190 struct resource *p, **pp; 1191 struct resource **firstpp = NULL; 1192 1193 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1194 if (p->end < res->start) 1195 continue; 1196 if (res->end < p->start) 1197 break; 1198 if (p->start < res->start || p->end > res->end) 1199 return -1; /* not completely contained */ 1200 if (firstpp == NULL) 1201 firstpp = pp; 1202 } 1203 if (firstpp == NULL) 1204 return -1; /* didn't find any conflicting entries? */ 1205 res->parent = parent; 1206 res->child = *firstpp; 1207 res->sibling = *pp; 1208 *firstpp = res; 1209 *pp = NULL; 1210 for (p = res->child; p != NULL; p = p->sibling) { 1211 p->parent = res; 1212 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1213 p->name, 1214 (unsigned long long)p->start, 1215 (unsigned long long)p->end, res->name); 1216 } 1217 return 0; 1218 } 1219 1220 /* 1221 * Handle resources of PCI devices. If the world were perfect, we could 1222 * just allocate all the resource regions and do nothing more. It isn't. 1223 * On the other hand, we cannot just re-allocate all devices, as it would 1224 * require us to know lots of host bridge internals. So we attempt to 1225 * keep as much of the original configuration as possible, but tweak it 1226 * when it's found to be wrong. 1227 * 1228 * Known BIOS problems we have to work around: 1229 * - I/O or memory regions not configured 1230 * - regions configured, but not enabled in the command register 1231 * - bogus I/O addresses above 64K used 1232 * - expansion ROMs left enabled (this may sound harmless, but given 1233 * the fact the PCI specs explicitly allow address decoders to be 1234 * shared between expansion ROMs and other resource regions, it's 1235 * at least dangerous) 1236 * 1237 * Our solution: 1238 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1239 * This gives us fixed barriers on where we can allocate. 1240 * (2) Allocate resources for all enabled devices. If there is 1241 * a collision, just mark the resource as unallocated. Also 1242 * disable expansion ROMs during this step. 1243 * (3) Try to allocate resources for disabled devices. If the 1244 * resources were assigned correctly, everything goes well, 1245 * if they weren't, they won't disturb allocation of other 1246 * resources. 1247 * (4) Assign new addresses to resources which were either 1248 * not configured at all or misconfigured. If explicitly 1249 * requested by the user, configure expansion ROM address 1250 * as well. 1251 */ 1252 1253 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1254 { 1255 struct pci_bus *b; 1256 int i; 1257 struct resource *res, *pr; 1258 1259 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1260 pci_domain_nr(bus), bus->number); 1261 1262 pci_bus_for_each_resource(bus, res, i) { 1263 if (!res || !res->flags || res->start > res->end || res->parent) 1264 continue; 1265 if (bus->parent == NULL) 1266 pr = (res->flags & IORESOURCE_IO) ? 1267 &ioport_resource : &iomem_resource; 1268 else { 1269 /* Don't bother with non-root busses when 1270 * re-assigning all resources. We clear the 1271 * resource flags as if they were colliding 1272 * and as such ensure proper re-allocation 1273 * later. 1274 */ 1275 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 1276 goto clear_resource; 1277 pr = pci_find_parent_resource(bus->self, res); 1278 if (pr == res) { 1279 /* this happens when the generic PCI 1280 * code (wrongly) decides that this 1281 * bridge is transparent -- paulus 1282 */ 1283 continue; 1284 } 1285 } 1286 1287 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1288 "[0x%x], parent %p (%s)\n", 1289 bus->self ? pci_name(bus->self) : "PHB", 1290 bus->number, i, 1291 (unsigned long long)res->start, 1292 (unsigned long long)res->end, 1293 (unsigned int)res->flags, 1294 pr, (pr && pr->name) ? pr->name : "nil"); 1295 1296 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1297 if (request_resource(pr, res) == 0) 1298 continue; 1299 /* 1300 * Must be a conflict with an existing entry. 1301 * Move that entry (or entries) under the 1302 * bridge resource and try again. 1303 */ 1304 if (reparent_resources(pr, res) == 0) 1305 continue; 1306 } 1307 printk(KERN_WARNING "PCI: Cannot allocate resource region " 1308 "%d of PCI bridge %d, will remap\n", i, bus->number); 1309 clear_resource: 1310 res->start = res->end = 0; 1311 res->flags = 0; 1312 } 1313 1314 list_for_each_entry(b, &bus->children, node) 1315 pcibios_allocate_bus_resources(b); 1316 } 1317 1318 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) 1319 { 1320 struct resource *pr, *r = &dev->resource[idx]; 1321 1322 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1323 pci_name(dev), idx, 1324 (unsigned long long)r->start, 1325 (unsigned long long)r->end, 1326 (unsigned int)r->flags); 1327 1328 pr = pci_find_parent_resource(dev, r); 1329 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1330 request_resource(pr, r) < 0) { 1331 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1332 " of device %s, will remap\n", idx, pci_name(dev)); 1333 if (pr) 1334 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1335 pr, 1336 (unsigned long long)pr->start, 1337 (unsigned long long)pr->end, 1338 (unsigned int)pr->flags); 1339 /* We'll assign a new address later */ 1340 r->flags |= IORESOURCE_UNSET; 1341 r->end -= r->start; 1342 r->start = 0; 1343 } 1344 } 1345 1346 static void __init pcibios_allocate_resources(int pass) 1347 { 1348 struct pci_dev *dev = NULL; 1349 int idx, disabled; 1350 u16 command; 1351 struct resource *r; 1352 1353 for_each_pci_dev(dev) { 1354 pci_read_config_word(dev, PCI_COMMAND, &command); 1355 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1356 r = &dev->resource[idx]; 1357 if (r->parent) /* Already allocated */ 1358 continue; 1359 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1360 continue; /* Not assigned at all */ 1361 /* We only allocate ROMs on pass 1 just in case they 1362 * have been screwed up by firmware 1363 */ 1364 if (idx == PCI_ROM_RESOURCE ) 1365 disabled = 1; 1366 if (r->flags & IORESOURCE_IO) 1367 disabled = !(command & PCI_COMMAND_IO); 1368 else 1369 disabled = !(command & PCI_COMMAND_MEMORY); 1370 if (pass == disabled) 1371 alloc_resource(dev, idx); 1372 } 1373 if (pass) 1374 continue; 1375 r = &dev->resource[PCI_ROM_RESOURCE]; 1376 if (r->flags) { 1377 /* Turn the ROM off, leave the resource region, 1378 * but keep it unregistered. 1379 */ 1380 u32 reg; 1381 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1382 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1383 pr_debug("PCI: Switching off ROM of %s\n", 1384 pci_name(dev)); 1385 r->flags &= ~IORESOURCE_ROM_ENABLE; 1386 pci_write_config_dword(dev, dev->rom_base_reg, 1387 reg & ~PCI_ROM_ADDRESS_ENABLE); 1388 } 1389 } 1390 } 1391 } 1392 1393 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1394 { 1395 struct pci_controller *hose = pci_bus_to_host(bus); 1396 resource_size_t offset; 1397 struct resource *res, *pres; 1398 int i; 1399 1400 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1401 1402 /* Check for IO */ 1403 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1404 goto no_io; 1405 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1406 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1407 BUG_ON(res == NULL); 1408 res->name = "Legacy IO"; 1409 res->flags = IORESOURCE_IO; 1410 res->start = offset; 1411 res->end = (offset + 0xfff) & 0xfffffffful; 1412 pr_debug("Candidate legacy IO: %pR\n", res); 1413 if (request_resource(&hose->io_resource, res)) { 1414 printk(KERN_DEBUG 1415 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1416 pci_domain_nr(bus), bus->number, res); 1417 kfree(res); 1418 } 1419 1420 no_io: 1421 /* Check for memory */ 1422 offset = hose->pci_mem_offset; 1423 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); 1424 for (i = 0; i < 3; i++) { 1425 pres = &hose->mem_resources[i]; 1426 if (!(pres->flags & IORESOURCE_MEM)) 1427 continue; 1428 pr_debug("hose mem res: %pR\n", pres); 1429 if ((pres->start - offset) <= 0xa0000 && 1430 (pres->end - offset) >= 0xbffff) 1431 break; 1432 } 1433 if (i >= 3) 1434 return; 1435 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1436 BUG_ON(res == NULL); 1437 res->name = "Legacy VGA memory"; 1438 res->flags = IORESOURCE_MEM; 1439 res->start = 0xa0000 + offset; 1440 res->end = 0xbffff + offset; 1441 pr_debug("Candidate VGA memory: %pR\n", res); 1442 if (request_resource(pres, res)) { 1443 printk(KERN_DEBUG 1444 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1445 pci_domain_nr(bus), bus->number, res); 1446 kfree(res); 1447 } 1448 } 1449 1450 void __init pcibios_resource_survey(void) 1451 { 1452 struct pci_bus *b; 1453 1454 /* Allocate and assign resources. If we re-assign everything, then 1455 * we skip the allocate phase 1456 */ 1457 list_for_each_entry(b, &pci_root_buses, node) 1458 pcibios_allocate_bus_resources(b); 1459 1460 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1461 pcibios_allocate_resources(0); 1462 pcibios_allocate_resources(1); 1463 } 1464 1465 /* Before we start assigning unassigned resource, we try to reserve 1466 * the low IO area and the VGA memory area if they intersect the 1467 * bus available resources to avoid allocating things on top of them 1468 */ 1469 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1470 list_for_each_entry(b, &pci_root_buses, node) 1471 pcibios_reserve_legacy_regions(b); 1472 } 1473 1474 /* Now, if the platform didn't decide to blindly trust the firmware, 1475 * we proceed to assigning things that were left unassigned 1476 */ 1477 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1478 pr_debug("PCI: Assigning unassigned resources...\n"); 1479 pci_assign_unassigned_resources(); 1480 } 1481 1482 /* Call machine dependent fixup */ 1483 if (ppc_md.pcibios_fixup) 1484 ppc_md.pcibios_fixup(); 1485 } 1486 1487 #ifdef CONFIG_HOTPLUG 1488 1489 /* This is used by the PCI hotplug driver to allocate resource 1490 * of newly plugged busses. We can try to consolidate with the 1491 * rest of the code later, for now, keep it as-is as our main 1492 * resource allocation function doesn't deal with sub-trees yet. 1493 */ 1494 void pcibios_claim_one_bus(struct pci_bus *bus) 1495 { 1496 struct pci_dev *dev; 1497 struct pci_bus *child_bus; 1498 1499 list_for_each_entry(dev, &bus->devices, bus_list) { 1500 int i; 1501 1502 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1503 struct resource *r = &dev->resource[i]; 1504 1505 if (r->parent || !r->start || !r->flags) 1506 continue; 1507 1508 pr_debug("PCI: Claiming %s: " 1509 "Resource %d: %016llx..%016llx [%x]\n", 1510 pci_name(dev), i, 1511 (unsigned long long)r->start, 1512 (unsigned long long)r->end, 1513 (unsigned int)r->flags); 1514 1515 pci_claim_resource(dev, i); 1516 } 1517 } 1518 1519 list_for_each_entry(child_bus, &bus->children, node) 1520 pcibios_claim_one_bus(child_bus); 1521 } 1522 1523 1524 /* pcibios_finish_adding_to_bus 1525 * 1526 * This is to be called by the hotplug code after devices have been 1527 * added to a bus, this include calling it for a PHB that is just 1528 * being added 1529 */ 1530 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1531 { 1532 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1533 pci_domain_nr(bus), bus->number); 1534 1535 /* Allocate bus and devices resources */ 1536 pcibios_allocate_bus_resources(bus); 1537 pcibios_claim_one_bus(bus); 1538 1539 /* Add new devices to global lists. Register in proc, sysfs. */ 1540 pci_bus_add_devices(bus); 1541 1542 /* Fixup EEH */ 1543 eeh_add_device_tree_late(bus); 1544 } 1545 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1546 1547 #endif /* CONFIG_HOTPLUG */ 1548 1549 int pcibios_enable_device(struct pci_dev *dev, int mask) 1550 { 1551 if (ppc_md.pcibios_enable_device_hook) 1552 if (ppc_md.pcibios_enable_device_hook(dev)) 1553 return -EINVAL; 1554 1555 return pci_enable_resources(dev, mask); 1556 } 1557 1558 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) 1559 { 1560 struct pci_bus *bus = hose->bus; 1561 struct resource *res; 1562 int i; 1563 1564 /* Hookup PHB IO resource */ 1565 bus->resource[0] = res = &hose->io_resource; 1566 1567 if (!res->flags) { 1568 printk(KERN_WARNING "PCI: I/O resource not set for host" 1569 " bridge %s (domain %d)\n", 1570 hose->dn->full_name, hose->global_number); 1571 #ifdef CONFIG_PPC32 1572 /* Workaround for lack of IO resource only on 32-bit */ 1573 res->start = (unsigned long)hose->io_base_virt - isa_io_base; 1574 res->end = res->start + IO_SPACE_LIMIT; 1575 res->flags = IORESOURCE_IO; 1576 #endif /* CONFIG_PPC32 */ 1577 } 1578 1579 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", 1580 (unsigned long long)res->start, 1581 (unsigned long long)res->end, 1582 (unsigned long)res->flags); 1583 1584 /* Hookup PHB Memory resources */ 1585 for (i = 0; i < 3; ++i) { 1586 res = &hose->mem_resources[i]; 1587 if (!res->flags) { 1588 if (i > 0) 1589 continue; 1590 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1591 "host bridge %s (domain %d)\n", 1592 hose->dn->full_name, hose->global_number); 1593 #ifdef CONFIG_PPC32 1594 /* Workaround for lack of MEM resource only on 32-bit */ 1595 res->start = hose->pci_mem_offset; 1596 res->end = (resource_size_t)-1LL; 1597 res->flags = IORESOURCE_MEM; 1598 #endif /* CONFIG_PPC32 */ 1599 } 1600 bus->resource[i+1] = res; 1601 1602 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, 1603 (unsigned long long)res->start, 1604 (unsigned long long)res->end, 1605 (unsigned long)res->flags); 1606 } 1607 1608 pr_debug("PCI: PHB MEM offset = %016llx\n", 1609 (unsigned long long)hose->pci_mem_offset); 1610 pr_debug("PCI: PHB IO offset = %08lx\n", 1611 (unsigned long)hose->io_base_virt - _IO_BASE); 1612 1613 } 1614 1615 /* 1616 * Null PCI config access functions, for the case when we can't 1617 * find a hose. 1618 */ 1619 #define NULL_PCI_OP(rw, size, type) \ 1620 static int \ 1621 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1622 { \ 1623 return PCIBIOS_DEVICE_NOT_FOUND; \ 1624 } 1625 1626 static int 1627 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1628 int len, u32 *val) 1629 { 1630 return PCIBIOS_DEVICE_NOT_FOUND; 1631 } 1632 1633 static int 1634 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1635 int len, u32 val) 1636 { 1637 return PCIBIOS_DEVICE_NOT_FOUND; 1638 } 1639 1640 static struct pci_ops null_pci_ops = 1641 { 1642 .read = null_read_config, 1643 .write = null_write_config, 1644 }; 1645 1646 /* 1647 * These functions are used early on before PCI scanning is done 1648 * and all of the pci_dev and pci_bus structures have been created. 1649 */ 1650 static struct pci_bus * 1651 fake_pci_bus(struct pci_controller *hose, int busnr) 1652 { 1653 static struct pci_bus bus; 1654 1655 if (hose == 0) { 1656 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1657 } 1658 bus.number = busnr; 1659 bus.sysdata = hose; 1660 bus.ops = hose? hose->ops: &null_pci_ops; 1661 return &bus; 1662 } 1663 1664 #define EARLY_PCI_OP(rw, size, type) \ 1665 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1666 int devfn, int offset, type value) \ 1667 { \ 1668 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1669 devfn, offset, value); \ 1670 } 1671 1672 EARLY_PCI_OP(read, byte, u8 *) 1673 EARLY_PCI_OP(read, word, u16 *) 1674 EARLY_PCI_OP(read, dword, u32 *) 1675 EARLY_PCI_OP(write, byte, u8) 1676 EARLY_PCI_OP(write, word, u16) 1677 EARLY_PCI_OP(write, dword, u32) 1678 1679 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1680 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1681 int cap) 1682 { 1683 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1684 } 1685 1686 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1687 { 1688 struct pci_controller *hose = bus->sysdata; 1689 1690 return of_node_get(hose->dn); 1691 } 1692 1693 /** 1694 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1695 * @hose: Pointer to the PCI host controller instance structure 1696 */ 1697 void __devinit pcibios_scan_phb(struct pci_controller *hose) 1698 { 1699 struct pci_bus *bus; 1700 struct device_node *node = hose->dn; 1701 int mode; 1702 1703 pr_debug("PCI: Scanning PHB %s\n", 1704 node ? node->full_name : "<NO NAME>"); 1705 1706 /* Create an empty bus for the toplevel */ 1707 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose); 1708 if (bus == NULL) { 1709 pr_err("Failed to create bus for PCI domain %04x\n", 1710 hose->global_number); 1711 return; 1712 } 1713 bus->secondary = hose->first_busno; 1714 hose->bus = bus; 1715 1716 /* Get some IO space for the new PHB */ 1717 pcibios_setup_phb_io_space(hose); 1718 1719 /* Wire up PHB bus resources */ 1720 pcibios_setup_phb_resources(hose); 1721 1722 /* Get probe mode and perform scan */ 1723 mode = PCI_PROBE_NORMAL; 1724 if (node && ppc_md.pci_probe_mode) 1725 mode = ppc_md.pci_probe_mode(bus); 1726 pr_debug(" probe mode: %d\n", mode); 1727 if (mode == PCI_PROBE_DEVTREE) { 1728 bus->subordinate = hose->last_busno; 1729 of_scan_bus(node, bus); 1730 } 1731 1732 if (mode == PCI_PROBE_NORMAL) 1733 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); 1734 1735 /* Configure PCI Express settings */ 1736 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1737 struct pci_bus *child; 1738 list_for_each_entry(child, &bus->children, node) { 1739 struct pci_dev *self = child->self; 1740 if (!self) 1741 continue; 1742 pcie_bus_configure_settings(child, self->pcie_mpss); 1743 } 1744 } 1745 } 1746 1747 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1748 { 1749 int i, class = dev->class >> 8; 1750 1751 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1752 class == PCI_CLASS_BRIDGE_OTHER) && 1753 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1754 (dev->bus->parent == NULL)) { 1755 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1756 dev->resource[i].start = 0; 1757 dev->resource[i].end = 0; 1758 dev->resource[i].flags = 0; 1759 } 1760 } 1761 } 1762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1764