1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/export.h> 25 #include <linux/of_address.h> 26 #include <linux/of_pci.h> 27 #include <linux/mm.h> 28 #include <linux/list.h> 29 #include <linux/syscalls.h> 30 #include <linux/irq.h> 31 #include <linux/vmalloc.h> 32 #include <linux/slab.h> 33 #include <linux/vgaarb.h> 34 35 #include <asm/processor.h> 36 #include <asm/io.h> 37 #include <asm/prom.h> 38 #include <asm/pci-bridge.h> 39 #include <asm/byteorder.h> 40 #include <asm/machdep.h> 41 #include <asm/ppc-pci.h> 42 #include <asm/eeh.h> 43 44 static DEFINE_SPINLOCK(hose_spinlock); 45 LIST_HEAD(hose_list); 46 47 /* XXX kill that some day ... */ 48 static int global_phb_number; /* Global phb counter */ 49 50 /* ISA Memory physical address */ 51 resource_size_t isa_mem_base; 52 53 54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 55 56 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 57 { 58 pci_dma_ops = dma_ops; 59 } 60 61 struct dma_map_ops *get_pci_dma_ops(void) 62 { 63 return pci_dma_ops; 64 } 65 EXPORT_SYMBOL(get_pci_dma_ops); 66 67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 68 { 69 struct pci_controller *phb; 70 71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 72 if (phb == NULL) 73 return NULL; 74 spin_lock(&hose_spinlock); 75 phb->global_number = global_phb_number++; 76 list_add_tail(&phb->list_node, &hose_list); 77 spin_unlock(&hose_spinlock); 78 phb->dn = dev; 79 phb->is_dynamic = mem_init_done; 80 #ifdef CONFIG_PPC64 81 if (dev) { 82 int nid = of_node_to_nid(dev); 83 84 if (nid < 0 || !node_online(nid)) 85 nid = -1; 86 87 PHB_SET_NODE(phb, nid); 88 } 89 #endif 90 return phb; 91 } 92 93 void pcibios_free_controller(struct pci_controller *phb) 94 { 95 spin_lock(&hose_spinlock); 96 list_del(&phb->list_node); 97 spin_unlock(&hose_spinlock); 98 99 if (phb->is_dynamic) 100 kfree(phb); 101 } 102 103 /* 104 * The function is used to return the minimal alignment 105 * for memory or I/O windows of the associated P2P bridge. 106 * By default, 4KiB alignment for I/O windows and 1MiB for 107 * memory windows. 108 */ 109 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 110 unsigned long type) 111 { 112 if (ppc_md.pcibios_window_alignment) 113 return ppc_md.pcibios_window_alignment(bus, type); 114 115 /* 116 * PCI core will figure out the default 117 * alignment: 4KiB for I/O and 1MiB for 118 * memory window. 119 */ 120 return 1; 121 } 122 123 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 124 { 125 #ifdef CONFIG_PPC64 126 return hose->pci_io_size; 127 #else 128 return resource_size(&hose->io_resource); 129 #endif 130 } 131 132 int pcibios_vaddr_is_ioport(void __iomem *address) 133 { 134 int ret = 0; 135 struct pci_controller *hose; 136 resource_size_t size; 137 138 spin_lock(&hose_spinlock); 139 list_for_each_entry(hose, &hose_list, list_node) { 140 size = pcibios_io_size(hose); 141 if (address >= hose->io_base_virt && 142 address < (hose->io_base_virt + size)) { 143 ret = 1; 144 break; 145 } 146 } 147 spin_unlock(&hose_spinlock); 148 return ret; 149 } 150 151 unsigned long pci_address_to_pio(phys_addr_t address) 152 { 153 struct pci_controller *hose; 154 resource_size_t size; 155 unsigned long ret = ~0; 156 157 spin_lock(&hose_spinlock); 158 list_for_each_entry(hose, &hose_list, list_node) { 159 size = pcibios_io_size(hose); 160 if (address >= hose->io_base_phys && 161 address < (hose->io_base_phys + size)) { 162 unsigned long base = 163 (unsigned long)hose->io_base_virt - _IO_BASE; 164 ret = base + (address - hose->io_base_phys); 165 break; 166 } 167 } 168 spin_unlock(&hose_spinlock); 169 170 return ret; 171 } 172 EXPORT_SYMBOL_GPL(pci_address_to_pio); 173 174 /* 175 * Return the domain number for this bus. 176 */ 177 int pci_domain_nr(struct pci_bus *bus) 178 { 179 struct pci_controller *hose = pci_bus_to_host(bus); 180 181 return hose->global_number; 182 } 183 EXPORT_SYMBOL(pci_domain_nr); 184 185 /* This routine is meant to be used early during boot, when the 186 * PCI bus numbers have not yet been assigned, and you need to 187 * issue PCI config cycles to an OF device. 188 * It could also be used to "fix" RTAS config cycles if you want 189 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 190 * config cycles. 191 */ 192 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 193 { 194 while(node) { 195 struct pci_controller *hose, *tmp; 196 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 197 if (hose->dn == node) 198 return hose; 199 node = node->parent; 200 } 201 return NULL; 202 } 203 204 static ssize_t pci_show_devspec(struct device *dev, 205 struct device_attribute *attr, char *buf) 206 { 207 struct pci_dev *pdev; 208 struct device_node *np; 209 210 pdev = to_pci_dev (dev); 211 np = pci_device_to_OF_node(pdev); 212 if (np == NULL || np->full_name == NULL) 213 return 0; 214 return sprintf(buf, "%s", np->full_name); 215 } 216 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 217 218 /* Add sysfs properties */ 219 int pcibios_add_platform_entries(struct pci_dev *pdev) 220 { 221 return device_create_file(&pdev->dev, &dev_attr_devspec); 222 } 223 224 /* 225 * Reads the interrupt pin to determine if interrupt is use by card. 226 * If the interrupt is used, then gets the interrupt line from the 227 * openfirmware and sets it in the pci_dev and pci_config line. 228 */ 229 static int pci_read_irq_line(struct pci_dev *pci_dev) 230 { 231 struct of_irq oirq; 232 unsigned int virq; 233 234 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 235 236 #ifdef DEBUG 237 memset(&oirq, 0xff, sizeof(oirq)); 238 #endif 239 /* Try to get a mapping from the device-tree */ 240 if (of_irq_map_pci(pci_dev, &oirq)) { 241 u8 line, pin; 242 243 /* If that fails, lets fallback to what is in the config 244 * space and map that through the default controller. We 245 * also set the type to level low since that's what PCI 246 * interrupts are. If your platform does differently, then 247 * either provide a proper interrupt tree or don't use this 248 * function. 249 */ 250 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 251 return -1; 252 if (pin == 0) 253 return -1; 254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 255 line == 0xff || line == 0) { 256 return -1; 257 } 258 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 259 line, pin); 260 261 virq = irq_create_mapping(NULL, line); 262 if (virq != NO_IRQ) 263 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 264 } else { 265 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 266 oirq.size, oirq.specifier[0], oirq.specifier[1], 267 of_node_full_name(oirq.controller)); 268 269 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 270 oirq.size); 271 } 272 if(virq == NO_IRQ) { 273 pr_debug(" Failed to map !\n"); 274 return -1; 275 } 276 277 pr_debug(" Mapped to linux irq %d\n", virq); 278 279 pci_dev->irq = virq; 280 281 return 0; 282 } 283 284 /* 285 * Platform support for /proc/bus/pci/X/Y mmap()s, 286 * modelled on the sparc64 implementation by Dave Miller. 287 * -- paulus. 288 */ 289 290 /* 291 * Adjust vm_pgoff of VMA such that it is the physical page offset 292 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 293 * 294 * Basically, the user finds the base address for his device which he wishes 295 * to mmap. They read the 32-bit value from the config space base register, 296 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 297 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 298 * 299 * Returns negative error code on failure, zero on success. 300 */ 301 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 302 resource_size_t *offset, 303 enum pci_mmap_state mmap_state) 304 { 305 struct pci_controller *hose = pci_bus_to_host(dev->bus); 306 unsigned long io_offset = 0; 307 int i, res_bit; 308 309 if (hose == 0) 310 return NULL; /* should never happen */ 311 312 /* If memory, add on the PCI bridge address offset */ 313 if (mmap_state == pci_mmap_mem) { 314 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 315 *offset += hose->pci_mem_offset; 316 #endif 317 res_bit = IORESOURCE_MEM; 318 } else { 319 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 320 *offset += io_offset; 321 res_bit = IORESOURCE_IO; 322 } 323 324 /* 325 * Check that the offset requested corresponds to one of the 326 * resources of the device. 327 */ 328 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 329 struct resource *rp = &dev->resource[i]; 330 int flags = rp->flags; 331 332 /* treat ROM as memory (should be already) */ 333 if (i == PCI_ROM_RESOURCE) 334 flags |= IORESOURCE_MEM; 335 336 /* Active and same type? */ 337 if ((flags & res_bit) == 0) 338 continue; 339 340 /* In the range of this resource? */ 341 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 342 continue; 343 344 /* found it! construct the final physical address */ 345 if (mmap_state == pci_mmap_io) 346 *offset += hose->io_base_phys - io_offset; 347 return rp; 348 } 349 350 return NULL; 351 } 352 353 /* 354 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 355 * device mapping. 356 */ 357 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 358 pgprot_t protection, 359 enum pci_mmap_state mmap_state, 360 int write_combine) 361 { 362 unsigned long prot = pgprot_val(protection); 363 364 /* Write combine is always 0 on non-memory space mappings. On 365 * memory space, if the user didn't pass 1, we check for a 366 * "prefetchable" resource. This is a bit hackish, but we use 367 * this to workaround the inability of /sysfs to provide a write 368 * combine bit 369 */ 370 if (mmap_state != pci_mmap_mem) 371 write_combine = 0; 372 else if (write_combine == 0) { 373 if (rp->flags & IORESOURCE_PREFETCH) 374 write_combine = 1; 375 } 376 377 /* XXX would be nice to have a way to ask for write-through */ 378 if (write_combine) 379 return pgprot_noncached_wc(prot); 380 else 381 return pgprot_noncached(prot); 382 } 383 384 /* 385 * This one is used by /dev/mem and fbdev who have no clue about the 386 * PCI device, it tries to find the PCI device first and calls the 387 * above routine 388 */ 389 pgprot_t pci_phys_mem_access_prot(struct file *file, 390 unsigned long pfn, 391 unsigned long size, 392 pgprot_t prot) 393 { 394 struct pci_dev *pdev = NULL; 395 struct resource *found = NULL; 396 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 397 int i; 398 399 if (page_is_ram(pfn)) 400 return prot; 401 402 prot = pgprot_noncached(prot); 403 for_each_pci_dev(pdev) { 404 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 405 struct resource *rp = &pdev->resource[i]; 406 int flags = rp->flags; 407 408 /* Active and same type? */ 409 if ((flags & IORESOURCE_MEM) == 0) 410 continue; 411 /* In the range of this resource? */ 412 if (offset < (rp->start & PAGE_MASK) || 413 offset > rp->end) 414 continue; 415 found = rp; 416 break; 417 } 418 if (found) 419 break; 420 } 421 if (found) { 422 if (found->flags & IORESOURCE_PREFETCH) 423 prot = pgprot_noncached_wc(prot); 424 pci_dev_put(pdev); 425 } 426 427 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 428 (unsigned long long)offset, pgprot_val(prot)); 429 430 return prot; 431 } 432 433 434 /* 435 * Perform the actual remap of the pages for a PCI device mapping, as 436 * appropriate for this architecture. The region in the process to map 437 * is described by vm_start and vm_end members of VMA, the base physical 438 * address is found in vm_pgoff. 439 * The pci device structure is provided so that architectures may make mapping 440 * decisions on a per-device or per-bus basis. 441 * 442 * Returns a negative error code on failure, zero on success. 443 */ 444 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 445 enum pci_mmap_state mmap_state, int write_combine) 446 { 447 resource_size_t offset = 448 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 449 struct resource *rp; 450 int ret; 451 452 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 453 if (rp == NULL) 454 return -EINVAL; 455 456 vma->vm_pgoff = offset >> PAGE_SHIFT; 457 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 458 vma->vm_page_prot, 459 mmap_state, write_combine); 460 461 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 462 vma->vm_end - vma->vm_start, vma->vm_page_prot); 463 464 return ret; 465 } 466 467 /* This provides legacy IO read access on a bus */ 468 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 469 { 470 unsigned long offset; 471 struct pci_controller *hose = pci_bus_to_host(bus); 472 struct resource *rp = &hose->io_resource; 473 void __iomem *addr; 474 475 /* Check if port can be supported by that bus. We only check 476 * the ranges of the PHB though, not the bus itself as the rules 477 * for forwarding legacy cycles down bridges are not our problem 478 * here. So if the host bridge supports it, we do it. 479 */ 480 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 481 offset += port; 482 483 if (!(rp->flags & IORESOURCE_IO)) 484 return -ENXIO; 485 if (offset < rp->start || (offset + size) > rp->end) 486 return -ENXIO; 487 addr = hose->io_base_virt + port; 488 489 switch(size) { 490 case 1: 491 *((u8 *)val) = in_8(addr); 492 return 1; 493 case 2: 494 if (port & 1) 495 return -EINVAL; 496 *((u16 *)val) = in_le16(addr); 497 return 2; 498 case 4: 499 if (port & 3) 500 return -EINVAL; 501 *((u32 *)val) = in_le32(addr); 502 return 4; 503 } 504 return -EINVAL; 505 } 506 507 /* This provides legacy IO write access on a bus */ 508 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 509 { 510 unsigned long offset; 511 struct pci_controller *hose = pci_bus_to_host(bus); 512 struct resource *rp = &hose->io_resource; 513 void __iomem *addr; 514 515 /* Check if port can be supported by that bus. We only check 516 * the ranges of the PHB though, not the bus itself as the rules 517 * for forwarding legacy cycles down bridges are not our problem 518 * here. So if the host bridge supports it, we do it. 519 */ 520 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 521 offset += port; 522 523 if (!(rp->flags & IORESOURCE_IO)) 524 return -ENXIO; 525 if (offset < rp->start || (offset + size) > rp->end) 526 return -ENXIO; 527 addr = hose->io_base_virt + port; 528 529 /* WARNING: The generic code is idiotic. It gets passed a pointer 530 * to what can be a 1, 2 or 4 byte quantity and always reads that 531 * as a u32, which means that we have to correct the location of 532 * the data read within those 32 bits for size 1 and 2 533 */ 534 switch(size) { 535 case 1: 536 out_8(addr, val >> 24); 537 return 1; 538 case 2: 539 if (port & 1) 540 return -EINVAL; 541 out_le16(addr, val >> 16); 542 return 2; 543 case 4: 544 if (port & 3) 545 return -EINVAL; 546 out_le32(addr, val); 547 return 4; 548 } 549 return -EINVAL; 550 } 551 552 /* This provides legacy IO or memory mmap access on a bus */ 553 int pci_mmap_legacy_page_range(struct pci_bus *bus, 554 struct vm_area_struct *vma, 555 enum pci_mmap_state mmap_state) 556 { 557 struct pci_controller *hose = pci_bus_to_host(bus); 558 resource_size_t offset = 559 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 560 resource_size_t size = vma->vm_end - vma->vm_start; 561 struct resource *rp; 562 563 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 564 pci_domain_nr(bus), bus->number, 565 mmap_state == pci_mmap_mem ? "MEM" : "IO", 566 (unsigned long long)offset, 567 (unsigned long long)(offset + size - 1)); 568 569 if (mmap_state == pci_mmap_mem) { 570 /* Hack alert ! 571 * 572 * Because X is lame and can fail starting if it gets an error trying 573 * to mmap legacy_mem (instead of just moving on without legacy memory 574 * access) we fake it here by giving it anonymous memory, effectively 575 * behaving just like /dev/zero 576 */ 577 if ((offset + size) > hose->isa_mem_size) { 578 printk(KERN_DEBUG 579 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 580 current->comm, current->pid, pci_domain_nr(bus), bus->number); 581 if (vma->vm_flags & VM_SHARED) 582 return shmem_zero_setup(vma); 583 return 0; 584 } 585 offset += hose->isa_mem_phys; 586 } else { 587 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 588 unsigned long roffset = offset + io_offset; 589 rp = &hose->io_resource; 590 if (!(rp->flags & IORESOURCE_IO)) 591 return -ENXIO; 592 if (roffset < rp->start || (roffset + size) > rp->end) 593 return -ENXIO; 594 offset += hose->io_base_phys; 595 } 596 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 597 598 vma->vm_pgoff = offset >> PAGE_SHIFT; 599 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 600 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 601 vma->vm_end - vma->vm_start, 602 vma->vm_page_prot); 603 } 604 605 void pci_resource_to_user(const struct pci_dev *dev, int bar, 606 const struct resource *rsrc, 607 resource_size_t *start, resource_size_t *end) 608 { 609 struct pci_controller *hose = pci_bus_to_host(dev->bus); 610 resource_size_t offset = 0; 611 612 if (hose == NULL) 613 return; 614 615 if (rsrc->flags & IORESOURCE_IO) 616 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 617 618 /* We pass a fully fixed up address to userland for MMIO instead of 619 * a BAR value because X is lame and expects to be able to use that 620 * to pass to /dev/mem ! 621 * 622 * That means that we'll have potentially 64 bits values where some 623 * userland apps only expect 32 (like X itself since it thinks only 624 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 625 * 32 bits CHRPs :-( 626 * 627 * Hopefully, the sysfs insterface is immune to that gunk. Once X 628 * has been fixed (and the fix spread enough), we can re-enable the 629 * 2 lines below and pass down a BAR value to userland. In that case 630 * we'll also have to re-enable the matching code in 631 * __pci_mmap_make_offset(). 632 * 633 * BenH. 634 */ 635 #if 0 636 else if (rsrc->flags & IORESOURCE_MEM) 637 offset = hose->pci_mem_offset; 638 #endif 639 640 *start = rsrc->start - offset; 641 *end = rsrc->end - offset; 642 } 643 644 /** 645 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 646 * @hose: newly allocated pci_controller to be setup 647 * @dev: device node of the host bridge 648 * @primary: set if primary bus (32 bits only, soon to be deprecated) 649 * 650 * This function will parse the "ranges" property of a PCI host bridge device 651 * node and setup the resource mapping of a pci controller based on its 652 * content. 653 * 654 * Life would be boring if it wasn't for a few issues that we have to deal 655 * with here: 656 * 657 * - We can only cope with one IO space range and up to 3 Memory space 658 * ranges. However, some machines (thanks Apple !) tend to split their 659 * space into lots of small contiguous ranges. So we have to coalesce. 660 * 661 * - We can only cope with all memory ranges having the same offset 662 * between CPU addresses and PCI addresses. Unfortunately, some bridges 663 * are setup for a large 1:1 mapping along with a small "window" which 664 * maps PCI address 0 to some arbitrary high address of the CPU space in 665 * order to give access to the ISA memory hole. 666 * The way out of here that I've chosen for now is to always set the 667 * offset based on the first resource found, then override it if we 668 * have a different offset and the previous was set by an ISA hole. 669 * 670 * - Some busses have IO space not starting at 0, which causes trouble with 671 * the way we do our IO resource renumbering. The code somewhat deals with 672 * it for 64 bits but I would expect problems on 32 bits. 673 * 674 * - Some 32 bits platforms such as 4xx can have physical space larger than 675 * 32 bits so we need to use 64 bits values for the parsing 676 */ 677 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 678 struct device_node *dev, int primary) 679 { 680 const u32 *ranges; 681 int rlen; 682 int pna = of_n_addr_cells(dev); 683 int np = pna + 5; 684 int memno = 0, isa_hole = -1; 685 u32 pci_space; 686 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 687 unsigned long long isa_mb = 0; 688 struct resource *res; 689 690 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 691 dev->full_name, primary ? "(primary)" : ""); 692 693 /* Get ranges property */ 694 ranges = of_get_property(dev, "ranges", &rlen); 695 if (ranges == NULL) 696 return; 697 698 /* Parse it */ 699 while ((rlen -= np * 4) >= 0) { 700 /* Read next ranges element */ 701 pci_space = ranges[0]; 702 pci_addr = of_read_number(ranges + 1, 2); 703 cpu_addr = of_translate_address(dev, ranges + 3); 704 size = of_read_number(ranges + pna + 3, 2); 705 ranges += np; 706 707 /* If we failed translation or got a zero-sized region 708 * (some FW try to feed us with non sensical zero sized regions 709 * such as power3 which look like some kind of attempt at exposing 710 * the VGA memory hole) 711 */ 712 if (cpu_addr == OF_BAD_ADDR || size == 0) 713 continue; 714 715 /* Now consume following elements while they are contiguous */ 716 for (; rlen >= np * sizeof(u32); 717 ranges += np, rlen -= np * 4) { 718 if (ranges[0] != pci_space) 719 break; 720 pci_next = of_read_number(ranges + 1, 2); 721 cpu_next = of_translate_address(dev, ranges + 3); 722 if (pci_next != pci_addr + size || 723 cpu_next != cpu_addr + size) 724 break; 725 size += of_read_number(ranges + pna + 3, 2); 726 } 727 728 /* Act based on address space type */ 729 res = NULL; 730 switch ((pci_space >> 24) & 0x3) { 731 case 1: /* PCI IO space */ 732 printk(KERN_INFO 733 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 734 cpu_addr, cpu_addr + size - 1, pci_addr); 735 736 /* We support only one IO range */ 737 if (hose->pci_io_size) { 738 printk(KERN_INFO 739 " \\--> Skipped (too many) !\n"); 740 continue; 741 } 742 #ifdef CONFIG_PPC32 743 /* On 32 bits, limit I/O space to 16MB */ 744 if (size > 0x01000000) 745 size = 0x01000000; 746 747 /* 32 bits needs to map IOs here */ 748 hose->io_base_virt = ioremap(cpu_addr, size); 749 750 /* Expect trouble if pci_addr is not 0 */ 751 if (primary) 752 isa_io_base = 753 (unsigned long)hose->io_base_virt; 754 #endif /* CONFIG_PPC32 */ 755 /* pci_io_size and io_base_phys always represent IO 756 * space starting at 0 so we factor in pci_addr 757 */ 758 hose->pci_io_size = pci_addr + size; 759 hose->io_base_phys = cpu_addr - pci_addr; 760 761 /* Build resource */ 762 res = &hose->io_resource; 763 res->flags = IORESOURCE_IO; 764 res->start = pci_addr; 765 break; 766 case 2: /* PCI Memory space */ 767 case 3: /* PCI 64 bits Memory space */ 768 printk(KERN_INFO 769 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 770 cpu_addr, cpu_addr + size - 1, pci_addr, 771 (pci_space & 0x40000000) ? "Prefetch" : ""); 772 773 /* We support only 3 memory ranges */ 774 if (memno >= 3) { 775 printk(KERN_INFO 776 " \\--> Skipped (too many) !\n"); 777 continue; 778 } 779 /* Handles ISA memory hole space here */ 780 if (pci_addr == 0) { 781 isa_mb = cpu_addr; 782 isa_hole = memno; 783 if (primary || isa_mem_base == 0) 784 isa_mem_base = cpu_addr; 785 hose->isa_mem_phys = cpu_addr; 786 hose->isa_mem_size = size; 787 } 788 789 /* We get the PCI/Mem offset from the first range or 790 * the, current one if the offset came from an ISA 791 * hole. If they don't match, bugger. 792 */ 793 if (memno == 0 || 794 (isa_hole >= 0 && pci_addr != 0 && 795 hose->pci_mem_offset == isa_mb)) 796 hose->pci_mem_offset = cpu_addr - pci_addr; 797 else if (pci_addr != 0 && 798 hose->pci_mem_offset != cpu_addr - pci_addr) { 799 printk(KERN_INFO 800 " \\--> Skipped (offset mismatch) !\n"); 801 continue; 802 } 803 804 /* Build resource */ 805 res = &hose->mem_resources[memno++]; 806 res->flags = IORESOURCE_MEM; 807 if (pci_space & 0x40000000) 808 res->flags |= IORESOURCE_PREFETCH; 809 res->start = cpu_addr; 810 break; 811 } 812 if (res != NULL) { 813 res->name = dev->full_name; 814 res->end = res->start + size - 1; 815 res->parent = NULL; 816 res->sibling = NULL; 817 res->child = NULL; 818 } 819 } 820 821 /* If there's an ISA hole and the pci_mem_offset is -not- matching 822 * the ISA hole offset, then we need to remove the ISA hole from 823 * the resource list for that brige 824 */ 825 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { 826 unsigned int next = isa_hole + 1; 827 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); 828 if (next < memno) 829 memmove(&hose->mem_resources[isa_hole], 830 &hose->mem_resources[next], 831 sizeof(struct resource) * (memno - next)); 832 hose->mem_resources[--memno].flags = 0; 833 } 834 } 835 836 /* Decide whether to display the domain number in /proc */ 837 int pci_proc_domain(struct pci_bus *bus) 838 { 839 struct pci_controller *hose = pci_bus_to_host(bus); 840 841 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 842 return 0; 843 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 844 return hose->global_number != 0; 845 return 1; 846 } 847 848 /* This header fixup will do the resource fixup for all devices as they are 849 * probed, but not for bridge ranges 850 */ 851 static void pcibios_fixup_resources(struct pci_dev *dev) 852 { 853 struct pci_controller *hose = pci_bus_to_host(dev->bus); 854 int i; 855 856 if (!hose) { 857 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 858 pci_name(dev)); 859 return; 860 } 861 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 862 struct resource *res = dev->resource + i; 863 if (!res->flags) 864 continue; 865 866 /* If we're going to re-assign everything, we mark all resources 867 * as unset (and 0-base them). In addition, we mark BARs starting 868 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 869 * since in that case, we don't want to re-assign anything 870 */ 871 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 872 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 873 /* Only print message if not re-assigning */ 874 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 875 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 876 "is unassigned\n", 877 pci_name(dev), i, 878 (unsigned long long)res->start, 879 (unsigned long long)res->end, 880 (unsigned int)res->flags); 881 res->end -= res->start; 882 res->start = 0; 883 res->flags |= IORESOURCE_UNSET; 884 continue; 885 } 886 887 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", 888 pci_name(dev), i, 889 (unsigned long long)res->start,\ 890 (unsigned long long)res->end, 891 (unsigned int)res->flags); 892 } 893 894 /* Call machine specific resource fixup */ 895 if (ppc_md.pcibios_fixup_resources) 896 ppc_md.pcibios_fixup_resources(dev); 897 } 898 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 899 900 /* This function tries to figure out if a bridge resource has been initialized 901 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 902 * things go more smoothly when it gets it right. It should covers cases such 903 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 904 */ 905 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 906 struct resource *res) 907 { 908 struct pci_controller *hose = pci_bus_to_host(bus); 909 struct pci_dev *dev = bus->self; 910 resource_size_t offset; 911 u16 command; 912 int i; 913 914 /* We don't do anything if PCI_PROBE_ONLY is set */ 915 if (pci_has_flag(PCI_PROBE_ONLY)) 916 return 0; 917 918 /* Job is a bit different between memory and IO */ 919 if (res->flags & IORESOURCE_MEM) { 920 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been 921 * initialized by somebody 922 */ 923 if (res->start != hose->pci_mem_offset) 924 return 0; 925 926 /* The BAR is 0, let's check if memory decoding is enabled on 927 * the bridge. If not, we consider it unassigned 928 */ 929 pci_read_config_word(dev, PCI_COMMAND, &command); 930 if ((command & PCI_COMMAND_MEMORY) == 0) 931 return 1; 932 933 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 934 * resources covers that starting address (0 then it's good enough for 935 * us for memory 936 */ 937 for (i = 0; i < 3; i++) { 938 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 939 hose->mem_resources[i].start == hose->pci_mem_offset) 940 return 0; 941 } 942 943 /* Well, it starts at 0 and we know it will collide so we may as 944 * well consider it as unassigned. That covers the Apple case. 945 */ 946 return 1; 947 } else { 948 /* If the BAR is non-0, then we consider it assigned */ 949 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 950 if (((res->start - offset) & 0xfffffffful) != 0) 951 return 0; 952 953 /* Here, we are a bit different than memory as typically IO space 954 * starting at low addresses -is- valid. What we do instead if that 955 * we consider as unassigned anything that doesn't have IO enabled 956 * in the PCI command register, and that's it. 957 */ 958 pci_read_config_word(dev, PCI_COMMAND, &command); 959 if (command & PCI_COMMAND_IO) 960 return 0; 961 962 /* It's starting at 0 and IO is disabled in the bridge, consider 963 * it unassigned 964 */ 965 return 1; 966 } 967 } 968 969 /* Fixup resources of a PCI<->PCI bridge */ 970 static void pcibios_fixup_bridge(struct pci_bus *bus) 971 { 972 struct resource *res; 973 int i; 974 975 struct pci_dev *dev = bus->self; 976 977 pci_bus_for_each_resource(bus, res, i) { 978 if (!res || !res->flags) 979 continue; 980 if (i >= 3 && bus->self->transparent) 981 continue; 982 983 /* If we're going to reassign everything, we can 984 * shrink the P2P resource to have size as being 985 * of 0 in order to save space. 986 */ 987 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 988 res->flags |= IORESOURCE_UNSET; 989 res->start = 0; 990 res->end = -1; 991 continue; 992 } 993 994 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", 995 pci_name(dev), i, 996 (unsigned long long)res->start,\ 997 (unsigned long long)res->end, 998 (unsigned int)res->flags); 999 1000 /* Try to detect uninitialized P2P bridge resources, 1001 * and clear them out so they get re-assigned later 1002 */ 1003 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1004 res->flags = 0; 1005 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1006 } 1007 } 1008 } 1009 1010 void pcibios_setup_bus_self(struct pci_bus *bus) 1011 { 1012 /* Fix up the bus resources for P2P bridges */ 1013 if (bus->self != NULL) 1014 pcibios_fixup_bridge(bus); 1015 1016 /* Platform specific bus fixups. This is currently only used 1017 * by fsl_pci and I'm hoping to get rid of it at some point 1018 */ 1019 if (ppc_md.pcibios_fixup_bus) 1020 ppc_md.pcibios_fixup_bus(bus); 1021 1022 /* Setup bus DMA mappings */ 1023 if (ppc_md.pci_dma_bus_setup) 1024 ppc_md.pci_dma_bus_setup(bus); 1025 } 1026 1027 void pcibios_setup_device(struct pci_dev *dev) 1028 { 1029 /* Fixup NUMA node as it may not be setup yet by the generic 1030 * code and is needed by the DMA init 1031 */ 1032 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1033 1034 /* Hook up default DMA ops */ 1035 set_dma_ops(&dev->dev, pci_dma_ops); 1036 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1037 1038 /* Additional platform DMA/iommu setup */ 1039 if (ppc_md.pci_dma_dev_setup) 1040 ppc_md.pci_dma_dev_setup(dev); 1041 1042 /* Read default IRQs and fixup if necessary */ 1043 pci_read_irq_line(dev); 1044 if (ppc_md.pci_irq_fixup) 1045 ppc_md.pci_irq_fixup(dev); 1046 } 1047 1048 void pcibios_setup_bus_devices(struct pci_bus *bus) 1049 { 1050 struct pci_dev *dev; 1051 1052 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1053 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1054 1055 list_for_each_entry(dev, &bus->devices, bus_list) { 1056 /* Cardbus can call us to add new devices to a bus, so ignore 1057 * those who are already fully discovered 1058 */ 1059 if (dev->is_added) 1060 continue; 1061 1062 pcibios_setup_device(dev); 1063 } 1064 } 1065 1066 void pcibios_set_master(struct pci_dev *dev) 1067 { 1068 /* No special bus mastering setup handling */ 1069 } 1070 1071 void pcibios_fixup_bus(struct pci_bus *bus) 1072 { 1073 /* When called from the generic PCI probe, read PCI<->PCI bridge 1074 * bases. This is -not- called when generating the PCI tree from 1075 * the OF device-tree. 1076 */ 1077 if (bus->self != NULL) 1078 pci_read_bridge_bases(bus); 1079 1080 /* Now fixup the bus bus */ 1081 pcibios_setup_bus_self(bus); 1082 1083 /* Now fixup devices on that bus */ 1084 pcibios_setup_bus_devices(bus); 1085 } 1086 EXPORT_SYMBOL(pcibios_fixup_bus); 1087 1088 void pci_fixup_cardbus(struct pci_bus *bus) 1089 { 1090 /* Now fixup devices on that bus */ 1091 pcibios_setup_bus_devices(bus); 1092 } 1093 1094 1095 static int skip_isa_ioresource_align(struct pci_dev *dev) 1096 { 1097 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1098 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1099 return 1; 1100 return 0; 1101 } 1102 1103 /* 1104 * We need to avoid collisions with `mirrored' VGA ports 1105 * and other strange ISA hardware, so we always want the 1106 * addresses to be allocated in the 0x000-0x0ff region 1107 * modulo 0x400. 1108 * 1109 * Why? Because some silly external IO cards only decode 1110 * the low 10 bits of the IO address. The 0x00-0xff region 1111 * is reserved for motherboard devices that decode all 16 1112 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1113 * but we want to try to avoid allocating at 0x2900-0x2bff 1114 * which might have be mirrored at 0x0100-0x03ff.. 1115 */ 1116 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1117 resource_size_t size, resource_size_t align) 1118 { 1119 struct pci_dev *dev = data; 1120 resource_size_t start = res->start; 1121 1122 if (res->flags & IORESOURCE_IO) { 1123 if (skip_isa_ioresource_align(dev)) 1124 return start; 1125 if (start & 0x300) 1126 start = (start + 0x3ff) & ~0x3ff; 1127 } 1128 1129 return start; 1130 } 1131 EXPORT_SYMBOL(pcibios_align_resource); 1132 1133 /* 1134 * Reparent resource children of pr that conflict with res 1135 * under res, and make res replace those children. 1136 */ 1137 static int reparent_resources(struct resource *parent, 1138 struct resource *res) 1139 { 1140 struct resource *p, **pp; 1141 struct resource **firstpp = NULL; 1142 1143 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1144 if (p->end < res->start) 1145 continue; 1146 if (res->end < p->start) 1147 break; 1148 if (p->start < res->start || p->end > res->end) 1149 return -1; /* not completely contained */ 1150 if (firstpp == NULL) 1151 firstpp = pp; 1152 } 1153 if (firstpp == NULL) 1154 return -1; /* didn't find any conflicting entries? */ 1155 res->parent = parent; 1156 res->child = *firstpp; 1157 res->sibling = *pp; 1158 *firstpp = res; 1159 *pp = NULL; 1160 for (p = res->child; p != NULL; p = p->sibling) { 1161 p->parent = res; 1162 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1163 p->name, 1164 (unsigned long long)p->start, 1165 (unsigned long long)p->end, res->name); 1166 } 1167 return 0; 1168 } 1169 1170 /* 1171 * Handle resources of PCI devices. If the world were perfect, we could 1172 * just allocate all the resource regions and do nothing more. It isn't. 1173 * On the other hand, we cannot just re-allocate all devices, as it would 1174 * require us to know lots of host bridge internals. So we attempt to 1175 * keep as much of the original configuration as possible, but tweak it 1176 * when it's found to be wrong. 1177 * 1178 * Known BIOS problems we have to work around: 1179 * - I/O or memory regions not configured 1180 * - regions configured, but not enabled in the command register 1181 * - bogus I/O addresses above 64K used 1182 * - expansion ROMs left enabled (this may sound harmless, but given 1183 * the fact the PCI specs explicitly allow address decoders to be 1184 * shared between expansion ROMs and other resource regions, it's 1185 * at least dangerous) 1186 * 1187 * Our solution: 1188 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1189 * This gives us fixed barriers on where we can allocate. 1190 * (2) Allocate resources for all enabled devices. If there is 1191 * a collision, just mark the resource as unallocated. Also 1192 * disable expansion ROMs during this step. 1193 * (3) Try to allocate resources for disabled devices. If the 1194 * resources were assigned correctly, everything goes well, 1195 * if they weren't, they won't disturb allocation of other 1196 * resources. 1197 * (4) Assign new addresses to resources which were either 1198 * not configured at all or misconfigured. If explicitly 1199 * requested by the user, configure expansion ROM address 1200 * as well. 1201 */ 1202 1203 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1204 { 1205 struct pci_bus *b; 1206 int i; 1207 struct resource *res, *pr; 1208 1209 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1210 pci_domain_nr(bus), bus->number); 1211 1212 pci_bus_for_each_resource(bus, res, i) { 1213 if (!res || !res->flags || res->start > res->end || res->parent) 1214 continue; 1215 1216 /* If the resource was left unset at this point, we clear it */ 1217 if (res->flags & IORESOURCE_UNSET) 1218 goto clear_resource; 1219 1220 if (bus->parent == NULL) 1221 pr = (res->flags & IORESOURCE_IO) ? 1222 &ioport_resource : &iomem_resource; 1223 else { 1224 pr = pci_find_parent_resource(bus->self, res); 1225 if (pr == res) { 1226 /* this happens when the generic PCI 1227 * code (wrongly) decides that this 1228 * bridge is transparent -- paulus 1229 */ 1230 continue; 1231 } 1232 } 1233 1234 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1235 "[0x%x], parent %p (%s)\n", 1236 bus->self ? pci_name(bus->self) : "PHB", 1237 bus->number, i, 1238 (unsigned long long)res->start, 1239 (unsigned long long)res->end, 1240 (unsigned int)res->flags, 1241 pr, (pr && pr->name) ? pr->name : "nil"); 1242 1243 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1244 if (request_resource(pr, res) == 0) 1245 continue; 1246 /* 1247 * Must be a conflict with an existing entry. 1248 * Move that entry (or entries) under the 1249 * bridge resource and try again. 1250 */ 1251 if (reparent_resources(pr, res) == 0) 1252 continue; 1253 } 1254 pr_warning("PCI: Cannot allocate resource region " 1255 "%d of PCI bridge %d, will remap\n", i, bus->number); 1256 clear_resource: 1257 /* The resource might be figured out when doing 1258 * reassignment based on the resources required 1259 * by the downstream PCI devices. Here we set 1260 * the size of the resource to be 0 in order to 1261 * save more space. 1262 */ 1263 res->start = 0; 1264 res->end = -1; 1265 res->flags = 0; 1266 } 1267 1268 list_for_each_entry(b, &bus->children, node) 1269 pcibios_allocate_bus_resources(b); 1270 } 1271 1272 static inline void alloc_resource(struct pci_dev *dev, int idx) 1273 { 1274 struct resource *pr, *r = &dev->resource[idx]; 1275 1276 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1277 pci_name(dev), idx, 1278 (unsigned long long)r->start, 1279 (unsigned long long)r->end, 1280 (unsigned int)r->flags); 1281 1282 pr = pci_find_parent_resource(dev, r); 1283 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1284 request_resource(pr, r) < 0) { 1285 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1286 " of device %s, will remap\n", idx, pci_name(dev)); 1287 if (pr) 1288 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1289 pr, 1290 (unsigned long long)pr->start, 1291 (unsigned long long)pr->end, 1292 (unsigned int)pr->flags); 1293 /* We'll assign a new address later */ 1294 r->flags |= IORESOURCE_UNSET; 1295 r->end -= r->start; 1296 r->start = 0; 1297 } 1298 } 1299 1300 static void __init pcibios_allocate_resources(int pass) 1301 { 1302 struct pci_dev *dev = NULL; 1303 int idx, disabled; 1304 u16 command; 1305 struct resource *r; 1306 1307 for_each_pci_dev(dev) { 1308 pci_read_config_word(dev, PCI_COMMAND, &command); 1309 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1310 r = &dev->resource[idx]; 1311 if (r->parent) /* Already allocated */ 1312 continue; 1313 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1314 continue; /* Not assigned at all */ 1315 /* We only allocate ROMs on pass 1 just in case they 1316 * have been screwed up by firmware 1317 */ 1318 if (idx == PCI_ROM_RESOURCE ) 1319 disabled = 1; 1320 if (r->flags & IORESOURCE_IO) 1321 disabled = !(command & PCI_COMMAND_IO); 1322 else 1323 disabled = !(command & PCI_COMMAND_MEMORY); 1324 if (pass == disabled) 1325 alloc_resource(dev, idx); 1326 } 1327 if (pass) 1328 continue; 1329 r = &dev->resource[PCI_ROM_RESOURCE]; 1330 if (r->flags) { 1331 /* Turn the ROM off, leave the resource region, 1332 * but keep it unregistered. 1333 */ 1334 u32 reg; 1335 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1336 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1337 pr_debug("PCI: Switching off ROM of %s\n", 1338 pci_name(dev)); 1339 r->flags &= ~IORESOURCE_ROM_ENABLE; 1340 pci_write_config_dword(dev, dev->rom_base_reg, 1341 reg & ~PCI_ROM_ADDRESS_ENABLE); 1342 } 1343 } 1344 } 1345 } 1346 1347 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1348 { 1349 struct pci_controller *hose = pci_bus_to_host(bus); 1350 resource_size_t offset; 1351 struct resource *res, *pres; 1352 int i; 1353 1354 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1355 1356 /* Check for IO */ 1357 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1358 goto no_io; 1359 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1360 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1361 BUG_ON(res == NULL); 1362 res->name = "Legacy IO"; 1363 res->flags = IORESOURCE_IO; 1364 res->start = offset; 1365 res->end = (offset + 0xfff) & 0xfffffffful; 1366 pr_debug("Candidate legacy IO: %pR\n", res); 1367 if (request_resource(&hose->io_resource, res)) { 1368 printk(KERN_DEBUG 1369 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1370 pci_domain_nr(bus), bus->number, res); 1371 kfree(res); 1372 } 1373 1374 no_io: 1375 /* Check for memory */ 1376 offset = hose->pci_mem_offset; 1377 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); 1378 for (i = 0; i < 3; i++) { 1379 pres = &hose->mem_resources[i]; 1380 if (!(pres->flags & IORESOURCE_MEM)) 1381 continue; 1382 pr_debug("hose mem res: %pR\n", pres); 1383 if ((pres->start - offset) <= 0xa0000 && 1384 (pres->end - offset) >= 0xbffff) 1385 break; 1386 } 1387 if (i >= 3) 1388 return; 1389 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1390 BUG_ON(res == NULL); 1391 res->name = "Legacy VGA memory"; 1392 res->flags = IORESOURCE_MEM; 1393 res->start = 0xa0000 + offset; 1394 res->end = 0xbffff + offset; 1395 pr_debug("Candidate VGA memory: %pR\n", res); 1396 if (request_resource(pres, res)) { 1397 printk(KERN_DEBUG 1398 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1399 pci_domain_nr(bus), bus->number, res); 1400 kfree(res); 1401 } 1402 } 1403 1404 void __init pcibios_resource_survey(void) 1405 { 1406 struct pci_bus *b; 1407 1408 /* Allocate and assign resources */ 1409 list_for_each_entry(b, &pci_root_buses, node) 1410 pcibios_allocate_bus_resources(b); 1411 pcibios_allocate_resources(0); 1412 pcibios_allocate_resources(1); 1413 1414 /* Before we start assigning unassigned resource, we try to reserve 1415 * the low IO area and the VGA memory area if they intersect the 1416 * bus available resources to avoid allocating things on top of them 1417 */ 1418 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1419 list_for_each_entry(b, &pci_root_buses, node) 1420 pcibios_reserve_legacy_regions(b); 1421 } 1422 1423 /* Now, if the platform didn't decide to blindly trust the firmware, 1424 * we proceed to assigning things that were left unassigned 1425 */ 1426 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1427 pr_debug("PCI: Assigning unassigned resources...\n"); 1428 pci_assign_unassigned_resources(); 1429 } 1430 1431 /* Call machine dependent fixup */ 1432 if (ppc_md.pcibios_fixup) 1433 ppc_md.pcibios_fixup(); 1434 } 1435 1436 /* This is used by the PCI hotplug driver to allocate resource 1437 * of newly plugged busses. We can try to consolidate with the 1438 * rest of the code later, for now, keep it as-is as our main 1439 * resource allocation function doesn't deal with sub-trees yet. 1440 */ 1441 void pcibios_claim_one_bus(struct pci_bus *bus) 1442 { 1443 struct pci_dev *dev; 1444 struct pci_bus *child_bus; 1445 1446 list_for_each_entry(dev, &bus->devices, bus_list) { 1447 int i; 1448 1449 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1450 struct resource *r = &dev->resource[i]; 1451 1452 if (r->parent || !r->start || !r->flags) 1453 continue; 1454 1455 pr_debug("PCI: Claiming %s: " 1456 "Resource %d: %016llx..%016llx [%x]\n", 1457 pci_name(dev), i, 1458 (unsigned long long)r->start, 1459 (unsigned long long)r->end, 1460 (unsigned int)r->flags); 1461 1462 pci_claim_resource(dev, i); 1463 } 1464 } 1465 1466 list_for_each_entry(child_bus, &bus->children, node) 1467 pcibios_claim_one_bus(child_bus); 1468 } 1469 1470 1471 /* pcibios_finish_adding_to_bus 1472 * 1473 * This is to be called by the hotplug code after devices have been 1474 * added to a bus, this include calling it for a PHB that is just 1475 * being added 1476 */ 1477 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1478 { 1479 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1480 pci_domain_nr(bus), bus->number); 1481 1482 /* Allocate bus and devices resources */ 1483 pcibios_allocate_bus_resources(bus); 1484 pcibios_claim_one_bus(bus); 1485 1486 /* Fixup EEH */ 1487 eeh_add_device_tree_late(bus); 1488 1489 /* Add new devices to global lists. Register in proc, sysfs. */ 1490 pci_bus_add_devices(bus); 1491 1492 /* sysfs files should only be added after devices are added */ 1493 eeh_add_sysfs_files(bus); 1494 } 1495 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1496 1497 int pcibios_enable_device(struct pci_dev *dev, int mask) 1498 { 1499 if (ppc_md.pcibios_enable_device_hook) 1500 if (ppc_md.pcibios_enable_device_hook(dev)) 1501 return -EINVAL; 1502 1503 /* avoid pcie irq fix up impact on cardbus */ 1504 if (dev->hdr_type != PCI_HEADER_TYPE_CARDBUS) 1505 pcibios_setup_device(dev); 1506 1507 return pci_enable_resources(dev, mask); 1508 } 1509 1510 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1511 { 1512 return (unsigned long) hose->io_base_virt - _IO_BASE; 1513 } 1514 1515 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1516 struct list_head *resources) 1517 { 1518 struct resource *res; 1519 int i; 1520 1521 /* Hookup PHB IO resource */ 1522 res = &hose->io_resource; 1523 1524 if (!res->flags) { 1525 printk(KERN_WARNING "PCI: I/O resource not set for host" 1526 " bridge %s (domain %d)\n", 1527 hose->dn->full_name, hose->global_number); 1528 #ifdef CONFIG_PPC32 1529 /* Workaround for lack of IO resource only on 32-bit */ 1530 res->start = (unsigned long)hose->io_base_virt - isa_io_base; 1531 res->end = res->start + IO_SPACE_LIMIT; 1532 res->flags = IORESOURCE_IO; 1533 #endif /* CONFIG_PPC32 */ 1534 } 1535 1536 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", 1537 (unsigned long long)res->start, 1538 (unsigned long long)res->end, 1539 (unsigned long)res->flags); 1540 pci_add_resource_offset(resources, res, pcibios_io_space_offset(hose)); 1541 1542 /* Hookup PHB Memory resources */ 1543 for (i = 0; i < 3; ++i) { 1544 res = &hose->mem_resources[i]; 1545 if (!res->flags) { 1546 if (i > 0) 1547 continue; 1548 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1549 "host bridge %s (domain %d)\n", 1550 hose->dn->full_name, hose->global_number); 1551 #ifdef CONFIG_PPC32 1552 /* Workaround for lack of MEM resource only on 32-bit */ 1553 res->start = hose->pci_mem_offset; 1554 res->end = (resource_size_t)-1LL; 1555 res->flags = IORESOURCE_MEM; 1556 #endif /* CONFIG_PPC32 */ 1557 } 1558 1559 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, 1560 (unsigned long long)res->start, 1561 (unsigned long long)res->end, 1562 (unsigned long)res->flags); 1563 pci_add_resource_offset(resources, res, hose->pci_mem_offset); 1564 } 1565 1566 pr_debug("PCI: PHB MEM offset = %016llx\n", 1567 (unsigned long long)hose->pci_mem_offset); 1568 pr_debug("PCI: PHB IO offset = %08lx\n", 1569 (unsigned long)hose->io_base_virt - _IO_BASE); 1570 1571 } 1572 1573 /* 1574 * Null PCI config access functions, for the case when we can't 1575 * find a hose. 1576 */ 1577 #define NULL_PCI_OP(rw, size, type) \ 1578 static int \ 1579 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1580 { \ 1581 return PCIBIOS_DEVICE_NOT_FOUND; \ 1582 } 1583 1584 static int 1585 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1586 int len, u32 *val) 1587 { 1588 return PCIBIOS_DEVICE_NOT_FOUND; 1589 } 1590 1591 static int 1592 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1593 int len, u32 val) 1594 { 1595 return PCIBIOS_DEVICE_NOT_FOUND; 1596 } 1597 1598 static struct pci_ops null_pci_ops = 1599 { 1600 .read = null_read_config, 1601 .write = null_write_config, 1602 }; 1603 1604 /* 1605 * These functions are used early on before PCI scanning is done 1606 * and all of the pci_dev and pci_bus structures have been created. 1607 */ 1608 static struct pci_bus * 1609 fake_pci_bus(struct pci_controller *hose, int busnr) 1610 { 1611 static struct pci_bus bus; 1612 1613 if (hose == 0) { 1614 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1615 } 1616 bus.number = busnr; 1617 bus.sysdata = hose; 1618 bus.ops = hose? hose->ops: &null_pci_ops; 1619 return &bus; 1620 } 1621 1622 #define EARLY_PCI_OP(rw, size, type) \ 1623 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1624 int devfn, int offset, type value) \ 1625 { \ 1626 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1627 devfn, offset, value); \ 1628 } 1629 1630 EARLY_PCI_OP(read, byte, u8 *) 1631 EARLY_PCI_OP(read, word, u16 *) 1632 EARLY_PCI_OP(read, dword, u32 *) 1633 EARLY_PCI_OP(write, byte, u8) 1634 EARLY_PCI_OP(write, word, u16) 1635 EARLY_PCI_OP(write, dword, u32) 1636 1637 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1638 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1639 int cap) 1640 { 1641 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1642 } 1643 1644 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1645 { 1646 struct pci_controller *hose = bus->sysdata; 1647 1648 return of_node_get(hose->dn); 1649 } 1650 1651 /** 1652 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1653 * @hose: Pointer to the PCI host controller instance structure 1654 */ 1655 void pcibios_scan_phb(struct pci_controller *hose) 1656 { 1657 LIST_HEAD(resources); 1658 struct pci_bus *bus; 1659 struct device_node *node = hose->dn; 1660 int mode; 1661 1662 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); 1663 1664 /* Get some IO space for the new PHB */ 1665 pcibios_setup_phb_io_space(hose); 1666 1667 /* Wire up PHB bus resources */ 1668 pcibios_setup_phb_resources(hose, &resources); 1669 1670 hose->busn.start = hose->first_busno; 1671 hose->busn.end = hose->last_busno; 1672 hose->busn.flags = IORESOURCE_BUS; 1673 pci_add_resource(&resources, &hose->busn); 1674 1675 /* Create an empty bus for the toplevel */ 1676 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1677 hose->ops, hose, &resources); 1678 if (bus == NULL) { 1679 pr_err("Failed to create bus for PCI domain %04x\n", 1680 hose->global_number); 1681 pci_free_resource_list(&resources); 1682 return; 1683 } 1684 hose->bus = bus; 1685 1686 /* Get probe mode and perform scan */ 1687 mode = PCI_PROBE_NORMAL; 1688 if (node && ppc_md.pci_probe_mode) 1689 mode = ppc_md.pci_probe_mode(bus); 1690 pr_debug(" probe mode: %d\n", mode); 1691 if (mode == PCI_PROBE_DEVTREE) 1692 of_scan_bus(node, bus); 1693 1694 if (mode == PCI_PROBE_NORMAL) { 1695 pci_bus_update_busn_res_end(bus, 255); 1696 hose->last_busno = pci_scan_child_bus(bus); 1697 pci_bus_update_busn_res_end(bus, hose->last_busno); 1698 } 1699 1700 /* Platform gets a chance to do some global fixups before 1701 * we proceed to resource allocation 1702 */ 1703 if (ppc_md.pcibios_fixup_phb) 1704 ppc_md.pcibios_fixup_phb(hose); 1705 1706 /* Configure PCI Express settings */ 1707 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1708 struct pci_bus *child; 1709 list_for_each_entry(child, &bus->children, node) { 1710 struct pci_dev *self = child->self; 1711 if (!self) 1712 continue; 1713 pcie_bus_configure_settings(child, self->pcie_mpss); 1714 } 1715 } 1716 } 1717 1718 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1719 { 1720 int i, class = dev->class >> 8; 1721 /* When configured as agent, programing interface = 1 */ 1722 int prog_if = dev->class & 0xf; 1723 1724 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1725 class == PCI_CLASS_BRIDGE_OTHER) && 1726 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1727 (prog_if == 0) && 1728 (dev->bus->parent == NULL)) { 1729 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1730 dev->resource[i].start = 0; 1731 dev->resource[i].end = 0; 1732 dev->resource[i].flags = 0; 1733 } 1734 } 1735 } 1736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1737 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1738 1739 static void fixup_vga(struct pci_dev *pdev) 1740 { 1741 u16 cmd; 1742 1743 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1744 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) 1745 vga_set_default_device(pdev); 1746 1747 } 1748 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1749 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); 1750