1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/export.h> 25 #include <linux/of_address.h> 26 #include <linux/of_pci.h> 27 #include <linux/mm.h> 28 #include <linux/shmem_fs.h> 29 #include <linux/list.h> 30 #include <linux/syscalls.h> 31 #include <linux/irq.h> 32 #include <linux/vmalloc.h> 33 #include <linux/slab.h> 34 #include <linux/vgaarb.h> 35 36 #include <asm/processor.h> 37 #include <asm/io.h> 38 #include <asm/prom.h> 39 #include <asm/pci-bridge.h> 40 #include <asm/byteorder.h> 41 #include <asm/machdep.h> 42 #include <asm/ppc-pci.h> 43 #include <asm/eeh.h> 44 45 #include "../../../drivers/pci/pci.h" 46 47 /* hose_spinlock protects accesses to the the phb_bitmap. */ 48 static DEFINE_SPINLOCK(hose_spinlock); 49 LIST_HEAD(hose_list); 50 51 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */ 52 #define MAX_PHBS 0x10000 53 54 /* 55 * For dynamic PHB numbering: used/free PHBs tracking bitmap. 56 * Accesses to this bitmap should be protected by hose_spinlock. 57 */ 58 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS); 59 60 /* ISA Memory physical address */ 61 resource_size_t isa_mem_base; 62 EXPORT_SYMBOL(isa_mem_base); 63 64 65 static const struct dma_map_ops *pci_dma_ops; 66 67 void set_pci_dma_ops(const struct dma_map_ops *dma_ops) 68 { 69 pci_dma_ops = dma_ops; 70 } 71 72 /* 73 * This function should run under locking protection, specifically 74 * hose_spinlock. 75 */ 76 static int get_phb_number(struct device_node *dn) 77 { 78 int ret, phb_id = -1; 79 u32 prop_32; 80 u64 prop; 81 82 /* 83 * Try fixed PHB numbering first, by checking archs and reading 84 * the respective device-tree properties. Firstly, try powernv by 85 * reading "ibm,opal-phbid", only present in OPAL environment. 86 */ 87 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); 88 if (ret) { 89 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32); 90 prop = prop_32; 91 } 92 93 if (!ret) 94 phb_id = (int)(prop & (MAX_PHBS - 1)); 95 96 /* We need to be sure to not use the same PHB number twice. */ 97 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap)) 98 return phb_id; 99 100 /* 101 * If not pseries nor powernv, or if fixed PHB numbering tried to add 102 * the same PHB number twice, then fallback to dynamic PHB numbering. 103 */ 104 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS); 105 BUG_ON(phb_id >= MAX_PHBS); 106 set_bit(phb_id, phb_bitmap); 107 108 return phb_id; 109 } 110 111 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 112 { 113 struct pci_controller *phb; 114 115 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 116 if (phb == NULL) 117 return NULL; 118 spin_lock(&hose_spinlock); 119 phb->global_number = get_phb_number(dev); 120 list_add_tail(&phb->list_node, &hose_list); 121 spin_unlock(&hose_spinlock); 122 phb->dn = dev; 123 phb->is_dynamic = slab_is_available(); 124 #ifdef CONFIG_PPC64 125 if (dev) { 126 int nid = of_node_to_nid(dev); 127 128 if (nid < 0 || !node_online(nid)) 129 nid = -1; 130 131 PHB_SET_NODE(phb, nid); 132 } 133 #endif 134 return phb; 135 } 136 EXPORT_SYMBOL_GPL(pcibios_alloc_controller); 137 138 void pcibios_free_controller(struct pci_controller *phb) 139 { 140 spin_lock(&hose_spinlock); 141 142 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */ 143 if (phb->global_number < MAX_PHBS) 144 clear_bit(phb->global_number, phb_bitmap); 145 146 list_del(&phb->list_node); 147 spin_unlock(&hose_spinlock); 148 149 if (phb->is_dynamic) 150 kfree(phb); 151 } 152 EXPORT_SYMBOL_GPL(pcibios_free_controller); 153 154 /* 155 * This function is used to call pcibios_free_controller() 156 * in a deferred manner: a callback from the PCI subsystem. 157 * 158 * _*DO NOT*_ call pcibios_free_controller() explicitly if 159 * this is used (or it may access an invalid *phb pointer). 160 * 161 * The callback occurs when all references to the root bus 162 * are dropped (e.g., child buses/devices and their users). 163 * 164 * It's called as .release_fn() of 'struct pci_host_bridge' 165 * which is associated with the 'struct pci_controller.bus' 166 * (root bus) - it expects .release_data to hold a pointer 167 * to 'struct pci_controller'. 168 * 169 * In order to use it, register .release_fn()/release_data 170 * like this: 171 * 172 * pci_set_host_bridge_release(bridge, 173 * pcibios_free_controller_deferred 174 * (void *) phb); 175 * 176 * e.g. in the pcibios_root_bridge_prepare() callback from 177 * pci_create_root_bus(). 178 */ 179 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge) 180 { 181 struct pci_controller *phb = (struct pci_controller *) 182 bridge->release_data; 183 184 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); 185 186 pcibios_free_controller(phb); 187 } 188 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred); 189 190 /* 191 * The function is used to return the minimal alignment 192 * for memory or I/O windows of the associated P2P bridge. 193 * By default, 4KiB alignment for I/O windows and 1MiB for 194 * memory windows. 195 */ 196 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 197 unsigned long type) 198 { 199 struct pci_controller *phb = pci_bus_to_host(bus); 200 201 if (phb->controller_ops.window_alignment) 202 return phb->controller_ops.window_alignment(bus, type); 203 204 /* 205 * PCI core will figure out the default 206 * alignment: 4KiB for I/O and 1MiB for 207 * memory window. 208 */ 209 return 1; 210 } 211 212 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) 213 { 214 struct pci_controller *hose = pci_bus_to_host(bus); 215 216 if (hose->controller_ops.setup_bridge) 217 hose->controller_ops.setup_bridge(bus, type); 218 } 219 220 void pcibios_reset_secondary_bus(struct pci_dev *dev) 221 { 222 struct pci_controller *phb = pci_bus_to_host(dev->bus); 223 224 if (phb->controller_ops.reset_secondary_bus) { 225 phb->controller_ops.reset_secondary_bus(dev); 226 return; 227 } 228 229 pci_reset_secondary_bus(dev); 230 } 231 232 resource_size_t pcibios_default_alignment(void) 233 { 234 if (ppc_md.pcibios_default_alignment) 235 return ppc_md.pcibios_default_alignment(); 236 237 return 0; 238 } 239 240 #ifdef CONFIG_PCI_IOV 241 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) 242 { 243 if (ppc_md.pcibios_iov_resource_alignment) 244 return ppc_md.pcibios_iov_resource_alignment(pdev, resno); 245 246 return pci_iov_resource_size(pdev, resno); 247 } 248 249 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 250 { 251 if (ppc_md.pcibios_sriov_enable) 252 return ppc_md.pcibios_sriov_enable(pdev, num_vfs); 253 254 return 0; 255 } 256 257 int pcibios_sriov_disable(struct pci_dev *pdev) 258 { 259 if (ppc_md.pcibios_sriov_disable) 260 return ppc_md.pcibios_sriov_disable(pdev); 261 262 return 0; 263 } 264 265 #endif /* CONFIG_PCI_IOV */ 266 267 void pcibios_bus_add_device(struct pci_dev *pdev) 268 { 269 if (ppc_md.pcibios_bus_add_device) 270 ppc_md.pcibios_bus_add_device(pdev); 271 } 272 273 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 274 { 275 #ifdef CONFIG_PPC64 276 return hose->pci_io_size; 277 #else 278 return resource_size(&hose->io_resource); 279 #endif 280 } 281 282 int pcibios_vaddr_is_ioport(void __iomem *address) 283 { 284 int ret = 0; 285 struct pci_controller *hose; 286 resource_size_t size; 287 288 spin_lock(&hose_spinlock); 289 list_for_each_entry(hose, &hose_list, list_node) { 290 size = pcibios_io_size(hose); 291 if (address >= hose->io_base_virt && 292 address < (hose->io_base_virt + size)) { 293 ret = 1; 294 break; 295 } 296 } 297 spin_unlock(&hose_spinlock); 298 return ret; 299 } 300 301 unsigned long pci_address_to_pio(phys_addr_t address) 302 { 303 struct pci_controller *hose; 304 resource_size_t size; 305 unsigned long ret = ~0; 306 307 spin_lock(&hose_spinlock); 308 list_for_each_entry(hose, &hose_list, list_node) { 309 size = pcibios_io_size(hose); 310 if (address >= hose->io_base_phys && 311 address < (hose->io_base_phys + size)) { 312 unsigned long base = 313 (unsigned long)hose->io_base_virt - _IO_BASE; 314 ret = base + (address - hose->io_base_phys); 315 break; 316 } 317 } 318 spin_unlock(&hose_spinlock); 319 320 return ret; 321 } 322 EXPORT_SYMBOL_GPL(pci_address_to_pio); 323 324 /* 325 * Return the domain number for this bus. 326 */ 327 int pci_domain_nr(struct pci_bus *bus) 328 { 329 struct pci_controller *hose = pci_bus_to_host(bus); 330 331 return hose->global_number; 332 } 333 EXPORT_SYMBOL(pci_domain_nr); 334 335 /* This routine is meant to be used early during boot, when the 336 * PCI bus numbers have not yet been assigned, and you need to 337 * issue PCI config cycles to an OF device. 338 * It could also be used to "fix" RTAS config cycles if you want 339 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 340 * config cycles. 341 */ 342 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 343 { 344 while(node) { 345 struct pci_controller *hose, *tmp; 346 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 347 if (hose->dn == node) 348 return hose; 349 node = node->parent; 350 } 351 return NULL; 352 } 353 354 struct pci_controller *pci_find_controller_for_domain(int domain_nr) 355 { 356 struct pci_controller *hose; 357 358 list_for_each_entry(hose, &hose_list, list_node) 359 if (hose->global_number == domain_nr) 360 return hose; 361 362 return NULL; 363 } 364 365 /* 366 * Reads the interrupt pin to determine if interrupt is use by card. 367 * If the interrupt is used, then gets the interrupt line from the 368 * openfirmware and sets it in the pci_dev and pci_config line. 369 */ 370 static int pci_read_irq_line(struct pci_dev *pci_dev) 371 { 372 int virq; 373 374 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 375 376 /* Try to get a mapping from the device-tree */ 377 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0); 378 if (virq <= 0) { 379 u8 line, pin; 380 381 /* If that fails, lets fallback to what is in the config 382 * space and map that through the default controller. We 383 * also set the type to level low since that's what PCI 384 * interrupts are. If your platform does differently, then 385 * either provide a proper interrupt tree or don't use this 386 * function. 387 */ 388 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 389 return -1; 390 if (pin == 0) 391 return -1; 392 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 393 line == 0xff || line == 0) { 394 return -1; 395 } 396 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 397 line, pin); 398 399 virq = irq_create_mapping(NULL, line); 400 if (virq) 401 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 402 } 403 404 if (!virq) { 405 pr_debug(" Failed to map !\n"); 406 return -1; 407 } 408 409 pr_debug(" Mapped to linux irq %d\n", virq); 410 411 pci_dev->irq = virq; 412 413 return 0; 414 } 415 416 /* 417 * Platform support for /proc/bus/pci/X/Y mmap()s. 418 * -- paulus. 419 */ 420 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) 421 { 422 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 423 resource_size_t ioaddr = pci_resource_start(pdev, bar); 424 425 if (!hose) 426 return -EINVAL; 427 428 /* Convert to an offset within this PCI controller */ 429 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; 430 431 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; 432 return 0; 433 } 434 435 /* 436 * This one is used by /dev/mem and fbdev who have no clue about the 437 * PCI device, it tries to find the PCI device first and calls the 438 * above routine 439 */ 440 pgprot_t pci_phys_mem_access_prot(struct file *file, 441 unsigned long pfn, 442 unsigned long size, 443 pgprot_t prot) 444 { 445 struct pci_dev *pdev = NULL; 446 struct resource *found = NULL; 447 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 448 int i; 449 450 if (page_is_ram(pfn)) 451 return prot; 452 453 prot = pgprot_noncached(prot); 454 for_each_pci_dev(pdev) { 455 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 456 struct resource *rp = &pdev->resource[i]; 457 int flags = rp->flags; 458 459 /* Active and same type? */ 460 if ((flags & IORESOURCE_MEM) == 0) 461 continue; 462 /* In the range of this resource? */ 463 if (offset < (rp->start & PAGE_MASK) || 464 offset > rp->end) 465 continue; 466 found = rp; 467 break; 468 } 469 if (found) 470 break; 471 } 472 if (found) { 473 if (found->flags & IORESOURCE_PREFETCH) 474 prot = pgprot_noncached_wc(prot); 475 pci_dev_put(pdev); 476 } 477 478 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 479 (unsigned long long)offset, pgprot_val(prot)); 480 481 return prot; 482 } 483 484 /* This provides legacy IO read access on a bus */ 485 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 486 { 487 unsigned long offset; 488 struct pci_controller *hose = pci_bus_to_host(bus); 489 struct resource *rp = &hose->io_resource; 490 void __iomem *addr; 491 492 /* Check if port can be supported by that bus. We only check 493 * the ranges of the PHB though, not the bus itself as the rules 494 * for forwarding legacy cycles down bridges are not our problem 495 * here. So if the host bridge supports it, we do it. 496 */ 497 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 498 offset += port; 499 500 if (!(rp->flags & IORESOURCE_IO)) 501 return -ENXIO; 502 if (offset < rp->start || (offset + size) > rp->end) 503 return -ENXIO; 504 addr = hose->io_base_virt + port; 505 506 switch(size) { 507 case 1: 508 *((u8 *)val) = in_8(addr); 509 return 1; 510 case 2: 511 if (port & 1) 512 return -EINVAL; 513 *((u16 *)val) = in_le16(addr); 514 return 2; 515 case 4: 516 if (port & 3) 517 return -EINVAL; 518 *((u32 *)val) = in_le32(addr); 519 return 4; 520 } 521 return -EINVAL; 522 } 523 524 /* This provides legacy IO write access on a bus */ 525 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 526 { 527 unsigned long offset; 528 struct pci_controller *hose = pci_bus_to_host(bus); 529 struct resource *rp = &hose->io_resource; 530 void __iomem *addr; 531 532 /* Check if port can be supported by that bus. We only check 533 * the ranges of the PHB though, not the bus itself as the rules 534 * for forwarding legacy cycles down bridges are not our problem 535 * here. So if the host bridge supports it, we do it. 536 */ 537 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 538 offset += port; 539 540 if (!(rp->flags & IORESOURCE_IO)) 541 return -ENXIO; 542 if (offset < rp->start || (offset + size) > rp->end) 543 return -ENXIO; 544 addr = hose->io_base_virt + port; 545 546 /* WARNING: The generic code is idiotic. It gets passed a pointer 547 * to what can be a 1, 2 or 4 byte quantity and always reads that 548 * as a u32, which means that we have to correct the location of 549 * the data read within those 32 bits for size 1 and 2 550 */ 551 switch(size) { 552 case 1: 553 out_8(addr, val >> 24); 554 return 1; 555 case 2: 556 if (port & 1) 557 return -EINVAL; 558 out_le16(addr, val >> 16); 559 return 2; 560 case 4: 561 if (port & 3) 562 return -EINVAL; 563 out_le32(addr, val); 564 return 4; 565 } 566 return -EINVAL; 567 } 568 569 /* This provides legacy IO or memory mmap access on a bus */ 570 int pci_mmap_legacy_page_range(struct pci_bus *bus, 571 struct vm_area_struct *vma, 572 enum pci_mmap_state mmap_state) 573 { 574 struct pci_controller *hose = pci_bus_to_host(bus); 575 resource_size_t offset = 576 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 577 resource_size_t size = vma->vm_end - vma->vm_start; 578 struct resource *rp; 579 580 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 581 pci_domain_nr(bus), bus->number, 582 mmap_state == pci_mmap_mem ? "MEM" : "IO", 583 (unsigned long long)offset, 584 (unsigned long long)(offset + size - 1)); 585 586 if (mmap_state == pci_mmap_mem) { 587 /* Hack alert ! 588 * 589 * Because X is lame and can fail starting if it gets an error trying 590 * to mmap legacy_mem (instead of just moving on without legacy memory 591 * access) we fake it here by giving it anonymous memory, effectively 592 * behaving just like /dev/zero 593 */ 594 if ((offset + size) > hose->isa_mem_size) { 595 printk(KERN_DEBUG 596 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 597 current->comm, current->pid, pci_domain_nr(bus), bus->number); 598 if (vma->vm_flags & VM_SHARED) 599 return shmem_zero_setup(vma); 600 return 0; 601 } 602 offset += hose->isa_mem_phys; 603 } else { 604 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 605 unsigned long roffset = offset + io_offset; 606 rp = &hose->io_resource; 607 if (!(rp->flags & IORESOURCE_IO)) 608 return -ENXIO; 609 if (roffset < rp->start || (roffset + size) > rp->end) 610 return -ENXIO; 611 offset += hose->io_base_phys; 612 } 613 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 614 615 vma->vm_pgoff = offset >> PAGE_SHIFT; 616 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 617 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 618 vma->vm_end - vma->vm_start, 619 vma->vm_page_prot); 620 } 621 622 void pci_resource_to_user(const struct pci_dev *dev, int bar, 623 const struct resource *rsrc, 624 resource_size_t *start, resource_size_t *end) 625 { 626 struct pci_bus_region region; 627 628 if (rsrc->flags & IORESOURCE_IO) { 629 pcibios_resource_to_bus(dev->bus, ®ion, 630 (struct resource *) rsrc); 631 *start = region.start; 632 *end = region.end; 633 return; 634 } 635 636 /* We pass a CPU physical address to userland for MMIO instead of a 637 * BAR value because X is lame and expects to be able to use that 638 * to pass to /dev/mem! 639 * 640 * That means we may have 64-bit values where some apps only expect 641 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). 642 */ 643 *start = rsrc->start; 644 *end = rsrc->end; 645 } 646 647 /** 648 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 649 * @hose: newly allocated pci_controller to be setup 650 * @dev: device node of the host bridge 651 * @primary: set if primary bus (32 bits only, soon to be deprecated) 652 * 653 * This function will parse the "ranges" property of a PCI host bridge device 654 * node and setup the resource mapping of a pci controller based on its 655 * content. 656 * 657 * Life would be boring if it wasn't for a few issues that we have to deal 658 * with here: 659 * 660 * - We can only cope with one IO space range and up to 3 Memory space 661 * ranges. However, some machines (thanks Apple !) tend to split their 662 * space into lots of small contiguous ranges. So we have to coalesce. 663 * 664 * - Some busses have IO space not starting at 0, which causes trouble with 665 * the way we do our IO resource renumbering. The code somewhat deals with 666 * it for 64 bits but I would expect problems on 32 bits. 667 * 668 * - Some 32 bits platforms such as 4xx can have physical space larger than 669 * 32 bits so we need to use 64 bits values for the parsing 670 */ 671 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 672 struct device_node *dev, int primary) 673 { 674 int memno = 0; 675 struct resource *res; 676 struct of_pci_range range; 677 struct of_pci_range_parser parser; 678 679 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n", 680 dev, primary ? "(primary)" : ""); 681 682 /* Check for ranges property */ 683 if (of_pci_range_parser_init(&parser, dev)) 684 return; 685 686 /* Parse it */ 687 for_each_of_pci_range(&parser, &range) { 688 /* If we failed translation or got a zero-sized region 689 * (some FW try to feed us with non sensical zero sized regions 690 * such as power3 which look like some kind of attempt at exposing 691 * the VGA memory hole) 692 */ 693 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) 694 continue; 695 696 /* Act based on address space type */ 697 res = NULL; 698 switch (range.flags & IORESOURCE_TYPE_BITS) { 699 case IORESOURCE_IO: 700 printk(KERN_INFO 701 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 702 range.cpu_addr, range.cpu_addr + range.size - 1, 703 range.pci_addr); 704 705 /* We support only one IO range */ 706 if (hose->pci_io_size) { 707 printk(KERN_INFO 708 " \\--> Skipped (too many) !\n"); 709 continue; 710 } 711 #ifdef CONFIG_PPC32 712 /* On 32 bits, limit I/O space to 16MB */ 713 if (range.size > 0x01000000) 714 range.size = 0x01000000; 715 716 /* 32 bits needs to map IOs here */ 717 hose->io_base_virt = ioremap(range.cpu_addr, 718 range.size); 719 720 /* Expect trouble if pci_addr is not 0 */ 721 if (primary) 722 isa_io_base = 723 (unsigned long)hose->io_base_virt; 724 #endif /* CONFIG_PPC32 */ 725 /* pci_io_size and io_base_phys always represent IO 726 * space starting at 0 so we factor in pci_addr 727 */ 728 hose->pci_io_size = range.pci_addr + range.size; 729 hose->io_base_phys = range.cpu_addr - range.pci_addr; 730 731 /* Build resource */ 732 res = &hose->io_resource; 733 range.cpu_addr = range.pci_addr; 734 break; 735 case IORESOURCE_MEM: 736 printk(KERN_INFO 737 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 738 range.cpu_addr, range.cpu_addr + range.size - 1, 739 range.pci_addr, 740 (range.pci_space & 0x40000000) ? 741 "Prefetch" : ""); 742 743 /* We support only 3 memory ranges */ 744 if (memno >= 3) { 745 printk(KERN_INFO 746 " \\--> Skipped (too many) !\n"); 747 continue; 748 } 749 /* Handles ISA memory hole space here */ 750 if (range.pci_addr == 0) { 751 if (primary || isa_mem_base == 0) 752 isa_mem_base = range.cpu_addr; 753 hose->isa_mem_phys = range.cpu_addr; 754 hose->isa_mem_size = range.size; 755 } 756 757 /* Build resource */ 758 hose->mem_offset[memno] = range.cpu_addr - 759 range.pci_addr; 760 res = &hose->mem_resources[memno++]; 761 break; 762 } 763 if (res != NULL) { 764 res->name = dev->full_name; 765 res->flags = range.flags; 766 res->start = range.cpu_addr; 767 res->end = range.cpu_addr + range.size - 1; 768 res->parent = res->child = res->sibling = NULL; 769 } 770 } 771 } 772 773 /* Decide whether to display the domain number in /proc */ 774 int pci_proc_domain(struct pci_bus *bus) 775 { 776 struct pci_controller *hose = pci_bus_to_host(bus); 777 778 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 779 return 0; 780 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 781 return hose->global_number != 0; 782 return 1; 783 } 784 785 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 786 { 787 if (ppc_md.pcibios_root_bridge_prepare) 788 return ppc_md.pcibios_root_bridge_prepare(bridge); 789 790 return 0; 791 } 792 793 /* This header fixup will do the resource fixup for all devices as they are 794 * probed, but not for bridge ranges 795 */ 796 static void pcibios_fixup_resources(struct pci_dev *dev) 797 { 798 struct pci_controller *hose = pci_bus_to_host(dev->bus); 799 int i; 800 801 if (!hose) { 802 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 803 pci_name(dev)); 804 return; 805 } 806 807 if (dev->is_virtfn) 808 return; 809 810 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 811 struct resource *res = dev->resource + i; 812 struct pci_bus_region reg; 813 if (!res->flags) 814 continue; 815 816 /* If we're going to re-assign everything, we mark all resources 817 * as unset (and 0-base them). In addition, we mark BARs starting 818 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 819 * since in that case, we don't want to re-assign anything 820 */ 821 pcibios_resource_to_bus(dev->bus, ®, res); 822 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 823 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 824 /* Only print message if not re-assigning */ 825 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 826 pr_debug("PCI:%s Resource %d %pR is unassigned\n", 827 pci_name(dev), i, res); 828 res->end -= res->start; 829 res->start = 0; 830 res->flags |= IORESOURCE_UNSET; 831 continue; 832 } 833 834 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res); 835 } 836 837 /* Call machine specific resource fixup */ 838 if (ppc_md.pcibios_fixup_resources) 839 ppc_md.pcibios_fixup_resources(dev); 840 } 841 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 842 843 /* This function tries to figure out if a bridge resource has been initialized 844 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 845 * things go more smoothly when it gets it right. It should covers cases such 846 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 847 */ 848 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 849 struct resource *res) 850 { 851 struct pci_controller *hose = pci_bus_to_host(bus); 852 struct pci_dev *dev = bus->self; 853 resource_size_t offset; 854 struct pci_bus_region region; 855 u16 command; 856 int i; 857 858 /* We don't do anything if PCI_PROBE_ONLY is set */ 859 if (pci_has_flag(PCI_PROBE_ONLY)) 860 return 0; 861 862 /* Job is a bit different between memory and IO */ 863 if (res->flags & IORESOURCE_MEM) { 864 pcibios_resource_to_bus(dev->bus, ®ion, res); 865 866 /* If the BAR is non-0 then it's probably been initialized */ 867 if (region.start != 0) 868 return 0; 869 870 /* The BAR is 0, let's check if memory decoding is enabled on 871 * the bridge. If not, we consider it unassigned 872 */ 873 pci_read_config_word(dev, PCI_COMMAND, &command); 874 if ((command & PCI_COMMAND_MEMORY) == 0) 875 return 1; 876 877 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 878 * resources covers that starting address (0 then it's good enough for 879 * us for memory space) 880 */ 881 for (i = 0; i < 3; i++) { 882 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 883 hose->mem_resources[i].start == hose->mem_offset[i]) 884 return 0; 885 } 886 887 /* Well, it starts at 0 and we know it will collide so we may as 888 * well consider it as unassigned. That covers the Apple case. 889 */ 890 return 1; 891 } else { 892 /* If the BAR is non-0, then we consider it assigned */ 893 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 894 if (((res->start - offset) & 0xfffffffful) != 0) 895 return 0; 896 897 /* Here, we are a bit different than memory as typically IO space 898 * starting at low addresses -is- valid. What we do instead if that 899 * we consider as unassigned anything that doesn't have IO enabled 900 * in the PCI command register, and that's it. 901 */ 902 pci_read_config_word(dev, PCI_COMMAND, &command); 903 if (command & PCI_COMMAND_IO) 904 return 0; 905 906 /* It's starting at 0 and IO is disabled in the bridge, consider 907 * it unassigned 908 */ 909 return 1; 910 } 911 } 912 913 /* Fixup resources of a PCI<->PCI bridge */ 914 static void pcibios_fixup_bridge(struct pci_bus *bus) 915 { 916 struct resource *res; 917 int i; 918 919 struct pci_dev *dev = bus->self; 920 921 pci_bus_for_each_resource(bus, res, i) { 922 if (!res || !res->flags) 923 continue; 924 if (i >= 3 && bus->self->transparent) 925 continue; 926 927 /* If we're going to reassign everything, we can 928 * shrink the P2P resource to have size as being 929 * of 0 in order to save space. 930 */ 931 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 932 res->flags |= IORESOURCE_UNSET; 933 res->start = 0; 934 res->end = -1; 935 continue; 936 } 937 938 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); 939 940 /* Try to detect uninitialized P2P bridge resources, 941 * and clear them out so they get re-assigned later 942 */ 943 if (pcibios_uninitialized_bridge_resource(bus, res)) { 944 res->flags = 0; 945 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 946 } 947 } 948 } 949 950 void pcibios_setup_bus_self(struct pci_bus *bus) 951 { 952 struct pci_controller *phb; 953 954 /* Fix up the bus resources for P2P bridges */ 955 if (bus->self != NULL) 956 pcibios_fixup_bridge(bus); 957 958 /* Platform specific bus fixups. This is currently only used 959 * by fsl_pci and I'm hoping to get rid of it at some point 960 */ 961 if (ppc_md.pcibios_fixup_bus) 962 ppc_md.pcibios_fixup_bus(bus); 963 964 /* Setup bus DMA mappings */ 965 phb = pci_bus_to_host(bus); 966 if (phb->controller_ops.dma_bus_setup) 967 phb->controller_ops.dma_bus_setup(bus); 968 } 969 970 static void pcibios_setup_device(struct pci_dev *dev) 971 { 972 struct pci_controller *phb; 973 /* Fixup NUMA node as it may not be setup yet by the generic 974 * code and is needed by the DMA init 975 */ 976 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 977 978 /* Hook up default DMA ops */ 979 set_dma_ops(&dev->dev, pci_dma_ops); 980 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET; 981 982 /* Additional platform DMA/iommu setup */ 983 phb = pci_bus_to_host(dev->bus); 984 if (phb->controller_ops.dma_dev_setup) 985 phb->controller_ops.dma_dev_setup(dev); 986 987 /* Read default IRQs and fixup if necessary */ 988 pci_read_irq_line(dev); 989 if (ppc_md.pci_irq_fixup) 990 ppc_md.pci_irq_fixup(dev); 991 } 992 993 int pcibios_add_device(struct pci_dev *dev) 994 { 995 /* 996 * We can only call pcibios_setup_device() after bus setup is complete, 997 * since some of the platform specific DMA setup code depends on it. 998 */ 999 if (dev->bus->is_added) 1000 pcibios_setup_device(dev); 1001 1002 #ifdef CONFIG_PCI_IOV 1003 if (ppc_md.pcibios_fixup_sriov) 1004 ppc_md.pcibios_fixup_sriov(dev); 1005 #endif /* CONFIG_PCI_IOV */ 1006 1007 return 0; 1008 } 1009 1010 void pcibios_setup_bus_devices(struct pci_bus *bus) 1011 { 1012 struct pci_dev *dev; 1013 1014 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1015 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1016 1017 list_for_each_entry(dev, &bus->devices, bus_list) { 1018 /* Cardbus can call us to add new devices to a bus, so ignore 1019 * those who are already fully discovered 1020 */ 1021 if (pci_dev_is_added(dev)) 1022 continue; 1023 1024 pcibios_setup_device(dev); 1025 } 1026 } 1027 1028 void pcibios_set_master(struct pci_dev *dev) 1029 { 1030 /* No special bus mastering setup handling */ 1031 } 1032 1033 void pcibios_fixup_bus(struct pci_bus *bus) 1034 { 1035 /* When called from the generic PCI probe, read PCI<->PCI bridge 1036 * bases. This is -not- called when generating the PCI tree from 1037 * the OF device-tree. 1038 */ 1039 pci_read_bridge_bases(bus); 1040 1041 /* Now fixup the bus bus */ 1042 pcibios_setup_bus_self(bus); 1043 1044 /* Now fixup devices on that bus */ 1045 pcibios_setup_bus_devices(bus); 1046 } 1047 EXPORT_SYMBOL(pcibios_fixup_bus); 1048 1049 void pci_fixup_cardbus(struct pci_bus *bus) 1050 { 1051 /* Now fixup devices on that bus */ 1052 pcibios_setup_bus_devices(bus); 1053 } 1054 1055 1056 static int skip_isa_ioresource_align(struct pci_dev *dev) 1057 { 1058 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1059 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1060 return 1; 1061 return 0; 1062 } 1063 1064 /* 1065 * We need to avoid collisions with `mirrored' VGA ports 1066 * and other strange ISA hardware, so we always want the 1067 * addresses to be allocated in the 0x000-0x0ff region 1068 * modulo 0x400. 1069 * 1070 * Why? Because some silly external IO cards only decode 1071 * the low 10 bits of the IO address. The 0x00-0xff region 1072 * is reserved for motherboard devices that decode all 16 1073 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1074 * but we want to try to avoid allocating at 0x2900-0x2bff 1075 * which might have be mirrored at 0x0100-0x03ff.. 1076 */ 1077 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1078 resource_size_t size, resource_size_t align) 1079 { 1080 struct pci_dev *dev = data; 1081 resource_size_t start = res->start; 1082 1083 if (res->flags & IORESOURCE_IO) { 1084 if (skip_isa_ioresource_align(dev)) 1085 return start; 1086 if (start & 0x300) 1087 start = (start + 0x3ff) & ~0x3ff; 1088 } 1089 1090 return start; 1091 } 1092 EXPORT_SYMBOL(pcibios_align_resource); 1093 1094 /* 1095 * Reparent resource children of pr that conflict with res 1096 * under res, and make res replace those children. 1097 */ 1098 static int reparent_resources(struct resource *parent, 1099 struct resource *res) 1100 { 1101 struct resource *p, **pp; 1102 struct resource **firstpp = NULL; 1103 1104 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1105 if (p->end < res->start) 1106 continue; 1107 if (res->end < p->start) 1108 break; 1109 if (p->start < res->start || p->end > res->end) 1110 return -1; /* not completely contained */ 1111 if (firstpp == NULL) 1112 firstpp = pp; 1113 } 1114 if (firstpp == NULL) 1115 return -1; /* didn't find any conflicting entries? */ 1116 res->parent = parent; 1117 res->child = *firstpp; 1118 res->sibling = *pp; 1119 *firstpp = res; 1120 *pp = NULL; 1121 for (p = res->child; p != NULL; p = p->sibling) { 1122 p->parent = res; 1123 pr_debug("PCI: Reparented %s %pR under %s\n", 1124 p->name, p, res->name); 1125 } 1126 return 0; 1127 } 1128 1129 /* 1130 * Handle resources of PCI devices. If the world were perfect, we could 1131 * just allocate all the resource regions and do nothing more. It isn't. 1132 * On the other hand, we cannot just re-allocate all devices, as it would 1133 * require us to know lots of host bridge internals. So we attempt to 1134 * keep as much of the original configuration as possible, but tweak it 1135 * when it's found to be wrong. 1136 * 1137 * Known BIOS problems we have to work around: 1138 * - I/O or memory regions not configured 1139 * - regions configured, but not enabled in the command register 1140 * - bogus I/O addresses above 64K used 1141 * - expansion ROMs left enabled (this may sound harmless, but given 1142 * the fact the PCI specs explicitly allow address decoders to be 1143 * shared between expansion ROMs and other resource regions, it's 1144 * at least dangerous) 1145 * 1146 * Our solution: 1147 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1148 * This gives us fixed barriers on where we can allocate. 1149 * (2) Allocate resources for all enabled devices. If there is 1150 * a collision, just mark the resource as unallocated. Also 1151 * disable expansion ROMs during this step. 1152 * (3) Try to allocate resources for disabled devices. If the 1153 * resources were assigned correctly, everything goes well, 1154 * if they weren't, they won't disturb allocation of other 1155 * resources. 1156 * (4) Assign new addresses to resources which were either 1157 * not configured at all or misconfigured. If explicitly 1158 * requested by the user, configure expansion ROM address 1159 * as well. 1160 */ 1161 1162 static void pcibios_allocate_bus_resources(struct pci_bus *bus) 1163 { 1164 struct pci_bus *b; 1165 int i; 1166 struct resource *res, *pr; 1167 1168 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1169 pci_domain_nr(bus), bus->number); 1170 1171 pci_bus_for_each_resource(bus, res, i) { 1172 if (!res || !res->flags || res->start > res->end || res->parent) 1173 continue; 1174 1175 /* If the resource was left unset at this point, we clear it */ 1176 if (res->flags & IORESOURCE_UNSET) 1177 goto clear_resource; 1178 1179 if (bus->parent == NULL) 1180 pr = (res->flags & IORESOURCE_IO) ? 1181 &ioport_resource : &iomem_resource; 1182 else { 1183 pr = pci_find_parent_resource(bus->self, res); 1184 if (pr == res) { 1185 /* this happens when the generic PCI 1186 * code (wrongly) decides that this 1187 * bridge is transparent -- paulus 1188 */ 1189 continue; 1190 } 1191 } 1192 1193 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", 1194 bus->self ? pci_name(bus->self) : "PHB", bus->number, 1195 i, res, pr, (pr && pr->name) ? pr->name : "nil"); 1196 1197 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1198 struct pci_dev *dev = bus->self; 1199 1200 if (request_resource(pr, res) == 0) 1201 continue; 1202 /* 1203 * Must be a conflict with an existing entry. 1204 * Move that entry (or entries) under the 1205 * bridge resource and try again. 1206 */ 1207 if (reparent_resources(pr, res) == 0) 1208 continue; 1209 1210 if (dev && i < PCI_BRIDGE_RESOURCE_NUM && 1211 pci_claim_bridge_resource(dev, 1212 i + PCI_BRIDGE_RESOURCES) == 0) 1213 continue; 1214 } 1215 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n", 1216 i, bus->number); 1217 clear_resource: 1218 /* The resource might be figured out when doing 1219 * reassignment based on the resources required 1220 * by the downstream PCI devices. Here we set 1221 * the size of the resource to be 0 in order to 1222 * save more space. 1223 */ 1224 res->start = 0; 1225 res->end = -1; 1226 res->flags = 0; 1227 } 1228 1229 list_for_each_entry(b, &bus->children, node) 1230 pcibios_allocate_bus_resources(b); 1231 } 1232 1233 static inline void alloc_resource(struct pci_dev *dev, int idx) 1234 { 1235 struct resource *pr, *r = &dev->resource[idx]; 1236 1237 pr_debug("PCI: Allocating %s: Resource %d: %pR\n", 1238 pci_name(dev), idx, r); 1239 1240 pr = pci_find_parent_resource(dev, r); 1241 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1242 request_resource(pr, r) < 0) { 1243 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1244 " of device %s, will remap\n", idx, pci_name(dev)); 1245 if (pr) 1246 pr_debug("PCI: parent is %p: %pR\n", pr, pr); 1247 /* We'll assign a new address later */ 1248 r->flags |= IORESOURCE_UNSET; 1249 r->end -= r->start; 1250 r->start = 0; 1251 } 1252 } 1253 1254 static void __init pcibios_allocate_resources(int pass) 1255 { 1256 struct pci_dev *dev = NULL; 1257 int idx, disabled; 1258 u16 command; 1259 struct resource *r; 1260 1261 for_each_pci_dev(dev) { 1262 pci_read_config_word(dev, PCI_COMMAND, &command); 1263 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1264 r = &dev->resource[idx]; 1265 if (r->parent) /* Already allocated */ 1266 continue; 1267 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1268 continue; /* Not assigned at all */ 1269 /* We only allocate ROMs on pass 1 just in case they 1270 * have been screwed up by firmware 1271 */ 1272 if (idx == PCI_ROM_RESOURCE ) 1273 disabled = 1; 1274 if (r->flags & IORESOURCE_IO) 1275 disabled = !(command & PCI_COMMAND_IO); 1276 else 1277 disabled = !(command & PCI_COMMAND_MEMORY); 1278 if (pass == disabled) 1279 alloc_resource(dev, idx); 1280 } 1281 if (pass) 1282 continue; 1283 r = &dev->resource[PCI_ROM_RESOURCE]; 1284 if (r->flags) { 1285 /* Turn the ROM off, leave the resource region, 1286 * but keep it unregistered. 1287 */ 1288 u32 reg; 1289 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1290 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1291 pr_debug("PCI: Switching off ROM of %s\n", 1292 pci_name(dev)); 1293 r->flags &= ~IORESOURCE_ROM_ENABLE; 1294 pci_write_config_dword(dev, dev->rom_base_reg, 1295 reg & ~PCI_ROM_ADDRESS_ENABLE); 1296 } 1297 } 1298 } 1299 } 1300 1301 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1302 { 1303 struct pci_controller *hose = pci_bus_to_host(bus); 1304 resource_size_t offset; 1305 struct resource *res, *pres; 1306 int i; 1307 1308 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1309 1310 /* Check for IO */ 1311 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1312 goto no_io; 1313 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1314 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1315 BUG_ON(res == NULL); 1316 res->name = "Legacy IO"; 1317 res->flags = IORESOURCE_IO; 1318 res->start = offset; 1319 res->end = (offset + 0xfff) & 0xfffffffful; 1320 pr_debug("Candidate legacy IO: %pR\n", res); 1321 if (request_resource(&hose->io_resource, res)) { 1322 printk(KERN_DEBUG 1323 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1324 pci_domain_nr(bus), bus->number, res); 1325 kfree(res); 1326 } 1327 1328 no_io: 1329 /* Check for memory */ 1330 for (i = 0; i < 3; i++) { 1331 pres = &hose->mem_resources[i]; 1332 offset = hose->mem_offset[i]; 1333 if (!(pres->flags & IORESOURCE_MEM)) 1334 continue; 1335 pr_debug("hose mem res: %pR\n", pres); 1336 if ((pres->start - offset) <= 0xa0000 && 1337 (pres->end - offset) >= 0xbffff) 1338 break; 1339 } 1340 if (i >= 3) 1341 return; 1342 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1343 BUG_ON(res == NULL); 1344 res->name = "Legacy VGA memory"; 1345 res->flags = IORESOURCE_MEM; 1346 res->start = 0xa0000 + offset; 1347 res->end = 0xbffff + offset; 1348 pr_debug("Candidate VGA memory: %pR\n", res); 1349 if (request_resource(pres, res)) { 1350 printk(KERN_DEBUG 1351 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1352 pci_domain_nr(bus), bus->number, res); 1353 kfree(res); 1354 } 1355 } 1356 1357 void __init pcibios_resource_survey(void) 1358 { 1359 struct pci_bus *b; 1360 1361 /* Allocate and assign resources */ 1362 list_for_each_entry(b, &pci_root_buses, node) 1363 pcibios_allocate_bus_resources(b); 1364 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1365 pcibios_allocate_resources(0); 1366 pcibios_allocate_resources(1); 1367 } 1368 1369 /* Before we start assigning unassigned resource, we try to reserve 1370 * the low IO area and the VGA memory area if they intersect the 1371 * bus available resources to avoid allocating things on top of them 1372 */ 1373 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1374 list_for_each_entry(b, &pci_root_buses, node) 1375 pcibios_reserve_legacy_regions(b); 1376 } 1377 1378 /* Now, if the platform didn't decide to blindly trust the firmware, 1379 * we proceed to assigning things that were left unassigned 1380 */ 1381 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1382 pr_debug("PCI: Assigning unassigned resources...\n"); 1383 pci_assign_unassigned_resources(); 1384 } 1385 1386 /* Call machine dependent fixup */ 1387 if (ppc_md.pcibios_fixup) 1388 ppc_md.pcibios_fixup(); 1389 } 1390 1391 /* This is used by the PCI hotplug driver to allocate resource 1392 * of newly plugged busses. We can try to consolidate with the 1393 * rest of the code later, for now, keep it as-is as our main 1394 * resource allocation function doesn't deal with sub-trees yet. 1395 */ 1396 void pcibios_claim_one_bus(struct pci_bus *bus) 1397 { 1398 struct pci_dev *dev; 1399 struct pci_bus *child_bus; 1400 1401 list_for_each_entry(dev, &bus->devices, bus_list) { 1402 int i; 1403 1404 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1405 struct resource *r = &dev->resource[i]; 1406 1407 if (r->parent || !r->start || !r->flags) 1408 continue; 1409 1410 pr_debug("PCI: Claiming %s: Resource %d: %pR\n", 1411 pci_name(dev), i, r); 1412 1413 if (pci_claim_resource(dev, i) == 0) 1414 continue; 1415 1416 pci_claim_bridge_resource(dev, i); 1417 } 1418 } 1419 1420 list_for_each_entry(child_bus, &bus->children, node) 1421 pcibios_claim_one_bus(child_bus); 1422 } 1423 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); 1424 1425 1426 /* pcibios_finish_adding_to_bus 1427 * 1428 * This is to be called by the hotplug code after devices have been 1429 * added to a bus, this include calling it for a PHB that is just 1430 * being added 1431 */ 1432 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1433 { 1434 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1435 pci_domain_nr(bus), bus->number); 1436 1437 /* Allocate bus and devices resources */ 1438 pcibios_allocate_bus_resources(bus); 1439 pcibios_claim_one_bus(bus); 1440 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1441 if (bus->self) 1442 pci_assign_unassigned_bridge_resources(bus->self); 1443 else 1444 pci_assign_unassigned_bus_resources(bus); 1445 } 1446 1447 /* Fixup EEH */ 1448 eeh_add_device_tree_late(bus); 1449 1450 /* Add new devices to global lists. Register in proc, sysfs. */ 1451 pci_bus_add_devices(bus); 1452 1453 /* sysfs files should only be added after devices are added */ 1454 eeh_add_sysfs_files(bus); 1455 } 1456 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1457 1458 int pcibios_enable_device(struct pci_dev *dev, int mask) 1459 { 1460 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1461 1462 if (phb->controller_ops.enable_device_hook) 1463 if (!phb->controller_ops.enable_device_hook(dev)) 1464 return -EINVAL; 1465 1466 return pci_enable_resources(dev, mask); 1467 } 1468 1469 void pcibios_disable_device(struct pci_dev *dev) 1470 { 1471 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1472 1473 if (phb->controller_ops.disable_device) 1474 phb->controller_ops.disable_device(dev); 1475 } 1476 1477 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1478 { 1479 return (unsigned long) hose->io_base_virt - _IO_BASE; 1480 } 1481 1482 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1483 struct list_head *resources) 1484 { 1485 struct resource *res; 1486 resource_size_t offset; 1487 int i; 1488 1489 /* Hookup PHB IO resource */ 1490 res = &hose->io_resource; 1491 1492 if (!res->flags) { 1493 pr_debug("PCI: I/O resource not set for host" 1494 " bridge %pOF (domain %d)\n", 1495 hose->dn, hose->global_number); 1496 } else { 1497 offset = pcibios_io_space_offset(hose); 1498 1499 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n", 1500 res, (unsigned long long)offset); 1501 pci_add_resource_offset(resources, res, offset); 1502 } 1503 1504 /* Hookup PHB Memory resources */ 1505 for (i = 0; i < 3; ++i) { 1506 res = &hose->mem_resources[i]; 1507 if (!res->flags) 1508 continue; 1509 1510 offset = hose->mem_offset[i]; 1511 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i, 1512 res, (unsigned long long)offset); 1513 1514 pci_add_resource_offset(resources, res, offset); 1515 } 1516 } 1517 1518 /* 1519 * Null PCI config access functions, for the case when we can't 1520 * find a hose. 1521 */ 1522 #define NULL_PCI_OP(rw, size, type) \ 1523 static int \ 1524 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1525 { \ 1526 return PCIBIOS_DEVICE_NOT_FOUND; \ 1527 } 1528 1529 static int 1530 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1531 int len, u32 *val) 1532 { 1533 return PCIBIOS_DEVICE_NOT_FOUND; 1534 } 1535 1536 static int 1537 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1538 int len, u32 val) 1539 { 1540 return PCIBIOS_DEVICE_NOT_FOUND; 1541 } 1542 1543 static struct pci_ops null_pci_ops = 1544 { 1545 .read = null_read_config, 1546 .write = null_write_config, 1547 }; 1548 1549 /* 1550 * These functions are used early on before PCI scanning is done 1551 * and all of the pci_dev and pci_bus structures have been created. 1552 */ 1553 static struct pci_bus * 1554 fake_pci_bus(struct pci_controller *hose, int busnr) 1555 { 1556 static struct pci_bus bus; 1557 1558 if (hose == NULL) { 1559 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1560 } 1561 bus.number = busnr; 1562 bus.sysdata = hose; 1563 bus.ops = hose? hose->ops: &null_pci_ops; 1564 return &bus; 1565 } 1566 1567 #define EARLY_PCI_OP(rw, size, type) \ 1568 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1569 int devfn, int offset, type value) \ 1570 { \ 1571 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1572 devfn, offset, value); \ 1573 } 1574 1575 EARLY_PCI_OP(read, byte, u8 *) 1576 EARLY_PCI_OP(read, word, u16 *) 1577 EARLY_PCI_OP(read, dword, u32 *) 1578 EARLY_PCI_OP(write, byte, u8) 1579 EARLY_PCI_OP(write, word, u16) 1580 EARLY_PCI_OP(write, dword, u32) 1581 1582 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1583 int cap) 1584 { 1585 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1586 } 1587 1588 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1589 { 1590 struct pci_controller *hose = bus->sysdata; 1591 1592 return of_node_get(hose->dn); 1593 } 1594 1595 /** 1596 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1597 * @hose: Pointer to the PCI host controller instance structure 1598 */ 1599 void pcibios_scan_phb(struct pci_controller *hose) 1600 { 1601 LIST_HEAD(resources); 1602 struct pci_bus *bus; 1603 struct device_node *node = hose->dn; 1604 int mode; 1605 1606 pr_debug("PCI: Scanning PHB %pOF\n", node); 1607 1608 /* Get some IO space for the new PHB */ 1609 pcibios_setup_phb_io_space(hose); 1610 1611 /* Wire up PHB bus resources */ 1612 pcibios_setup_phb_resources(hose, &resources); 1613 1614 hose->busn.start = hose->first_busno; 1615 hose->busn.end = hose->last_busno; 1616 hose->busn.flags = IORESOURCE_BUS; 1617 pci_add_resource(&resources, &hose->busn); 1618 1619 /* Create an empty bus for the toplevel */ 1620 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1621 hose->ops, hose, &resources); 1622 if (bus == NULL) { 1623 pr_err("Failed to create bus for PCI domain %04x\n", 1624 hose->global_number); 1625 pci_free_resource_list(&resources); 1626 return; 1627 } 1628 hose->bus = bus; 1629 1630 /* Get probe mode and perform scan */ 1631 mode = PCI_PROBE_NORMAL; 1632 if (node && hose->controller_ops.probe_mode) 1633 mode = hose->controller_ops.probe_mode(bus); 1634 pr_debug(" probe mode: %d\n", mode); 1635 if (mode == PCI_PROBE_DEVTREE) 1636 of_scan_bus(node, bus); 1637 1638 if (mode == PCI_PROBE_NORMAL) { 1639 pci_bus_update_busn_res_end(bus, 255); 1640 hose->last_busno = pci_scan_child_bus(bus); 1641 pci_bus_update_busn_res_end(bus, hose->last_busno); 1642 } 1643 1644 /* Platform gets a chance to do some global fixups before 1645 * we proceed to resource allocation 1646 */ 1647 if (ppc_md.pcibios_fixup_phb) 1648 ppc_md.pcibios_fixup_phb(hose); 1649 1650 /* Configure PCI Express settings */ 1651 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1652 struct pci_bus *child; 1653 list_for_each_entry(child, &bus->children, node) 1654 pcie_bus_configure_settings(child); 1655 } 1656 } 1657 EXPORT_SYMBOL_GPL(pcibios_scan_phb); 1658 1659 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1660 { 1661 int i, class = dev->class >> 8; 1662 /* When configured as agent, programing interface = 1 */ 1663 int prog_if = dev->class & 0xf; 1664 1665 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1666 class == PCI_CLASS_BRIDGE_OTHER) && 1667 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1668 (prog_if == 0) && 1669 (dev->bus->parent == NULL)) { 1670 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1671 dev->resource[i].start = 0; 1672 dev->resource[i].end = 0; 1673 dev->resource[i].flags = 0; 1674 } 1675 } 1676 } 1677 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1678 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1679