1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/mm.h> 25 #include <linux/list.h> 26 #include <linux/syscalls.h> 27 #include <linux/irq.h> 28 #include <linux/vmalloc.h> 29 30 #include <asm/processor.h> 31 #include <asm/io.h> 32 #include <asm/prom.h> 33 #include <asm/pci-bridge.h> 34 #include <asm/byteorder.h> 35 #include <asm/machdep.h> 36 #include <asm/ppc-pci.h> 37 #include <asm/firmware.h> 38 #include <asm/eeh.h> 39 40 static DEFINE_SPINLOCK(hose_spinlock); 41 42 /* XXX kill that some day ... */ 43 static int global_phb_number; /* Global phb counter */ 44 45 /* ISA Memory physical address */ 46 resource_size_t isa_mem_base; 47 48 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */ 49 unsigned int ppc_pci_flags = 0; 50 51 52 static struct dma_mapping_ops *pci_dma_ops; 53 54 void set_pci_dma_ops(struct dma_mapping_ops *dma_ops) 55 { 56 pci_dma_ops = dma_ops; 57 } 58 59 struct dma_mapping_ops *get_pci_dma_ops(void) 60 { 61 return pci_dma_ops; 62 } 63 EXPORT_SYMBOL(get_pci_dma_ops); 64 65 int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 66 { 67 return dma_set_mask(&dev->dev, mask); 68 } 69 70 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 71 { 72 int rc; 73 74 rc = dma_set_mask(&dev->dev, mask); 75 dev->dev.coherent_dma_mask = dev->dma_mask; 76 77 return rc; 78 } 79 80 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 81 { 82 struct pci_controller *phb; 83 84 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 85 if (phb == NULL) 86 return NULL; 87 spin_lock(&hose_spinlock); 88 phb->global_number = global_phb_number++; 89 list_add_tail(&phb->list_node, &hose_list); 90 spin_unlock(&hose_spinlock); 91 phb->dn = dev; 92 phb->is_dynamic = mem_init_done; 93 #ifdef CONFIG_PPC64 94 if (dev) { 95 int nid = of_node_to_nid(dev); 96 97 if (nid < 0 || !node_online(nid)) 98 nid = -1; 99 100 PHB_SET_NODE(phb, nid); 101 } 102 #endif 103 return phb; 104 } 105 106 void pcibios_free_controller(struct pci_controller *phb) 107 { 108 spin_lock(&hose_spinlock); 109 list_del(&phb->list_node); 110 spin_unlock(&hose_spinlock); 111 112 if (phb->is_dynamic) 113 kfree(phb); 114 } 115 116 int pcibios_vaddr_is_ioport(void __iomem *address) 117 { 118 int ret = 0; 119 struct pci_controller *hose; 120 unsigned long size; 121 122 spin_lock(&hose_spinlock); 123 list_for_each_entry(hose, &hose_list, list_node) { 124 #ifdef CONFIG_PPC64 125 size = hose->pci_io_size; 126 #else 127 size = hose->io_resource.end - hose->io_resource.start + 1; 128 #endif 129 if (address >= hose->io_base_virt && 130 address < (hose->io_base_virt + size)) { 131 ret = 1; 132 break; 133 } 134 } 135 spin_unlock(&hose_spinlock); 136 return ret; 137 } 138 139 /* 140 * Return the domain number for this bus. 141 */ 142 int pci_domain_nr(struct pci_bus *bus) 143 { 144 struct pci_controller *hose = pci_bus_to_host(bus); 145 146 return hose->global_number; 147 } 148 EXPORT_SYMBOL(pci_domain_nr); 149 150 #ifdef CONFIG_PPC_OF 151 152 /* This routine is meant to be used early during boot, when the 153 * PCI bus numbers have not yet been assigned, and you need to 154 * issue PCI config cycles to an OF device. 155 * It could also be used to "fix" RTAS config cycles if you want 156 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 157 * config cycles. 158 */ 159 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 160 { 161 while(node) { 162 struct pci_controller *hose, *tmp; 163 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 164 if (hose->dn == node) 165 return hose; 166 node = node->parent; 167 } 168 return NULL; 169 } 170 171 static ssize_t pci_show_devspec(struct device *dev, 172 struct device_attribute *attr, char *buf) 173 { 174 struct pci_dev *pdev; 175 struct device_node *np; 176 177 pdev = to_pci_dev (dev); 178 np = pci_device_to_OF_node(pdev); 179 if (np == NULL || np->full_name == NULL) 180 return 0; 181 return sprintf(buf, "%s", np->full_name); 182 } 183 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 184 #endif /* CONFIG_PPC_OF */ 185 186 /* Add sysfs properties */ 187 int pcibios_add_platform_entries(struct pci_dev *pdev) 188 { 189 #ifdef CONFIG_PPC_OF 190 return device_create_file(&pdev->dev, &dev_attr_devspec); 191 #else 192 return 0; 193 #endif /* CONFIG_PPC_OF */ 194 195 } 196 197 char __devinit *pcibios_setup(char *str) 198 { 199 return str; 200 } 201 202 /* 203 * Reads the interrupt pin to determine if interrupt is use by card. 204 * If the interrupt is used, then gets the interrupt line from the 205 * openfirmware and sets it in the pci_dev and pci_config line. 206 */ 207 int pci_read_irq_line(struct pci_dev *pci_dev) 208 { 209 struct of_irq oirq; 210 unsigned int virq; 211 212 /* The current device-tree that iSeries generates from the HV 213 * PCI informations doesn't contain proper interrupt routing, 214 * and all the fallback would do is print out crap, so we 215 * don't attempt to resolve the interrupts here at all, some 216 * iSeries specific fixup does it. 217 * 218 * In the long run, we will hopefully fix the generated device-tree 219 * instead. 220 */ 221 #ifdef CONFIG_PPC_ISERIES 222 if (firmware_has_feature(FW_FEATURE_ISERIES)) 223 return -1; 224 #endif 225 226 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 227 228 #ifdef DEBUG 229 memset(&oirq, 0xff, sizeof(oirq)); 230 #endif 231 /* Try to get a mapping from the device-tree */ 232 if (of_irq_map_pci(pci_dev, &oirq)) { 233 u8 line, pin; 234 235 /* If that fails, lets fallback to what is in the config 236 * space and map that through the default controller. We 237 * also set the type to level low since that's what PCI 238 * interrupts are. If your platform does differently, then 239 * either provide a proper interrupt tree or don't use this 240 * function. 241 */ 242 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 243 return -1; 244 if (pin == 0) 245 return -1; 246 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 247 line == 0xff || line == 0) { 248 return -1; 249 } 250 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 251 line, pin); 252 253 virq = irq_create_mapping(NULL, line); 254 if (virq != NO_IRQ) 255 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 256 } else { 257 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 258 oirq.size, oirq.specifier[0], oirq.specifier[1], 259 oirq.controller ? oirq.controller->full_name : 260 "<default>"); 261 262 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 263 oirq.size); 264 } 265 if(virq == NO_IRQ) { 266 pr_debug(" Failed to map !\n"); 267 return -1; 268 } 269 270 pr_debug(" Mapped to linux irq %d\n", virq); 271 272 pci_dev->irq = virq; 273 274 return 0; 275 } 276 EXPORT_SYMBOL(pci_read_irq_line); 277 278 /* 279 * Platform support for /proc/bus/pci/X/Y mmap()s, 280 * modelled on the sparc64 implementation by Dave Miller. 281 * -- paulus. 282 */ 283 284 /* 285 * Adjust vm_pgoff of VMA such that it is the physical page offset 286 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 287 * 288 * Basically, the user finds the base address for his device which he wishes 289 * to mmap. They read the 32-bit value from the config space base register, 290 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 291 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 292 * 293 * Returns negative error code on failure, zero on success. 294 */ 295 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 296 resource_size_t *offset, 297 enum pci_mmap_state mmap_state) 298 { 299 struct pci_controller *hose = pci_bus_to_host(dev->bus); 300 unsigned long io_offset = 0; 301 int i, res_bit; 302 303 if (hose == 0) 304 return NULL; /* should never happen */ 305 306 /* If memory, add on the PCI bridge address offset */ 307 if (mmap_state == pci_mmap_mem) { 308 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 309 *offset += hose->pci_mem_offset; 310 #endif 311 res_bit = IORESOURCE_MEM; 312 } else { 313 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 314 *offset += io_offset; 315 res_bit = IORESOURCE_IO; 316 } 317 318 /* 319 * Check that the offset requested corresponds to one of the 320 * resources of the device. 321 */ 322 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 323 struct resource *rp = &dev->resource[i]; 324 int flags = rp->flags; 325 326 /* treat ROM as memory (should be already) */ 327 if (i == PCI_ROM_RESOURCE) 328 flags |= IORESOURCE_MEM; 329 330 /* Active and same type? */ 331 if ((flags & res_bit) == 0) 332 continue; 333 334 /* In the range of this resource? */ 335 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 336 continue; 337 338 /* found it! construct the final physical address */ 339 if (mmap_state == pci_mmap_io) 340 *offset += hose->io_base_phys - io_offset; 341 return rp; 342 } 343 344 return NULL; 345 } 346 347 /* 348 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 349 * device mapping. 350 */ 351 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 352 pgprot_t protection, 353 enum pci_mmap_state mmap_state, 354 int write_combine) 355 { 356 unsigned long prot = pgprot_val(protection); 357 358 /* Write combine is always 0 on non-memory space mappings. On 359 * memory space, if the user didn't pass 1, we check for a 360 * "prefetchable" resource. This is a bit hackish, but we use 361 * this to workaround the inability of /sysfs to provide a write 362 * combine bit 363 */ 364 if (mmap_state != pci_mmap_mem) 365 write_combine = 0; 366 else if (write_combine == 0) { 367 if (rp->flags & IORESOURCE_PREFETCH) 368 write_combine = 1; 369 } 370 371 /* XXX would be nice to have a way to ask for write-through */ 372 if (write_combine) 373 return pgprot_noncached_wc(prot); 374 else 375 return pgprot_noncached(prot); 376 } 377 378 /* 379 * This one is used by /dev/mem and fbdev who have no clue about the 380 * PCI device, it tries to find the PCI device first and calls the 381 * above routine 382 */ 383 pgprot_t pci_phys_mem_access_prot(struct file *file, 384 unsigned long pfn, 385 unsigned long size, 386 pgprot_t prot) 387 { 388 struct pci_dev *pdev = NULL; 389 struct resource *found = NULL; 390 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 391 int i; 392 393 if (page_is_ram(pfn)) 394 return prot; 395 396 prot = pgprot_noncached(prot); 397 for_each_pci_dev(pdev) { 398 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 399 struct resource *rp = &pdev->resource[i]; 400 int flags = rp->flags; 401 402 /* Active and same type? */ 403 if ((flags & IORESOURCE_MEM) == 0) 404 continue; 405 /* In the range of this resource? */ 406 if (offset < (rp->start & PAGE_MASK) || 407 offset > rp->end) 408 continue; 409 found = rp; 410 break; 411 } 412 if (found) 413 break; 414 } 415 if (found) { 416 if (found->flags & IORESOURCE_PREFETCH) 417 prot = pgprot_noncached_wc(prot); 418 pci_dev_put(pdev); 419 } 420 421 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 422 (unsigned long long)offset, pgprot_val(prot)); 423 424 return prot; 425 } 426 427 428 /* 429 * Perform the actual remap of the pages for a PCI device mapping, as 430 * appropriate for this architecture. The region in the process to map 431 * is described by vm_start and vm_end members of VMA, the base physical 432 * address is found in vm_pgoff. 433 * The pci device structure is provided so that architectures may make mapping 434 * decisions on a per-device or per-bus basis. 435 * 436 * Returns a negative error code on failure, zero on success. 437 */ 438 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 439 enum pci_mmap_state mmap_state, int write_combine) 440 { 441 resource_size_t offset = 442 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 443 struct resource *rp; 444 int ret; 445 446 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 447 if (rp == NULL) 448 return -EINVAL; 449 450 vma->vm_pgoff = offset >> PAGE_SHIFT; 451 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 452 vma->vm_page_prot, 453 mmap_state, write_combine); 454 455 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 456 vma->vm_end - vma->vm_start, vma->vm_page_prot); 457 458 return ret; 459 } 460 461 /* This provides legacy IO read access on a bus */ 462 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 463 { 464 unsigned long offset; 465 struct pci_controller *hose = pci_bus_to_host(bus); 466 struct resource *rp = &hose->io_resource; 467 void __iomem *addr; 468 469 /* Check if port can be supported by that bus. We only check 470 * the ranges of the PHB though, not the bus itself as the rules 471 * for forwarding legacy cycles down bridges are not our problem 472 * here. So if the host bridge supports it, we do it. 473 */ 474 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 475 offset += port; 476 477 if (!(rp->flags & IORESOURCE_IO)) 478 return -ENXIO; 479 if (offset < rp->start || (offset + size) > rp->end) 480 return -ENXIO; 481 addr = hose->io_base_virt + port; 482 483 switch(size) { 484 case 1: 485 *((u8 *)val) = in_8(addr); 486 return 1; 487 case 2: 488 if (port & 1) 489 return -EINVAL; 490 *((u16 *)val) = in_le16(addr); 491 return 2; 492 case 4: 493 if (port & 3) 494 return -EINVAL; 495 *((u32 *)val) = in_le32(addr); 496 return 4; 497 } 498 return -EINVAL; 499 } 500 501 /* This provides legacy IO write access on a bus */ 502 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 503 { 504 unsigned long offset; 505 struct pci_controller *hose = pci_bus_to_host(bus); 506 struct resource *rp = &hose->io_resource; 507 void __iomem *addr; 508 509 /* Check if port can be supported by that bus. We only check 510 * the ranges of the PHB though, not the bus itself as the rules 511 * for forwarding legacy cycles down bridges are not our problem 512 * here. So if the host bridge supports it, we do it. 513 */ 514 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 515 offset += port; 516 517 if (!(rp->flags & IORESOURCE_IO)) 518 return -ENXIO; 519 if (offset < rp->start || (offset + size) > rp->end) 520 return -ENXIO; 521 addr = hose->io_base_virt + port; 522 523 /* WARNING: The generic code is idiotic. It gets passed a pointer 524 * to what can be a 1, 2 or 4 byte quantity and always reads that 525 * as a u32, which means that we have to correct the location of 526 * the data read within those 32 bits for size 1 and 2 527 */ 528 switch(size) { 529 case 1: 530 out_8(addr, val >> 24); 531 return 1; 532 case 2: 533 if (port & 1) 534 return -EINVAL; 535 out_le16(addr, val >> 16); 536 return 2; 537 case 4: 538 if (port & 3) 539 return -EINVAL; 540 out_le32(addr, val); 541 return 4; 542 } 543 return -EINVAL; 544 } 545 546 /* This provides legacy IO or memory mmap access on a bus */ 547 int pci_mmap_legacy_page_range(struct pci_bus *bus, 548 struct vm_area_struct *vma, 549 enum pci_mmap_state mmap_state) 550 { 551 struct pci_controller *hose = pci_bus_to_host(bus); 552 resource_size_t offset = 553 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 554 resource_size_t size = vma->vm_end - vma->vm_start; 555 struct resource *rp; 556 557 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 558 pci_domain_nr(bus), bus->number, 559 mmap_state == pci_mmap_mem ? "MEM" : "IO", 560 (unsigned long long)offset, 561 (unsigned long long)(offset + size - 1)); 562 563 if (mmap_state == pci_mmap_mem) { 564 /* Hack alert ! 565 * 566 * Because X is lame and can fail starting if it gets an error trying 567 * to mmap legacy_mem (instead of just moving on without legacy memory 568 * access) we fake it here by giving it anonymous memory, effectively 569 * behaving just like /dev/zero 570 */ 571 if ((offset + size) > hose->isa_mem_size) { 572 printk(KERN_DEBUG 573 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 574 current->comm, current->pid, pci_domain_nr(bus), bus->number); 575 if (vma->vm_flags & VM_SHARED) 576 return shmem_zero_setup(vma); 577 return 0; 578 } 579 offset += hose->isa_mem_phys; 580 } else { 581 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 582 unsigned long roffset = offset + io_offset; 583 rp = &hose->io_resource; 584 if (!(rp->flags & IORESOURCE_IO)) 585 return -ENXIO; 586 if (roffset < rp->start || (roffset + size) > rp->end) 587 return -ENXIO; 588 offset += hose->io_base_phys; 589 } 590 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 591 592 vma->vm_pgoff = offset >> PAGE_SHIFT; 593 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 594 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 595 vma->vm_end - vma->vm_start, 596 vma->vm_page_prot); 597 } 598 599 void pci_resource_to_user(const struct pci_dev *dev, int bar, 600 const struct resource *rsrc, 601 resource_size_t *start, resource_size_t *end) 602 { 603 struct pci_controller *hose = pci_bus_to_host(dev->bus); 604 resource_size_t offset = 0; 605 606 if (hose == NULL) 607 return; 608 609 if (rsrc->flags & IORESOURCE_IO) 610 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 611 612 /* We pass a fully fixed up address to userland for MMIO instead of 613 * a BAR value because X is lame and expects to be able to use that 614 * to pass to /dev/mem ! 615 * 616 * That means that we'll have potentially 64 bits values where some 617 * userland apps only expect 32 (like X itself since it thinks only 618 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 619 * 32 bits CHRPs :-( 620 * 621 * Hopefully, the sysfs insterface is immune to that gunk. Once X 622 * has been fixed (and the fix spread enough), we can re-enable the 623 * 2 lines below and pass down a BAR value to userland. In that case 624 * we'll also have to re-enable the matching code in 625 * __pci_mmap_make_offset(). 626 * 627 * BenH. 628 */ 629 #if 0 630 else if (rsrc->flags & IORESOURCE_MEM) 631 offset = hose->pci_mem_offset; 632 #endif 633 634 *start = rsrc->start - offset; 635 *end = rsrc->end - offset; 636 } 637 638 /** 639 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 640 * @hose: newly allocated pci_controller to be setup 641 * @dev: device node of the host bridge 642 * @primary: set if primary bus (32 bits only, soon to be deprecated) 643 * 644 * This function will parse the "ranges" property of a PCI host bridge device 645 * node and setup the resource mapping of a pci controller based on its 646 * content. 647 * 648 * Life would be boring if it wasn't for a few issues that we have to deal 649 * with here: 650 * 651 * - We can only cope with one IO space range and up to 3 Memory space 652 * ranges. However, some machines (thanks Apple !) tend to split their 653 * space into lots of small contiguous ranges. So we have to coalesce. 654 * 655 * - We can only cope with all memory ranges having the same offset 656 * between CPU addresses and PCI addresses. Unfortunately, some bridges 657 * are setup for a large 1:1 mapping along with a small "window" which 658 * maps PCI address 0 to some arbitrary high address of the CPU space in 659 * order to give access to the ISA memory hole. 660 * The way out of here that I've chosen for now is to always set the 661 * offset based on the first resource found, then override it if we 662 * have a different offset and the previous was set by an ISA hole. 663 * 664 * - Some busses have IO space not starting at 0, which causes trouble with 665 * the way we do our IO resource renumbering. The code somewhat deals with 666 * it for 64 bits but I would expect problems on 32 bits. 667 * 668 * - Some 32 bits platforms such as 4xx can have physical space larger than 669 * 32 bits so we need to use 64 bits values for the parsing 670 */ 671 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, 672 struct device_node *dev, 673 int primary) 674 { 675 const u32 *ranges; 676 int rlen; 677 int pna = of_n_addr_cells(dev); 678 int np = pna + 5; 679 int memno = 0, isa_hole = -1; 680 u32 pci_space; 681 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 682 unsigned long long isa_mb = 0; 683 struct resource *res; 684 685 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 686 dev->full_name, primary ? "(primary)" : ""); 687 688 /* Get ranges property */ 689 ranges = of_get_property(dev, "ranges", &rlen); 690 if (ranges == NULL) 691 return; 692 693 /* Parse it */ 694 while ((rlen -= np * 4) >= 0) { 695 /* Read next ranges element */ 696 pci_space = ranges[0]; 697 pci_addr = of_read_number(ranges + 1, 2); 698 cpu_addr = of_translate_address(dev, ranges + 3); 699 size = of_read_number(ranges + pna + 3, 2); 700 ranges += np; 701 702 /* If we failed translation or got a zero-sized region 703 * (some FW try to feed us with non sensical zero sized regions 704 * such as power3 which look like some kind of attempt at exposing 705 * the VGA memory hole) 706 */ 707 if (cpu_addr == OF_BAD_ADDR || size == 0) 708 continue; 709 710 /* Now consume following elements while they are contiguous */ 711 for (; rlen >= np * sizeof(u32); 712 ranges += np, rlen -= np * 4) { 713 if (ranges[0] != pci_space) 714 break; 715 pci_next = of_read_number(ranges + 1, 2); 716 cpu_next = of_translate_address(dev, ranges + 3); 717 if (pci_next != pci_addr + size || 718 cpu_next != cpu_addr + size) 719 break; 720 size += of_read_number(ranges + pna + 3, 2); 721 } 722 723 /* Act based on address space type */ 724 res = NULL; 725 switch ((pci_space >> 24) & 0x3) { 726 case 1: /* PCI IO space */ 727 printk(KERN_INFO 728 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 729 cpu_addr, cpu_addr + size - 1, pci_addr); 730 731 /* We support only one IO range */ 732 if (hose->pci_io_size) { 733 printk(KERN_INFO 734 " \\--> Skipped (too many) !\n"); 735 continue; 736 } 737 #ifdef CONFIG_PPC32 738 /* On 32 bits, limit I/O space to 16MB */ 739 if (size > 0x01000000) 740 size = 0x01000000; 741 742 /* 32 bits needs to map IOs here */ 743 hose->io_base_virt = ioremap(cpu_addr, size); 744 745 /* Expect trouble if pci_addr is not 0 */ 746 if (primary) 747 isa_io_base = 748 (unsigned long)hose->io_base_virt; 749 #endif /* CONFIG_PPC32 */ 750 /* pci_io_size and io_base_phys always represent IO 751 * space starting at 0 so we factor in pci_addr 752 */ 753 hose->pci_io_size = pci_addr + size; 754 hose->io_base_phys = cpu_addr - pci_addr; 755 756 /* Build resource */ 757 res = &hose->io_resource; 758 res->flags = IORESOURCE_IO; 759 res->start = pci_addr; 760 break; 761 case 2: /* PCI Memory space */ 762 case 3: /* PCI 64 bits Memory space */ 763 printk(KERN_INFO 764 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 765 cpu_addr, cpu_addr + size - 1, pci_addr, 766 (pci_space & 0x40000000) ? "Prefetch" : ""); 767 768 /* We support only 3 memory ranges */ 769 if (memno >= 3) { 770 printk(KERN_INFO 771 " \\--> Skipped (too many) !\n"); 772 continue; 773 } 774 /* Handles ISA memory hole space here */ 775 if (pci_addr == 0) { 776 isa_mb = cpu_addr; 777 isa_hole = memno; 778 if (primary || isa_mem_base == 0) 779 isa_mem_base = cpu_addr; 780 hose->isa_mem_phys = cpu_addr; 781 hose->isa_mem_size = size; 782 } 783 784 /* We get the PCI/Mem offset from the first range or 785 * the, current one if the offset came from an ISA 786 * hole. If they don't match, bugger. 787 */ 788 if (memno == 0 || 789 (isa_hole >= 0 && pci_addr != 0 && 790 hose->pci_mem_offset == isa_mb)) 791 hose->pci_mem_offset = cpu_addr - pci_addr; 792 else if (pci_addr != 0 && 793 hose->pci_mem_offset != cpu_addr - pci_addr) { 794 printk(KERN_INFO 795 " \\--> Skipped (offset mismatch) !\n"); 796 continue; 797 } 798 799 /* Build resource */ 800 res = &hose->mem_resources[memno++]; 801 res->flags = IORESOURCE_MEM; 802 if (pci_space & 0x40000000) 803 res->flags |= IORESOURCE_PREFETCH; 804 res->start = cpu_addr; 805 break; 806 } 807 if (res != NULL) { 808 res->name = dev->full_name; 809 res->end = res->start + size - 1; 810 res->parent = NULL; 811 res->sibling = NULL; 812 res->child = NULL; 813 } 814 } 815 816 /* If there's an ISA hole and the pci_mem_offset is -not- matching 817 * the ISA hole offset, then we need to remove the ISA hole from 818 * the resource list for that brige 819 */ 820 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { 821 unsigned int next = isa_hole + 1; 822 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); 823 if (next < memno) 824 memmove(&hose->mem_resources[isa_hole], 825 &hose->mem_resources[next], 826 sizeof(struct resource) * (memno - next)); 827 hose->mem_resources[--memno].flags = 0; 828 } 829 } 830 831 /* Decide whether to display the domain number in /proc */ 832 int pci_proc_domain(struct pci_bus *bus) 833 { 834 struct pci_controller *hose = pci_bus_to_host(bus); 835 836 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS)) 837 return 0; 838 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0) 839 return hose->global_number != 0; 840 return 1; 841 } 842 843 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 844 struct resource *res) 845 { 846 resource_size_t offset = 0, mask = (resource_size_t)-1; 847 struct pci_controller *hose = pci_bus_to_host(dev->bus); 848 849 if (!hose) 850 return; 851 if (res->flags & IORESOURCE_IO) { 852 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 853 mask = 0xffffffffu; 854 } else if (res->flags & IORESOURCE_MEM) 855 offset = hose->pci_mem_offset; 856 857 region->start = (res->start - offset) & mask; 858 region->end = (res->end - offset) & mask; 859 } 860 EXPORT_SYMBOL(pcibios_resource_to_bus); 861 862 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 863 struct pci_bus_region *region) 864 { 865 resource_size_t offset = 0, mask = (resource_size_t)-1; 866 struct pci_controller *hose = pci_bus_to_host(dev->bus); 867 868 if (!hose) 869 return; 870 if (res->flags & IORESOURCE_IO) { 871 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 872 mask = 0xffffffffu; 873 } else if (res->flags & IORESOURCE_MEM) 874 offset = hose->pci_mem_offset; 875 res->start = (region->start + offset) & mask; 876 res->end = (region->end + offset) & mask; 877 } 878 EXPORT_SYMBOL(pcibios_bus_to_resource); 879 880 /* Fixup a bus resource into a linux resource */ 881 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) 882 { 883 struct pci_controller *hose = pci_bus_to_host(dev->bus); 884 resource_size_t offset = 0, mask = (resource_size_t)-1; 885 886 if (res->flags & IORESOURCE_IO) { 887 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 888 mask = 0xffffffffu; 889 } else if (res->flags & IORESOURCE_MEM) 890 offset = hose->pci_mem_offset; 891 892 res->start = (res->start + offset) & mask; 893 res->end = (res->end + offset) & mask; 894 } 895 896 897 /* This header fixup will do the resource fixup for all devices as they are 898 * probed, but not for bridge ranges 899 */ 900 static void __devinit pcibios_fixup_resources(struct pci_dev *dev) 901 { 902 struct pci_controller *hose = pci_bus_to_host(dev->bus); 903 int i; 904 905 if (!hose) { 906 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 907 pci_name(dev)); 908 return; 909 } 910 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 911 struct resource *res = dev->resource + i; 912 if (!res->flags) 913 continue; 914 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't 915 * consider 0 as an unassigned BAR value. It's technically 916 * a valid value, but linux doesn't like it... so when we can 917 * re-assign things, we do so, but if we can't, we keep it 918 * around and hope for the best... 919 */ 920 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 921 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", 922 pci_name(dev), i, 923 (unsigned long long)res->start, 924 (unsigned long long)res->end, 925 (unsigned int)res->flags); 926 res->end -= res->start; 927 res->start = 0; 928 res->flags |= IORESOURCE_UNSET; 929 continue; 930 } 931 932 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", 933 pci_name(dev), i, 934 (unsigned long long)res->start,\ 935 (unsigned long long)res->end, 936 (unsigned int)res->flags); 937 938 fixup_resource(res, dev); 939 940 pr_debug("PCI:%s %016llx-%016llx\n", 941 pci_name(dev), 942 (unsigned long long)res->start, 943 (unsigned long long)res->end); 944 } 945 946 /* Call machine specific resource fixup */ 947 if (ppc_md.pcibios_fixup_resources) 948 ppc_md.pcibios_fixup_resources(dev); 949 } 950 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 951 952 /* This function tries to figure out if a bridge resource has been initialized 953 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 954 * things go more smoothly when it gets it right. It should covers cases such 955 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 956 */ 957 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 958 struct resource *res) 959 { 960 struct pci_controller *hose = pci_bus_to_host(bus); 961 struct pci_dev *dev = bus->self; 962 resource_size_t offset; 963 u16 command; 964 int i; 965 966 /* We don't do anything if PCI_PROBE_ONLY is set */ 967 if (ppc_pci_flags & PPC_PCI_PROBE_ONLY) 968 return 0; 969 970 /* Job is a bit different between memory and IO */ 971 if (res->flags & IORESOURCE_MEM) { 972 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been 973 * initialized by somebody 974 */ 975 if (res->start != hose->pci_mem_offset) 976 return 0; 977 978 /* The BAR is 0, let's check if memory decoding is enabled on 979 * the bridge. If not, we consider it unassigned 980 */ 981 pci_read_config_word(dev, PCI_COMMAND, &command); 982 if ((command & PCI_COMMAND_MEMORY) == 0) 983 return 1; 984 985 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 986 * resources covers that starting address (0 then it's good enough for 987 * us for memory 988 */ 989 for (i = 0; i < 3; i++) { 990 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 991 hose->mem_resources[i].start == hose->pci_mem_offset) 992 return 0; 993 } 994 995 /* Well, it starts at 0 and we know it will collide so we may as 996 * well consider it as unassigned. That covers the Apple case. 997 */ 998 return 1; 999 } else { 1000 /* If the BAR is non-0, then we consider it assigned */ 1001 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1002 if (((res->start - offset) & 0xfffffffful) != 0) 1003 return 0; 1004 1005 /* Here, we are a bit different than memory as typically IO space 1006 * starting at low addresses -is- valid. What we do instead if that 1007 * we consider as unassigned anything that doesn't have IO enabled 1008 * in the PCI command register, and that's it. 1009 */ 1010 pci_read_config_word(dev, PCI_COMMAND, &command); 1011 if (command & PCI_COMMAND_IO) 1012 return 0; 1013 1014 /* It's starting at 0 and IO is disabled in the bridge, consider 1015 * it unassigned 1016 */ 1017 return 1; 1018 } 1019 } 1020 1021 /* Fixup resources of a PCI<->PCI bridge */ 1022 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus) 1023 { 1024 struct resource *res; 1025 int i; 1026 1027 struct pci_dev *dev = bus->self; 1028 1029 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { 1030 if ((res = bus->resource[i]) == NULL) 1031 continue; 1032 if (!res->flags) 1033 continue; 1034 if (i >= 3 && bus->self->transparent) 1035 continue; 1036 1037 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", 1038 pci_name(dev), i, 1039 (unsigned long long)res->start,\ 1040 (unsigned long long)res->end, 1041 (unsigned int)res->flags); 1042 1043 /* Perform fixup */ 1044 fixup_resource(res, dev); 1045 1046 /* Try to detect uninitialized P2P bridge resources, 1047 * and clear them out so they get re-assigned later 1048 */ 1049 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1050 res->flags = 0; 1051 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1052 } else { 1053 1054 pr_debug("PCI:%s %016llx-%016llx\n", 1055 pci_name(dev), 1056 (unsigned long long)res->start, 1057 (unsigned long long)res->end); 1058 } 1059 } 1060 } 1061 1062 void __devinit pcibios_setup_bus_self(struct pci_bus *bus) 1063 { 1064 /* Fix up the bus resources for P2P bridges */ 1065 if (bus->self != NULL) 1066 pcibios_fixup_bridge(bus); 1067 1068 /* Platform specific bus fixups. This is currently only used 1069 * by fsl_pci and I'm hoping to get rid of it at some point 1070 */ 1071 if (ppc_md.pcibios_fixup_bus) 1072 ppc_md.pcibios_fixup_bus(bus); 1073 1074 /* Setup bus DMA mappings */ 1075 if (ppc_md.pci_dma_bus_setup) 1076 ppc_md.pci_dma_bus_setup(bus); 1077 } 1078 1079 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus) 1080 { 1081 struct pci_dev *dev; 1082 1083 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1084 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1085 1086 list_for_each_entry(dev, &bus->devices, bus_list) { 1087 struct dev_archdata *sd = &dev->dev.archdata; 1088 1089 /* Setup OF node pointer in archdata */ 1090 sd->of_node = pci_device_to_OF_node(dev); 1091 1092 /* Fixup NUMA node as it may not be setup yet by the generic 1093 * code and is needed by the DMA init 1094 */ 1095 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1096 1097 /* Hook up default DMA ops */ 1098 sd->dma_ops = pci_dma_ops; 1099 sd->dma_data = (void *)PCI_DRAM_OFFSET; 1100 1101 /* Additional platform DMA/iommu setup */ 1102 if (ppc_md.pci_dma_dev_setup) 1103 ppc_md.pci_dma_dev_setup(dev); 1104 1105 /* Read default IRQs and fixup if necessary */ 1106 pci_read_irq_line(dev); 1107 if (ppc_md.pci_irq_fixup) 1108 ppc_md.pci_irq_fixup(dev); 1109 } 1110 } 1111 1112 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 1113 { 1114 /* When called from the generic PCI probe, read PCI<->PCI bridge 1115 * bases. This is -not- called when generating the PCI tree from 1116 * the OF device-tree. 1117 */ 1118 if (bus->self != NULL) 1119 pci_read_bridge_bases(bus); 1120 1121 /* Now fixup the bus bus */ 1122 pcibios_setup_bus_self(bus); 1123 1124 /* Now fixup devices on that bus */ 1125 pcibios_setup_bus_devices(bus); 1126 } 1127 EXPORT_SYMBOL(pcibios_fixup_bus); 1128 1129 static int skip_isa_ioresource_align(struct pci_dev *dev) 1130 { 1131 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) && 1132 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1133 return 1; 1134 return 0; 1135 } 1136 1137 /* 1138 * We need to avoid collisions with `mirrored' VGA ports 1139 * and other strange ISA hardware, so we always want the 1140 * addresses to be allocated in the 0x000-0x0ff region 1141 * modulo 0x400. 1142 * 1143 * Why? Because some silly external IO cards only decode 1144 * the low 10 bits of the IO address. The 0x00-0xff region 1145 * is reserved for motherboard devices that decode all 16 1146 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1147 * but we want to try to avoid allocating at 0x2900-0x2bff 1148 * which might have be mirrored at 0x0100-0x03ff.. 1149 */ 1150 void pcibios_align_resource(void *data, struct resource *res, 1151 resource_size_t size, resource_size_t align) 1152 { 1153 struct pci_dev *dev = data; 1154 1155 if (res->flags & IORESOURCE_IO) { 1156 resource_size_t start = res->start; 1157 1158 if (skip_isa_ioresource_align(dev)) 1159 return; 1160 if (start & 0x300) { 1161 start = (start + 0x3ff) & ~0x3ff; 1162 res->start = start; 1163 } 1164 } 1165 } 1166 EXPORT_SYMBOL(pcibios_align_resource); 1167 1168 /* 1169 * Reparent resource children of pr that conflict with res 1170 * under res, and make res replace those children. 1171 */ 1172 static int __init reparent_resources(struct resource *parent, 1173 struct resource *res) 1174 { 1175 struct resource *p, **pp; 1176 struct resource **firstpp = NULL; 1177 1178 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1179 if (p->end < res->start) 1180 continue; 1181 if (res->end < p->start) 1182 break; 1183 if (p->start < res->start || p->end > res->end) 1184 return -1; /* not completely contained */ 1185 if (firstpp == NULL) 1186 firstpp = pp; 1187 } 1188 if (firstpp == NULL) 1189 return -1; /* didn't find any conflicting entries? */ 1190 res->parent = parent; 1191 res->child = *firstpp; 1192 res->sibling = *pp; 1193 *firstpp = res; 1194 *pp = NULL; 1195 for (p = res->child; p != NULL; p = p->sibling) { 1196 p->parent = res; 1197 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1198 p->name, 1199 (unsigned long long)p->start, 1200 (unsigned long long)p->end, res->name); 1201 } 1202 return 0; 1203 } 1204 1205 /* 1206 * Handle resources of PCI devices. If the world were perfect, we could 1207 * just allocate all the resource regions and do nothing more. It isn't. 1208 * On the other hand, we cannot just re-allocate all devices, as it would 1209 * require us to know lots of host bridge internals. So we attempt to 1210 * keep as much of the original configuration as possible, but tweak it 1211 * when it's found to be wrong. 1212 * 1213 * Known BIOS problems we have to work around: 1214 * - I/O or memory regions not configured 1215 * - regions configured, but not enabled in the command register 1216 * - bogus I/O addresses above 64K used 1217 * - expansion ROMs left enabled (this may sound harmless, but given 1218 * the fact the PCI specs explicitly allow address decoders to be 1219 * shared between expansion ROMs and other resource regions, it's 1220 * at least dangerous) 1221 * 1222 * Our solution: 1223 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1224 * This gives us fixed barriers on where we can allocate. 1225 * (2) Allocate resources for all enabled devices. If there is 1226 * a collision, just mark the resource as unallocated. Also 1227 * disable expansion ROMs during this step. 1228 * (3) Try to allocate resources for disabled devices. If the 1229 * resources were assigned correctly, everything goes well, 1230 * if they weren't, they won't disturb allocation of other 1231 * resources. 1232 * (4) Assign new addresses to resources which were either 1233 * not configured at all or misconfigured. If explicitly 1234 * requested by the user, configure expansion ROM address 1235 * as well. 1236 */ 1237 1238 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1239 { 1240 struct pci_bus *b; 1241 int i; 1242 struct resource *res, *pr; 1243 1244 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1245 pci_domain_nr(bus), bus->number); 1246 1247 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { 1248 if ((res = bus->resource[i]) == NULL || !res->flags 1249 || res->start > res->end || res->parent) 1250 continue; 1251 if (bus->parent == NULL) 1252 pr = (res->flags & IORESOURCE_IO) ? 1253 &ioport_resource : &iomem_resource; 1254 else { 1255 /* Don't bother with non-root busses when 1256 * re-assigning all resources. We clear the 1257 * resource flags as if they were colliding 1258 * and as such ensure proper re-allocation 1259 * later. 1260 */ 1261 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) 1262 goto clear_resource; 1263 pr = pci_find_parent_resource(bus->self, res); 1264 if (pr == res) { 1265 /* this happens when the generic PCI 1266 * code (wrongly) decides that this 1267 * bridge is transparent -- paulus 1268 */ 1269 continue; 1270 } 1271 } 1272 1273 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1274 "[0x%x], parent %p (%s)\n", 1275 bus->self ? pci_name(bus->self) : "PHB", 1276 bus->number, i, 1277 (unsigned long long)res->start, 1278 (unsigned long long)res->end, 1279 (unsigned int)res->flags, 1280 pr, (pr && pr->name) ? pr->name : "nil"); 1281 1282 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1283 if (request_resource(pr, res) == 0) 1284 continue; 1285 /* 1286 * Must be a conflict with an existing entry. 1287 * Move that entry (or entries) under the 1288 * bridge resource and try again. 1289 */ 1290 if (reparent_resources(pr, res) == 0) 1291 continue; 1292 } 1293 printk(KERN_WARNING "PCI: Cannot allocate resource region " 1294 "%d of PCI bridge %d, will remap\n", i, bus->number); 1295 clear_resource: 1296 res->flags = 0; 1297 } 1298 1299 list_for_each_entry(b, &bus->children, node) 1300 pcibios_allocate_bus_resources(b); 1301 } 1302 1303 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) 1304 { 1305 struct resource *pr, *r = &dev->resource[idx]; 1306 1307 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1308 pci_name(dev), idx, 1309 (unsigned long long)r->start, 1310 (unsigned long long)r->end, 1311 (unsigned int)r->flags); 1312 1313 pr = pci_find_parent_resource(dev, r); 1314 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1315 request_resource(pr, r) < 0) { 1316 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1317 " of device %s, will remap\n", idx, pci_name(dev)); 1318 if (pr) 1319 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1320 pr, 1321 (unsigned long long)pr->start, 1322 (unsigned long long)pr->end, 1323 (unsigned int)pr->flags); 1324 /* We'll assign a new address later */ 1325 r->flags |= IORESOURCE_UNSET; 1326 r->end -= r->start; 1327 r->start = 0; 1328 } 1329 } 1330 1331 static void __init pcibios_allocate_resources(int pass) 1332 { 1333 struct pci_dev *dev = NULL; 1334 int idx, disabled; 1335 u16 command; 1336 struct resource *r; 1337 1338 for_each_pci_dev(dev) { 1339 pci_read_config_word(dev, PCI_COMMAND, &command); 1340 for (idx = 0; idx < 6; idx++) { 1341 r = &dev->resource[idx]; 1342 if (r->parent) /* Already allocated */ 1343 continue; 1344 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1345 continue; /* Not assigned at all */ 1346 if (r->flags & IORESOURCE_IO) 1347 disabled = !(command & PCI_COMMAND_IO); 1348 else 1349 disabled = !(command & PCI_COMMAND_MEMORY); 1350 if (pass == disabled) 1351 alloc_resource(dev, idx); 1352 } 1353 if (pass) 1354 continue; 1355 r = &dev->resource[PCI_ROM_RESOURCE]; 1356 if (r->flags & IORESOURCE_ROM_ENABLE) { 1357 /* Turn the ROM off, leave the resource region, 1358 * but keep it unregistered. 1359 */ 1360 u32 reg; 1361 pr_debug("PCI: Switching off ROM of %s\n", 1362 pci_name(dev)); 1363 r->flags &= ~IORESOURCE_ROM_ENABLE; 1364 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1365 pci_write_config_dword(dev, dev->rom_base_reg, 1366 reg & ~PCI_ROM_ADDRESS_ENABLE); 1367 } 1368 } 1369 } 1370 1371 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1372 { 1373 struct pci_controller *hose = pci_bus_to_host(bus); 1374 resource_size_t offset; 1375 struct resource *res, *pres; 1376 int i; 1377 1378 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1379 1380 /* Check for IO */ 1381 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1382 goto no_io; 1383 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1384 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1385 BUG_ON(res == NULL); 1386 res->name = "Legacy IO"; 1387 res->flags = IORESOURCE_IO; 1388 res->start = offset; 1389 res->end = (offset + 0xfff) & 0xfffffffful; 1390 pr_debug("Candidate legacy IO: %pR\n", res); 1391 if (request_resource(&hose->io_resource, res)) { 1392 printk(KERN_DEBUG 1393 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1394 pci_domain_nr(bus), bus->number, res); 1395 kfree(res); 1396 } 1397 1398 no_io: 1399 /* Check for memory */ 1400 offset = hose->pci_mem_offset; 1401 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); 1402 for (i = 0; i < 3; i++) { 1403 pres = &hose->mem_resources[i]; 1404 if (!(pres->flags & IORESOURCE_MEM)) 1405 continue; 1406 pr_debug("hose mem res: %pR\n", pres); 1407 if ((pres->start - offset) <= 0xa0000 && 1408 (pres->end - offset) >= 0xbffff) 1409 break; 1410 } 1411 if (i >= 3) 1412 return; 1413 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1414 BUG_ON(res == NULL); 1415 res->name = "Legacy VGA memory"; 1416 res->flags = IORESOURCE_MEM; 1417 res->start = 0xa0000 + offset; 1418 res->end = 0xbffff + offset; 1419 pr_debug("Candidate VGA memory: %pR\n", res); 1420 if (request_resource(pres, res)) { 1421 printk(KERN_DEBUG 1422 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1423 pci_domain_nr(bus), bus->number, res); 1424 kfree(res); 1425 } 1426 } 1427 1428 void __init pcibios_resource_survey(void) 1429 { 1430 struct pci_bus *b; 1431 1432 /* Allocate and assign resources. If we re-assign everything, then 1433 * we skip the allocate phase 1434 */ 1435 list_for_each_entry(b, &pci_root_buses, node) 1436 pcibios_allocate_bus_resources(b); 1437 1438 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { 1439 pcibios_allocate_resources(0); 1440 pcibios_allocate_resources(1); 1441 } 1442 1443 /* Before we start assigning unassigned resource, we try to reserve 1444 * the low IO area and the VGA memory area if they intersect the 1445 * bus available resources to avoid allocating things on top of them 1446 */ 1447 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1448 list_for_each_entry(b, &pci_root_buses, node) 1449 pcibios_reserve_legacy_regions(b); 1450 } 1451 1452 /* Now, if the platform didn't decide to blindly trust the firmware, 1453 * we proceed to assigning things that were left unassigned 1454 */ 1455 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1456 pr_debug("PCI: Assigning unassigned resouces...\n"); 1457 pci_assign_unassigned_resources(); 1458 } 1459 1460 /* Call machine dependent fixup */ 1461 if (ppc_md.pcibios_fixup) 1462 ppc_md.pcibios_fixup(); 1463 } 1464 1465 #ifdef CONFIG_HOTPLUG 1466 1467 /* This is used by the PCI hotplug driver to allocate resource 1468 * of newly plugged busses. We can try to consolidate with the 1469 * rest of the code later, for now, keep it as-is as our main 1470 * resource allocation function doesn't deal with sub-trees yet. 1471 */ 1472 void __devinit pcibios_claim_one_bus(struct pci_bus *bus) 1473 { 1474 struct pci_dev *dev; 1475 struct pci_bus *child_bus; 1476 1477 list_for_each_entry(dev, &bus->devices, bus_list) { 1478 int i; 1479 1480 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1481 struct resource *r = &dev->resource[i]; 1482 1483 if (r->parent || !r->start || !r->flags) 1484 continue; 1485 1486 pr_debug("PCI: Claiming %s: " 1487 "Resource %d: %016llx..%016llx [%x]\n", 1488 pci_name(dev), i, 1489 (unsigned long long)r->start, 1490 (unsigned long long)r->end, 1491 (unsigned int)r->flags); 1492 1493 pci_claim_resource(dev, i); 1494 } 1495 } 1496 1497 list_for_each_entry(child_bus, &bus->children, node) 1498 pcibios_claim_one_bus(child_bus); 1499 } 1500 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); 1501 1502 1503 /* pcibios_finish_adding_to_bus 1504 * 1505 * This is to be called by the hotplug code after devices have been 1506 * added to a bus, this include calling it for a PHB that is just 1507 * being added 1508 */ 1509 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1510 { 1511 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1512 pci_domain_nr(bus), bus->number); 1513 1514 /* Allocate bus and devices resources */ 1515 pcibios_allocate_bus_resources(bus); 1516 pcibios_claim_one_bus(bus); 1517 1518 /* Add new devices to global lists. Register in proc, sysfs. */ 1519 pci_bus_add_devices(bus); 1520 1521 /* Fixup EEH */ 1522 eeh_add_device_tree_late(bus); 1523 } 1524 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1525 1526 #endif /* CONFIG_HOTPLUG */ 1527 1528 int pcibios_enable_device(struct pci_dev *dev, int mask) 1529 { 1530 if (ppc_md.pcibios_enable_device_hook) 1531 if (ppc_md.pcibios_enable_device_hook(dev)) 1532 return -EINVAL; 1533 1534 return pci_enable_resources(dev, mask); 1535 } 1536 1537 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) 1538 { 1539 struct pci_bus *bus = hose->bus; 1540 struct resource *res; 1541 int i; 1542 1543 /* Hookup PHB IO resource */ 1544 bus->resource[0] = res = &hose->io_resource; 1545 1546 if (!res->flags) { 1547 printk(KERN_WARNING "PCI: I/O resource not set for host" 1548 " bridge %s (domain %d)\n", 1549 hose->dn->full_name, hose->global_number); 1550 #ifdef CONFIG_PPC32 1551 /* Workaround for lack of IO resource only on 32-bit */ 1552 res->start = (unsigned long)hose->io_base_virt - isa_io_base; 1553 res->end = res->start + IO_SPACE_LIMIT; 1554 res->flags = IORESOURCE_IO; 1555 #endif /* CONFIG_PPC32 */ 1556 } 1557 1558 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", 1559 (unsigned long long)res->start, 1560 (unsigned long long)res->end, 1561 (unsigned long)res->flags); 1562 1563 /* Hookup PHB Memory resources */ 1564 for (i = 0; i < 3; ++i) { 1565 res = &hose->mem_resources[i]; 1566 if (!res->flags) { 1567 if (i > 0) 1568 continue; 1569 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1570 "host bridge %s (domain %d)\n", 1571 hose->dn->full_name, hose->global_number); 1572 #ifdef CONFIG_PPC32 1573 /* Workaround for lack of MEM resource only on 32-bit */ 1574 res->start = hose->pci_mem_offset; 1575 res->end = (resource_size_t)-1LL; 1576 res->flags = IORESOURCE_MEM; 1577 #endif /* CONFIG_PPC32 */ 1578 } 1579 bus->resource[i+1] = res; 1580 1581 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, 1582 (unsigned long long)res->start, 1583 (unsigned long long)res->end, 1584 (unsigned long)res->flags); 1585 } 1586 1587 pr_debug("PCI: PHB MEM offset = %016llx\n", 1588 (unsigned long long)hose->pci_mem_offset); 1589 pr_debug("PCI: PHB IO offset = %08lx\n", 1590 (unsigned long)hose->io_base_virt - _IO_BASE); 1591 1592 } 1593 1594