1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/mm.h> 25 #include <linux/list.h> 26 #include <linux/syscalls.h> 27 #include <linux/irq.h> 28 #include <linux/vmalloc.h> 29 #include <linux/slab.h> 30 31 #include <asm/processor.h> 32 #include <asm/io.h> 33 #include <asm/prom.h> 34 #include <asm/pci-bridge.h> 35 #include <asm/byteorder.h> 36 #include <asm/machdep.h> 37 #include <asm/ppc-pci.h> 38 #include <asm/firmware.h> 39 #include <asm/eeh.h> 40 41 static DEFINE_SPINLOCK(hose_spinlock); 42 LIST_HEAD(hose_list); 43 44 /* XXX kill that some day ... */ 45 static int global_phb_number; /* Global phb counter */ 46 47 /* ISA Memory physical address */ 48 resource_size_t isa_mem_base; 49 50 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */ 51 unsigned int ppc_pci_flags = 0; 52 53 54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 55 56 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 57 { 58 pci_dma_ops = dma_ops; 59 } 60 61 struct dma_map_ops *get_pci_dma_ops(void) 62 { 63 return pci_dma_ops; 64 } 65 EXPORT_SYMBOL(get_pci_dma_ops); 66 67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 68 { 69 struct pci_controller *phb; 70 71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 72 if (phb == NULL) 73 return NULL; 74 spin_lock(&hose_spinlock); 75 phb->global_number = global_phb_number++; 76 list_add_tail(&phb->list_node, &hose_list); 77 spin_unlock(&hose_spinlock); 78 phb->dn = dev; 79 phb->is_dynamic = mem_init_done; 80 #ifdef CONFIG_PPC64 81 if (dev) { 82 int nid = of_node_to_nid(dev); 83 84 if (nid < 0 || !node_online(nid)) 85 nid = -1; 86 87 PHB_SET_NODE(phb, nid); 88 } 89 #endif 90 return phb; 91 } 92 93 void pcibios_free_controller(struct pci_controller *phb) 94 { 95 spin_lock(&hose_spinlock); 96 list_del(&phb->list_node); 97 spin_unlock(&hose_spinlock); 98 99 if (phb->is_dynamic) 100 kfree(phb); 101 } 102 103 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 104 { 105 #ifdef CONFIG_PPC64 106 return hose->pci_io_size; 107 #else 108 return hose->io_resource.end - hose->io_resource.start + 1; 109 #endif 110 } 111 112 int pcibios_vaddr_is_ioport(void __iomem *address) 113 { 114 int ret = 0; 115 struct pci_controller *hose; 116 resource_size_t size; 117 118 spin_lock(&hose_spinlock); 119 list_for_each_entry(hose, &hose_list, list_node) { 120 size = pcibios_io_size(hose); 121 if (address >= hose->io_base_virt && 122 address < (hose->io_base_virt + size)) { 123 ret = 1; 124 break; 125 } 126 } 127 spin_unlock(&hose_spinlock); 128 return ret; 129 } 130 131 unsigned long pci_address_to_pio(phys_addr_t address) 132 { 133 struct pci_controller *hose; 134 resource_size_t size; 135 unsigned long ret = ~0; 136 137 spin_lock(&hose_spinlock); 138 list_for_each_entry(hose, &hose_list, list_node) { 139 size = pcibios_io_size(hose); 140 if (address >= hose->io_base_phys && 141 address < (hose->io_base_phys + size)) { 142 unsigned long base = 143 (unsigned long)hose->io_base_virt - _IO_BASE; 144 ret = base + (address - hose->io_base_phys); 145 break; 146 } 147 } 148 spin_unlock(&hose_spinlock); 149 150 return ret; 151 } 152 EXPORT_SYMBOL_GPL(pci_address_to_pio); 153 154 /* 155 * Return the domain number for this bus. 156 */ 157 int pci_domain_nr(struct pci_bus *bus) 158 { 159 struct pci_controller *hose = pci_bus_to_host(bus); 160 161 return hose->global_number; 162 } 163 EXPORT_SYMBOL(pci_domain_nr); 164 165 /* This routine is meant to be used early during boot, when the 166 * PCI bus numbers have not yet been assigned, and you need to 167 * issue PCI config cycles to an OF device. 168 * It could also be used to "fix" RTAS config cycles if you want 169 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 170 * config cycles. 171 */ 172 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 173 { 174 while(node) { 175 struct pci_controller *hose, *tmp; 176 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 177 if (hose->dn == node) 178 return hose; 179 node = node->parent; 180 } 181 return NULL; 182 } 183 184 static ssize_t pci_show_devspec(struct device *dev, 185 struct device_attribute *attr, char *buf) 186 { 187 struct pci_dev *pdev; 188 struct device_node *np; 189 190 pdev = to_pci_dev (dev); 191 np = pci_device_to_OF_node(pdev); 192 if (np == NULL || np->full_name == NULL) 193 return 0; 194 return sprintf(buf, "%s", np->full_name); 195 } 196 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 197 198 /* Add sysfs properties */ 199 int pcibios_add_platform_entries(struct pci_dev *pdev) 200 { 201 return device_create_file(&pdev->dev, &dev_attr_devspec); 202 } 203 204 char __devinit *pcibios_setup(char *str) 205 { 206 return str; 207 } 208 209 /* 210 * Reads the interrupt pin to determine if interrupt is use by card. 211 * If the interrupt is used, then gets the interrupt line from the 212 * openfirmware and sets it in the pci_dev and pci_config line. 213 */ 214 int pci_read_irq_line(struct pci_dev *pci_dev) 215 { 216 struct of_irq oirq; 217 unsigned int virq; 218 219 /* The current device-tree that iSeries generates from the HV 220 * PCI informations doesn't contain proper interrupt routing, 221 * and all the fallback would do is print out crap, so we 222 * don't attempt to resolve the interrupts here at all, some 223 * iSeries specific fixup does it. 224 * 225 * In the long run, we will hopefully fix the generated device-tree 226 * instead. 227 */ 228 #ifdef CONFIG_PPC_ISERIES 229 if (firmware_has_feature(FW_FEATURE_ISERIES)) 230 return -1; 231 #endif 232 233 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 234 235 #ifdef DEBUG 236 memset(&oirq, 0xff, sizeof(oirq)); 237 #endif 238 /* Try to get a mapping from the device-tree */ 239 if (of_irq_map_pci(pci_dev, &oirq)) { 240 u8 line, pin; 241 242 /* If that fails, lets fallback to what is in the config 243 * space and map that through the default controller. We 244 * also set the type to level low since that's what PCI 245 * interrupts are. If your platform does differently, then 246 * either provide a proper interrupt tree or don't use this 247 * function. 248 */ 249 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 250 return -1; 251 if (pin == 0) 252 return -1; 253 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 254 line == 0xff || line == 0) { 255 return -1; 256 } 257 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 258 line, pin); 259 260 virq = irq_create_mapping(NULL, line); 261 if (virq != NO_IRQ) 262 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 263 } else { 264 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 265 oirq.size, oirq.specifier[0], oirq.specifier[1], 266 oirq.controller ? oirq.controller->full_name : 267 "<default>"); 268 269 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 270 oirq.size); 271 } 272 if(virq == NO_IRQ) { 273 pr_debug(" Failed to map !\n"); 274 return -1; 275 } 276 277 pr_debug(" Mapped to linux irq %d\n", virq); 278 279 pci_dev->irq = virq; 280 281 return 0; 282 } 283 EXPORT_SYMBOL(pci_read_irq_line); 284 285 /* 286 * Platform support for /proc/bus/pci/X/Y mmap()s, 287 * modelled on the sparc64 implementation by Dave Miller. 288 * -- paulus. 289 */ 290 291 /* 292 * Adjust vm_pgoff of VMA such that it is the physical page offset 293 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 294 * 295 * Basically, the user finds the base address for his device which he wishes 296 * to mmap. They read the 32-bit value from the config space base register, 297 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 298 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 299 * 300 * Returns negative error code on failure, zero on success. 301 */ 302 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 303 resource_size_t *offset, 304 enum pci_mmap_state mmap_state) 305 { 306 struct pci_controller *hose = pci_bus_to_host(dev->bus); 307 unsigned long io_offset = 0; 308 int i, res_bit; 309 310 if (hose == 0) 311 return NULL; /* should never happen */ 312 313 /* If memory, add on the PCI bridge address offset */ 314 if (mmap_state == pci_mmap_mem) { 315 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 316 *offset += hose->pci_mem_offset; 317 #endif 318 res_bit = IORESOURCE_MEM; 319 } else { 320 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 321 *offset += io_offset; 322 res_bit = IORESOURCE_IO; 323 } 324 325 /* 326 * Check that the offset requested corresponds to one of the 327 * resources of the device. 328 */ 329 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 330 struct resource *rp = &dev->resource[i]; 331 int flags = rp->flags; 332 333 /* treat ROM as memory (should be already) */ 334 if (i == PCI_ROM_RESOURCE) 335 flags |= IORESOURCE_MEM; 336 337 /* Active and same type? */ 338 if ((flags & res_bit) == 0) 339 continue; 340 341 /* In the range of this resource? */ 342 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 343 continue; 344 345 /* found it! construct the final physical address */ 346 if (mmap_state == pci_mmap_io) 347 *offset += hose->io_base_phys - io_offset; 348 return rp; 349 } 350 351 return NULL; 352 } 353 354 /* 355 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 356 * device mapping. 357 */ 358 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 359 pgprot_t protection, 360 enum pci_mmap_state mmap_state, 361 int write_combine) 362 { 363 unsigned long prot = pgprot_val(protection); 364 365 /* Write combine is always 0 on non-memory space mappings. On 366 * memory space, if the user didn't pass 1, we check for a 367 * "prefetchable" resource. This is a bit hackish, but we use 368 * this to workaround the inability of /sysfs to provide a write 369 * combine bit 370 */ 371 if (mmap_state != pci_mmap_mem) 372 write_combine = 0; 373 else if (write_combine == 0) { 374 if (rp->flags & IORESOURCE_PREFETCH) 375 write_combine = 1; 376 } 377 378 /* XXX would be nice to have a way to ask for write-through */ 379 if (write_combine) 380 return pgprot_noncached_wc(prot); 381 else 382 return pgprot_noncached(prot); 383 } 384 385 /* 386 * This one is used by /dev/mem and fbdev who have no clue about the 387 * PCI device, it tries to find the PCI device first and calls the 388 * above routine 389 */ 390 pgprot_t pci_phys_mem_access_prot(struct file *file, 391 unsigned long pfn, 392 unsigned long size, 393 pgprot_t prot) 394 { 395 struct pci_dev *pdev = NULL; 396 struct resource *found = NULL; 397 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 398 int i; 399 400 if (page_is_ram(pfn)) 401 return prot; 402 403 prot = pgprot_noncached(prot); 404 for_each_pci_dev(pdev) { 405 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 406 struct resource *rp = &pdev->resource[i]; 407 int flags = rp->flags; 408 409 /* Active and same type? */ 410 if ((flags & IORESOURCE_MEM) == 0) 411 continue; 412 /* In the range of this resource? */ 413 if (offset < (rp->start & PAGE_MASK) || 414 offset > rp->end) 415 continue; 416 found = rp; 417 break; 418 } 419 if (found) 420 break; 421 } 422 if (found) { 423 if (found->flags & IORESOURCE_PREFETCH) 424 prot = pgprot_noncached_wc(prot); 425 pci_dev_put(pdev); 426 } 427 428 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 429 (unsigned long long)offset, pgprot_val(prot)); 430 431 return prot; 432 } 433 434 435 /* 436 * Perform the actual remap of the pages for a PCI device mapping, as 437 * appropriate for this architecture. The region in the process to map 438 * is described by vm_start and vm_end members of VMA, the base physical 439 * address is found in vm_pgoff. 440 * The pci device structure is provided so that architectures may make mapping 441 * decisions on a per-device or per-bus basis. 442 * 443 * Returns a negative error code on failure, zero on success. 444 */ 445 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 446 enum pci_mmap_state mmap_state, int write_combine) 447 { 448 resource_size_t offset = 449 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 450 struct resource *rp; 451 int ret; 452 453 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 454 if (rp == NULL) 455 return -EINVAL; 456 457 vma->vm_pgoff = offset >> PAGE_SHIFT; 458 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 459 vma->vm_page_prot, 460 mmap_state, write_combine); 461 462 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 463 vma->vm_end - vma->vm_start, vma->vm_page_prot); 464 465 return ret; 466 } 467 468 /* This provides legacy IO read access on a bus */ 469 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 470 { 471 unsigned long offset; 472 struct pci_controller *hose = pci_bus_to_host(bus); 473 struct resource *rp = &hose->io_resource; 474 void __iomem *addr; 475 476 /* Check if port can be supported by that bus. We only check 477 * the ranges of the PHB though, not the bus itself as the rules 478 * for forwarding legacy cycles down bridges are not our problem 479 * here. So if the host bridge supports it, we do it. 480 */ 481 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 482 offset += port; 483 484 if (!(rp->flags & IORESOURCE_IO)) 485 return -ENXIO; 486 if (offset < rp->start || (offset + size) > rp->end) 487 return -ENXIO; 488 addr = hose->io_base_virt + port; 489 490 switch(size) { 491 case 1: 492 *((u8 *)val) = in_8(addr); 493 return 1; 494 case 2: 495 if (port & 1) 496 return -EINVAL; 497 *((u16 *)val) = in_le16(addr); 498 return 2; 499 case 4: 500 if (port & 3) 501 return -EINVAL; 502 *((u32 *)val) = in_le32(addr); 503 return 4; 504 } 505 return -EINVAL; 506 } 507 508 /* This provides legacy IO write access on a bus */ 509 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 510 { 511 unsigned long offset; 512 struct pci_controller *hose = pci_bus_to_host(bus); 513 struct resource *rp = &hose->io_resource; 514 void __iomem *addr; 515 516 /* Check if port can be supported by that bus. We only check 517 * the ranges of the PHB though, not the bus itself as the rules 518 * for forwarding legacy cycles down bridges are not our problem 519 * here. So if the host bridge supports it, we do it. 520 */ 521 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 522 offset += port; 523 524 if (!(rp->flags & IORESOURCE_IO)) 525 return -ENXIO; 526 if (offset < rp->start || (offset + size) > rp->end) 527 return -ENXIO; 528 addr = hose->io_base_virt + port; 529 530 /* WARNING: The generic code is idiotic. It gets passed a pointer 531 * to what can be a 1, 2 or 4 byte quantity and always reads that 532 * as a u32, which means that we have to correct the location of 533 * the data read within those 32 bits for size 1 and 2 534 */ 535 switch(size) { 536 case 1: 537 out_8(addr, val >> 24); 538 return 1; 539 case 2: 540 if (port & 1) 541 return -EINVAL; 542 out_le16(addr, val >> 16); 543 return 2; 544 case 4: 545 if (port & 3) 546 return -EINVAL; 547 out_le32(addr, val); 548 return 4; 549 } 550 return -EINVAL; 551 } 552 553 /* This provides legacy IO or memory mmap access on a bus */ 554 int pci_mmap_legacy_page_range(struct pci_bus *bus, 555 struct vm_area_struct *vma, 556 enum pci_mmap_state mmap_state) 557 { 558 struct pci_controller *hose = pci_bus_to_host(bus); 559 resource_size_t offset = 560 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 561 resource_size_t size = vma->vm_end - vma->vm_start; 562 struct resource *rp; 563 564 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 565 pci_domain_nr(bus), bus->number, 566 mmap_state == pci_mmap_mem ? "MEM" : "IO", 567 (unsigned long long)offset, 568 (unsigned long long)(offset + size - 1)); 569 570 if (mmap_state == pci_mmap_mem) { 571 /* Hack alert ! 572 * 573 * Because X is lame and can fail starting if it gets an error trying 574 * to mmap legacy_mem (instead of just moving on without legacy memory 575 * access) we fake it here by giving it anonymous memory, effectively 576 * behaving just like /dev/zero 577 */ 578 if ((offset + size) > hose->isa_mem_size) { 579 printk(KERN_DEBUG 580 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 581 current->comm, current->pid, pci_domain_nr(bus), bus->number); 582 if (vma->vm_flags & VM_SHARED) 583 return shmem_zero_setup(vma); 584 return 0; 585 } 586 offset += hose->isa_mem_phys; 587 } else { 588 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 589 unsigned long roffset = offset + io_offset; 590 rp = &hose->io_resource; 591 if (!(rp->flags & IORESOURCE_IO)) 592 return -ENXIO; 593 if (roffset < rp->start || (roffset + size) > rp->end) 594 return -ENXIO; 595 offset += hose->io_base_phys; 596 } 597 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 598 599 vma->vm_pgoff = offset >> PAGE_SHIFT; 600 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 601 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 602 vma->vm_end - vma->vm_start, 603 vma->vm_page_prot); 604 } 605 606 void pci_resource_to_user(const struct pci_dev *dev, int bar, 607 const struct resource *rsrc, 608 resource_size_t *start, resource_size_t *end) 609 { 610 struct pci_controller *hose = pci_bus_to_host(dev->bus); 611 resource_size_t offset = 0; 612 613 if (hose == NULL) 614 return; 615 616 if (rsrc->flags & IORESOURCE_IO) 617 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 618 619 /* We pass a fully fixed up address to userland for MMIO instead of 620 * a BAR value because X is lame and expects to be able to use that 621 * to pass to /dev/mem ! 622 * 623 * That means that we'll have potentially 64 bits values where some 624 * userland apps only expect 32 (like X itself since it thinks only 625 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 626 * 32 bits CHRPs :-( 627 * 628 * Hopefully, the sysfs insterface is immune to that gunk. Once X 629 * has been fixed (and the fix spread enough), we can re-enable the 630 * 2 lines below and pass down a BAR value to userland. In that case 631 * we'll also have to re-enable the matching code in 632 * __pci_mmap_make_offset(). 633 * 634 * BenH. 635 */ 636 #if 0 637 else if (rsrc->flags & IORESOURCE_MEM) 638 offset = hose->pci_mem_offset; 639 #endif 640 641 *start = rsrc->start - offset; 642 *end = rsrc->end - offset; 643 } 644 645 /** 646 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 647 * @hose: newly allocated pci_controller to be setup 648 * @dev: device node of the host bridge 649 * @primary: set if primary bus (32 bits only, soon to be deprecated) 650 * 651 * This function will parse the "ranges" property of a PCI host bridge device 652 * node and setup the resource mapping of a pci controller based on its 653 * content. 654 * 655 * Life would be boring if it wasn't for a few issues that we have to deal 656 * with here: 657 * 658 * - We can only cope with one IO space range and up to 3 Memory space 659 * ranges. However, some machines (thanks Apple !) tend to split their 660 * space into lots of small contiguous ranges. So we have to coalesce. 661 * 662 * - We can only cope with all memory ranges having the same offset 663 * between CPU addresses and PCI addresses. Unfortunately, some bridges 664 * are setup for a large 1:1 mapping along with a small "window" which 665 * maps PCI address 0 to some arbitrary high address of the CPU space in 666 * order to give access to the ISA memory hole. 667 * The way out of here that I've chosen for now is to always set the 668 * offset based on the first resource found, then override it if we 669 * have a different offset and the previous was set by an ISA hole. 670 * 671 * - Some busses have IO space not starting at 0, which causes trouble with 672 * the way we do our IO resource renumbering. The code somewhat deals with 673 * it for 64 bits but I would expect problems on 32 bits. 674 * 675 * - Some 32 bits platforms such as 4xx can have physical space larger than 676 * 32 bits so we need to use 64 bits values for the parsing 677 */ 678 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, 679 struct device_node *dev, 680 int primary) 681 { 682 const u32 *ranges; 683 int rlen; 684 int pna = of_n_addr_cells(dev); 685 int np = pna + 5; 686 int memno = 0, isa_hole = -1; 687 u32 pci_space; 688 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 689 unsigned long long isa_mb = 0; 690 struct resource *res; 691 692 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 693 dev->full_name, primary ? "(primary)" : ""); 694 695 /* Get ranges property */ 696 ranges = of_get_property(dev, "ranges", &rlen); 697 if (ranges == NULL) 698 return; 699 700 /* Parse it */ 701 while ((rlen -= np * 4) >= 0) { 702 /* Read next ranges element */ 703 pci_space = ranges[0]; 704 pci_addr = of_read_number(ranges + 1, 2); 705 cpu_addr = of_translate_address(dev, ranges + 3); 706 size = of_read_number(ranges + pna + 3, 2); 707 ranges += np; 708 709 /* If we failed translation or got a zero-sized region 710 * (some FW try to feed us with non sensical zero sized regions 711 * such as power3 which look like some kind of attempt at exposing 712 * the VGA memory hole) 713 */ 714 if (cpu_addr == OF_BAD_ADDR || size == 0) 715 continue; 716 717 /* Now consume following elements while they are contiguous */ 718 for (; rlen >= np * sizeof(u32); 719 ranges += np, rlen -= np * 4) { 720 if (ranges[0] != pci_space) 721 break; 722 pci_next = of_read_number(ranges + 1, 2); 723 cpu_next = of_translate_address(dev, ranges + 3); 724 if (pci_next != pci_addr + size || 725 cpu_next != cpu_addr + size) 726 break; 727 size += of_read_number(ranges + pna + 3, 2); 728 } 729 730 /* Act based on address space type */ 731 res = NULL; 732 switch ((pci_space >> 24) & 0x3) { 733 case 1: /* PCI IO space */ 734 printk(KERN_INFO 735 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 736 cpu_addr, cpu_addr + size - 1, pci_addr); 737 738 /* We support only one IO range */ 739 if (hose->pci_io_size) { 740 printk(KERN_INFO 741 " \\--> Skipped (too many) !\n"); 742 continue; 743 } 744 #ifdef CONFIG_PPC32 745 /* On 32 bits, limit I/O space to 16MB */ 746 if (size > 0x01000000) 747 size = 0x01000000; 748 749 /* 32 bits needs to map IOs here */ 750 hose->io_base_virt = ioremap(cpu_addr, size); 751 752 /* Expect trouble if pci_addr is not 0 */ 753 if (primary) 754 isa_io_base = 755 (unsigned long)hose->io_base_virt; 756 #endif /* CONFIG_PPC32 */ 757 /* pci_io_size and io_base_phys always represent IO 758 * space starting at 0 so we factor in pci_addr 759 */ 760 hose->pci_io_size = pci_addr + size; 761 hose->io_base_phys = cpu_addr - pci_addr; 762 763 /* Build resource */ 764 res = &hose->io_resource; 765 res->flags = IORESOURCE_IO; 766 res->start = pci_addr; 767 break; 768 case 2: /* PCI Memory space */ 769 case 3: /* PCI 64 bits Memory space */ 770 printk(KERN_INFO 771 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 772 cpu_addr, cpu_addr + size - 1, pci_addr, 773 (pci_space & 0x40000000) ? "Prefetch" : ""); 774 775 /* We support only 3 memory ranges */ 776 if (memno >= 3) { 777 printk(KERN_INFO 778 " \\--> Skipped (too many) !\n"); 779 continue; 780 } 781 /* Handles ISA memory hole space here */ 782 if (pci_addr == 0) { 783 isa_mb = cpu_addr; 784 isa_hole = memno; 785 if (primary || isa_mem_base == 0) 786 isa_mem_base = cpu_addr; 787 hose->isa_mem_phys = cpu_addr; 788 hose->isa_mem_size = size; 789 } 790 791 /* We get the PCI/Mem offset from the first range or 792 * the, current one if the offset came from an ISA 793 * hole. If they don't match, bugger. 794 */ 795 if (memno == 0 || 796 (isa_hole >= 0 && pci_addr != 0 && 797 hose->pci_mem_offset == isa_mb)) 798 hose->pci_mem_offset = cpu_addr - pci_addr; 799 else if (pci_addr != 0 && 800 hose->pci_mem_offset != cpu_addr - pci_addr) { 801 printk(KERN_INFO 802 " \\--> Skipped (offset mismatch) !\n"); 803 continue; 804 } 805 806 /* Build resource */ 807 res = &hose->mem_resources[memno++]; 808 res->flags = IORESOURCE_MEM; 809 if (pci_space & 0x40000000) 810 res->flags |= IORESOURCE_PREFETCH; 811 res->start = cpu_addr; 812 break; 813 } 814 if (res != NULL) { 815 res->name = dev->full_name; 816 res->end = res->start + size - 1; 817 res->parent = NULL; 818 res->sibling = NULL; 819 res->child = NULL; 820 } 821 } 822 823 /* If there's an ISA hole and the pci_mem_offset is -not- matching 824 * the ISA hole offset, then we need to remove the ISA hole from 825 * the resource list for that brige 826 */ 827 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { 828 unsigned int next = isa_hole + 1; 829 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); 830 if (next < memno) 831 memmove(&hose->mem_resources[isa_hole], 832 &hose->mem_resources[next], 833 sizeof(struct resource) * (memno - next)); 834 hose->mem_resources[--memno].flags = 0; 835 } 836 } 837 838 /* Decide whether to display the domain number in /proc */ 839 int pci_proc_domain(struct pci_bus *bus) 840 { 841 struct pci_controller *hose = pci_bus_to_host(bus); 842 843 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS)) 844 return 0; 845 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0) 846 return hose->global_number != 0; 847 return 1; 848 } 849 850 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 851 struct resource *res) 852 { 853 resource_size_t offset = 0, mask = (resource_size_t)-1; 854 struct pci_controller *hose = pci_bus_to_host(dev->bus); 855 856 if (!hose) 857 return; 858 if (res->flags & IORESOURCE_IO) { 859 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 860 mask = 0xffffffffu; 861 } else if (res->flags & IORESOURCE_MEM) 862 offset = hose->pci_mem_offset; 863 864 region->start = (res->start - offset) & mask; 865 region->end = (res->end - offset) & mask; 866 } 867 EXPORT_SYMBOL(pcibios_resource_to_bus); 868 869 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 870 struct pci_bus_region *region) 871 { 872 resource_size_t offset = 0, mask = (resource_size_t)-1; 873 struct pci_controller *hose = pci_bus_to_host(dev->bus); 874 875 if (!hose) 876 return; 877 if (res->flags & IORESOURCE_IO) { 878 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 879 mask = 0xffffffffu; 880 } else if (res->flags & IORESOURCE_MEM) 881 offset = hose->pci_mem_offset; 882 res->start = (region->start + offset) & mask; 883 res->end = (region->end + offset) & mask; 884 } 885 EXPORT_SYMBOL(pcibios_bus_to_resource); 886 887 /* Fixup a bus resource into a linux resource */ 888 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) 889 { 890 struct pci_controller *hose = pci_bus_to_host(dev->bus); 891 resource_size_t offset = 0, mask = (resource_size_t)-1; 892 893 if (res->flags & IORESOURCE_IO) { 894 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 895 mask = 0xffffffffu; 896 } else if (res->flags & IORESOURCE_MEM) 897 offset = hose->pci_mem_offset; 898 899 res->start = (res->start + offset) & mask; 900 res->end = (res->end + offset) & mask; 901 } 902 903 904 /* This header fixup will do the resource fixup for all devices as they are 905 * probed, but not for bridge ranges 906 */ 907 static void __devinit pcibios_fixup_resources(struct pci_dev *dev) 908 { 909 struct pci_controller *hose = pci_bus_to_host(dev->bus); 910 int i; 911 912 if (!hose) { 913 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 914 pci_name(dev)); 915 return; 916 } 917 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 918 struct resource *res = dev->resource + i; 919 if (!res->flags) 920 continue; 921 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't 922 * consider 0 as an unassigned BAR value. It's technically 923 * a valid value, but linux doesn't like it... so when we can 924 * re-assign things, we do so, but if we can't, we keep it 925 * around and hope for the best... 926 */ 927 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 928 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", 929 pci_name(dev), i, 930 (unsigned long long)res->start, 931 (unsigned long long)res->end, 932 (unsigned int)res->flags); 933 res->end -= res->start; 934 res->start = 0; 935 res->flags |= IORESOURCE_UNSET; 936 continue; 937 } 938 939 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", 940 pci_name(dev), i, 941 (unsigned long long)res->start,\ 942 (unsigned long long)res->end, 943 (unsigned int)res->flags); 944 945 fixup_resource(res, dev); 946 947 pr_debug("PCI:%s %016llx-%016llx\n", 948 pci_name(dev), 949 (unsigned long long)res->start, 950 (unsigned long long)res->end); 951 } 952 953 /* Call machine specific resource fixup */ 954 if (ppc_md.pcibios_fixup_resources) 955 ppc_md.pcibios_fixup_resources(dev); 956 } 957 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 958 959 /* This function tries to figure out if a bridge resource has been initialized 960 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 961 * things go more smoothly when it gets it right. It should covers cases such 962 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 963 */ 964 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 965 struct resource *res) 966 { 967 struct pci_controller *hose = pci_bus_to_host(bus); 968 struct pci_dev *dev = bus->self; 969 resource_size_t offset; 970 u16 command; 971 int i; 972 973 /* We don't do anything if PCI_PROBE_ONLY is set */ 974 if (ppc_pci_flags & PPC_PCI_PROBE_ONLY) 975 return 0; 976 977 /* Job is a bit different between memory and IO */ 978 if (res->flags & IORESOURCE_MEM) { 979 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been 980 * initialized by somebody 981 */ 982 if (res->start != hose->pci_mem_offset) 983 return 0; 984 985 /* The BAR is 0, let's check if memory decoding is enabled on 986 * the bridge. If not, we consider it unassigned 987 */ 988 pci_read_config_word(dev, PCI_COMMAND, &command); 989 if ((command & PCI_COMMAND_MEMORY) == 0) 990 return 1; 991 992 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 993 * resources covers that starting address (0 then it's good enough for 994 * us for memory 995 */ 996 for (i = 0; i < 3; i++) { 997 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 998 hose->mem_resources[i].start == hose->pci_mem_offset) 999 return 0; 1000 } 1001 1002 /* Well, it starts at 0 and we know it will collide so we may as 1003 * well consider it as unassigned. That covers the Apple case. 1004 */ 1005 return 1; 1006 } else { 1007 /* If the BAR is non-0, then we consider it assigned */ 1008 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1009 if (((res->start - offset) & 0xfffffffful) != 0) 1010 return 0; 1011 1012 /* Here, we are a bit different than memory as typically IO space 1013 * starting at low addresses -is- valid. What we do instead if that 1014 * we consider as unassigned anything that doesn't have IO enabled 1015 * in the PCI command register, and that's it. 1016 */ 1017 pci_read_config_word(dev, PCI_COMMAND, &command); 1018 if (command & PCI_COMMAND_IO) 1019 return 0; 1020 1021 /* It's starting at 0 and IO is disabled in the bridge, consider 1022 * it unassigned 1023 */ 1024 return 1; 1025 } 1026 } 1027 1028 /* Fixup resources of a PCI<->PCI bridge */ 1029 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus) 1030 { 1031 struct resource *res; 1032 int i; 1033 1034 struct pci_dev *dev = bus->self; 1035 1036 pci_bus_for_each_resource(bus, res, i) { 1037 if (!res || !res->flags) 1038 continue; 1039 if (i >= 3 && bus->self->transparent) 1040 continue; 1041 1042 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", 1043 pci_name(dev), i, 1044 (unsigned long long)res->start,\ 1045 (unsigned long long)res->end, 1046 (unsigned int)res->flags); 1047 1048 /* Perform fixup */ 1049 fixup_resource(res, dev); 1050 1051 /* Try to detect uninitialized P2P bridge resources, 1052 * and clear them out so they get re-assigned later 1053 */ 1054 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1055 res->flags = 0; 1056 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1057 } else { 1058 1059 pr_debug("PCI:%s %016llx-%016llx\n", 1060 pci_name(dev), 1061 (unsigned long long)res->start, 1062 (unsigned long long)res->end); 1063 } 1064 } 1065 } 1066 1067 void __devinit pcibios_setup_bus_self(struct pci_bus *bus) 1068 { 1069 /* Fix up the bus resources for P2P bridges */ 1070 if (bus->self != NULL) 1071 pcibios_fixup_bridge(bus); 1072 1073 /* Platform specific bus fixups. This is currently only used 1074 * by fsl_pci and I'm hoping to get rid of it at some point 1075 */ 1076 if (ppc_md.pcibios_fixup_bus) 1077 ppc_md.pcibios_fixup_bus(bus); 1078 1079 /* Setup bus DMA mappings */ 1080 if (ppc_md.pci_dma_bus_setup) 1081 ppc_md.pci_dma_bus_setup(bus); 1082 } 1083 1084 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus) 1085 { 1086 struct pci_dev *dev; 1087 1088 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1089 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1090 1091 list_for_each_entry(dev, &bus->devices, bus_list) { 1092 struct dev_archdata *sd = &dev->dev.archdata; 1093 1094 /* Cardbus can call us to add new devices to a bus, so ignore 1095 * those who are already fully discovered 1096 */ 1097 if (dev->is_added) 1098 continue; 1099 1100 /* Setup OF node pointer in archdata */ 1101 sd->of_node = pci_device_to_OF_node(dev); 1102 1103 /* Fixup NUMA node as it may not be setup yet by the generic 1104 * code and is needed by the DMA init 1105 */ 1106 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1107 1108 /* Hook up default DMA ops */ 1109 sd->dma_ops = pci_dma_ops; 1110 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1111 1112 /* Additional platform DMA/iommu setup */ 1113 if (ppc_md.pci_dma_dev_setup) 1114 ppc_md.pci_dma_dev_setup(dev); 1115 1116 /* Read default IRQs and fixup if necessary */ 1117 pci_read_irq_line(dev); 1118 if (ppc_md.pci_irq_fixup) 1119 ppc_md.pci_irq_fixup(dev); 1120 } 1121 } 1122 1123 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 1124 { 1125 /* When called from the generic PCI probe, read PCI<->PCI bridge 1126 * bases. This is -not- called when generating the PCI tree from 1127 * the OF device-tree. 1128 */ 1129 if (bus->self != NULL) 1130 pci_read_bridge_bases(bus); 1131 1132 /* Now fixup the bus bus */ 1133 pcibios_setup_bus_self(bus); 1134 1135 /* Now fixup devices on that bus */ 1136 pcibios_setup_bus_devices(bus); 1137 } 1138 EXPORT_SYMBOL(pcibios_fixup_bus); 1139 1140 void __devinit pci_fixup_cardbus(struct pci_bus *bus) 1141 { 1142 /* Now fixup devices on that bus */ 1143 pcibios_setup_bus_devices(bus); 1144 } 1145 1146 1147 static int skip_isa_ioresource_align(struct pci_dev *dev) 1148 { 1149 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) && 1150 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1151 return 1; 1152 return 0; 1153 } 1154 1155 /* 1156 * We need to avoid collisions with `mirrored' VGA ports 1157 * and other strange ISA hardware, so we always want the 1158 * addresses to be allocated in the 0x000-0x0ff region 1159 * modulo 0x400. 1160 * 1161 * Why? Because some silly external IO cards only decode 1162 * the low 10 bits of the IO address. The 0x00-0xff region 1163 * is reserved for motherboard devices that decode all 16 1164 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1165 * but we want to try to avoid allocating at 0x2900-0x2bff 1166 * which might have be mirrored at 0x0100-0x03ff.. 1167 */ 1168 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1169 resource_size_t size, resource_size_t align) 1170 { 1171 struct pci_dev *dev = data; 1172 resource_size_t start = res->start; 1173 1174 if (res->flags & IORESOURCE_IO) { 1175 if (skip_isa_ioresource_align(dev)) 1176 return start; 1177 if (start & 0x300) 1178 start = (start + 0x3ff) & ~0x3ff; 1179 } 1180 1181 return start; 1182 } 1183 EXPORT_SYMBOL(pcibios_align_resource); 1184 1185 /* 1186 * Reparent resource children of pr that conflict with res 1187 * under res, and make res replace those children. 1188 */ 1189 static int reparent_resources(struct resource *parent, 1190 struct resource *res) 1191 { 1192 struct resource *p, **pp; 1193 struct resource **firstpp = NULL; 1194 1195 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1196 if (p->end < res->start) 1197 continue; 1198 if (res->end < p->start) 1199 break; 1200 if (p->start < res->start || p->end > res->end) 1201 return -1; /* not completely contained */ 1202 if (firstpp == NULL) 1203 firstpp = pp; 1204 } 1205 if (firstpp == NULL) 1206 return -1; /* didn't find any conflicting entries? */ 1207 res->parent = parent; 1208 res->child = *firstpp; 1209 res->sibling = *pp; 1210 *firstpp = res; 1211 *pp = NULL; 1212 for (p = res->child; p != NULL; p = p->sibling) { 1213 p->parent = res; 1214 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1215 p->name, 1216 (unsigned long long)p->start, 1217 (unsigned long long)p->end, res->name); 1218 } 1219 return 0; 1220 } 1221 1222 /* 1223 * Handle resources of PCI devices. If the world were perfect, we could 1224 * just allocate all the resource regions and do nothing more. It isn't. 1225 * On the other hand, we cannot just re-allocate all devices, as it would 1226 * require us to know lots of host bridge internals. So we attempt to 1227 * keep as much of the original configuration as possible, but tweak it 1228 * when it's found to be wrong. 1229 * 1230 * Known BIOS problems we have to work around: 1231 * - I/O or memory regions not configured 1232 * - regions configured, but not enabled in the command register 1233 * - bogus I/O addresses above 64K used 1234 * - expansion ROMs left enabled (this may sound harmless, but given 1235 * the fact the PCI specs explicitly allow address decoders to be 1236 * shared between expansion ROMs and other resource regions, it's 1237 * at least dangerous) 1238 * 1239 * Our solution: 1240 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1241 * This gives us fixed barriers on where we can allocate. 1242 * (2) Allocate resources for all enabled devices. If there is 1243 * a collision, just mark the resource as unallocated. Also 1244 * disable expansion ROMs during this step. 1245 * (3) Try to allocate resources for disabled devices. If the 1246 * resources were assigned correctly, everything goes well, 1247 * if they weren't, they won't disturb allocation of other 1248 * resources. 1249 * (4) Assign new addresses to resources which were either 1250 * not configured at all or misconfigured. If explicitly 1251 * requested by the user, configure expansion ROM address 1252 * as well. 1253 */ 1254 1255 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1256 { 1257 struct pci_bus *b; 1258 int i; 1259 struct resource *res, *pr; 1260 1261 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1262 pci_domain_nr(bus), bus->number); 1263 1264 pci_bus_for_each_resource(bus, res, i) { 1265 if (!res || !res->flags || res->start > res->end || res->parent) 1266 continue; 1267 if (bus->parent == NULL) 1268 pr = (res->flags & IORESOURCE_IO) ? 1269 &ioport_resource : &iomem_resource; 1270 else { 1271 /* Don't bother with non-root busses when 1272 * re-assigning all resources. We clear the 1273 * resource flags as if they were colliding 1274 * and as such ensure proper re-allocation 1275 * later. 1276 */ 1277 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) 1278 goto clear_resource; 1279 pr = pci_find_parent_resource(bus->self, res); 1280 if (pr == res) { 1281 /* this happens when the generic PCI 1282 * code (wrongly) decides that this 1283 * bridge is transparent -- paulus 1284 */ 1285 continue; 1286 } 1287 } 1288 1289 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1290 "[0x%x], parent %p (%s)\n", 1291 bus->self ? pci_name(bus->self) : "PHB", 1292 bus->number, i, 1293 (unsigned long long)res->start, 1294 (unsigned long long)res->end, 1295 (unsigned int)res->flags, 1296 pr, (pr && pr->name) ? pr->name : "nil"); 1297 1298 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1299 if (request_resource(pr, res) == 0) 1300 continue; 1301 /* 1302 * Must be a conflict with an existing entry. 1303 * Move that entry (or entries) under the 1304 * bridge resource and try again. 1305 */ 1306 if (reparent_resources(pr, res) == 0) 1307 continue; 1308 } 1309 printk(KERN_WARNING "PCI: Cannot allocate resource region " 1310 "%d of PCI bridge %d, will remap\n", i, bus->number); 1311 clear_resource: 1312 res->flags = 0; 1313 } 1314 1315 list_for_each_entry(b, &bus->children, node) 1316 pcibios_allocate_bus_resources(b); 1317 } 1318 1319 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) 1320 { 1321 struct resource *pr, *r = &dev->resource[idx]; 1322 1323 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1324 pci_name(dev), idx, 1325 (unsigned long long)r->start, 1326 (unsigned long long)r->end, 1327 (unsigned int)r->flags); 1328 1329 pr = pci_find_parent_resource(dev, r); 1330 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1331 request_resource(pr, r) < 0) { 1332 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1333 " of device %s, will remap\n", idx, pci_name(dev)); 1334 if (pr) 1335 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1336 pr, 1337 (unsigned long long)pr->start, 1338 (unsigned long long)pr->end, 1339 (unsigned int)pr->flags); 1340 /* We'll assign a new address later */ 1341 r->flags |= IORESOURCE_UNSET; 1342 r->end -= r->start; 1343 r->start = 0; 1344 } 1345 } 1346 1347 static void __init pcibios_allocate_resources(int pass) 1348 { 1349 struct pci_dev *dev = NULL; 1350 int idx, disabled; 1351 u16 command; 1352 struct resource *r; 1353 1354 for_each_pci_dev(dev) { 1355 pci_read_config_word(dev, PCI_COMMAND, &command); 1356 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1357 r = &dev->resource[idx]; 1358 if (r->parent) /* Already allocated */ 1359 continue; 1360 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1361 continue; /* Not assigned at all */ 1362 /* We only allocate ROMs on pass 1 just in case they 1363 * have been screwed up by firmware 1364 */ 1365 if (idx == PCI_ROM_RESOURCE ) 1366 disabled = 1; 1367 if (r->flags & IORESOURCE_IO) 1368 disabled = !(command & PCI_COMMAND_IO); 1369 else 1370 disabled = !(command & PCI_COMMAND_MEMORY); 1371 if (pass == disabled) 1372 alloc_resource(dev, idx); 1373 } 1374 if (pass) 1375 continue; 1376 r = &dev->resource[PCI_ROM_RESOURCE]; 1377 if (r->flags) { 1378 /* Turn the ROM off, leave the resource region, 1379 * but keep it unregistered. 1380 */ 1381 u32 reg; 1382 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1383 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1384 pr_debug("PCI: Switching off ROM of %s\n", 1385 pci_name(dev)); 1386 r->flags &= ~IORESOURCE_ROM_ENABLE; 1387 pci_write_config_dword(dev, dev->rom_base_reg, 1388 reg & ~PCI_ROM_ADDRESS_ENABLE); 1389 } 1390 } 1391 } 1392 } 1393 1394 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1395 { 1396 struct pci_controller *hose = pci_bus_to_host(bus); 1397 resource_size_t offset; 1398 struct resource *res, *pres; 1399 int i; 1400 1401 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1402 1403 /* Check for IO */ 1404 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1405 goto no_io; 1406 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1407 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1408 BUG_ON(res == NULL); 1409 res->name = "Legacy IO"; 1410 res->flags = IORESOURCE_IO; 1411 res->start = offset; 1412 res->end = (offset + 0xfff) & 0xfffffffful; 1413 pr_debug("Candidate legacy IO: %pR\n", res); 1414 if (request_resource(&hose->io_resource, res)) { 1415 printk(KERN_DEBUG 1416 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1417 pci_domain_nr(bus), bus->number, res); 1418 kfree(res); 1419 } 1420 1421 no_io: 1422 /* Check for memory */ 1423 offset = hose->pci_mem_offset; 1424 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); 1425 for (i = 0; i < 3; i++) { 1426 pres = &hose->mem_resources[i]; 1427 if (!(pres->flags & IORESOURCE_MEM)) 1428 continue; 1429 pr_debug("hose mem res: %pR\n", pres); 1430 if ((pres->start - offset) <= 0xa0000 && 1431 (pres->end - offset) >= 0xbffff) 1432 break; 1433 } 1434 if (i >= 3) 1435 return; 1436 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1437 BUG_ON(res == NULL); 1438 res->name = "Legacy VGA memory"; 1439 res->flags = IORESOURCE_MEM; 1440 res->start = 0xa0000 + offset; 1441 res->end = 0xbffff + offset; 1442 pr_debug("Candidate VGA memory: %pR\n", res); 1443 if (request_resource(pres, res)) { 1444 printk(KERN_DEBUG 1445 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1446 pci_domain_nr(bus), bus->number, res); 1447 kfree(res); 1448 } 1449 } 1450 1451 void __init pcibios_resource_survey(void) 1452 { 1453 struct pci_bus *b; 1454 1455 /* Allocate and assign resources. If we re-assign everything, then 1456 * we skip the allocate phase 1457 */ 1458 list_for_each_entry(b, &pci_root_buses, node) 1459 pcibios_allocate_bus_resources(b); 1460 1461 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { 1462 pcibios_allocate_resources(0); 1463 pcibios_allocate_resources(1); 1464 } 1465 1466 /* Before we start assigning unassigned resource, we try to reserve 1467 * the low IO area and the VGA memory area if they intersect the 1468 * bus available resources to avoid allocating things on top of them 1469 */ 1470 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1471 list_for_each_entry(b, &pci_root_buses, node) 1472 pcibios_reserve_legacy_regions(b); 1473 } 1474 1475 /* Now, if the platform didn't decide to blindly trust the firmware, 1476 * we proceed to assigning things that were left unassigned 1477 */ 1478 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1479 pr_debug("PCI: Assigning unassigned resources...\n"); 1480 pci_assign_unassigned_resources(); 1481 } 1482 1483 /* Call machine dependent fixup */ 1484 if (ppc_md.pcibios_fixup) 1485 ppc_md.pcibios_fixup(); 1486 } 1487 1488 #ifdef CONFIG_HOTPLUG 1489 1490 /* This is used by the PCI hotplug driver to allocate resource 1491 * of newly plugged busses. We can try to consolidate with the 1492 * rest of the code later, for now, keep it as-is as our main 1493 * resource allocation function doesn't deal with sub-trees yet. 1494 */ 1495 void pcibios_claim_one_bus(struct pci_bus *bus) 1496 { 1497 struct pci_dev *dev; 1498 struct pci_bus *child_bus; 1499 1500 list_for_each_entry(dev, &bus->devices, bus_list) { 1501 int i; 1502 1503 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1504 struct resource *r = &dev->resource[i]; 1505 1506 if (r->parent || !r->start || !r->flags) 1507 continue; 1508 1509 pr_debug("PCI: Claiming %s: " 1510 "Resource %d: %016llx..%016llx [%x]\n", 1511 pci_name(dev), i, 1512 (unsigned long long)r->start, 1513 (unsigned long long)r->end, 1514 (unsigned int)r->flags); 1515 1516 pci_claim_resource(dev, i); 1517 } 1518 } 1519 1520 list_for_each_entry(child_bus, &bus->children, node) 1521 pcibios_claim_one_bus(child_bus); 1522 } 1523 1524 1525 /* pcibios_finish_adding_to_bus 1526 * 1527 * This is to be called by the hotplug code after devices have been 1528 * added to a bus, this include calling it for a PHB that is just 1529 * being added 1530 */ 1531 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1532 { 1533 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1534 pci_domain_nr(bus), bus->number); 1535 1536 /* Allocate bus and devices resources */ 1537 pcibios_allocate_bus_resources(bus); 1538 pcibios_claim_one_bus(bus); 1539 1540 /* Add new devices to global lists. Register in proc, sysfs. */ 1541 pci_bus_add_devices(bus); 1542 1543 /* Fixup EEH */ 1544 eeh_add_device_tree_late(bus); 1545 } 1546 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1547 1548 #endif /* CONFIG_HOTPLUG */ 1549 1550 int pcibios_enable_device(struct pci_dev *dev, int mask) 1551 { 1552 if (ppc_md.pcibios_enable_device_hook) 1553 if (ppc_md.pcibios_enable_device_hook(dev)) 1554 return -EINVAL; 1555 1556 return pci_enable_resources(dev, mask); 1557 } 1558 1559 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) 1560 { 1561 struct pci_bus *bus = hose->bus; 1562 struct resource *res; 1563 int i; 1564 1565 /* Hookup PHB IO resource */ 1566 bus->resource[0] = res = &hose->io_resource; 1567 1568 if (!res->flags) { 1569 printk(KERN_WARNING "PCI: I/O resource not set for host" 1570 " bridge %s (domain %d)\n", 1571 hose->dn->full_name, hose->global_number); 1572 #ifdef CONFIG_PPC32 1573 /* Workaround for lack of IO resource only on 32-bit */ 1574 res->start = (unsigned long)hose->io_base_virt - isa_io_base; 1575 res->end = res->start + IO_SPACE_LIMIT; 1576 res->flags = IORESOURCE_IO; 1577 #endif /* CONFIG_PPC32 */ 1578 } 1579 1580 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", 1581 (unsigned long long)res->start, 1582 (unsigned long long)res->end, 1583 (unsigned long)res->flags); 1584 1585 /* Hookup PHB Memory resources */ 1586 for (i = 0; i < 3; ++i) { 1587 res = &hose->mem_resources[i]; 1588 if (!res->flags) { 1589 if (i > 0) 1590 continue; 1591 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1592 "host bridge %s (domain %d)\n", 1593 hose->dn->full_name, hose->global_number); 1594 #ifdef CONFIG_PPC32 1595 /* Workaround for lack of MEM resource only on 32-bit */ 1596 res->start = hose->pci_mem_offset; 1597 res->end = (resource_size_t)-1LL; 1598 res->flags = IORESOURCE_MEM; 1599 #endif /* CONFIG_PPC32 */ 1600 } 1601 bus->resource[i+1] = res; 1602 1603 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, 1604 (unsigned long long)res->start, 1605 (unsigned long long)res->end, 1606 (unsigned long)res->flags); 1607 } 1608 1609 pr_debug("PCI: PHB MEM offset = %016llx\n", 1610 (unsigned long long)hose->pci_mem_offset); 1611 pr_debug("PCI: PHB IO offset = %08lx\n", 1612 (unsigned long)hose->io_base_virt - _IO_BASE); 1613 1614 } 1615 1616 /* 1617 * Null PCI config access functions, for the case when we can't 1618 * find a hose. 1619 */ 1620 #define NULL_PCI_OP(rw, size, type) \ 1621 static int \ 1622 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1623 { \ 1624 return PCIBIOS_DEVICE_NOT_FOUND; \ 1625 } 1626 1627 static int 1628 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1629 int len, u32 *val) 1630 { 1631 return PCIBIOS_DEVICE_NOT_FOUND; 1632 } 1633 1634 static int 1635 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1636 int len, u32 val) 1637 { 1638 return PCIBIOS_DEVICE_NOT_FOUND; 1639 } 1640 1641 static struct pci_ops null_pci_ops = 1642 { 1643 .read = null_read_config, 1644 .write = null_write_config, 1645 }; 1646 1647 /* 1648 * These functions are used early on before PCI scanning is done 1649 * and all of the pci_dev and pci_bus structures have been created. 1650 */ 1651 static struct pci_bus * 1652 fake_pci_bus(struct pci_controller *hose, int busnr) 1653 { 1654 static struct pci_bus bus; 1655 1656 if (hose == 0) { 1657 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1658 } 1659 bus.number = busnr; 1660 bus.sysdata = hose; 1661 bus.ops = hose? hose->ops: &null_pci_ops; 1662 return &bus; 1663 } 1664 1665 #define EARLY_PCI_OP(rw, size, type) \ 1666 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1667 int devfn, int offset, type value) \ 1668 { \ 1669 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1670 devfn, offset, value); \ 1671 } 1672 1673 EARLY_PCI_OP(read, byte, u8 *) 1674 EARLY_PCI_OP(read, word, u16 *) 1675 EARLY_PCI_OP(read, dword, u32 *) 1676 EARLY_PCI_OP(write, byte, u8) 1677 EARLY_PCI_OP(write, word, u16) 1678 EARLY_PCI_OP(write, dword, u32) 1679 1680 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1681 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1682 int cap) 1683 { 1684 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1685 } 1686 1687 /** 1688 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1689 * @hose: Pointer to the PCI host controller instance structure 1690 * @sysdata: value to use for sysdata pointer. ppc32 and ppc64 differ here 1691 * 1692 * Note: the 'data' pointer is a temporary measure. As 32 and 64 bit 1693 * pci code gets merged, this parameter should become unnecessary because 1694 * both will use the same value. 1695 */ 1696 void __devinit pcibios_scan_phb(struct pci_controller *hose, void *sysdata) 1697 { 1698 struct pci_bus *bus; 1699 struct device_node *node = hose->dn; 1700 int mode; 1701 1702 pr_debug("PCI: Scanning PHB %s\n", 1703 node ? node->full_name : "<NO NAME>"); 1704 1705 /* Create an empty bus for the toplevel */ 1706 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, 1707 sysdata); 1708 if (bus == NULL) { 1709 pr_err("Failed to create bus for PCI domain %04x\n", 1710 hose->global_number); 1711 return; 1712 } 1713 bus->secondary = hose->first_busno; 1714 hose->bus = bus; 1715 1716 /* Get some IO space for the new PHB */ 1717 pcibios_setup_phb_io_space(hose); 1718 1719 /* Wire up PHB bus resources */ 1720 pcibios_setup_phb_resources(hose); 1721 1722 /* Get probe mode and perform scan */ 1723 mode = PCI_PROBE_NORMAL; 1724 if (node && ppc_md.pci_probe_mode) 1725 mode = ppc_md.pci_probe_mode(bus); 1726 pr_debug(" probe mode: %d\n", mode); 1727 if (mode == PCI_PROBE_DEVTREE) { 1728 bus->subordinate = hose->last_busno; 1729 of_scan_bus(node, bus); 1730 } 1731 1732 if (mode == PCI_PROBE_NORMAL) 1733 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); 1734 } 1735