1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/export.h> 25 #include <linux/of_address.h> 26 #include <linux/of_pci.h> 27 #include <linux/mm.h> 28 #include <linux/list.h> 29 #include <linux/syscalls.h> 30 #include <linux/irq.h> 31 #include <linux/vmalloc.h> 32 #include <linux/slab.h> 33 #include <linux/vgaarb.h> 34 35 #include <asm/processor.h> 36 #include <asm/io.h> 37 #include <asm/prom.h> 38 #include <asm/pci-bridge.h> 39 #include <asm/byteorder.h> 40 #include <asm/machdep.h> 41 #include <asm/ppc-pci.h> 42 #include <asm/eeh.h> 43 44 static DEFINE_SPINLOCK(hose_spinlock); 45 LIST_HEAD(hose_list); 46 47 /* XXX kill that some day ... */ 48 static int global_phb_number; /* Global phb counter */ 49 50 /* ISA Memory physical address */ 51 resource_size_t isa_mem_base; 52 53 54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 55 56 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 57 { 58 pci_dma_ops = dma_ops; 59 } 60 61 struct dma_map_ops *get_pci_dma_ops(void) 62 { 63 return pci_dma_ops; 64 } 65 EXPORT_SYMBOL(get_pci_dma_ops); 66 67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 68 { 69 struct pci_controller *phb; 70 71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 72 if (phb == NULL) 73 return NULL; 74 spin_lock(&hose_spinlock); 75 phb->global_number = global_phb_number++; 76 list_add_tail(&phb->list_node, &hose_list); 77 spin_unlock(&hose_spinlock); 78 phb->dn = dev; 79 phb->is_dynamic = mem_init_done; 80 #ifdef CONFIG_PPC64 81 if (dev) { 82 int nid = of_node_to_nid(dev); 83 84 if (nid < 0 || !node_online(nid)) 85 nid = -1; 86 87 PHB_SET_NODE(phb, nid); 88 } 89 #endif 90 return phb; 91 } 92 93 void pcibios_free_controller(struct pci_controller *phb) 94 { 95 spin_lock(&hose_spinlock); 96 list_del(&phb->list_node); 97 spin_unlock(&hose_spinlock); 98 99 if (phb->is_dynamic) 100 kfree(phb); 101 } 102 103 /* 104 * The function is used to return the minimal alignment 105 * for memory or I/O windows of the associated P2P bridge. 106 * By default, 4KiB alignment for I/O windows and 1MiB for 107 * memory windows. 108 */ 109 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 110 unsigned long type) 111 { 112 if (ppc_md.pcibios_window_alignment) 113 return ppc_md.pcibios_window_alignment(bus, type); 114 115 /* 116 * PCI core will figure out the default 117 * alignment: 4KiB for I/O and 1MiB for 118 * memory window. 119 */ 120 return 1; 121 } 122 123 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 124 { 125 #ifdef CONFIG_PPC64 126 return hose->pci_io_size; 127 #else 128 return resource_size(&hose->io_resource); 129 #endif 130 } 131 132 int pcibios_vaddr_is_ioport(void __iomem *address) 133 { 134 int ret = 0; 135 struct pci_controller *hose; 136 resource_size_t size; 137 138 spin_lock(&hose_spinlock); 139 list_for_each_entry(hose, &hose_list, list_node) { 140 size = pcibios_io_size(hose); 141 if (address >= hose->io_base_virt && 142 address < (hose->io_base_virt + size)) { 143 ret = 1; 144 break; 145 } 146 } 147 spin_unlock(&hose_spinlock); 148 return ret; 149 } 150 151 unsigned long pci_address_to_pio(phys_addr_t address) 152 { 153 struct pci_controller *hose; 154 resource_size_t size; 155 unsigned long ret = ~0; 156 157 spin_lock(&hose_spinlock); 158 list_for_each_entry(hose, &hose_list, list_node) { 159 size = pcibios_io_size(hose); 160 if (address >= hose->io_base_phys && 161 address < (hose->io_base_phys + size)) { 162 unsigned long base = 163 (unsigned long)hose->io_base_virt - _IO_BASE; 164 ret = base + (address - hose->io_base_phys); 165 break; 166 } 167 } 168 spin_unlock(&hose_spinlock); 169 170 return ret; 171 } 172 EXPORT_SYMBOL_GPL(pci_address_to_pio); 173 174 /* 175 * Return the domain number for this bus. 176 */ 177 int pci_domain_nr(struct pci_bus *bus) 178 { 179 struct pci_controller *hose = pci_bus_to_host(bus); 180 181 return hose->global_number; 182 } 183 EXPORT_SYMBOL(pci_domain_nr); 184 185 /* This routine is meant to be used early during boot, when the 186 * PCI bus numbers have not yet been assigned, and you need to 187 * issue PCI config cycles to an OF device. 188 * It could also be used to "fix" RTAS config cycles if you want 189 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 190 * config cycles. 191 */ 192 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 193 { 194 while(node) { 195 struct pci_controller *hose, *tmp; 196 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 197 if (hose->dn == node) 198 return hose; 199 node = node->parent; 200 } 201 return NULL; 202 } 203 204 static ssize_t pci_show_devspec(struct device *dev, 205 struct device_attribute *attr, char *buf) 206 { 207 struct pci_dev *pdev; 208 struct device_node *np; 209 210 pdev = to_pci_dev (dev); 211 np = pci_device_to_OF_node(pdev); 212 if (np == NULL || np->full_name == NULL) 213 return 0; 214 return sprintf(buf, "%s", np->full_name); 215 } 216 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 217 218 /* Add sysfs properties */ 219 int pcibios_add_platform_entries(struct pci_dev *pdev) 220 { 221 return device_create_file(&pdev->dev, &dev_attr_devspec); 222 } 223 224 /* 225 * Reads the interrupt pin to determine if interrupt is use by card. 226 * If the interrupt is used, then gets the interrupt line from the 227 * openfirmware and sets it in the pci_dev and pci_config line. 228 */ 229 static int pci_read_irq_line(struct pci_dev *pci_dev) 230 { 231 struct of_irq oirq; 232 unsigned int virq; 233 234 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 235 236 #ifdef DEBUG 237 memset(&oirq, 0xff, sizeof(oirq)); 238 #endif 239 /* Try to get a mapping from the device-tree */ 240 if (of_irq_map_pci(pci_dev, &oirq)) { 241 u8 line, pin; 242 243 /* If that fails, lets fallback to what is in the config 244 * space and map that through the default controller. We 245 * also set the type to level low since that's what PCI 246 * interrupts are. If your platform does differently, then 247 * either provide a proper interrupt tree or don't use this 248 * function. 249 */ 250 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 251 return -1; 252 if (pin == 0) 253 return -1; 254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 255 line == 0xff || line == 0) { 256 return -1; 257 } 258 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 259 line, pin); 260 261 virq = irq_create_mapping(NULL, line); 262 if (virq != NO_IRQ) 263 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 264 } else { 265 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 266 oirq.size, oirq.specifier[0], oirq.specifier[1], 267 of_node_full_name(oirq.controller)); 268 269 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 270 oirq.size); 271 } 272 if(virq == NO_IRQ) { 273 pr_debug(" Failed to map !\n"); 274 return -1; 275 } 276 277 pr_debug(" Mapped to linux irq %d\n", virq); 278 279 pci_dev->irq = virq; 280 281 return 0; 282 } 283 284 /* 285 * Platform support for /proc/bus/pci/X/Y mmap()s, 286 * modelled on the sparc64 implementation by Dave Miller. 287 * -- paulus. 288 */ 289 290 /* 291 * Adjust vm_pgoff of VMA such that it is the physical page offset 292 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 293 * 294 * Basically, the user finds the base address for his device which he wishes 295 * to mmap. They read the 32-bit value from the config space base register, 296 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 297 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 298 * 299 * Returns negative error code on failure, zero on success. 300 */ 301 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 302 resource_size_t *offset, 303 enum pci_mmap_state mmap_state) 304 { 305 struct pci_controller *hose = pci_bus_to_host(dev->bus); 306 unsigned long io_offset = 0; 307 int i, res_bit; 308 309 if (hose == 0) 310 return NULL; /* should never happen */ 311 312 /* If memory, add on the PCI bridge address offset */ 313 if (mmap_state == pci_mmap_mem) { 314 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 315 *offset += hose->pci_mem_offset; 316 #endif 317 res_bit = IORESOURCE_MEM; 318 } else { 319 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 320 *offset += io_offset; 321 res_bit = IORESOURCE_IO; 322 } 323 324 /* 325 * Check that the offset requested corresponds to one of the 326 * resources of the device. 327 */ 328 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 329 struct resource *rp = &dev->resource[i]; 330 int flags = rp->flags; 331 332 /* treat ROM as memory (should be already) */ 333 if (i == PCI_ROM_RESOURCE) 334 flags |= IORESOURCE_MEM; 335 336 /* Active and same type? */ 337 if ((flags & res_bit) == 0) 338 continue; 339 340 /* In the range of this resource? */ 341 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 342 continue; 343 344 /* found it! construct the final physical address */ 345 if (mmap_state == pci_mmap_io) 346 *offset += hose->io_base_phys - io_offset; 347 return rp; 348 } 349 350 return NULL; 351 } 352 353 /* 354 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 355 * device mapping. 356 */ 357 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 358 pgprot_t protection, 359 enum pci_mmap_state mmap_state, 360 int write_combine) 361 { 362 363 /* Write combine is always 0 on non-memory space mappings. On 364 * memory space, if the user didn't pass 1, we check for a 365 * "prefetchable" resource. This is a bit hackish, but we use 366 * this to workaround the inability of /sysfs to provide a write 367 * combine bit 368 */ 369 if (mmap_state != pci_mmap_mem) 370 write_combine = 0; 371 else if (write_combine == 0) { 372 if (rp->flags & IORESOURCE_PREFETCH) 373 write_combine = 1; 374 } 375 376 /* XXX would be nice to have a way to ask for write-through */ 377 if (write_combine) 378 return pgprot_noncached_wc(protection); 379 else 380 return pgprot_noncached(protection); 381 } 382 383 /* 384 * This one is used by /dev/mem and fbdev who have no clue about the 385 * PCI device, it tries to find the PCI device first and calls the 386 * above routine 387 */ 388 pgprot_t pci_phys_mem_access_prot(struct file *file, 389 unsigned long pfn, 390 unsigned long size, 391 pgprot_t prot) 392 { 393 struct pci_dev *pdev = NULL; 394 struct resource *found = NULL; 395 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 396 int i; 397 398 if (page_is_ram(pfn)) 399 return prot; 400 401 prot = pgprot_noncached(prot); 402 for_each_pci_dev(pdev) { 403 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 404 struct resource *rp = &pdev->resource[i]; 405 int flags = rp->flags; 406 407 /* Active and same type? */ 408 if ((flags & IORESOURCE_MEM) == 0) 409 continue; 410 /* In the range of this resource? */ 411 if (offset < (rp->start & PAGE_MASK) || 412 offset > rp->end) 413 continue; 414 found = rp; 415 break; 416 } 417 if (found) 418 break; 419 } 420 if (found) { 421 if (found->flags & IORESOURCE_PREFETCH) 422 prot = pgprot_noncached_wc(prot); 423 pci_dev_put(pdev); 424 } 425 426 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 427 (unsigned long long)offset, pgprot_val(prot)); 428 429 return prot; 430 } 431 432 433 /* 434 * Perform the actual remap of the pages for a PCI device mapping, as 435 * appropriate for this architecture. The region in the process to map 436 * is described by vm_start and vm_end members of VMA, the base physical 437 * address is found in vm_pgoff. 438 * The pci device structure is provided so that architectures may make mapping 439 * decisions on a per-device or per-bus basis. 440 * 441 * Returns a negative error code on failure, zero on success. 442 */ 443 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 444 enum pci_mmap_state mmap_state, int write_combine) 445 { 446 resource_size_t offset = 447 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 448 struct resource *rp; 449 int ret; 450 451 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 452 if (rp == NULL) 453 return -EINVAL; 454 455 vma->vm_pgoff = offset >> PAGE_SHIFT; 456 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 457 vma->vm_page_prot, 458 mmap_state, write_combine); 459 460 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 461 vma->vm_end - vma->vm_start, vma->vm_page_prot); 462 463 return ret; 464 } 465 466 /* This provides legacy IO read access on a bus */ 467 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 468 { 469 unsigned long offset; 470 struct pci_controller *hose = pci_bus_to_host(bus); 471 struct resource *rp = &hose->io_resource; 472 void __iomem *addr; 473 474 /* Check if port can be supported by that bus. We only check 475 * the ranges of the PHB though, not the bus itself as the rules 476 * for forwarding legacy cycles down bridges are not our problem 477 * here. So if the host bridge supports it, we do it. 478 */ 479 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 480 offset += port; 481 482 if (!(rp->flags & IORESOURCE_IO)) 483 return -ENXIO; 484 if (offset < rp->start || (offset + size) > rp->end) 485 return -ENXIO; 486 addr = hose->io_base_virt + port; 487 488 switch(size) { 489 case 1: 490 *((u8 *)val) = in_8(addr); 491 return 1; 492 case 2: 493 if (port & 1) 494 return -EINVAL; 495 *((u16 *)val) = in_le16(addr); 496 return 2; 497 case 4: 498 if (port & 3) 499 return -EINVAL; 500 *((u32 *)val) = in_le32(addr); 501 return 4; 502 } 503 return -EINVAL; 504 } 505 506 /* This provides legacy IO write access on a bus */ 507 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 508 { 509 unsigned long offset; 510 struct pci_controller *hose = pci_bus_to_host(bus); 511 struct resource *rp = &hose->io_resource; 512 void __iomem *addr; 513 514 /* Check if port can be supported by that bus. We only check 515 * the ranges of the PHB though, not the bus itself as the rules 516 * for forwarding legacy cycles down bridges are not our problem 517 * here. So if the host bridge supports it, we do it. 518 */ 519 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 520 offset += port; 521 522 if (!(rp->flags & IORESOURCE_IO)) 523 return -ENXIO; 524 if (offset < rp->start || (offset + size) > rp->end) 525 return -ENXIO; 526 addr = hose->io_base_virt + port; 527 528 /* WARNING: The generic code is idiotic. It gets passed a pointer 529 * to what can be a 1, 2 or 4 byte quantity and always reads that 530 * as a u32, which means that we have to correct the location of 531 * the data read within those 32 bits for size 1 and 2 532 */ 533 switch(size) { 534 case 1: 535 out_8(addr, val >> 24); 536 return 1; 537 case 2: 538 if (port & 1) 539 return -EINVAL; 540 out_le16(addr, val >> 16); 541 return 2; 542 case 4: 543 if (port & 3) 544 return -EINVAL; 545 out_le32(addr, val); 546 return 4; 547 } 548 return -EINVAL; 549 } 550 551 /* This provides legacy IO or memory mmap access on a bus */ 552 int pci_mmap_legacy_page_range(struct pci_bus *bus, 553 struct vm_area_struct *vma, 554 enum pci_mmap_state mmap_state) 555 { 556 struct pci_controller *hose = pci_bus_to_host(bus); 557 resource_size_t offset = 558 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 559 resource_size_t size = vma->vm_end - vma->vm_start; 560 struct resource *rp; 561 562 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 563 pci_domain_nr(bus), bus->number, 564 mmap_state == pci_mmap_mem ? "MEM" : "IO", 565 (unsigned long long)offset, 566 (unsigned long long)(offset + size - 1)); 567 568 if (mmap_state == pci_mmap_mem) { 569 /* Hack alert ! 570 * 571 * Because X is lame and can fail starting if it gets an error trying 572 * to mmap legacy_mem (instead of just moving on without legacy memory 573 * access) we fake it here by giving it anonymous memory, effectively 574 * behaving just like /dev/zero 575 */ 576 if ((offset + size) > hose->isa_mem_size) { 577 printk(KERN_DEBUG 578 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 579 current->comm, current->pid, pci_domain_nr(bus), bus->number); 580 if (vma->vm_flags & VM_SHARED) 581 return shmem_zero_setup(vma); 582 return 0; 583 } 584 offset += hose->isa_mem_phys; 585 } else { 586 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 587 unsigned long roffset = offset + io_offset; 588 rp = &hose->io_resource; 589 if (!(rp->flags & IORESOURCE_IO)) 590 return -ENXIO; 591 if (roffset < rp->start || (roffset + size) > rp->end) 592 return -ENXIO; 593 offset += hose->io_base_phys; 594 } 595 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 596 597 vma->vm_pgoff = offset >> PAGE_SHIFT; 598 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 599 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 600 vma->vm_end - vma->vm_start, 601 vma->vm_page_prot); 602 } 603 604 void pci_resource_to_user(const struct pci_dev *dev, int bar, 605 const struct resource *rsrc, 606 resource_size_t *start, resource_size_t *end) 607 { 608 struct pci_controller *hose = pci_bus_to_host(dev->bus); 609 resource_size_t offset = 0; 610 611 if (hose == NULL) 612 return; 613 614 if (rsrc->flags & IORESOURCE_IO) 615 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 616 617 /* We pass a fully fixed up address to userland for MMIO instead of 618 * a BAR value because X is lame and expects to be able to use that 619 * to pass to /dev/mem ! 620 * 621 * That means that we'll have potentially 64 bits values where some 622 * userland apps only expect 32 (like X itself since it thinks only 623 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 624 * 32 bits CHRPs :-( 625 * 626 * Hopefully, the sysfs insterface is immune to that gunk. Once X 627 * has been fixed (and the fix spread enough), we can re-enable the 628 * 2 lines below and pass down a BAR value to userland. In that case 629 * we'll also have to re-enable the matching code in 630 * __pci_mmap_make_offset(). 631 * 632 * BenH. 633 */ 634 #if 0 635 else if (rsrc->flags & IORESOURCE_MEM) 636 offset = hose->pci_mem_offset; 637 #endif 638 639 *start = rsrc->start - offset; 640 *end = rsrc->end - offset; 641 } 642 643 /** 644 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 645 * @hose: newly allocated pci_controller to be setup 646 * @dev: device node of the host bridge 647 * @primary: set if primary bus (32 bits only, soon to be deprecated) 648 * 649 * This function will parse the "ranges" property of a PCI host bridge device 650 * node and setup the resource mapping of a pci controller based on its 651 * content. 652 * 653 * Life would be boring if it wasn't for a few issues that we have to deal 654 * with here: 655 * 656 * - We can only cope with one IO space range and up to 3 Memory space 657 * ranges. However, some machines (thanks Apple !) tend to split their 658 * space into lots of small contiguous ranges. So we have to coalesce. 659 * 660 * - We can only cope with all memory ranges having the same offset 661 * between CPU addresses and PCI addresses. Unfortunately, some bridges 662 * are setup for a large 1:1 mapping along with a small "window" which 663 * maps PCI address 0 to some arbitrary high address of the CPU space in 664 * order to give access to the ISA memory hole. 665 * The way out of here that I've chosen for now is to always set the 666 * offset based on the first resource found, then override it if we 667 * have a different offset and the previous was set by an ISA hole. 668 * 669 * - Some busses have IO space not starting at 0, which causes trouble with 670 * the way we do our IO resource renumbering. The code somewhat deals with 671 * it for 64 bits but I would expect problems on 32 bits. 672 * 673 * - Some 32 bits platforms such as 4xx can have physical space larger than 674 * 32 bits so we need to use 64 bits values for the parsing 675 */ 676 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 677 struct device_node *dev, int primary) 678 { 679 const u32 *ranges; 680 int rlen; 681 int pna = of_n_addr_cells(dev); 682 int np = pna + 5; 683 int memno = 0, isa_hole = -1; 684 u32 pci_space; 685 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 686 unsigned long long isa_mb = 0; 687 struct resource *res; 688 689 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 690 dev->full_name, primary ? "(primary)" : ""); 691 692 /* Get ranges property */ 693 ranges = of_get_property(dev, "ranges", &rlen); 694 if (ranges == NULL) 695 return; 696 697 /* Parse it */ 698 while ((rlen -= np * 4) >= 0) { 699 /* Read next ranges element */ 700 pci_space = ranges[0]; 701 pci_addr = of_read_number(ranges + 1, 2); 702 cpu_addr = of_translate_address(dev, ranges + 3); 703 size = of_read_number(ranges + pna + 3, 2); 704 ranges += np; 705 706 /* If we failed translation or got a zero-sized region 707 * (some FW try to feed us with non sensical zero sized regions 708 * such as power3 which look like some kind of attempt at exposing 709 * the VGA memory hole) 710 */ 711 if (cpu_addr == OF_BAD_ADDR || size == 0) 712 continue; 713 714 /* Now consume following elements while they are contiguous */ 715 for (; rlen >= np * sizeof(u32); 716 ranges += np, rlen -= np * 4) { 717 if (ranges[0] != pci_space) 718 break; 719 pci_next = of_read_number(ranges + 1, 2); 720 cpu_next = of_translate_address(dev, ranges + 3); 721 if (pci_next != pci_addr + size || 722 cpu_next != cpu_addr + size) 723 break; 724 size += of_read_number(ranges + pna + 3, 2); 725 } 726 727 /* Act based on address space type */ 728 res = NULL; 729 switch ((pci_space >> 24) & 0x3) { 730 case 1: /* PCI IO space */ 731 printk(KERN_INFO 732 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 733 cpu_addr, cpu_addr + size - 1, pci_addr); 734 735 /* We support only one IO range */ 736 if (hose->pci_io_size) { 737 printk(KERN_INFO 738 " \\--> Skipped (too many) !\n"); 739 continue; 740 } 741 #ifdef CONFIG_PPC32 742 /* On 32 bits, limit I/O space to 16MB */ 743 if (size > 0x01000000) 744 size = 0x01000000; 745 746 /* 32 bits needs to map IOs here */ 747 hose->io_base_virt = ioremap(cpu_addr, size); 748 749 /* Expect trouble if pci_addr is not 0 */ 750 if (primary) 751 isa_io_base = 752 (unsigned long)hose->io_base_virt; 753 #endif /* CONFIG_PPC32 */ 754 /* pci_io_size and io_base_phys always represent IO 755 * space starting at 0 so we factor in pci_addr 756 */ 757 hose->pci_io_size = pci_addr + size; 758 hose->io_base_phys = cpu_addr - pci_addr; 759 760 /* Build resource */ 761 res = &hose->io_resource; 762 res->flags = IORESOURCE_IO; 763 res->start = pci_addr; 764 break; 765 case 2: /* PCI Memory space */ 766 case 3: /* PCI 64 bits Memory space */ 767 printk(KERN_INFO 768 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 769 cpu_addr, cpu_addr + size - 1, pci_addr, 770 (pci_space & 0x40000000) ? "Prefetch" : ""); 771 772 /* We support only 3 memory ranges */ 773 if (memno >= 3) { 774 printk(KERN_INFO 775 " \\--> Skipped (too many) !\n"); 776 continue; 777 } 778 /* Handles ISA memory hole space here */ 779 if (pci_addr == 0) { 780 isa_mb = cpu_addr; 781 isa_hole = memno; 782 if (primary || isa_mem_base == 0) 783 isa_mem_base = cpu_addr; 784 hose->isa_mem_phys = cpu_addr; 785 hose->isa_mem_size = size; 786 } 787 788 /* Build resource */ 789 hose->mem_offset[memno] = cpu_addr - pci_addr; 790 res = &hose->mem_resources[memno++]; 791 res->flags = IORESOURCE_MEM; 792 if (pci_space & 0x40000000) 793 res->flags |= IORESOURCE_PREFETCH; 794 res->start = cpu_addr; 795 break; 796 } 797 if (res != NULL) { 798 res->name = dev->full_name; 799 res->end = res->start + size - 1; 800 res->parent = NULL; 801 res->sibling = NULL; 802 res->child = NULL; 803 } 804 } 805 } 806 807 /* Decide whether to display the domain number in /proc */ 808 int pci_proc_domain(struct pci_bus *bus) 809 { 810 struct pci_controller *hose = pci_bus_to_host(bus); 811 812 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 813 return 0; 814 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 815 return hose->global_number != 0; 816 return 1; 817 } 818 819 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 820 { 821 if (ppc_md.pcibios_root_bridge_prepare) 822 return ppc_md.pcibios_root_bridge_prepare(bridge); 823 824 return 0; 825 } 826 827 /* This header fixup will do the resource fixup for all devices as they are 828 * probed, but not for bridge ranges 829 */ 830 static void pcibios_fixup_resources(struct pci_dev *dev) 831 { 832 struct pci_controller *hose = pci_bus_to_host(dev->bus); 833 int i; 834 835 if (!hose) { 836 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 837 pci_name(dev)); 838 return; 839 } 840 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 841 struct resource *res = dev->resource + i; 842 if (!res->flags) 843 continue; 844 845 /* If we're going to re-assign everything, we mark all resources 846 * as unset (and 0-base them). In addition, we mark BARs starting 847 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 848 * since in that case, we don't want to re-assign anything 849 */ 850 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 851 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 852 /* Only print message if not re-assigning */ 853 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 854 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 855 "is unassigned\n", 856 pci_name(dev), i, 857 (unsigned long long)res->start, 858 (unsigned long long)res->end, 859 (unsigned int)res->flags); 860 res->end -= res->start; 861 res->start = 0; 862 res->flags |= IORESOURCE_UNSET; 863 continue; 864 } 865 866 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", 867 pci_name(dev), i, 868 (unsigned long long)res->start,\ 869 (unsigned long long)res->end, 870 (unsigned int)res->flags); 871 } 872 873 /* Call machine specific resource fixup */ 874 if (ppc_md.pcibios_fixup_resources) 875 ppc_md.pcibios_fixup_resources(dev); 876 } 877 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 878 879 /* This function tries to figure out if a bridge resource has been initialized 880 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 881 * things go more smoothly when it gets it right. It should covers cases such 882 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 883 */ 884 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 885 struct resource *res) 886 { 887 struct pci_controller *hose = pci_bus_to_host(bus); 888 struct pci_dev *dev = bus->self; 889 resource_size_t offset; 890 struct pci_bus_region region; 891 u16 command; 892 int i; 893 894 /* We don't do anything if PCI_PROBE_ONLY is set */ 895 if (pci_has_flag(PCI_PROBE_ONLY)) 896 return 0; 897 898 /* Job is a bit different between memory and IO */ 899 if (res->flags & IORESOURCE_MEM) { 900 pcibios_resource_to_bus(dev, ®ion, res); 901 902 /* If the BAR is non-0 then it's probably been initialized */ 903 if (region.start != 0) 904 return 0; 905 906 /* The BAR is 0, let's check if memory decoding is enabled on 907 * the bridge. If not, we consider it unassigned 908 */ 909 pci_read_config_word(dev, PCI_COMMAND, &command); 910 if ((command & PCI_COMMAND_MEMORY) == 0) 911 return 1; 912 913 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 914 * resources covers that starting address (0 then it's good enough for 915 * us for memory space) 916 */ 917 for (i = 0; i < 3; i++) { 918 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 919 hose->mem_resources[i].start == hose->mem_offset[i]) 920 return 0; 921 } 922 923 /* Well, it starts at 0 and we know it will collide so we may as 924 * well consider it as unassigned. That covers the Apple case. 925 */ 926 return 1; 927 } else { 928 /* If the BAR is non-0, then we consider it assigned */ 929 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 930 if (((res->start - offset) & 0xfffffffful) != 0) 931 return 0; 932 933 /* Here, we are a bit different than memory as typically IO space 934 * starting at low addresses -is- valid. What we do instead if that 935 * we consider as unassigned anything that doesn't have IO enabled 936 * in the PCI command register, and that's it. 937 */ 938 pci_read_config_word(dev, PCI_COMMAND, &command); 939 if (command & PCI_COMMAND_IO) 940 return 0; 941 942 /* It's starting at 0 and IO is disabled in the bridge, consider 943 * it unassigned 944 */ 945 return 1; 946 } 947 } 948 949 /* Fixup resources of a PCI<->PCI bridge */ 950 static void pcibios_fixup_bridge(struct pci_bus *bus) 951 { 952 struct resource *res; 953 int i; 954 955 struct pci_dev *dev = bus->self; 956 957 pci_bus_for_each_resource(bus, res, i) { 958 if (!res || !res->flags) 959 continue; 960 if (i >= 3 && bus->self->transparent) 961 continue; 962 963 /* If we're going to reassign everything, we can 964 * shrink the P2P resource to have size as being 965 * of 0 in order to save space. 966 */ 967 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 968 res->flags |= IORESOURCE_UNSET; 969 res->start = 0; 970 res->end = -1; 971 continue; 972 } 973 974 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", 975 pci_name(dev), i, 976 (unsigned long long)res->start,\ 977 (unsigned long long)res->end, 978 (unsigned int)res->flags); 979 980 /* Try to detect uninitialized P2P bridge resources, 981 * and clear them out so they get re-assigned later 982 */ 983 if (pcibios_uninitialized_bridge_resource(bus, res)) { 984 res->flags = 0; 985 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 986 } 987 } 988 } 989 990 void pcibios_setup_bus_self(struct pci_bus *bus) 991 { 992 /* Fix up the bus resources for P2P bridges */ 993 if (bus->self != NULL) 994 pcibios_fixup_bridge(bus); 995 996 /* Platform specific bus fixups. This is currently only used 997 * by fsl_pci and I'm hoping to get rid of it at some point 998 */ 999 if (ppc_md.pcibios_fixup_bus) 1000 ppc_md.pcibios_fixup_bus(bus); 1001 1002 /* Setup bus DMA mappings */ 1003 if (ppc_md.pci_dma_bus_setup) 1004 ppc_md.pci_dma_bus_setup(bus); 1005 } 1006 1007 void pcibios_setup_device(struct pci_dev *dev) 1008 { 1009 /* Fixup NUMA node as it may not be setup yet by the generic 1010 * code and is needed by the DMA init 1011 */ 1012 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1013 1014 /* Hook up default DMA ops */ 1015 set_dma_ops(&dev->dev, pci_dma_ops); 1016 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1017 1018 /* Additional platform DMA/iommu setup */ 1019 if (ppc_md.pci_dma_dev_setup) 1020 ppc_md.pci_dma_dev_setup(dev); 1021 1022 /* Read default IRQs and fixup if necessary */ 1023 pci_read_irq_line(dev); 1024 if (ppc_md.pci_irq_fixup) 1025 ppc_md.pci_irq_fixup(dev); 1026 } 1027 1028 void pcibios_setup_bus_devices(struct pci_bus *bus) 1029 { 1030 struct pci_dev *dev; 1031 1032 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1033 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1034 1035 list_for_each_entry(dev, &bus->devices, bus_list) { 1036 /* Cardbus can call us to add new devices to a bus, so ignore 1037 * those who are already fully discovered 1038 */ 1039 if (dev->is_added) 1040 continue; 1041 1042 pcibios_setup_device(dev); 1043 } 1044 } 1045 1046 void pcibios_set_master(struct pci_dev *dev) 1047 { 1048 /* No special bus mastering setup handling */ 1049 } 1050 1051 void pcibios_fixup_bus(struct pci_bus *bus) 1052 { 1053 /* When called from the generic PCI probe, read PCI<->PCI bridge 1054 * bases. This is -not- called when generating the PCI tree from 1055 * the OF device-tree. 1056 */ 1057 if (bus->self != NULL) 1058 pci_read_bridge_bases(bus); 1059 1060 /* Now fixup the bus bus */ 1061 pcibios_setup_bus_self(bus); 1062 1063 /* Now fixup devices on that bus */ 1064 pcibios_setup_bus_devices(bus); 1065 } 1066 EXPORT_SYMBOL(pcibios_fixup_bus); 1067 1068 void pci_fixup_cardbus(struct pci_bus *bus) 1069 { 1070 /* Now fixup devices on that bus */ 1071 pcibios_setup_bus_devices(bus); 1072 } 1073 1074 1075 static int skip_isa_ioresource_align(struct pci_dev *dev) 1076 { 1077 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1078 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1079 return 1; 1080 return 0; 1081 } 1082 1083 /* 1084 * We need to avoid collisions with `mirrored' VGA ports 1085 * and other strange ISA hardware, so we always want the 1086 * addresses to be allocated in the 0x000-0x0ff region 1087 * modulo 0x400. 1088 * 1089 * Why? Because some silly external IO cards only decode 1090 * the low 10 bits of the IO address. The 0x00-0xff region 1091 * is reserved for motherboard devices that decode all 16 1092 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1093 * but we want to try to avoid allocating at 0x2900-0x2bff 1094 * which might have be mirrored at 0x0100-0x03ff.. 1095 */ 1096 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1097 resource_size_t size, resource_size_t align) 1098 { 1099 struct pci_dev *dev = data; 1100 resource_size_t start = res->start; 1101 1102 if (res->flags & IORESOURCE_IO) { 1103 if (skip_isa_ioresource_align(dev)) 1104 return start; 1105 if (start & 0x300) 1106 start = (start + 0x3ff) & ~0x3ff; 1107 } 1108 1109 return start; 1110 } 1111 EXPORT_SYMBOL(pcibios_align_resource); 1112 1113 /* 1114 * Reparent resource children of pr that conflict with res 1115 * under res, and make res replace those children. 1116 */ 1117 static int reparent_resources(struct resource *parent, 1118 struct resource *res) 1119 { 1120 struct resource *p, **pp; 1121 struct resource **firstpp = NULL; 1122 1123 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1124 if (p->end < res->start) 1125 continue; 1126 if (res->end < p->start) 1127 break; 1128 if (p->start < res->start || p->end > res->end) 1129 return -1; /* not completely contained */ 1130 if (firstpp == NULL) 1131 firstpp = pp; 1132 } 1133 if (firstpp == NULL) 1134 return -1; /* didn't find any conflicting entries? */ 1135 res->parent = parent; 1136 res->child = *firstpp; 1137 res->sibling = *pp; 1138 *firstpp = res; 1139 *pp = NULL; 1140 for (p = res->child; p != NULL; p = p->sibling) { 1141 p->parent = res; 1142 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1143 p->name, 1144 (unsigned long long)p->start, 1145 (unsigned long long)p->end, res->name); 1146 } 1147 return 0; 1148 } 1149 1150 /* 1151 * Handle resources of PCI devices. If the world were perfect, we could 1152 * just allocate all the resource regions and do nothing more. It isn't. 1153 * On the other hand, we cannot just re-allocate all devices, as it would 1154 * require us to know lots of host bridge internals. So we attempt to 1155 * keep as much of the original configuration as possible, but tweak it 1156 * when it's found to be wrong. 1157 * 1158 * Known BIOS problems we have to work around: 1159 * - I/O or memory regions not configured 1160 * - regions configured, but not enabled in the command register 1161 * - bogus I/O addresses above 64K used 1162 * - expansion ROMs left enabled (this may sound harmless, but given 1163 * the fact the PCI specs explicitly allow address decoders to be 1164 * shared between expansion ROMs and other resource regions, it's 1165 * at least dangerous) 1166 * 1167 * Our solution: 1168 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1169 * This gives us fixed barriers on where we can allocate. 1170 * (2) Allocate resources for all enabled devices. If there is 1171 * a collision, just mark the resource as unallocated. Also 1172 * disable expansion ROMs during this step. 1173 * (3) Try to allocate resources for disabled devices. If the 1174 * resources were assigned correctly, everything goes well, 1175 * if they weren't, they won't disturb allocation of other 1176 * resources. 1177 * (4) Assign new addresses to resources which were either 1178 * not configured at all or misconfigured. If explicitly 1179 * requested by the user, configure expansion ROM address 1180 * as well. 1181 */ 1182 1183 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1184 { 1185 struct pci_bus *b; 1186 int i; 1187 struct resource *res, *pr; 1188 1189 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1190 pci_domain_nr(bus), bus->number); 1191 1192 pci_bus_for_each_resource(bus, res, i) { 1193 if (!res || !res->flags || res->start > res->end || res->parent) 1194 continue; 1195 1196 /* If the resource was left unset at this point, we clear it */ 1197 if (res->flags & IORESOURCE_UNSET) 1198 goto clear_resource; 1199 1200 if (bus->parent == NULL) 1201 pr = (res->flags & IORESOURCE_IO) ? 1202 &ioport_resource : &iomem_resource; 1203 else { 1204 pr = pci_find_parent_resource(bus->self, res); 1205 if (pr == res) { 1206 /* this happens when the generic PCI 1207 * code (wrongly) decides that this 1208 * bridge is transparent -- paulus 1209 */ 1210 continue; 1211 } 1212 } 1213 1214 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1215 "[0x%x], parent %p (%s)\n", 1216 bus->self ? pci_name(bus->self) : "PHB", 1217 bus->number, i, 1218 (unsigned long long)res->start, 1219 (unsigned long long)res->end, 1220 (unsigned int)res->flags, 1221 pr, (pr && pr->name) ? pr->name : "nil"); 1222 1223 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1224 if (request_resource(pr, res) == 0) 1225 continue; 1226 /* 1227 * Must be a conflict with an existing entry. 1228 * Move that entry (or entries) under the 1229 * bridge resource and try again. 1230 */ 1231 if (reparent_resources(pr, res) == 0) 1232 continue; 1233 } 1234 pr_warning("PCI: Cannot allocate resource region " 1235 "%d of PCI bridge %d, will remap\n", i, bus->number); 1236 clear_resource: 1237 /* The resource might be figured out when doing 1238 * reassignment based on the resources required 1239 * by the downstream PCI devices. Here we set 1240 * the size of the resource to be 0 in order to 1241 * save more space. 1242 */ 1243 res->start = 0; 1244 res->end = -1; 1245 res->flags = 0; 1246 } 1247 1248 list_for_each_entry(b, &bus->children, node) 1249 pcibios_allocate_bus_resources(b); 1250 } 1251 1252 static inline void alloc_resource(struct pci_dev *dev, int idx) 1253 { 1254 struct resource *pr, *r = &dev->resource[idx]; 1255 1256 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1257 pci_name(dev), idx, 1258 (unsigned long long)r->start, 1259 (unsigned long long)r->end, 1260 (unsigned int)r->flags); 1261 1262 pr = pci_find_parent_resource(dev, r); 1263 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1264 request_resource(pr, r) < 0) { 1265 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1266 " of device %s, will remap\n", idx, pci_name(dev)); 1267 if (pr) 1268 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1269 pr, 1270 (unsigned long long)pr->start, 1271 (unsigned long long)pr->end, 1272 (unsigned int)pr->flags); 1273 /* We'll assign a new address later */ 1274 r->flags |= IORESOURCE_UNSET; 1275 r->end -= r->start; 1276 r->start = 0; 1277 } 1278 } 1279 1280 static void __init pcibios_allocate_resources(int pass) 1281 { 1282 struct pci_dev *dev = NULL; 1283 int idx, disabled; 1284 u16 command; 1285 struct resource *r; 1286 1287 for_each_pci_dev(dev) { 1288 pci_read_config_word(dev, PCI_COMMAND, &command); 1289 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1290 r = &dev->resource[idx]; 1291 if (r->parent) /* Already allocated */ 1292 continue; 1293 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1294 continue; /* Not assigned at all */ 1295 /* We only allocate ROMs on pass 1 just in case they 1296 * have been screwed up by firmware 1297 */ 1298 if (idx == PCI_ROM_RESOURCE ) 1299 disabled = 1; 1300 if (r->flags & IORESOURCE_IO) 1301 disabled = !(command & PCI_COMMAND_IO); 1302 else 1303 disabled = !(command & PCI_COMMAND_MEMORY); 1304 if (pass == disabled) 1305 alloc_resource(dev, idx); 1306 } 1307 if (pass) 1308 continue; 1309 r = &dev->resource[PCI_ROM_RESOURCE]; 1310 if (r->flags) { 1311 /* Turn the ROM off, leave the resource region, 1312 * but keep it unregistered. 1313 */ 1314 u32 reg; 1315 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1316 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1317 pr_debug("PCI: Switching off ROM of %s\n", 1318 pci_name(dev)); 1319 r->flags &= ~IORESOURCE_ROM_ENABLE; 1320 pci_write_config_dword(dev, dev->rom_base_reg, 1321 reg & ~PCI_ROM_ADDRESS_ENABLE); 1322 } 1323 } 1324 } 1325 } 1326 1327 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1328 { 1329 struct pci_controller *hose = pci_bus_to_host(bus); 1330 resource_size_t offset; 1331 struct resource *res, *pres; 1332 int i; 1333 1334 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1335 1336 /* Check for IO */ 1337 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1338 goto no_io; 1339 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1340 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1341 BUG_ON(res == NULL); 1342 res->name = "Legacy IO"; 1343 res->flags = IORESOURCE_IO; 1344 res->start = offset; 1345 res->end = (offset + 0xfff) & 0xfffffffful; 1346 pr_debug("Candidate legacy IO: %pR\n", res); 1347 if (request_resource(&hose->io_resource, res)) { 1348 printk(KERN_DEBUG 1349 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1350 pci_domain_nr(bus), bus->number, res); 1351 kfree(res); 1352 } 1353 1354 no_io: 1355 /* Check for memory */ 1356 for (i = 0; i < 3; i++) { 1357 pres = &hose->mem_resources[i]; 1358 offset = hose->mem_offset[i]; 1359 if (!(pres->flags & IORESOURCE_MEM)) 1360 continue; 1361 pr_debug("hose mem res: %pR\n", pres); 1362 if ((pres->start - offset) <= 0xa0000 && 1363 (pres->end - offset) >= 0xbffff) 1364 break; 1365 } 1366 if (i >= 3) 1367 return; 1368 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1369 BUG_ON(res == NULL); 1370 res->name = "Legacy VGA memory"; 1371 res->flags = IORESOURCE_MEM; 1372 res->start = 0xa0000 + offset; 1373 res->end = 0xbffff + offset; 1374 pr_debug("Candidate VGA memory: %pR\n", res); 1375 if (request_resource(pres, res)) { 1376 printk(KERN_DEBUG 1377 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1378 pci_domain_nr(bus), bus->number, res); 1379 kfree(res); 1380 } 1381 } 1382 1383 void __init pcibios_resource_survey(void) 1384 { 1385 struct pci_bus *b; 1386 1387 /* Allocate and assign resources */ 1388 list_for_each_entry(b, &pci_root_buses, node) 1389 pcibios_allocate_bus_resources(b); 1390 pcibios_allocate_resources(0); 1391 pcibios_allocate_resources(1); 1392 1393 /* Before we start assigning unassigned resource, we try to reserve 1394 * the low IO area and the VGA memory area if they intersect the 1395 * bus available resources to avoid allocating things on top of them 1396 */ 1397 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1398 list_for_each_entry(b, &pci_root_buses, node) 1399 pcibios_reserve_legacy_regions(b); 1400 } 1401 1402 /* Now, if the platform didn't decide to blindly trust the firmware, 1403 * we proceed to assigning things that were left unassigned 1404 */ 1405 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1406 pr_debug("PCI: Assigning unassigned resources...\n"); 1407 pci_assign_unassigned_resources(); 1408 } 1409 1410 /* Call machine dependent fixup */ 1411 if (ppc_md.pcibios_fixup) 1412 ppc_md.pcibios_fixup(); 1413 } 1414 1415 /* This is used by the PCI hotplug driver to allocate resource 1416 * of newly plugged busses. We can try to consolidate with the 1417 * rest of the code later, for now, keep it as-is as our main 1418 * resource allocation function doesn't deal with sub-trees yet. 1419 */ 1420 void pcibios_claim_one_bus(struct pci_bus *bus) 1421 { 1422 struct pci_dev *dev; 1423 struct pci_bus *child_bus; 1424 1425 list_for_each_entry(dev, &bus->devices, bus_list) { 1426 int i; 1427 1428 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1429 struct resource *r = &dev->resource[i]; 1430 1431 if (r->parent || !r->start || !r->flags) 1432 continue; 1433 1434 pr_debug("PCI: Claiming %s: " 1435 "Resource %d: %016llx..%016llx [%x]\n", 1436 pci_name(dev), i, 1437 (unsigned long long)r->start, 1438 (unsigned long long)r->end, 1439 (unsigned int)r->flags); 1440 1441 pci_claim_resource(dev, i); 1442 } 1443 } 1444 1445 list_for_each_entry(child_bus, &bus->children, node) 1446 pcibios_claim_one_bus(child_bus); 1447 } 1448 1449 1450 /* pcibios_finish_adding_to_bus 1451 * 1452 * This is to be called by the hotplug code after devices have been 1453 * added to a bus, this include calling it for a PHB that is just 1454 * being added 1455 */ 1456 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1457 { 1458 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1459 pci_domain_nr(bus), bus->number); 1460 1461 /* Allocate bus and devices resources */ 1462 pcibios_allocate_bus_resources(bus); 1463 pcibios_claim_one_bus(bus); 1464 1465 /* Fixup EEH */ 1466 eeh_add_device_tree_late(bus); 1467 1468 /* Add new devices to global lists. Register in proc, sysfs. */ 1469 pci_bus_add_devices(bus); 1470 1471 /* sysfs files should only be added after devices are added */ 1472 eeh_add_sysfs_files(bus); 1473 } 1474 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1475 1476 int pcibios_enable_device(struct pci_dev *dev, int mask) 1477 { 1478 if (ppc_md.pcibios_enable_device_hook) 1479 if (ppc_md.pcibios_enable_device_hook(dev)) 1480 return -EINVAL; 1481 1482 /* avoid pcie irq fix up impact on cardbus */ 1483 if (dev->hdr_type != PCI_HEADER_TYPE_CARDBUS) 1484 pcibios_setup_device(dev); 1485 1486 return pci_enable_resources(dev, mask); 1487 } 1488 1489 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1490 { 1491 return (unsigned long) hose->io_base_virt - _IO_BASE; 1492 } 1493 1494 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1495 struct list_head *resources) 1496 { 1497 struct resource *res; 1498 resource_size_t offset; 1499 int i; 1500 1501 /* Hookup PHB IO resource */ 1502 res = &hose->io_resource; 1503 1504 if (!res->flags) { 1505 printk(KERN_WARNING "PCI: I/O resource not set for host" 1506 " bridge %s (domain %d)\n", 1507 hose->dn->full_name, hose->global_number); 1508 } else { 1509 offset = pcibios_io_space_offset(hose); 1510 1511 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n", 1512 (unsigned long long)res->start, 1513 (unsigned long long)res->end, 1514 (unsigned long)res->flags, 1515 (unsigned long long)offset); 1516 pci_add_resource_offset(resources, res, offset); 1517 } 1518 1519 /* Hookup PHB Memory resources */ 1520 for (i = 0; i < 3; ++i) { 1521 res = &hose->mem_resources[i]; 1522 if (!res->flags) { 1523 if (i == 0) 1524 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1525 "host bridge %s (domain %d)\n", 1526 hose->dn->full_name, hose->global_number); 1527 continue; 1528 } 1529 offset = hose->mem_offset[i]; 1530 1531 1532 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i, 1533 (unsigned long long)res->start, 1534 (unsigned long long)res->end, 1535 (unsigned long)res->flags, 1536 (unsigned long long)offset); 1537 1538 pci_add_resource_offset(resources, res, offset); 1539 } 1540 } 1541 1542 /* 1543 * Null PCI config access functions, for the case when we can't 1544 * find a hose. 1545 */ 1546 #define NULL_PCI_OP(rw, size, type) \ 1547 static int \ 1548 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1549 { \ 1550 return PCIBIOS_DEVICE_NOT_FOUND; \ 1551 } 1552 1553 static int 1554 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1555 int len, u32 *val) 1556 { 1557 return PCIBIOS_DEVICE_NOT_FOUND; 1558 } 1559 1560 static int 1561 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1562 int len, u32 val) 1563 { 1564 return PCIBIOS_DEVICE_NOT_FOUND; 1565 } 1566 1567 static struct pci_ops null_pci_ops = 1568 { 1569 .read = null_read_config, 1570 .write = null_write_config, 1571 }; 1572 1573 /* 1574 * These functions are used early on before PCI scanning is done 1575 * and all of the pci_dev and pci_bus structures have been created. 1576 */ 1577 static struct pci_bus * 1578 fake_pci_bus(struct pci_controller *hose, int busnr) 1579 { 1580 static struct pci_bus bus; 1581 1582 if (hose == 0) { 1583 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1584 } 1585 bus.number = busnr; 1586 bus.sysdata = hose; 1587 bus.ops = hose? hose->ops: &null_pci_ops; 1588 return &bus; 1589 } 1590 1591 #define EARLY_PCI_OP(rw, size, type) \ 1592 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1593 int devfn, int offset, type value) \ 1594 { \ 1595 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1596 devfn, offset, value); \ 1597 } 1598 1599 EARLY_PCI_OP(read, byte, u8 *) 1600 EARLY_PCI_OP(read, word, u16 *) 1601 EARLY_PCI_OP(read, dword, u32 *) 1602 EARLY_PCI_OP(write, byte, u8) 1603 EARLY_PCI_OP(write, word, u16) 1604 EARLY_PCI_OP(write, dword, u32) 1605 1606 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1607 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1608 int cap) 1609 { 1610 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1611 } 1612 1613 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1614 { 1615 struct pci_controller *hose = bus->sysdata; 1616 1617 return of_node_get(hose->dn); 1618 } 1619 1620 /** 1621 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1622 * @hose: Pointer to the PCI host controller instance structure 1623 */ 1624 void pcibios_scan_phb(struct pci_controller *hose) 1625 { 1626 LIST_HEAD(resources); 1627 struct pci_bus *bus; 1628 struct device_node *node = hose->dn; 1629 int mode; 1630 1631 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); 1632 1633 /* Get some IO space for the new PHB */ 1634 pcibios_setup_phb_io_space(hose); 1635 1636 /* Wire up PHB bus resources */ 1637 pcibios_setup_phb_resources(hose, &resources); 1638 1639 hose->busn.start = hose->first_busno; 1640 hose->busn.end = hose->last_busno; 1641 hose->busn.flags = IORESOURCE_BUS; 1642 pci_add_resource(&resources, &hose->busn); 1643 1644 /* Create an empty bus for the toplevel */ 1645 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1646 hose->ops, hose, &resources); 1647 if (bus == NULL) { 1648 pr_err("Failed to create bus for PCI domain %04x\n", 1649 hose->global_number); 1650 pci_free_resource_list(&resources); 1651 return; 1652 } 1653 hose->bus = bus; 1654 1655 /* Get probe mode and perform scan */ 1656 mode = PCI_PROBE_NORMAL; 1657 if (node && ppc_md.pci_probe_mode) 1658 mode = ppc_md.pci_probe_mode(bus); 1659 pr_debug(" probe mode: %d\n", mode); 1660 if (mode == PCI_PROBE_DEVTREE) 1661 of_scan_bus(node, bus); 1662 1663 if (mode == PCI_PROBE_NORMAL) { 1664 pci_bus_update_busn_res_end(bus, 255); 1665 hose->last_busno = pci_scan_child_bus(bus); 1666 pci_bus_update_busn_res_end(bus, hose->last_busno); 1667 } 1668 1669 /* Platform gets a chance to do some global fixups before 1670 * we proceed to resource allocation 1671 */ 1672 if (ppc_md.pcibios_fixup_phb) 1673 ppc_md.pcibios_fixup_phb(hose); 1674 1675 /* Configure PCI Express settings */ 1676 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1677 struct pci_bus *child; 1678 list_for_each_entry(child, &bus->children, node) { 1679 struct pci_dev *self = child->self; 1680 if (!self) 1681 continue; 1682 pcie_bus_configure_settings(child, self->pcie_mpss); 1683 } 1684 } 1685 } 1686 1687 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1688 { 1689 int i, class = dev->class >> 8; 1690 /* When configured as agent, programing interface = 1 */ 1691 int prog_if = dev->class & 0xf; 1692 1693 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1694 class == PCI_CLASS_BRIDGE_OTHER) && 1695 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1696 (prog_if == 0) && 1697 (dev->bus->parent == NULL)) { 1698 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1699 dev->resource[i].start = 0; 1700 dev->resource[i].end = 0; 1701 dev->resource[i].flags = 0; 1702 } 1703 } 1704 } 1705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1707 1708 static void fixup_vga(struct pci_dev *pdev) 1709 { 1710 u16 cmd; 1711 1712 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1713 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) 1714 vga_set_default_device(pdev); 1715 1716 } 1717 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1718 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); 1719