1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/export.h> 25 #include <linux/of_address.h> 26 #include <linux/of_pci.h> 27 #include <linux/mm.h> 28 #include <linux/list.h> 29 #include <linux/syscalls.h> 30 #include <linux/irq.h> 31 #include <linux/vmalloc.h> 32 #include <linux/slab.h> 33 34 #include <asm/processor.h> 35 #include <asm/io.h> 36 #include <asm/prom.h> 37 #include <asm/pci-bridge.h> 38 #include <asm/byteorder.h> 39 #include <asm/machdep.h> 40 #include <asm/ppc-pci.h> 41 #include <asm/eeh.h> 42 43 static DEFINE_SPINLOCK(hose_spinlock); 44 LIST_HEAD(hose_list); 45 46 /* XXX kill that some day ... */ 47 static int global_phb_number; /* Global phb counter */ 48 49 /* ISA Memory physical address */ 50 resource_size_t isa_mem_base; 51 52 53 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 54 55 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 56 { 57 pci_dma_ops = dma_ops; 58 } 59 60 struct dma_map_ops *get_pci_dma_ops(void) 61 { 62 return pci_dma_ops; 63 } 64 EXPORT_SYMBOL(get_pci_dma_ops); 65 66 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 67 { 68 struct pci_controller *phb; 69 70 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 71 if (phb == NULL) 72 return NULL; 73 spin_lock(&hose_spinlock); 74 phb->global_number = global_phb_number++; 75 list_add_tail(&phb->list_node, &hose_list); 76 spin_unlock(&hose_spinlock); 77 phb->dn = dev; 78 phb->is_dynamic = mem_init_done; 79 #ifdef CONFIG_PPC64 80 if (dev) { 81 int nid = of_node_to_nid(dev); 82 83 if (nid < 0 || !node_online(nid)) 84 nid = -1; 85 86 PHB_SET_NODE(phb, nid); 87 } 88 #endif 89 return phb; 90 } 91 92 void pcibios_free_controller(struct pci_controller *phb) 93 { 94 spin_lock(&hose_spinlock); 95 list_del(&phb->list_node); 96 spin_unlock(&hose_spinlock); 97 98 if (phb->is_dynamic) 99 kfree(phb); 100 } 101 102 /* 103 * The function is used to return the minimal alignment 104 * for memory or I/O windows of the associated P2P bridge. 105 * By default, 4KiB alignment for I/O windows and 1MiB for 106 * memory windows. 107 */ 108 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 109 unsigned long type) 110 { 111 if (ppc_md.pcibios_window_alignment) 112 return ppc_md.pcibios_window_alignment(bus, type); 113 114 /* 115 * PCI core will figure out the default 116 * alignment: 4KiB for I/O and 1MiB for 117 * memory window. 118 */ 119 return 1; 120 } 121 122 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 123 { 124 #ifdef CONFIG_PPC64 125 return hose->pci_io_size; 126 #else 127 return resource_size(&hose->io_resource); 128 #endif 129 } 130 131 int pcibios_vaddr_is_ioport(void __iomem *address) 132 { 133 int ret = 0; 134 struct pci_controller *hose; 135 resource_size_t size; 136 137 spin_lock(&hose_spinlock); 138 list_for_each_entry(hose, &hose_list, list_node) { 139 size = pcibios_io_size(hose); 140 if (address >= hose->io_base_virt && 141 address < (hose->io_base_virt + size)) { 142 ret = 1; 143 break; 144 } 145 } 146 spin_unlock(&hose_spinlock); 147 return ret; 148 } 149 150 unsigned long pci_address_to_pio(phys_addr_t address) 151 { 152 struct pci_controller *hose; 153 resource_size_t size; 154 unsigned long ret = ~0; 155 156 spin_lock(&hose_spinlock); 157 list_for_each_entry(hose, &hose_list, list_node) { 158 size = pcibios_io_size(hose); 159 if (address >= hose->io_base_phys && 160 address < (hose->io_base_phys + size)) { 161 unsigned long base = 162 (unsigned long)hose->io_base_virt - _IO_BASE; 163 ret = base + (address - hose->io_base_phys); 164 break; 165 } 166 } 167 spin_unlock(&hose_spinlock); 168 169 return ret; 170 } 171 EXPORT_SYMBOL_GPL(pci_address_to_pio); 172 173 /* 174 * Return the domain number for this bus. 175 */ 176 int pci_domain_nr(struct pci_bus *bus) 177 { 178 struct pci_controller *hose = pci_bus_to_host(bus); 179 180 return hose->global_number; 181 } 182 EXPORT_SYMBOL(pci_domain_nr); 183 184 /* This routine is meant to be used early during boot, when the 185 * PCI bus numbers have not yet been assigned, and you need to 186 * issue PCI config cycles to an OF device. 187 * It could also be used to "fix" RTAS config cycles if you want 188 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 189 * config cycles. 190 */ 191 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 192 { 193 while(node) { 194 struct pci_controller *hose, *tmp; 195 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 196 if (hose->dn == node) 197 return hose; 198 node = node->parent; 199 } 200 return NULL; 201 } 202 203 static ssize_t pci_show_devspec(struct device *dev, 204 struct device_attribute *attr, char *buf) 205 { 206 struct pci_dev *pdev; 207 struct device_node *np; 208 209 pdev = to_pci_dev (dev); 210 np = pci_device_to_OF_node(pdev); 211 if (np == NULL || np->full_name == NULL) 212 return 0; 213 return sprintf(buf, "%s", np->full_name); 214 } 215 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 216 217 /* Add sysfs properties */ 218 int pcibios_add_platform_entries(struct pci_dev *pdev) 219 { 220 return device_create_file(&pdev->dev, &dev_attr_devspec); 221 } 222 223 /* 224 * Reads the interrupt pin to determine if interrupt is use by card. 225 * If the interrupt is used, then gets the interrupt line from the 226 * openfirmware and sets it in the pci_dev and pci_config line. 227 */ 228 static int pci_read_irq_line(struct pci_dev *pci_dev) 229 { 230 struct of_irq oirq; 231 unsigned int virq; 232 233 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 234 235 #ifdef DEBUG 236 memset(&oirq, 0xff, sizeof(oirq)); 237 #endif 238 /* Try to get a mapping from the device-tree */ 239 if (of_irq_map_pci(pci_dev, &oirq)) { 240 u8 line, pin; 241 242 /* If that fails, lets fallback to what is in the config 243 * space and map that through the default controller. We 244 * also set the type to level low since that's what PCI 245 * interrupts are. If your platform does differently, then 246 * either provide a proper interrupt tree or don't use this 247 * function. 248 */ 249 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 250 return -1; 251 if (pin == 0) 252 return -1; 253 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 254 line == 0xff || line == 0) { 255 return -1; 256 } 257 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 258 line, pin); 259 260 virq = irq_create_mapping(NULL, line); 261 if (virq != NO_IRQ) 262 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 263 } else { 264 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 265 oirq.size, oirq.specifier[0], oirq.specifier[1], 266 of_node_full_name(oirq.controller)); 267 268 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 269 oirq.size); 270 } 271 if(virq == NO_IRQ) { 272 pr_debug(" Failed to map !\n"); 273 return -1; 274 } 275 276 pr_debug(" Mapped to linux irq %d\n", virq); 277 278 pci_dev->irq = virq; 279 280 return 0; 281 } 282 283 /* 284 * Platform support for /proc/bus/pci/X/Y mmap()s, 285 * modelled on the sparc64 implementation by Dave Miller. 286 * -- paulus. 287 */ 288 289 /* 290 * Adjust vm_pgoff of VMA such that it is the physical page offset 291 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 292 * 293 * Basically, the user finds the base address for his device which he wishes 294 * to mmap. They read the 32-bit value from the config space base register, 295 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 296 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 297 * 298 * Returns negative error code on failure, zero on success. 299 */ 300 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 301 resource_size_t *offset, 302 enum pci_mmap_state mmap_state) 303 { 304 struct pci_controller *hose = pci_bus_to_host(dev->bus); 305 unsigned long io_offset = 0; 306 int i, res_bit; 307 308 if (hose == 0) 309 return NULL; /* should never happen */ 310 311 /* If memory, add on the PCI bridge address offset */ 312 if (mmap_state == pci_mmap_mem) { 313 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 314 *offset += hose->pci_mem_offset; 315 #endif 316 res_bit = IORESOURCE_MEM; 317 } else { 318 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 319 *offset += io_offset; 320 res_bit = IORESOURCE_IO; 321 } 322 323 /* 324 * Check that the offset requested corresponds to one of the 325 * resources of the device. 326 */ 327 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 328 struct resource *rp = &dev->resource[i]; 329 int flags = rp->flags; 330 331 /* treat ROM as memory (should be already) */ 332 if (i == PCI_ROM_RESOURCE) 333 flags |= IORESOURCE_MEM; 334 335 /* Active and same type? */ 336 if ((flags & res_bit) == 0) 337 continue; 338 339 /* In the range of this resource? */ 340 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 341 continue; 342 343 /* found it! construct the final physical address */ 344 if (mmap_state == pci_mmap_io) 345 *offset += hose->io_base_phys - io_offset; 346 return rp; 347 } 348 349 return NULL; 350 } 351 352 /* 353 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 354 * device mapping. 355 */ 356 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 357 pgprot_t protection, 358 enum pci_mmap_state mmap_state, 359 int write_combine) 360 { 361 unsigned long prot = pgprot_val(protection); 362 363 /* Write combine is always 0 on non-memory space mappings. On 364 * memory space, if the user didn't pass 1, we check for a 365 * "prefetchable" resource. This is a bit hackish, but we use 366 * this to workaround the inability of /sysfs to provide a write 367 * combine bit 368 */ 369 if (mmap_state != pci_mmap_mem) 370 write_combine = 0; 371 else if (write_combine == 0) { 372 if (rp->flags & IORESOURCE_PREFETCH) 373 write_combine = 1; 374 } 375 376 /* XXX would be nice to have a way to ask for write-through */ 377 if (write_combine) 378 return pgprot_noncached_wc(prot); 379 else 380 return pgprot_noncached(prot); 381 } 382 383 /* 384 * This one is used by /dev/mem and fbdev who have no clue about the 385 * PCI device, it tries to find the PCI device first and calls the 386 * above routine 387 */ 388 pgprot_t pci_phys_mem_access_prot(struct file *file, 389 unsigned long pfn, 390 unsigned long size, 391 pgprot_t prot) 392 { 393 struct pci_dev *pdev = NULL; 394 struct resource *found = NULL; 395 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 396 int i; 397 398 if (page_is_ram(pfn)) 399 return prot; 400 401 prot = pgprot_noncached(prot); 402 for_each_pci_dev(pdev) { 403 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 404 struct resource *rp = &pdev->resource[i]; 405 int flags = rp->flags; 406 407 /* Active and same type? */ 408 if ((flags & IORESOURCE_MEM) == 0) 409 continue; 410 /* In the range of this resource? */ 411 if (offset < (rp->start & PAGE_MASK) || 412 offset > rp->end) 413 continue; 414 found = rp; 415 break; 416 } 417 if (found) 418 break; 419 } 420 if (found) { 421 if (found->flags & IORESOURCE_PREFETCH) 422 prot = pgprot_noncached_wc(prot); 423 pci_dev_put(pdev); 424 } 425 426 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 427 (unsigned long long)offset, pgprot_val(prot)); 428 429 return prot; 430 } 431 432 433 /* 434 * Perform the actual remap of the pages for a PCI device mapping, as 435 * appropriate for this architecture. The region in the process to map 436 * is described by vm_start and vm_end members of VMA, the base physical 437 * address is found in vm_pgoff. 438 * The pci device structure is provided so that architectures may make mapping 439 * decisions on a per-device or per-bus basis. 440 * 441 * Returns a negative error code on failure, zero on success. 442 */ 443 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 444 enum pci_mmap_state mmap_state, int write_combine) 445 { 446 resource_size_t offset = 447 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 448 struct resource *rp; 449 int ret; 450 451 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 452 if (rp == NULL) 453 return -EINVAL; 454 455 vma->vm_pgoff = offset >> PAGE_SHIFT; 456 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 457 vma->vm_page_prot, 458 mmap_state, write_combine); 459 460 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 461 vma->vm_end - vma->vm_start, vma->vm_page_prot); 462 463 return ret; 464 } 465 466 /* This provides legacy IO read access on a bus */ 467 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 468 { 469 unsigned long offset; 470 struct pci_controller *hose = pci_bus_to_host(bus); 471 struct resource *rp = &hose->io_resource; 472 void __iomem *addr; 473 474 /* Check if port can be supported by that bus. We only check 475 * the ranges of the PHB though, not the bus itself as the rules 476 * for forwarding legacy cycles down bridges are not our problem 477 * here. So if the host bridge supports it, we do it. 478 */ 479 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 480 offset += port; 481 482 if (!(rp->flags & IORESOURCE_IO)) 483 return -ENXIO; 484 if (offset < rp->start || (offset + size) > rp->end) 485 return -ENXIO; 486 addr = hose->io_base_virt + port; 487 488 switch(size) { 489 case 1: 490 *((u8 *)val) = in_8(addr); 491 return 1; 492 case 2: 493 if (port & 1) 494 return -EINVAL; 495 *((u16 *)val) = in_le16(addr); 496 return 2; 497 case 4: 498 if (port & 3) 499 return -EINVAL; 500 *((u32 *)val) = in_le32(addr); 501 return 4; 502 } 503 return -EINVAL; 504 } 505 506 /* This provides legacy IO write access on a bus */ 507 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 508 { 509 unsigned long offset; 510 struct pci_controller *hose = pci_bus_to_host(bus); 511 struct resource *rp = &hose->io_resource; 512 void __iomem *addr; 513 514 /* Check if port can be supported by that bus. We only check 515 * the ranges of the PHB though, not the bus itself as the rules 516 * for forwarding legacy cycles down bridges are not our problem 517 * here. So if the host bridge supports it, we do it. 518 */ 519 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 520 offset += port; 521 522 if (!(rp->flags & IORESOURCE_IO)) 523 return -ENXIO; 524 if (offset < rp->start || (offset + size) > rp->end) 525 return -ENXIO; 526 addr = hose->io_base_virt + port; 527 528 /* WARNING: The generic code is idiotic. It gets passed a pointer 529 * to what can be a 1, 2 or 4 byte quantity and always reads that 530 * as a u32, which means that we have to correct the location of 531 * the data read within those 32 bits for size 1 and 2 532 */ 533 switch(size) { 534 case 1: 535 out_8(addr, val >> 24); 536 return 1; 537 case 2: 538 if (port & 1) 539 return -EINVAL; 540 out_le16(addr, val >> 16); 541 return 2; 542 case 4: 543 if (port & 3) 544 return -EINVAL; 545 out_le32(addr, val); 546 return 4; 547 } 548 return -EINVAL; 549 } 550 551 /* This provides legacy IO or memory mmap access on a bus */ 552 int pci_mmap_legacy_page_range(struct pci_bus *bus, 553 struct vm_area_struct *vma, 554 enum pci_mmap_state mmap_state) 555 { 556 struct pci_controller *hose = pci_bus_to_host(bus); 557 resource_size_t offset = 558 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 559 resource_size_t size = vma->vm_end - vma->vm_start; 560 struct resource *rp; 561 562 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 563 pci_domain_nr(bus), bus->number, 564 mmap_state == pci_mmap_mem ? "MEM" : "IO", 565 (unsigned long long)offset, 566 (unsigned long long)(offset + size - 1)); 567 568 if (mmap_state == pci_mmap_mem) { 569 /* Hack alert ! 570 * 571 * Because X is lame and can fail starting if it gets an error trying 572 * to mmap legacy_mem (instead of just moving on without legacy memory 573 * access) we fake it here by giving it anonymous memory, effectively 574 * behaving just like /dev/zero 575 */ 576 if ((offset + size) > hose->isa_mem_size) { 577 printk(KERN_DEBUG 578 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 579 current->comm, current->pid, pci_domain_nr(bus), bus->number); 580 if (vma->vm_flags & VM_SHARED) 581 return shmem_zero_setup(vma); 582 return 0; 583 } 584 offset += hose->isa_mem_phys; 585 } else { 586 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 587 unsigned long roffset = offset + io_offset; 588 rp = &hose->io_resource; 589 if (!(rp->flags & IORESOURCE_IO)) 590 return -ENXIO; 591 if (roffset < rp->start || (roffset + size) > rp->end) 592 return -ENXIO; 593 offset += hose->io_base_phys; 594 } 595 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 596 597 vma->vm_pgoff = offset >> PAGE_SHIFT; 598 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 599 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 600 vma->vm_end - vma->vm_start, 601 vma->vm_page_prot); 602 } 603 604 void pci_resource_to_user(const struct pci_dev *dev, int bar, 605 const struct resource *rsrc, 606 resource_size_t *start, resource_size_t *end) 607 { 608 struct pci_controller *hose = pci_bus_to_host(dev->bus); 609 resource_size_t offset = 0; 610 611 if (hose == NULL) 612 return; 613 614 if (rsrc->flags & IORESOURCE_IO) 615 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 616 617 /* We pass a fully fixed up address to userland for MMIO instead of 618 * a BAR value because X is lame and expects to be able to use that 619 * to pass to /dev/mem ! 620 * 621 * That means that we'll have potentially 64 bits values where some 622 * userland apps only expect 32 (like X itself since it thinks only 623 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 624 * 32 bits CHRPs :-( 625 * 626 * Hopefully, the sysfs insterface is immune to that gunk. Once X 627 * has been fixed (and the fix spread enough), we can re-enable the 628 * 2 lines below and pass down a BAR value to userland. In that case 629 * we'll also have to re-enable the matching code in 630 * __pci_mmap_make_offset(). 631 * 632 * BenH. 633 */ 634 #if 0 635 else if (rsrc->flags & IORESOURCE_MEM) 636 offset = hose->pci_mem_offset; 637 #endif 638 639 *start = rsrc->start - offset; 640 *end = rsrc->end - offset; 641 } 642 643 /** 644 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 645 * @hose: newly allocated pci_controller to be setup 646 * @dev: device node of the host bridge 647 * @primary: set if primary bus (32 bits only, soon to be deprecated) 648 * 649 * This function will parse the "ranges" property of a PCI host bridge device 650 * node and setup the resource mapping of a pci controller based on its 651 * content. 652 * 653 * Life would be boring if it wasn't for a few issues that we have to deal 654 * with here: 655 * 656 * - We can only cope with one IO space range and up to 3 Memory space 657 * ranges. However, some machines (thanks Apple !) tend to split their 658 * space into lots of small contiguous ranges. So we have to coalesce. 659 * 660 * - We can only cope with all memory ranges having the same offset 661 * between CPU addresses and PCI addresses. Unfortunately, some bridges 662 * are setup for a large 1:1 mapping along with a small "window" which 663 * maps PCI address 0 to some arbitrary high address of the CPU space in 664 * order to give access to the ISA memory hole. 665 * The way out of here that I've chosen for now is to always set the 666 * offset based on the first resource found, then override it if we 667 * have a different offset and the previous was set by an ISA hole. 668 * 669 * - Some busses have IO space not starting at 0, which causes trouble with 670 * the way we do our IO resource renumbering. The code somewhat deals with 671 * it for 64 bits but I would expect problems on 32 bits. 672 * 673 * - Some 32 bits platforms such as 4xx can have physical space larger than 674 * 32 bits so we need to use 64 bits values for the parsing 675 */ 676 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, 677 struct device_node *dev, 678 int primary) 679 { 680 const u32 *ranges; 681 int rlen; 682 int pna = of_n_addr_cells(dev); 683 int np = pna + 5; 684 int memno = 0, isa_hole = -1; 685 u32 pci_space; 686 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 687 unsigned long long isa_mb = 0; 688 struct resource *res; 689 690 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 691 dev->full_name, primary ? "(primary)" : ""); 692 693 /* Get ranges property */ 694 ranges = of_get_property(dev, "ranges", &rlen); 695 if (ranges == NULL) 696 return; 697 698 /* Parse it */ 699 while ((rlen -= np * 4) >= 0) { 700 /* Read next ranges element */ 701 pci_space = ranges[0]; 702 pci_addr = of_read_number(ranges + 1, 2); 703 cpu_addr = of_translate_address(dev, ranges + 3); 704 size = of_read_number(ranges + pna + 3, 2); 705 ranges += np; 706 707 /* If we failed translation or got a zero-sized region 708 * (some FW try to feed us with non sensical zero sized regions 709 * such as power3 which look like some kind of attempt at exposing 710 * the VGA memory hole) 711 */ 712 if (cpu_addr == OF_BAD_ADDR || size == 0) 713 continue; 714 715 /* Now consume following elements while they are contiguous */ 716 for (; rlen >= np * sizeof(u32); 717 ranges += np, rlen -= np * 4) { 718 if (ranges[0] != pci_space) 719 break; 720 pci_next = of_read_number(ranges + 1, 2); 721 cpu_next = of_translate_address(dev, ranges + 3); 722 if (pci_next != pci_addr + size || 723 cpu_next != cpu_addr + size) 724 break; 725 size += of_read_number(ranges + pna + 3, 2); 726 } 727 728 /* Act based on address space type */ 729 res = NULL; 730 switch ((pci_space >> 24) & 0x3) { 731 case 1: /* PCI IO space */ 732 printk(KERN_INFO 733 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 734 cpu_addr, cpu_addr + size - 1, pci_addr); 735 736 /* We support only one IO range */ 737 if (hose->pci_io_size) { 738 printk(KERN_INFO 739 " \\--> Skipped (too many) !\n"); 740 continue; 741 } 742 #ifdef CONFIG_PPC32 743 /* On 32 bits, limit I/O space to 16MB */ 744 if (size > 0x01000000) 745 size = 0x01000000; 746 747 /* 32 bits needs to map IOs here */ 748 hose->io_base_virt = ioremap(cpu_addr, size); 749 750 /* Expect trouble if pci_addr is not 0 */ 751 if (primary) 752 isa_io_base = 753 (unsigned long)hose->io_base_virt; 754 #endif /* CONFIG_PPC32 */ 755 /* pci_io_size and io_base_phys always represent IO 756 * space starting at 0 so we factor in pci_addr 757 */ 758 hose->pci_io_size = pci_addr + size; 759 hose->io_base_phys = cpu_addr - pci_addr; 760 761 /* Build resource */ 762 res = &hose->io_resource; 763 res->flags = IORESOURCE_IO; 764 res->start = pci_addr; 765 break; 766 case 2: /* PCI Memory space */ 767 case 3: /* PCI 64 bits Memory space */ 768 printk(KERN_INFO 769 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 770 cpu_addr, cpu_addr + size - 1, pci_addr, 771 (pci_space & 0x40000000) ? "Prefetch" : ""); 772 773 /* We support only 3 memory ranges */ 774 if (memno >= 3) { 775 printk(KERN_INFO 776 " \\--> Skipped (too many) !\n"); 777 continue; 778 } 779 /* Handles ISA memory hole space here */ 780 if (pci_addr == 0) { 781 isa_mb = cpu_addr; 782 isa_hole = memno; 783 if (primary || isa_mem_base == 0) 784 isa_mem_base = cpu_addr; 785 hose->isa_mem_phys = cpu_addr; 786 hose->isa_mem_size = size; 787 } 788 789 /* We get the PCI/Mem offset from the first range or 790 * the, current one if the offset came from an ISA 791 * hole. If they don't match, bugger. 792 */ 793 if (memno == 0 || 794 (isa_hole >= 0 && pci_addr != 0 && 795 hose->pci_mem_offset == isa_mb)) 796 hose->pci_mem_offset = cpu_addr - pci_addr; 797 else if (pci_addr != 0 && 798 hose->pci_mem_offset != cpu_addr - pci_addr) { 799 printk(KERN_INFO 800 " \\--> Skipped (offset mismatch) !\n"); 801 continue; 802 } 803 804 /* Build resource */ 805 res = &hose->mem_resources[memno++]; 806 res->flags = IORESOURCE_MEM; 807 if (pci_space & 0x40000000) 808 res->flags |= IORESOURCE_PREFETCH; 809 res->start = cpu_addr; 810 break; 811 } 812 if (res != NULL) { 813 res->name = dev->full_name; 814 res->end = res->start + size - 1; 815 res->parent = NULL; 816 res->sibling = NULL; 817 res->child = NULL; 818 } 819 } 820 821 /* If there's an ISA hole and the pci_mem_offset is -not- matching 822 * the ISA hole offset, then we need to remove the ISA hole from 823 * the resource list for that brige 824 */ 825 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { 826 unsigned int next = isa_hole + 1; 827 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); 828 if (next < memno) 829 memmove(&hose->mem_resources[isa_hole], 830 &hose->mem_resources[next], 831 sizeof(struct resource) * (memno - next)); 832 hose->mem_resources[--memno].flags = 0; 833 } 834 } 835 836 /* Decide whether to display the domain number in /proc */ 837 int pci_proc_domain(struct pci_bus *bus) 838 { 839 struct pci_controller *hose = pci_bus_to_host(bus); 840 841 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 842 return 0; 843 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 844 return hose->global_number != 0; 845 return 1; 846 } 847 848 /* This header fixup will do the resource fixup for all devices as they are 849 * probed, but not for bridge ranges 850 */ 851 static void __devinit pcibios_fixup_resources(struct pci_dev *dev) 852 { 853 struct pci_controller *hose = pci_bus_to_host(dev->bus); 854 int i; 855 856 if (!hose) { 857 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 858 pci_name(dev)); 859 return; 860 } 861 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 862 struct resource *res = dev->resource + i; 863 if (!res->flags) 864 continue; 865 866 /* If we're going to re-assign everything, we mark all resources 867 * as unset (and 0-base them). In addition, we mark BARs starting 868 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 869 * since in that case, we don't want to re-assign anything 870 */ 871 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 872 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 873 /* Only print message if not re-assigning */ 874 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 875 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 876 "is unassigned\n", 877 pci_name(dev), i, 878 (unsigned long long)res->start, 879 (unsigned long long)res->end, 880 (unsigned int)res->flags); 881 res->end -= res->start; 882 res->start = 0; 883 res->flags |= IORESOURCE_UNSET; 884 continue; 885 } 886 887 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", 888 pci_name(dev), i, 889 (unsigned long long)res->start,\ 890 (unsigned long long)res->end, 891 (unsigned int)res->flags); 892 } 893 894 /* Call machine specific resource fixup */ 895 if (ppc_md.pcibios_fixup_resources) 896 ppc_md.pcibios_fixup_resources(dev); 897 } 898 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 899 900 /* This function tries to figure out if a bridge resource has been initialized 901 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 902 * things go more smoothly when it gets it right. It should covers cases such 903 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 904 */ 905 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 906 struct resource *res) 907 { 908 struct pci_controller *hose = pci_bus_to_host(bus); 909 struct pci_dev *dev = bus->self; 910 resource_size_t offset; 911 u16 command; 912 int i; 913 914 /* We don't do anything if PCI_PROBE_ONLY is set */ 915 if (pci_has_flag(PCI_PROBE_ONLY)) 916 return 0; 917 918 /* Job is a bit different between memory and IO */ 919 if (res->flags & IORESOURCE_MEM) { 920 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been 921 * initialized by somebody 922 */ 923 if (res->start != hose->pci_mem_offset) 924 return 0; 925 926 /* The BAR is 0, let's check if memory decoding is enabled on 927 * the bridge. If not, we consider it unassigned 928 */ 929 pci_read_config_word(dev, PCI_COMMAND, &command); 930 if ((command & PCI_COMMAND_MEMORY) == 0) 931 return 1; 932 933 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 934 * resources covers that starting address (0 then it's good enough for 935 * us for memory 936 */ 937 for (i = 0; i < 3; i++) { 938 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 939 hose->mem_resources[i].start == hose->pci_mem_offset) 940 return 0; 941 } 942 943 /* Well, it starts at 0 and we know it will collide so we may as 944 * well consider it as unassigned. That covers the Apple case. 945 */ 946 return 1; 947 } else { 948 /* If the BAR is non-0, then we consider it assigned */ 949 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 950 if (((res->start - offset) & 0xfffffffful) != 0) 951 return 0; 952 953 /* Here, we are a bit different than memory as typically IO space 954 * starting at low addresses -is- valid. What we do instead if that 955 * we consider as unassigned anything that doesn't have IO enabled 956 * in the PCI command register, and that's it. 957 */ 958 pci_read_config_word(dev, PCI_COMMAND, &command); 959 if (command & PCI_COMMAND_IO) 960 return 0; 961 962 /* It's starting at 0 and IO is disabled in the bridge, consider 963 * it unassigned 964 */ 965 return 1; 966 } 967 } 968 969 /* Fixup resources of a PCI<->PCI bridge */ 970 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus) 971 { 972 struct resource *res; 973 int i; 974 975 struct pci_dev *dev = bus->self; 976 977 pci_bus_for_each_resource(bus, res, i) { 978 if (!res || !res->flags) 979 continue; 980 if (i >= 3 && bus->self->transparent) 981 continue; 982 983 /* If we're going to reassign everything, we can 984 * shrink the P2P resource to have size as being 985 * of 0 in order to save space. 986 */ 987 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 988 res->flags |= IORESOURCE_UNSET; 989 res->start = 0; 990 res->end = -1; 991 continue; 992 } 993 994 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", 995 pci_name(dev), i, 996 (unsigned long long)res->start,\ 997 (unsigned long long)res->end, 998 (unsigned int)res->flags); 999 1000 /* Try to detect uninitialized P2P bridge resources, 1001 * and clear them out so they get re-assigned later 1002 */ 1003 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1004 res->flags = 0; 1005 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1006 } 1007 } 1008 } 1009 1010 void __devinit pcibios_setup_bus_self(struct pci_bus *bus) 1011 { 1012 /* Fix up the bus resources for P2P bridges */ 1013 if (bus->self != NULL) 1014 pcibios_fixup_bridge(bus); 1015 1016 /* Platform specific bus fixups. This is currently only used 1017 * by fsl_pci and I'm hoping to get rid of it at some point 1018 */ 1019 if (ppc_md.pcibios_fixup_bus) 1020 ppc_md.pcibios_fixup_bus(bus); 1021 1022 /* Setup bus DMA mappings */ 1023 if (ppc_md.pci_dma_bus_setup) 1024 ppc_md.pci_dma_bus_setup(bus); 1025 } 1026 1027 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus) 1028 { 1029 struct pci_dev *dev; 1030 1031 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1032 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1033 1034 list_for_each_entry(dev, &bus->devices, bus_list) { 1035 /* Cardbus can call us to add new devices to a bus, so ignore 1036 * those who are already fully discovered 1037 */ 1038 if (dev->is_added) 1039 continue; 1040 1041 /* Fixup NUMA node as it may not be setup yet by the generic 1042 * code and is needed by the DMA init 1043 */ 1044 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1045 1046 /* Hook up default DMA ops */ 1047 set_dma_ops(&dev->dev, pci_dma_ops); 1048 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1049 1050 /* Additional platform DMA/iommu setup */ 1051 if (ppc_md.pci_dma_dev_setup) 1052 ppc_md.pci_dma_dev_setup(dev); 1053 1054 /* Read default IRQs and fixup if necessary */ 1055 pci_read_irq_line(dev); 1056 if (ppc_md.pci_irq_fixup) 1057 ppc_md.pci_irq_fixup(dev); 1058 } 1059 } 1060 1061 void pcibios_set_master(struct pci_dev *dev) 1062 { 1063 /* No special bus mastering setup handling */ 1064 } 1065 1066 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 1067 { 1068 /* When called from the generic PCI probe, read PCI<->PCI bridge 1069 * bases. This is -not- called when generating the PCI tree from 1070 * the OF device-tree. 1071 */ 1072 if (bus->self != NULL) 1073 pci_read_bridge_bases(bus); 1074 1075 /* Now fixup the bus bus */ 1076 pcibios_setup_bus_self(bus); 1077 1078 /* Now fixup devices on that bus */ 1079 pcibios_setup_bus_devices(bus); 1080 } 1081 EXPORT_SYMBOL(pcibios_fixup_bus); 1082 1083 void __devinit pci_fixup_cardbus(struct pci_bus *bus) 1084 { 1085 /* Now fixup devices on that bus */ 1086 pcibios_setup_bus_devices(bus); 1087 } 1088 1089 1090 static int skip_isa_ioresource_align(struct pci_dev *dev) 1091 { 1092 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1093 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1094 return 1; 1095 return 0; 1096 } 1097 1098 /* 1099 * We need to avoid collisions with `mirrored' VGA ports 1100 * and other strange ISA hardware, so we always want the 1101 * addresses to be allocated in the 0x000-0x0ff region 1102 * modulo 0x400. 1103 * 1104 * Why? Because some silly external IO cards only decode 1105 * the low 10 bits of the IO address. The 0x00-0xff region 1106 * is reserved for motherboard devices that decode all 16 1107 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1108 * but we want to try to avoid allocating at 0x2900-0x2bff 1109 * which might have be mirrored at 0x0100-0x03ff.. 1110 */ 1111 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1112 resource_size_t size, resource_size_t align) 1113 { 1114 struct pci_dev *dev = data; 1115 resource_size_t start = res->start; 1116 1117 if (res->flags & IORESOURCE_IO) { 1118 if (skip_isa_ioresource_align(dev)) 1119 return start; 1120 if (start & 0x300) 1121 start = (start + 0x3ff) & ~0x3ff; 1122 } 1123 1124 return start; 1125 } 1126 EXPORT_SYMBOL(pcibios_align_resource); 1127 1128 /* 1129 * Reparent resource children of pr that conflict with res 1130 * under res, and make res replace those children. 1131 */ 1132 static int reparent_resources(struct resource *parent, 1133 struct resource *res) 1134 { 1135 struct resource *p, **pp; 1136 struct resource **firstpp = NULL; 1137 1138 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1139 if (p->end < res->start) 1140 continue; 1141 if (res->end < p->start) 1142 break; 1143 if (p->start < res->start || p->end > res->end) 1144 return -1; /* not completely contained */ 1145 if (firstpp == NULL) 1146 firstpp = pp; 1147 } 1148 if (firstpp == NULL) 1149 return -1; /* didn't find any conflicting entries? */ 1150 res->parent = parent; 1151 res->child = *firstpp; 1152 res->sibling = *pp; 1153 *firstpp = res; 1154 *pp = NULL; 1155 for (p = res->child; p != NULL; p = p->sibling) { 1156 p->parent = res; 1157 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1158 p->name, 1159 (unsigned long long)p->start, 1160 (unsigned long long)p->end, res->name); 1161 } 1162 return 0; 1163 } 1164 1165 /* 1166 * Handle resources of PCI devices. If the world were perfect, we could 1167 * just allocate all the resource regions and do nothing more. It isn't. 1168 * On the other hand, we cannot just re-allocate all devices, as it would 1169 * require us to know lots of host bridge internals. So we attempt to 1170 * keep as much of the original configuration as possible, but tweak it 1171 * when it's found to be wrong. 1172 * 1173 * Known BIOS problems we have to work around: 1174 * - I/O or memory regions not configured 1175 * - regions configured, but not enabled in the command register 1176 * - bogus I/O addresses above 64K used 1177 * - expansion ROMs left enabled (this may sound harmless, but given 1178 * the fact the PCI specs explicitly allow address decoders to be 1179 * shared between expansion ROMs and other resource regions, it's 1180 * at least dangerous) 1181 * 1182 * Our solution: 1183 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1184 * This gives us fixed barriers on where we can allocate. 1185 * (2) Allocate resources for all enabled devices. If there is 1186 * a collision, just mark the resource as unallocated. Also 1187 * disable expansion ROMs during this step. 1188 * (3) Try to allocate resources for disabled devices. If the 1189 * resources were assigned correctly, everything goes well, 1190 * if they weren't, they won't disturb allocation of other 1191 * resources. 1192 * (4) Assign new addresses to resources which were either 1193 * not configured at all or misconfigured. If explicitly 1194 * requested by the user, configure expansion ROM address 1195 * as well. 1196 */ 1197 1198 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1199 { 1200 struct pci_bus *b; 1201 int i; 1202 struct resource *res, *pr; 1203 1204 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1205 pci_domain_nr(bus), bus->number); 1206 1207 pci_bus_for_each_resource(bus, res, i) { 1208 if (!res || !res->flags || res->start > res->end || res->parent) 1209 continue; 1210 1211 /* If the resource was left unset at this point, we clear it */ 1212 if (res->flags & IORESOURCE_UNSET) 1213 goto clear_resource; 1214 1215 if (bus->parent == NULL) 1216 pr = (res->flags & IORESOURCE_IO) ? 1217 &ioport_resource : &iomem_resource; 1218 else { 1219 pr = pci_find_parent_resource(bus->self, res); 1220 if (pr == res) { 1221 /* this happens when the generic PCI 1222 * code (wrongly) decides that this 1223 * bridge is transparent -- paulus 1224 */ 1225 continue; 1226 } 1227 } 1228 1229 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1230 "[0x%x], parent %p (%s)\n", 1231 bus->self ? pci_name(bus->self) : "PHB", 1232 bus->number, i, 1233 (unsigned long long)res->start, 1234 (unsigned long long)res->end, 1235 (unsigned int)res->flags, 1236 pr, (pr && pr->name) ? pr->name : "nil"); 1237 1238 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1239 if (request_resource(pr, res) == 0) 1240 continue; 1241 /* 1242 * Must be a conflict with an existing entry. 1243 * Move that entry (or entries) under the 1244 * bridge resource and try again. 1245 */ 1246 if (reparent_resources(pr, res) == 0) 1247 continue; 1248 } 1249 pr_warning("PCI: Cannot allocate resource region " 1250 "%d of PCI bridge %d, will remap\n", i, bus->number); 1251 clear_resource: 1252 /* The resource might be figured out when doing 1253 * reassignment based on the resources required 1254 * by the downstream PCI devices. Here we set 1255 * the size of the resource to be 0 in order to 1256 * save more space. 1257 */ 1258 res->start = 0; 1259 res->end = -1; 1260 res->flags = 0; 1261 } 1262 1263 list_for_each_entry(b, &bus->children, node) 1264 pcibios_allocate_bus_resources(b); 1265 } 1266 1267 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) 1268 { 1269 struct resource *pr, *r = &dev->resource[idx]; 1270 1271 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1272 pci_name(dev), idx, 1273 (unsigned long long)r->start, 1274 (unsigned long long)r->end, 1275 (unsigned int)r->flags); 1276 1277 pr = pci_find_parent_resource(dev, r); 1278 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1279 request_resource(pr, r) < 0) { 1280 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1281 " of device %s, will remap\n", idx, pci_name(dev)); 1282 if (pr) 1283 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1284 pr, 1285 (unsigned long long)pr->start, 1286 (unsigned long long)pr->end, 1287 (unsigned int)pr->flags); 1288 /* We'll assign a new address later */ 1289 r->flags |= IORESOURCE_UNSET; 1290 r->end -= r->start; 1291 r->start = 0; 1292 } 1293 } 1294 1295 static void __init pcibios_allocate_resources(int pass) 1296 { 1297 struct pci_dev *dev = NULL; 1298 int idx, disabled; 1299 u16 command; 1300 struct resource *r; 1301 1302 for_each_pci_dev(dev) { 1303 pci_read_config_word(dev, PCI_COMMAND, &command); 1304 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1305 r = &dev->resource[idx]; 1306 if (r->parent) /* Already allocated */ 1307 continue; 1308 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1309 continue; /* Not assigned at all */ 1310 /* We only allocate ROMs on pass 1 just in case they 1311 * have been screwed up by firmware 1312 */ 1313 if (idx == PCI_ROM_RESOURCE ) 1314 disabled = 1; 1315 if (r->flags & IORESOURCE_IO) 1316 disabled = !(command & PCI_COMMAND_IO); 1317 else 1318 disabled = !(command & PCI_COMMAND_MEMORY); 1319 if (pass == disabled) 1320 alloc_resource(dev, idx); 1321 } 1322 if (pass) 1323 continue; 1324 r = &dev->resource[PCI_ROM_RESOURCE]; 1325 if (r->flags) { 1326 /* Turn the ROM off, leave the resource region, 1327 * but keep it unregistered. 1328 */ 1329 u32 reg; 1330 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1331 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1332 pr_debug("PCI: Switching off ROM of %s\n", 1333 pci_name(dev)); 1334 r->flags &= ~IORESOURCE_ROM_ENABLE; 1335 pci_write_config_dword(dev, dev->rom_base_reg, 1336 reg & ~PCI_ROM_ADDRESS_ENABLE); 1337 } 1338 } 1339 } 1340 } 1341 1342 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1343 { 1344 struct pci_controller *hose = pci_bus_to_host(bus); 1345 resource_size_t offset; 1346 struct resource *res, *pres; 1347 int i; 1348 1349 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1350 1351 /* Check for IO */ 1352 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1353 goto no_io; 1354 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1355 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1356 BUG_ON(res == NULL); 1357 res->name = "Legacy IO"; 1358 res->flags = IORESOURCE_IO; 1359 res->start = offset; 1360 res->end = (offset + 0xfff) & 0xfffffffful; 1361 pr_debug("Candidate legacy IO: %pR\n", res); 1362 if (request_resource(&hose->io_resource, res)) { 1363 printk(KERN_DEBUG 1364 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1365 pci_domain_nr(bus), bus->number, res); 1366 kfree(res); 1367 } 1368 1369 no_io: 1370 /* Check for memory */ 1371 offset = hose->pci_mem_offset; 1372 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); 1373 for (i = 0; i < 3; i++) { 1374 pres = &hose->mem_resources[i]; 1375 if (!(pres->flags & IORESOURCE_MEM)) 1376 continue; 1377 pr_debug("hose mem res: %pR\n", pres); 1378 if ((pres->start - offset) <= 0xa0000 && 1379 (pres->end - offset) >= 0xbffff) 1380 break; 1381 } 1382 if (i >= 3) 1383 return; 1384 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1385 BUG_ON(res == NULL); 1386 res->name = "Legacy VGA memory"; 1387 res->flags = IORESOURCE_MEM; 1388 res->start = 0xa0000 + offset; 1389 res->end = 0xbffff + offset; 1390 pr_debug("Candidate VGA memory: %pR\n", res); 1391 if (request_resource(pres, res)) { 1392 printk(KERN_DEBUG 1393 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1394 pci_domain_nr(bus), bus->number, res); 1395 kfree(res); 1396 } 1397 } 1398 1399 void __init pcibios_resource_survey(void) 1400 { 1401 struct pci_bus *b; 1402 1403 /* Allocate and assign resources */ 1404 list_for_each_entry(b, &pci_root_buses, node) 1405 pcibios_allocate_bus_resources(b); 1406 pcibios_allocate_resources(0); 1407 pcibios_allocate_resources(1); 1408 1409 /* Before we start assigning unassigned resource, we try to reserve 1410 * the low IO area and the VGA memory area if they intersect the 1411 * bus available resources to avoid allocating things on top of them 1412 */ 1413 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1414 list_for_each_entry(b, &pci_root_buses, node) 1415 pcibios_reserve_legacy_regions(b); 1416 } 1417 1418 /* Now, if the platform didn't decide to blindly trust the firmware, 1419 * we proceed to assigning things that were left unassigned 1420 */ 1421 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1422 pr_debug("PCI: Assigning unassigned resources...\n"); 1423 pci_assign_unassigned_resources(); 1424 } 1425 1426 /* Call machine dependent fixup */ 1427 if (ppc_md.pcibios_fixup) 1428 ppc_md.pcibios_fixup(); 1429 } 1430 1431 /* This is used by the PCI hotplug driver to allocate resource 1432 * of newly plugged busses. We can try to consolidate with the 1433 * rest of the code later, for now, keep it as-is as our main 1434 * resource allocation function doesn't deal with sub-trees yet. 1435 */ 1436 void pcibios_claim_one_bus(struct pci_bus *bus) 1437 { 1438 struct pci_dev *dev; 1439 struct pci_bus *child_bus; 1440 1441 list_for_each_entry(dev, &bus->devices, bus_list) { 1442 int i; 1443 1444 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1445 struct resource *r = &dev->resource[i]; 1446 1447 if (r->parent || !r->start || !r->flags) 1448 continue; 1449 1450 pr_debug("PCI: Claiming %s: " 1451 "Resource %d: %016llx..%016llx [%x]\n", 1452 pci_name(dev), i, 1453 (unsigned long long)r->start, 1454 (unsigned long long)r->end, 1455 (unsigned int)r->flags); 1456 1457 pci_claim_resource(dev, i); 1458 } 1459 } 1460 1461 list_for_each_entry(child_bus, &bus->children, node) 1462 pcibios_claim_one_bus(child_bus); 1463 } 1464 1465 1466 /* pcibios_finish_adding_to_bus 1467 * 1468 * This is to be called by the hotplug code after devices have been 1469 * added to a bus, this include calling it for a PHB that is just 1470 * being added 1471 */ 1472 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1473 { 1474 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1475 pci_domain_nr(bus), bus->number); 1476 1477 /* Allocate bus and devices resources */ 1478 pcibios_allocate_bus_resources(bus); 1479 pcibios_claim_one_bus(bus); 1480 1481 /* Add new devices to global lists. Register in proc, sysfs. */ 1482 pci_bus_add_devices(bus); 1483 1484 /* Fixup EEH */ 1485 eeh_add_device_tree_late(bus); 1486 } 1487 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1488 1489 int pcibios_enable_device(struct pci_dev *dev, int mask) 1490 { 1491 if (ppc_md.pcibios_enable_device_hook) 1492 if (ppc_md.pcibios_enable_device_hook(dev)) 1493 return -EINVAL; 1494 1495 return pci_enable_resources(dev, mask); 1496 } 1497 1498 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1499 { 1500 return (unsigned long) hose->io_base_virt - _IO_BASE; 1501 } 1502 1503 static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources) 1504 { 1505 struct resource *res; 1506 int i; 1507 1508 /* Hookup PHB IO resource */ 1509 res = &hose->io_resource; 1510 1511 if (!res->flags) { 1512 printk(KERN_WARNING "PCI: I/O resource not set for host" 1513 " bridge %s (domain %d)\n", 1514 hose->dn->full_name, hose->global_number); 1515 #ifdef CONFIG_PPC32 1516 /* Workaround for lack of IO resource only on 32-bit */ 1517 res->start = (unsigned long)hose->io_base_virt - isa_io_base; 1518 res->end = res->start + IO_SPACE_LIMIT; 1519 res->flags = IORESOURCE_IO; 1520 #endif /* CONFIG_PPC32 */ 1521 } 1522 1523 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", 1524 (unsigned long long)res->start, 1525 (unsigned long long)res->end, 1526 (unsigned long)res->flags); 1527 pci_add_resource_offset(resources, res, pcibios_io_space_offset(hose)); 1528 1529 /* Hookup PHB Memory resources */ 1530 for (i = 0; i < 3; ++i) { 1531 res = &hose->mem_resources[i]; 1532 if (!res->flags) { 1533 if (i > 0) 1534 continue; 1535 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1536 "host bridge %s (domain %d)\n", 1537 hose->dn->full_name, hose->global_number); 1538 #ifdef CONFIG_PPC32 1539 /* Workaround for lack of MEM resource only on 32-bit */ 1540 res->start = hose->pci_mem_offset; 1541 res->end = (resource_size_t)-1LL; 1542 res->flags = IORESOURCE_MEM; 1543 #endif /* CONFIG_PPC32 */ 1544 } 1545 1546 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, 1547 (unsigned long long)res->start, 1548 (unsigned long long)res->end, 1549 (unsigned long)res->flags); 1550 pci_add_resource_offset(resources, res, hose->pci_mem_offset); 1551 } 1552 1553 pr_debug("PCI: PHB MEM offset = %016llx\n", 1554 (unsigned long long)hose->pci_mem_offset); 1555 pr_debug("PCI: PHB IO offset = %08lx\n", 1556 (unsigned long)hose->io_base_virt - _IO_BASE); 1557 1558 } 1559 1560 /* 1561 * Null PCI config access functions, for the case when we can't 1562 * find a hose. 1563 */ 1564 #define NULL_PCI_OP(rw, size, type) \ 1565 static int \ 1566 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1567 { \ 1568 return PCIBIOS_DEVICE_NOT_FOUND; \ 1569 } 1570 1571 static int 1572 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1573 int len, u32 *val) 1574 { 1575 return PCIBIOS_DEVICE_NOT_FOUND; 1576 } 1577 1578 static int 1579 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1580 int len, u32 val) 1581 { 1582 return PCIBIOS_DEVICE_NOT_FOUND; 1583 } 1584 1585 static struct pci_ops null_pci_ops = 1586 { 1587 .read = null_read_config, 1588 .write = null_write_config, 1589 }; 1590 1591 /* 1592 * These functions are used early on before PCI scanning is done 1593 * and all of the pci_dev and pci_bus structures have been created. 1594 */ 1595 static struct pci_bus * 1596 fake_pci_bus(struct pci_controller *hose, int busnr) 1597 { 1598 static struct pci_bus bus; 1599 1600 if (hose == 0) { 1601 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1602 } 1603 bus.number = busnr; 1604 bus.sysdata = hose; 1605 bus.ops = hose? hose->ops: &null_pci_ops; 1606 return &bus; 1607 } 1608 1609 #define EARLY_PCI_OP(rw, size, type) \ 1610 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1611 int devfn, int offset, type value) \ 1612 { \ 1613 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1614 devfn, offset, value); \ 1615 } 1616 1617 EARLY_PCI_OP(read, byte, u8 *) 1618 EARLY_PCI_OP(read, word, u16 *) 1619 EARLY_PCI_OP(read, dword, u32 *) 1620 EARLY_PCI_OP(write, byte, u8) 1621 EARLY_PCI_OP(write, word, u16) 1622 EARLY_PCI_OP(write, dword, u32) 1623 1624 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1625 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1626 int cap) 1627 { 1628 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1629 } 1630 1631 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1632 { 1633 struct pci_controller *hose = bus->sysdata; 1634 1635 return of_node_get(hose->dn); 1636 } 1637 1638 /** 1639 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1640 * @hose: Pointer to the PCI host controller instance structure 1641 */ 1642 void __devinit pcibios_scan_phb(struct pci_controller *hose) 1643 { 1644 LIST_HEAD(resources); 1645 struct pci_bus *bus; 1646 struct device_node *node = hose->dn; 1647 int mode; 1648 1649 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); 1650 1651 /* Get some IO space for the new PHB */ 1652 pcibios_setup_phb_io_space(hose); 1653 1654 /* Wire up PHB bus resources */ 1655 pcibios_setup_phb_resources(hose, &resources); 1656 1657 hose->busn.start = hose->first_busno; 1658 hose->busn.end = hose->last_busno; 1659 hose->busn.flags = IORESOURCE_BUS; 1660 pci_add_resource(&resources, &hose->busn); 1661 1662 /* Create an empty bus for the toplevel */ 1663 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1664 hose->ops, hose, &resources); 1665 if (bus == NULL) { 1666 pr_err("Failed to create bus for PCI domain %04x\n", 1667 hose->global_number); 1668 pci_free_resource_list(&resources); 1669 return; 1670 } 1671 hose->bus = bus; 1672 1673 /* Get probe mode and perform scan */ 1674 mode = PCI_PROBE_NORMAL; 1675 if (node && ppc_md.pci_probe_mode) 1676 mode = ppc_md.pci_probe_mode(bus); 1677 pr_debug(" probe mode: %d\n", mode); 1678 if (mode == PCI_PROBE_DEVTREE) 1679 of_scan_bus(node, bus); 1680 1681 if (mode == PCI_PROBE_NORMAL) { 1682 pci_bus_update_busn_res_end(bus, 255); 1683 hose->last_busno = pci_scan_child_bus(bus); 1684 pci_bus_update_busn_res_end(bus, hose->last_busno); 1685 } 1686 1687 /* Platform gets a chance to do some global fixups before 1688 * we proceed to resource allocation 1689 */ 1690 if (ppc_md.pcibios_fixup_phb) 1691 ppc_md.pcibios_fixup_phb(hose); 1692 1693 /* Configure PCI Express settings */ 1694 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1695 struct pci_bus *child; 1696 list_for_each_entry(child, &bus->children, node) { 1697 struct pci_dev *self = child->self; 1698 if (!self) 1699 continue; 1700 pcie_bus_configure_settings(child, self->pcie_mpss); 1701 } 1702 } 1703 } 1704 1705 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1706 { 1707 int i, class = dev->class >> 8; 1708 /* When configured as agent, programing interface = 1 */ 1709 int prog_if = dev->class & 0xf; 1710 1711 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1712 class == PCI_CLASS_BRIDGE_OTHER) && 1713 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1714 (prog_if == 0) && 1715 (dev->bus->parent == NULL)) { 1716 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1717 dev->resource[i].start = 0; 1718 dev->resource[i].end = 0; 1719 dev->resource[i].flags = 0; 1720 } 1721 } 1722 } 1723 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1724 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1725