1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * This file contains miscellaneous low-level functions. 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * 6 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) 7 * and Paul Mackerras. 8 * 9 * kexec bits: 10 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com> 11 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz 12 * PPC44x port. Copyright (C) 2011, IBM Corporation 13 * Author: Suzuki Poulose <suzuki@in.ibm.com> 14 */ 15 16#include <linux/sys.h> 17#include <asm/unistd.h> 18#include <asm/errno.h> 19#include <asm/reg.h> 20#include <asm/page.h> 21#include <asm/cache.h> 22#include <asm/cputable.h> 23#include <asm/mmu.h> 24#include <asm/ppc_asm.h> 25#include <asm/thread_info.h> 26#include <asm/asm-offsets.h> 27#include <asm/processor.h> 28#include <asm/kexec.h> 29#include <asm/bug.h> 30#include <asm/ptrace.h> 31#include <asm/export.h> 32#include <asm/feature-fixups.h> 33 34 .text 35 36/* 37 * We store the saved ksp_limit in the unused part 38 * of the STACK_FRAME_OVERHEAD 39 */ 40_GLOBAL(call_do_softirq) 41 mflr r0 42 stw r0,4(r1) 43 lwz r10,THREAD+KSP_LIMIT(r2) 44 stw r3, THREAD+KSP_LIMIT(r2) 45 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3) 46 mr r1,r3 47 stw r10,8(r1) 48 bl __do_softirq 49 lwz r10,8(r1) 50 lwz r1,0(r1) 51 lwz r0,4(r1) 52 stw r10,THREAD+KSP_LIMIT(r2) 53 mtlr r0 54 blr 55 56/* 57 * void call_do_irq(struct pt_regs *regs, void *sp); 58 */ 59_GLOBAL(call_do_irq) 60 mflr r0 61 stw r0,4(r1) 62 lwz r10,THREAD+KSP_LIMIT(r2) 63 stw r4, THREAD+KSP_LIMIT(r2) 64 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4) 65 mr r1,r4 66 stw r10,8(r1) 67 bl __do_irq 68 lwz r10,8(r1) 69 lwz r1,0(r1) 70 lwz r0,4(r1) 71 stw r10,THREAD+KSP_LIMIT(r2) 72 mtlr r0 73 blr 74 75/* 76 * This returns the high 64 bits of the product of two 64-bit numbers. 77 */ 78_GLOBAL(mulhdu) 79 cmpwi r6,0 80 cmpwi cr1,r3,0 81 mr r10,r4 82 mulhwu r4,r4,r5 83 beq 1f 84 mulhwu r0,r10,r6 85 mullw r7,r10,r5 86 addc r7,r0,r7 87 addze r4,r4 881: beqlr cr1 /* all done if high part of A is 0 */ 89 mullw r9,r3,r5 90 mulhwu r10,r3,r5 91 beq 2f 92 mullw r0,r3,r6 93 mulhwu r8,r3,r6 94 addc r7,r0,r7 95 adde r4,r4,r8 96 addze r10,r10 972: addc r4,r4,r9 98 addze r3,r10 99 blr 100 101/* 102 * reloc_got2 runs through the .got2 section adding an offset 103 * to each entry. 104 */ 105_GLOBAL(reloc_got2) 106 mflr r11 107 lis r7,__got2_start@ha 108 addi r7,r7,__got2_start@l 109 lis r8,__got2_end@ha 110 addi r8,r8,__got2_end@l 111 subf r8,r7,r8 112 srwi. r8,r8,2 113 beqlr 114 mtctr r8 115 bl 1f 1161: mflr r0 117 lis r4,1b@ha 118 addi r4,r4,1b@l 119 subf r0,r4,r0 120 add r7,r0,r7 1212: lwz r0,0(r7) 122 add r0,r0,r3 123 stw r0,0(r7) 124 addi r7,r7,4 125 bdnz 2b 126 mtlr r11 127 blr 128 129/* 130 * call_setup_cpu - call the setup_cpu function for this cpu 131 * r3 = data offset, r24 = cpu number 132 * 133 * Setup function is called with: 134 * r3 = data offset 135 * r4 = ptr to CPU spec (relocated) 136 */ 137_GLOBAL(call_setup_cpu) 138 addis r4,r3,cur_cpu_spec@ha 139 addi r4,r4,cur_cpu_spec@l 140 lwz r4,0(r4) 141 add r4,r4,r3 142 lwz r5,CPU_SPEC_SETUP(r4) 143 cmpwi 0,r5,0 144 add r5,r5,r3 145 beqlr 146 mtctr r5 147 bctr 148 149#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_PPC_BOOK3S_32) 150 151/* This gets called by via-pmu.c to switch the PLL selection 152 * on 750fx CPU. This function should really be moved to some 153 * other place (as most of the cpufreq code in via-pmu 154 */ 155_GLOBAL(low_choose_750fx_pll) 156 /* Clear MSR:EE */ 157 mfmsr r7 158 rlwinm r0,r7,0,17,15 159 mtmsr r0 160 161 /* If switching to PLL1, disable HID0:BTIC */ 162 cmplwi cr0,r3,0 163 beq 1f 164 mfspr r5,SPRN_HID0 165 rlwinm r5,r5,0,27,25 166 sync 167 mtspr SPRN_HID0,r5 168 isync 169 sync 170 1711: 172 /* Calc new HID1 value */ 173 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ 174 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ 175 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ 176 or r4,r4,r5 177 mtspr SPRN_HID1,r4 178 179#ifdef CONFIG_SMP 180 /* Store new HID1 image */ 181 lwz r6,TASK_CPU(r2) 182 slwi r6,r6,2 183#else 184 li r6, 0 185#endif 186 addis r6,r6,nap_save_hid1@ha 187 stw r4,nap_save_hid1@l(r6) 188 189 /* If switching to PLL0, enable HID0:BTIC */ 190 cmplwi cr0,r3,0 191 bne 1f 192 mfspr r5,SPRN_HID0 193 ori r5,r5,HID0_BTIC 194 sync 195 mtspr SPRN_HID0,r5 196 isync 197 sync 198 1991: 200 /* Return */ 201 mtmsr r7 202 blr 203 204_GLOBAL(low_choose_7447a_dfs) 205 /* Clear MSR:EE */ 206 mfmsr r7 207 rlwinm r0,r7,0,17,15 208 mtmsr r0 209 210 /* Calc new HID1 value */ 211 mfspr r4,SPRN_HID1 212 insrwi r4,r3,1,9 /* insert parameter into bit 9 */ 213 sync 214 mtspr SPRN_HID1,r4 215 sync 216 isync 217 218 /* Return */ 219 mtmsr r7 220 blr 221 222#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_PPC_BOOK3S_32 */ 223 224/* 225 * complement mask on the msr then "or" some values on. 226 * _nmask_and_or_msr(nmask, value_to_or) 227 */ 228_GLOBAL(_nmask_and_or_msr) 229 mfmsr r0 /* Get current msr */ 230 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ 231 or r0,r0,r4 /* Or on the bits in r4 (second parm) */ 232 SYNC /* Some chip revs have problems here... */ 233 mtmsr r0 /* Update machine state */ 234 isync 235 blr /* Done */ 236 237#ifdef CONFIG_40x 238 239/* 240 * Do an IO access in real mode 241 */ 242_GLOBAL(real_readb) 243 mfmsr r7 244 rlwinm r0,r7,0,~MSR_DR 245 sync 246 mtmsr r0 247 sync 248 isync 249 lbz r3,0(r3) 250 sync 251 mtmsr r7 252 sync 253 isync 254 blr 255 256 /* 257 * Do an IO access in real mode 258 */ 259_GLOBAL(real_writeb) 260 mfmsr r7 261 rlwinm r0,r7,0,~MSR_DR 262 sync 263 mtmsr r0 264 sync 265 isync 266 stb r3,0(r4) 267 sync 268 mtmsr r7 269 sync 270 isync 271 blr 272 273#endif /* CONFIG_40x */ 274 275 276/* 277 * Flush instruction cache. 278 * This is a no-op on the 601. 279 */ 280#ifndef CONFIG_PPC_8xx 281_GLOBAL(flush_instruction_cache) 282#if defined(CONFIG_4xx) 283#ifdef CONFIG_403GCX 284 li r3, 512 285 mtctr r3 286 lis r4, KERNELBASE@h 2871: iccci 0, r4 288 addi r4, r4, 16 289 bdnz 1b 290#else 291 lis r3, KERNELBASE@h 292 iccci 0,r3 293#endif 294#elif defined(CONFIG_FSL_BOOKE) 295BEGIN_FTR_SECTION 296 mfspr r3,SPRN_L1CSR0 297 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC 298 /* msync; isync recommended here */ 299 mtspr SPRN_L1CSR0,r3 300 isync 301 blr 302END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) 303 mfspr r3,SPRN_L1CSR1 304 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR 305 mtspr SPRN_L1CSR1,r3 306#else 307 mfspr r3,SPRN_PVR 308 rlwinm r3,r3,16,16,31 309 cmpwi 0,r3,1 310 beqlr /* for 601, do nothing */ 311 /* 603/604 processor - use invalidate-all bit in HID0 */ 312 mfspr r3,SPRN_HID0 313 ori r3,r3,HID0_ICFI 314 mtspr SPRN_HID0,r3 315#endif /* CONFIG_4xx */ 316 isync 317 blr 318EXPORT_SYMBOL(flush_instruction_cache) 319#endif /* CONFIG_PPC_8xx */ 320 321/* 322 * Write any modified data cache blocks out to memory 323 * and invalidate the corresponding instruction cache blocks. 324 * This is a no-op on the 601. 325 * 326 * flush_icache_range(unsigned long start, unsigned long stop) 327 */ 328_GLOBAL(flush_icache_range) 329BEGIN_FTR_SECTION 330 PURGE_PREFETCHED_INS 331 blr /* for 601, do nothing */ 332END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 333 rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT 334 subf r4,r3,r4 335 addi r4,r4,L1_CACHE_BYTES - 1 336 srwi. r4,r4,L1_CACHE_SHIFT 337 beqlr 338 mtctr r4 339 mr r6,r3 3401: dcbst 0,r3 341 addi r3,r3,L1_CACHE_BYTES 342 bdnz 1b 343 sync /* wait for dcbst's to get to ram */ 344#ifndef CONFIG_44x 345 mtctr r4 3462: icbi 0,r6 347 addi r6,r6,L1_CACHE_BYTES 348 bdnz 2b 349#else 350 /* Flash invalidate on 44x because we are passed kmapped addresses and 351 this doesn't work for userspace pages due to the virtually tagged 352 icache. Sigh. */ 353 iccci 0, r0 354#endif 355 sync /* additional sync needed on g4 */ 356 isync 357 blr 358_ASM_NOKPROBE_SYMBOL(flush_icache_range) 359EXPORT_SYMBOL(flush_icache_range) 360 361/* 362 * Flush a particular page from the data cache to RAM. 363 * Note: this is necessary because the instruction cache does *not* 364 * snoop from the data cache. 365 * This is a no-op on the 601 which has a unified cache. 366 * 367 * void __flush_dcache_icache(void *page) 368 */ 369_GLOBAL(__flush_dcache_icache) 370BEGIN_FTR_SECTION 371 PURGE_PREFETCHED_INS 372 blr 373END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 374 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */ 375 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */ 376 mtctr r4 377 mr r6,r3 3780: dcbst 0,r3 /* Write line to ram */ 379 addi r3,r3,L1_CACHE_BYTES 380 bdnz 0b 381 sync 382#ifdef CONFIG_44x 383 /* We don't flush the icache on 44x. Those have a virtual icache 384 * and we don't have access to the virtual address here (it's 385 * not the page vaddr but where it's mapped in user space). The 386 * flushing of the icache on these is handled elsewhere, when 387 * a change in the address space occurs, before returning to 388 * user space 389 */ 390BEGIN_MMU_FTR_SECTION 391 blr 392END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x) 393#endif /* CONFIG_44x */ 394 mtctr r4 3951: icbi 0,r6 396 addi r6,r6,L1_CACHE_BYTES 397 bdnz 1b 398 sync 399 isync 400 blr 401 402#ifndef CONFIG_BOOKE 403/* 404 * Flush a particular page from the data cache to RAM, identified 405 * by its physical address. We turn off the MMU so we can just use 406 * the physical address (this may be a highmem page without a kernel 407 * mapping). 408 * 409 * void __flush_dcache_icache_phys(unsigned long physaddr) 410 */ 411_GLOBAL(__flush_dcache_icache_phys) 412BEGIN_FTR_SECTION 413 PURGE_PREFETCHED_INS 414 blr /* for 601, do nothing */ 415END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 416 mfmsr r10 417 rlwinm r0,r10,0,28,26 /* clear DR */ 418 mtmsr r0 419 isync 420 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */ 421 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */ 422 mtctr r4 423 mr r6,r3 4240: dcbst 0,r3 /* Write line to ram */ 425 addi r3,r3,L1_CACHE_BYTES 426 bdnz 0b 427 sync 428 mtctr r4 4291: icbi 0,r6 430 addi r6,r6,L1_CACHE_BYTES 431 bdnz 1b 432 sync 433 mtmsr r10 /* restore DR */ 434 isync 435 blr 436#endif /* CONFIG_BOOKE */ 437 438/* 439 * Copy a whole page. We use the dcbz instruction on the destination 440 * to reduce memory traffic (it eliminates the unnecessary reads of 441 * the destination into cache). This requires that the destination 442 * is cacheable. 443 */ 444#define COPY_16_BYTES \ 445 lwz r6,4(r4); \ 446 lwz r7,8(r4); \ 447 lwz r8,12(r4); \ 448 lwzu r9,16(r4); \ 449 stw r6,4(r3); \ 450 stw r7,8(r3); \ 451 stw r8,12(r3); \ 452 stwu r9,16(r3) 453 454_GLOBAL(copy_page) 455 rlwinm r5, r3, 0, L1_CACHE_BYTES - 1 456 addi r3,r3,-4 457 4580: twnei r5, 0 /* WARN if r3 is not cache aligned */ 459 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING 460 461 addi r4,r4,-4 462 463 li r5,4 464 465#if MAX_COPY_PREFETCH > 1 466 li r0,MAX_COPY_PREFETCH 467 li r11,4 468 mtctr r0 46911: dcbt r11,r4 470 addi r11,r11,L1_CACHE_BYTES 471 bdnz 11b 472#else /* MAX_COPY_PREFETCH == 1 */ 473 dcbt r5,r4 474 li r11,L1_CACHE_BYTES+4 475#endif /* MAX_COPY_PREFETCH */ 476 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH 477 crclr 4*cr0+eq 4782: 479 mtctr r0 4801: 481 dcbt r11,r4 482 dcbz r5,r3 483 COPY_16_BYTES 484#if L1_CACHE_BYTES >= 32 485 COPY_16_BYTES 486#if L1_CACHE_BYTES >= 64 487 COPY_16_BYTES 488 COPY_16_BYTES 489#if L1_CACHE_BYTES >= 128 490 COPY_16_BYTES 491 COPY_16_BYTES 492 COPY_16_BYTES 493 COPY_16_BYTES 494#endif 495#endif 496#endif 497 bdnz 1b 498 beqlr 499 crnot 4*cr0+eq,4*cr0+eq 500 li r0,MAX_COPY_PREFETCH 501 li r11,4 502 b 2b 503EXPORT_SYMBOL(copy_page) 504 505/* 506 * Extended precision shifts. 507 * 508 * Updated to be valid for shift counts from 0 to 63 inclusive. 509 * -- Gabriel 510 * 511 * R3/R4 has 64 bit value 512 * R5 has shift count 513 * result in R3/R4 514 * 515 * ashrdi3: arithmetic right shift (sign propagation) 516 * lshrdi3: logical right shift 517 * ashldi3: left shift 518 */ 519_GLOBAL(__ashrdi3) 520 subfic r6,r5,32 521 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 522 addi r7,r5,32 # could be xori, or addi with -32 523 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 524 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 525 sraw r7,r3,r7 # t2 = MSW >> (count-32) 526 or r4,r4,r6 # LSW |= t1 527 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 528 sraw r3,r3,r5 # MSW = MSW >> count 529 or r4,r4,r7 # LSW |= t2 530 blr 531EXPORT_SYMBOL(__ashrdi3) 532 533_GLOBAL(__ashldi3) 534 subfic r6,r5,32 535 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count 536 addi r7,r5,32 # could be xori, or addi with -32 537 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) 538 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) 539 or r3,r3,r6 # MSW |= t1 540 slw r4,r4,r5 # LSW = LSW << count 541 or r3,r3,r7 # MSW |= t2 542 blr 543EXPORT_SYMBOL(__ashldi3) 544 545_GLOBAL(__lshrdi3) 546 subfic r6,r5,32 547 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 548 addi r7,r5,32 # could be xori, or addi with -32 549 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 550 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) 551 or r4,r4,r6 # LSW |= t1 552 srw r3,r3,r5 # MSW = MSW >> count 553 or r4,r4,r7 # LSW |= t2 554 blr 555EXPORT_SYMBOL(__lshrdi3) 556 557/* 558 * 64-bit comparison: __cmpdi2(s64 a, s64 b) 559 * Returns 0 if a < b, 1 if a == b, 2 if a > b. 560 */ 561_GLOBAL(__cmpdi2) 562 cmpw r3,r5 563 li r3,1 564 bne 1f 565 cmplw r4,r6 566 beqlr 5671: li r3,0 568 bltlr 569 li r3,2 570 blr 571EXPORT_SYMBOL(__cmpdi2) 572/* 573 * 64-bit comparison: __ucmpdi2(u64 a, u64 b) 574 * Returns 0 if a < b, 1 if a == b, 2 if a > b. 575 */ 576_GLOBAL(__ucmpdi2) 577 cmplw r3,r5 578 li r3,1 579 bne 1f 580 cmplw r4,r6 581 beqlr 5821: li r3,0 583 bltlr 584 li r3,2 585 blr 586EXPORT_SYMBOL(__ucmpdi2) 587 588_GLOBAL(__bswapdi2) 589 rotlwi r9,r4,8 590 rotlwi r10,r3,8 591 rlwimi r9,r4,24,0,7 592 rlwimi r10,r3,24,0,7 593 rlwimi r9,r4,24,16,23 594 rlwimi r10,r3,24,16,23 595 mr r3,r9 596 mr r4,r10 597 blr 598EXPORT_SYMBOL(__bswapdi2) 599 600#ifdef CONFIG_SMP 601_GLOBAL(start_secondary_resume) 602 /* Reset stack */ 603 rlwinm r1, r1, 0, 0, 31 - THREAD_SHIFT 604 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 605 li r3,0 606 stw r3,0(r1) /* Zero the stack frame pointer */ 607 bl start_secondary 608 b . 609#endif /* CONFIG_SMP */ 610 611/* 612 * This routine is just here to keep GCC happy - sigh... 613 */ 614_GLOBAL(__main) 615 blr 616 617#ifdef CONFIG_KEXEC_CORE 618 /* 619 * Must be relocatable PIC code callable as a C function. 620 */ 621 .globl relocate_new_kernel 622relocate_new_kernel: 623 /* r3 = page_list */ 624 /* r4 = reboot_code_buffer */ 625 /* r5 = start_address */ 626 627#ifdef CONFIG_FSL_BOOKE 628 629 mr r29, r3 630 mr r30, r4 631 mr r31, r5 632 633#define ENTRY_MAPPING_KEXEC_SETUP 634#include "fsl_booke_entry_mapping.S" 635#undef ENTRY_MAPPING_KEXEC_SETUP 636 637 mr r3, r29 638 mr r4, r30 639 mr r5, r31 640 641 li r0, 0 642#elif defined(CONFIG_44x) 643 644 /* Save our parameters */ 645 mr r29, r3 646 mr r30, r4 647 mr r31, r5 648 649#ifdef CONFIG_PPC_47x 650 /* Check for 47x cores */ 651 mfspr r3,SPRN_PVR 652 srwi r3,r3,16 653 cmplwi cr0,r3,PVR_476FPE@h 654 beq setup_map_47x 655 cmplwi cr0,r3,PVR_476@h 656 beq setup_map_47x 657 cmplwi cr0,r3,PVR_476_ISS@h 658 beq setup_map_47x 659#endif /* CONFIG_PPC_47x */ 660 661/* 662 * Code for setting up 1:1 mapping for PPC440x for KEXEC 663 * 664 * We cannot switch off the MMU on PPC44x. 665 * So we: 666 * 1) Invalidate all the mappings except the one we are running from. 667 * 2) Create a tmp mapping for our code in the other address space(TS) and 668 * jump to it. Invalidate the entry we started in. 669 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS. 670 * 4) Jump to the 1:1 mapping in original TS. 671 * 5) Invalidate the tmp mapping. 672 * 673 * - Based on the kexec support code for FSL BookE 674 * 675 */ 676 677 /* 678 * Load the PID with kernel PID (0). 679 * Also load our MSR_IS and TID to MMUCR for TLB search. 680 */ 681 li r3, 0 682 mtspr SPRN_PID, r3 683 mfmsr r4 684 andi. r4,r4,MSR_IS@l 685 beq wmmucr 686 oris r3,r3,PPC44x_MMUCR_STS@h 687wmmucr: 688 mtspr SPRN_MMUCR,r3 689 sync 690 691 /* 692 * Invalidate all the TLB entries except the current entry 693 * where we are running from 694 */ 695 bl 0f /* Find our address */ 6960: mflr r5 /* Make it accessible */ 697 tlbsx r23,0,r5 /* Find entry we are in */ 698 li r4,0 /* Start at TLB entry 0 */ 699 li r3,0 /* Set PAGEID inval value */ 7001: cmpw r23,r4 /* Is this our entry? */ 701 beq skip /* If so, skip the inval */ 702 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ 703skip: 704 addi r4,r4,1 /* Increment */ 705 cmpwi r4,64 /* Are we done? */ 706 bne 1b /* If not, repeat */ 707 isync 708 709 /* Create a temp mapping and jump to it */ 710 andi. r6, r23, 1 /* Find the index to use */ 711 addi r24, r6, 1 /* r24 will contain 1 or 2 */ 712 713 mfmsr r9 /* get the MSR */ 714 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */ 715 xori r7, r5, 1 /* Use the other address space */ 716 717 /* Read the current mapping entries */ 718 tlbre r3, r23, PPC44x_TLB_PAGEID 719 tlbre r4, r23, PPC44x_TLB_XLAT 720 tlbre r5, r23, PPC44x_TLB_ATTRIB 721 722 /* Save our current XLAT entry */ 723 mr r25, r4 724 725 /* Extract the TLB PageSize */ 726 li r10, 1 /* r10 will hold PageSize */ 727 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */ 728 729 /* XXX: As of now we use 256M, 4K pages */ 730 cmpwi r11, PPC44x_TLB_256M 731 bne tlb_4k 732 rotlwi r10, r10, 28 /* r10 = 256M */ 733 b write_out 734tlb_4k: 735 cmpwi r11, PPC44x_TLB_4K 736 bne default 737 rotlwi r10, r10, 12 /* r10 = 4K */ 738 b write_out 739default: 740 rotlwi r10, r10, 10 /* r10 = 1K */ 741 742write_out: 743 /* 744 * Write out the tmp 1:1 mapping for this code in other address space 745 * Fixup EPN = RPN , TS=other address space 746 */ 747 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */ 748 749 /* Write out the tmp mapping entries */ 750 tlbwe r3, r24, PPC44x_TLB_PAGEID 751 tlbwe r4, r24, PPC44x_TLB_XLAT 752 tlbwe r5, r24, PPC44x_TLB_ATTRIB 753 754 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */ 755 not r10, r11 /* Mask for PageNum */ 756 757 /* Switch to other address space in MSR */ 758 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ 759 760 bl 1f 7611: mflr r8 762 addi r8, r8, (2f-1b) /* Find the target offset */ 763 764 /* Jump to the tmp mapping */ 765 mtspr SPRN_SRR0, r8 766 mtspr SPRN_SRR1, r9 767 rfi 768 7692: 770 /* Invalidate the entry we were executing from */ 771 li r3, 0 772 tlbwe r3, r23, PPC44x_TLB_PAGEID 773 774 /* attribute fields. rwx for SUPERVISOR mode */ 775 li r5, 0 776 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) 777 778 /* Create 1:1 mapping in 256M pages */ 779 xori r7, r7, 1 /* Revert back to Original TS */ 780 781 li r8, 0 /* PageNumber */ 782 li r6, 3 /* TLB Index, start at 3 */ 783 784next_tlb: 785 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */ 786 mr r4, r3 /* RPN = EPN */ 787 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */ 788 insrwi r3, r7, 1, 23 /* Set TS from r7 */ 789 790 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */ 791 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */ 792 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */ 793 794 addi r8, r8, 1 /* Increment PN */ 795 addi r6, r6, 1 /* Increment TLB Index */ 796 cmpwi r8, 8 /* Are we done ? */ 797 bne next_tlb 798 isync 799 800 /* Jump to the new mapping 1:1 */ 801 li r9,0 802 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ 803 804 bl 1f 8051: mflr r8 806 and r8, r8, r11 /* Get our offset within page */ 807 addi r8, r8, (2f-1b) 808 809 and r5, r25, r10 /* Get our target PageNum */ 810 or r8, r8, r5 /* Target jump address */ 811 812 mtspr SPRN_SRR0, r8 813 mtspr SPRN_SRR1, r9 814 rfi 8152: 816 /* Invalidate the tmp entry we used */ 817 li r3, 0 818 tlbwe r3, r24, PPC44x_TLB_PAGEID 819 sync 820 b ppc44x_map_done 821 822#ifdef CONFIG_PPC_47x 823 824 /* 1:1 mapping for 47x */ 825 826setup_map_47x: 827 828 /* 829 * Load the kernel pid (0) to PID and also to MMUCR[TID]. 830 * Also set the MSR IS->MMUCR STS 831 */ 832 li r3, 0 833 mtspr SPRN_PID, r3 /* Set PID */ 834 mfmsr r4 /* Get MSR */ 835 andi. r4, r4, MSR_IS@l /* TS=1? */ 836 beq 1f /* If not, leave STS=0 */ 837 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */ 8381: mtspr SPRN_MMUCR, r3 /* Put MMUCR */ 839 sync 840 841 /* Find the entry we are running from */ 842 bl 2f 8432: mflr r23 844 tlbsx r23, 0, r23 845 tlbre r24, r23, 0 /* TLB Word 0 */ 846 tlbre r25, r23, 1 /* TLB Word 1 */ 847 tlbre r26, r23, 2 /* TLB Word 2 */ 848 849 850 /* 851 * Invalidates all the tlb entries by writing to 256 RPNs(r4) 852 * of 4k page size in all 4 ways (0-3 in r3). 853 * This would invalidate the entire UTLB including the one we are 854 * running from. However the shadow TLB entries would help us 855 * to continue the execution, until we flush them (rfi/isync). 856 */ 857 addis r3, 0, 0x8000 /* specify the way */ 858 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */ 859 addi r5, 0, 0 860 b clear_utlb_entry 861 862 /* Align the loop to speed things up. from head_44x.S */ 863 .align 6 864 865clear_utlb_entry: 866 867 tlbwe r4, r3, 0 868 tlbwe r5, r3, 1 869 tlbwe r5, r3, 2 870 addis r3, r3, 0x2000 /* Increment the way */ 871 cmpwi r3, 0 872 bne clear_utlb_entry 873 addis r3, 0, 0x8000 874 addis r4, r4, 0x100 /* Increment the EPN */ 875 cmpwi r4, 0 876 bne clear_utlb_entry 877 878 /* Create the entries in the other address space */ 879 mfmsr r5 880 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */ 881 xori r7, r7, 1 /* r7 = !TS */ 882 883 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */ 884 885 /* 886 * write out the TLB entries for the tmp mapping 887 * Use way '0' so that we could easily invalidate it later. 888 */ 889 lis r3, 0x8000 /* Way '0' */ 890 891 tlbwe r24, r3, 0 892 tlbwe r25, r3, 1 893 tlbwe r26, r3, 2 894 895 /* Update the msr to the new TS */ 896 insrwi r5, r7, 1, 26 897 898 bl 1f 8991: mflr r6 900 addi r6, r6, (2f-1b) 901 902 mtspr SPRN_SRR0, r6 903 mtspr SPRN_SRR1, r5 904 rfi 905 906 /* 907 * Now we are in the tmp address space. 908 * Create a 1:1 mapping for 0-2GiB in the original TS. 909 */ 9102: 911 li r3, 0 912 li r4, 0 /* TLB Word 0 */ 913 li r5, 0 /* TLB Word 1 */ 914 li r6, 0 915 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */ 916 917 li r8, 0 /* PageIndex */ 918 919 xori r7, r7, 1 /* revert back to original TS */ 920 921write_utlb: 922 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */ 923 /* ERPN = 0 as we don't use memory above 2G */ 924 925 mr r4, r5 /* EPN = RPN */ 926 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M) 927 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */ 928 929 tlbwe r4, r3, 0 /* Write out the entries */ 930 tlbwe r5, r3, 1 931 tlbwe r6, r3, 2 932 addi r8, r8, 1 933 cmpwi r8, 8 /* Have we completed ? */ 934 bne write_utlb 935 936 /* make sure we complete the TLB write up */ 937 isync 938 939 /* 940 * Prepare to jump to the 1:1 mapping. 941 * 1) Extract page size of the tmp mapping 942 * DSIZ = TLB_Word0[22:27] 943 * 2) Calculate the physical address of the address 944 * to jump to. 945 */ 946 rlwinm r10, r24, 0, 22, 27 947 948 cmpwi r10, PPC47x_TLB0_4K 949 bne 0f 950 li r10, 0x1000 /* r10 = 4k */ 951 bl 1f 952 9530: 954 /* Defaults to 256M */ 955 lis r10, 0x1000 956 957 bl 1f 9581: mflr r4 959 addi r4, r4, (2f-1b) /* virtual address of 2f */ 960 961 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */ 962 not r10, r11 /* Pagemask = ~(offsetmask) */ 963 964 and r5, r25, r10 /* Physical page */ 965 and r6, r4, r11 /* offset within the current page */ 966 967 or r5, r5, r6 /* Physical address for 2f */ 968 969 /* Switch the TS in MSR to the original one */ 970 mfmsr r8 971 insrwi r8, r7, 1, 26 972 973 mtspr SPRN_SRR1, r8 974 mtspr SPRN_SRR0, r5 975 rfi 976 9772: 978 /* Invalidate the tmp mapping */ 979 lis r3, 0x8000 /* Way '0' */ 980 981 clrrwi r24, r24, 12 /* Clear the valid bit */ 982 tlbwe r24, r3, 0 983 tlbwe r25, r3, 1 984 tlbwe r26, r3, 2 985 986 /* Make sure we complete the TLB write and flush the shadow TLB */ 987 isync 988 989#endif 990 991ppc44x_map_done: 992 993 994 /* Restore the parameters */ 995 mr r3, r29 996 mr r4, r30 997 mr r5, r31 998 999 li r0, 0 1000#else 1001 li r0, 0 1002 1003 /* 1004 * Set Machine Status Register to a known status, 1005 * switch the MMU off and jump to 1: in a single step. 1006 */ 1007 1008 mr r8, r0 1009 ori r8, r8, MSR_RI|MSR_ME 1010 mtspr SPRN_SRR1, r8 1011 addi r8, r4, 1f - relocate_new_kernel 1012 mtspr SPRN_SRR0, r8 1013 sync 1014 rfi 1015 10161: 1017#endif 1018 /* from this point address translation is turned off */ 1019 /* and interrupts are disabled */ 1020 1021 /* set a new stack at the bottom of our page... */ 1022 /* (not really needed now) */ 1023 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */ 1024 stw r0, 0(r1) 1025 1026 /* Do the copies */ 1027 li r6, 0 /* checksum */ 1028 mr r0, r3 1029 b 1f 1030 10310: /* top, read another word for the indirection page */ 1032 lwzu r0, 4(r3) 1033 10341: 1035 /* is it a destination page? (r8) */ 1036 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ 1037 beq 2f 1038 1039 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ 1040 b 0b 1041 10422: /* is it an indirection page? (r3) */ 1043 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ 1044 beq 2f 1045 1046 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ 1047 subi r3, r3, 4 1048 b 0b 1049 10502: /* are we done? */ 1051 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ 1052 beq 2f 1053 b 3f 1054 10552: /* is it a source page? (r9) */ 1056 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ 1057 beq 0b 1058 1059 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ 1060 1061 li r7, PAGE_SIZE / 4 1062 mtctr r7 1063 subi r9, r9, 4 1064 subi r8, r8, 4 10659: 1066 lwzu r0, 4(r9) /* do the copy */ 1067 xor r6, r6, r0 1068 stwu r0, 4(r8) 1069 dcbst 0, r8 1070 sync 1071 icbi 0, r8 1072 bdnz 9b 1073 1074 addi r9, r9, 4 1075 addi r8, r8, 4 1076 b 0b 1077 10783: 1079 1080 /* To be certain of avoiding problems with self-modifying code 1081 * execute a serializing instruction here. 1082 */ 1083 isync 1084 sync 1085 1086 mfspr r3, SPRN_PIR /* current core we are running on */ 1087 mr r4, r5 /* load physical address of chunk called */ 1088 1089 /* jump to the entry point, usually the setup routine */ 1090 mtlr r5 1091 blrl 1092 10931: b 1b 1094 1095relocate_new_kernel_end: 1096 1097 .globl relocate_new_kernel_size 1098relocate_new_kernel_size: 1099 .long relocate_new_kernel_end - relocate_new_kernel 1100#endif 1101