xref: /linux/arch/powerpc/kernel/misc_32.S (revision 8838a1a2d219a86ab05e679c73f68dd75a25aca5) 
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * This file contains miscellaneous low-level functions.
4 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 *
6 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras.
8 *
9 */
10
11#include <linux/export.h>
12#include <linux/sys.h>
13#include <asm/unistd.h>
14#include <asm/errno.h>
15#include <asm/reg.h>
16#include <asm/page.h>
17#include <asm/cache.h>
18#include <asm/cputable.h>
19#include <asm/mmu.h>
20#include <asm/ppc_asm.h>
21#include <asm/thread_info.h>
22#include <asm/asm-offsets.h>
23#include <asm/processor.h>
24#include <asm/bug.h>
25#include <asm/ptrace.h>
26#include <asm/feature-fixups.h>
27
28	.text
29
30/*
31 * reloc_got2 runs through the .got2 section adding an offset
32 * to each entry.
33 */
34_GLOBAL(reloc_got2)
35	mflr	r11
36	lis	r7,__got2_start@ha
37	addi	r7,r7,__got2_start@l
38	lis	r8,__got2_end@ha
39	addi	r8,r8,__got2_end@l
40	subf	r8,r7,r8
41	srwi.	r8,r8,2
42	beqlr
43	mtctr	r8
44	bcl	20,31,$+4
451:	mflr	r0
46	lis	r4,1b@ha
47	addi	r4,r4,1b@l
48	subf	r0,r4,r0
49	add	r7,r0,r7
502:	lwz	r0,0(r7)
51	add	r0,r0,r3
52	stw	r0,0(r7)
53	addi	r7,r7,4
54	bdnz	2b
55	mtlr	r11
56	blr
57
58/*
59 * call_setup_cpu - call the setup_cpu function for this cpu
60 * r3 = data offset, r24 = cpu number
61 *
62 * Setup function is called with:
63 *   r3 = data offset
64 *   r4 = ptr to CPU spec (relocated)
65 */
66_GLOBAL(call_setup_cpu)
67	addis	r4,r3,cur_cpu_spec@ha
68	addi	r4,r4,cur_cpu_spec@l
69	lwz	r4,0(r4)
70	add	r4,r4,r3
71	lwz	r5,CPU_SPEC_SETUP(r4)
72	cmpwi	0,r5,0
73	add	r5,r5,r3
74	beqlr
75	mtctr	r5
76	bctr
77
78#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_PPC_BOOK3S_32)
79
80/* This gets called by via-pmu.c to switch the PLL selection
81 * on 750fx CPU. This function should really be moved to some
82 * other place (as most of the cpufreq code in via-pmu
83 */
84_GLOBAL(low_choose_750fx_pll)
85	/* Clear MSR:EE */
86	mfmsr	r7
87	rlwinm	r0,r7,0,17,15
88	mtmsr	r0
89
90	/* If switching to PLL1, disable HID0:BTIC */
91	cmplwi	cr0,r3,0
92	beq	1f
93	mfspr	r5,SPRN_HID0
94	rlwinm	r5,r5,0,27,25
95	sync
96	mtspr	SPRN_HID0,r5
97	isync
98	sync
99
1001:
101	/* Calc new HID1 value */
102	mfspr	r4,SPRN_HID1	/* Build a HID1:PS bit from parameter */
103	rlwinm	r5,r3,16,15,15	/* Clear out HID1:PS from value read */
104	rlwinm	r4,r4,0,16,14	/* Could have I used rlwimi here ? */
105	or	r4,r4,r5
106	mtspr	SPRN_HID1,r4
107
108#ifdef CONFIG_SMP
109	/* Store new HID1 image */
110	lwz	r6,TASK_CPU(r2)
111	slwi	r6,r6,2
112#else
113	li	r6, 0
114#endif
115	addis	r6,r6,nap_save_hid1@ha
116	stw	r4,nap_save_hid1@l(r6)
117
118	/* If switching to PLL0, enable HID0:BTIC */
119	cmplwi	cr0,r3,0
120	bne	1f
121	mfspr	r5,SPRN_HID0
122	ori	r5,r5,HID0_BTIC
123	sync
124	mtspr	SPRN_HID0,r5
125	isync
126	sync
127
1281:
129	/* Return */
130	mtmsr	r7
131	blr
132
133_GLOBAL(low_choose_7447a_dfs)
134	/* Clear MSR:EE */
135	mfmsr	r7
136	rlwinm	r0,r7,0,17,15
137	mtmsr	r0
138
139	/* Calc new HID1 value */
140	mfspr	r4,SPRN_HID1
141	insrwi	r4,r3,1,9	/* insert parameter into bit 9 */
142	sync
143	mtspr	SPRN_HID1,r4
144	sync
145	isync
146
147	/* Return */
148	mtmsr	r7
149	blr
150
151#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_PPC_BOOK3S_32 */
152
153/*
154 * Copy a whole page.  We use the dcbz instruction on the destination
155 * to reduce memory traffic (it eliminates the unnecessary reads of
156 * the destination into cache).  This requires that the destination
157 * is cacheable.
158 */
159#define COPY_16_BYTES		\
160	lwz	r6,4(r4);	\
161	lwz	r7,8(r4);	\
162	lwz	r8,12(r4);	\
163	lwzu	r9,16(r4);	\
164	stw	r6,4(r3);	\
165	stw	r7,8(r3);	\
166	stw	r8,12(r3);	\
167	stwu	r9,16(r3)
168
169_GLOBAL(copy_page)
170	rlwinm	r5, r3, 0, L1_CACHE_BYTES - 1
171	addi	r3,r3,-4
172
1730:	twnei	r5, 0	/* WARN if r3 is not cache aligned */
174	EMIT_WARN_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
175
176	addi	r4,r4,-4
177
178	li	r5,4
179
180#if MAX_COPY_PREFETCH > 1
181	li	r0,MAX_COPY_PREFETCH
182	li	r11,4
183	mtctr	r0
18411:	dcbt	r11,r4
185	addi	r11,r11,L1_CACHE_BYTES
186	bdnz	11b
187#else /* MAX_COPY_PREFETCH == 1 */
188	dcbt	r5,r4
189	li	r11,L1_CACHE_BYTES+4
190#endif /* MAX_COPY_PREFETCH */
191	li	r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
192	crclr	4*cr0+eq
1932:
194	mtctr	r0
1951:
196	dcbt	r11,r4
197	dcbz	r5,r3
198	COPY_16_BYTES
199#if L1_CACHE_BYTES >= 32
200	COPY_16_BYTES
201#if L1_CACHE_BYTES >= 64
202	COPY_16_BYTES
203	COPY_16_BYTES
204#if L1_CACHE_BYTES >= 128
205	COPY_16_BYTES
206	COPY_16_BYTES
207	COPY_16_BYTES
208	COPY_16_BYTES
209#endif
210#endif
211#endif
212	bdnz	1b
213	beqlr
214	crnot	4*cr0+eq,4*cr0+eq
215	li	r0,MAX_COPY_PREFETCH
216	li	r11,4
217	b	2b
218EXPORT_SYMBOL(copy_page)
219
220/*
221 * Extended precision shifts.
222 *
223 * Updated to be valid for shift counts from 0 to 63 inclusive.
224 * -- Gabriel
225 *
226 * R3/R4 has 64 bit value
227 * R5    has shift count
228 * result in R3/R4
229 *
230 *  ashrdi3: arithmetic right shift (sign propagation)
231 *  lshrdi3: logical right shift
232 *  ashldi3: left shift
233 */
234_GLOBAL(__ashrdi3)
235	subfic	r6,r5,32
236	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
237	addi	r7,r5,32	# could be xori, or addi with -32
238	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
239	rlwinm	r8,r7,0,32	# t3 = (count < 32) ? 32 : 0
240	sraw	r7,r3,r7	# t2 = MSW >> (count-32)
241	or	r4,r4,r6	# LSW |= t1
242	slw	r7,r7,r8	# t2 = (count < 32) ? 0 : t2
243	sraw	r3,r3,r5	# MSW = MSW >> count
244	or	r4,r4,r7	# LSW |= t2
245	blr
246EXPORT_SYMBOL(__ashrdi3)
247
248_GLOBAL(__ashldi3)
249	subfic	r6,r5,32
250	slw	r3,r3,r5	# MSW = count > 31 ? 0 : MSW << count
251	addi	r7,r5,32	# could be xori, or addi with -32
252	srw	r6,r4,r6	# t1 = count > 31 ? 0 : LSW >> (32-count)
253	slw	r7,r4,r7	# t2 = count < 32 ? 0 : LSW << (count-32)
254	or	r3,r3,r6	# MSW |= t1
255	slw	r4,r4,r5	# LSW = LSW << count
256	or	r3,r3,r7	# MSW |= t2
257	blr
258EXPORT_SYMBOL(__ashldi3)
259
260_GLOBAL(__lshrdi3)
261	subfic	r6,r5,32
262	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
263	addi	r7,r5,32	# could be xori, or addi with -32
264	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
265	srw	r7,r3,r7	# t2 = count < 32 ? 0 : MSW >> (count-32)
266	or	r4,r4,r6	# LSW |= t1
267	srw	r3,r3,r5	# MSW = MSW >> count
268	or	r4,r4,r7	# LSW |= t2
269	blr
270EXPORT_SYMBOL(__lshrdi3)
271
272/*
273 * 64-bit comparison: __cmpdi2(s64 a, s64 b)
274 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
275 */
276_GLOBAL(__cmpdi2)
277	cmpw	r3,r5
278	li	r3,1
279	bne	1f
280	cmplw	r4,r6
281	beqlr
2821:	li	r3,0
283	bltlr
284	li	r3,2
285	blr
286EXPORT_SYMBOL(__cmpdi2)
287/*
288 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
289 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
290 */
291_GLOBAL(__ucmpdi2)
292	cmplw	r3,r5
293	li	r3,1
294	bne	1f
295	cmplw	r4,r6
296	beqlr
2971:	li	r3,0
298	bltlr
299	li	r3,2
300	blr
301EXPORT_SYMBOL(__ucmpdi2)
302
303_GLOBAL(__bswapdi2)
304	rotlwi  r9,r4,8
305	rotlwi  r10,r3,8
306	rlwimi  r9,r4,24,0,7
307	rlwimi  r10,r3,24,0,7
308	rlwimi  r9,r4,24,16,23
309	rlwimi  r10,r3,24,16,23
310	mr      r3,r9
311	mr      r4,r10
312	blr
313EXPORT_SYMBOL(__bswapdi2)
314
315#ifdef CONFIG_SMP
316_GLOBAL(start_secondary_resume)
317	/* Reset stack */
318	rlwinm	r1, r1, 0, 0, 31 - THREAD_SHIFT
319	addi	r1,r1,THREAD_SIZE-STACK_FRAME_MIN_SIZE
320	li	r3,0
321	stw	r3,0(r1)		/* Zero the stack frame pointer	*/
322	bl	start_secondary
323	b	.
324#endif /* CONFIG_SMP */
325