1/* 2 * This file contains miscellaneous low-level functions. 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) 6 * and Paul Mackerras. 7 * 8 * kexec bits: 9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com> 10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz 11 * PPC44x port. Copyright (C) 2011, IBM Corporation 12 * Author: Suzuki Poulose <suzuki@in.ibm.com> 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License 16 * as published by the Free Software Foundation; either version 17 * 2 of the License, or (at your option) any later version. 18 * 19 */ 20 21#include <linux/sys.h> 22#include <asm/unistd.h> 23#include <asm/errno.h> 24#include <asm/reg.h> 25#include <asm/page.h> 26#include <asm/cache.h> 27#include <asm/cputable.h> 28#include <asm/mmu.h> 29#include <asm/ppc_asm.h> 30#include <asm/thread_info.h> 31#include <asm/asm-offsets.h> 32#include <asm/processor.h> 33#include <asm/kexec.h> 34#include <asm/bug.h> 35#include <asm/ptrace.h> 36 37 .text 38 39/* 40 * We store the saved ksp_limit in the unused part 41 * of the STACK_FRAME_OVERHEAD 42 */ 43_GLOBAL(call_do_softirq) 44 mflr r0 45 stw r0,4(r1) 46 lwz r10,THREAD+KSP_LIMIT(r2) 47 addi r11,r3,THREAD_INFO_GAP 48 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3) 49 mr r1,r3 50 stw r10,8(r1) 51 stw r11,THREAD+KSP_LIMIT(r2) 52 bl __do_softirq 53 lwz r10,8(r1) 54 lwz r1,0(r1) 55 lwz r0,4(r1) 56 stw r10,THREAD+KSP_LIMIT(r2) 57 mtlr r0 58 blr 59 60/* 61 * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp); 62 */ 63_GLOBAL(call_do_irq) 64 mflr r0 65 stw r0,4(r1) 66 lwz r10,THREAD+KSP_LIMIT(r2) 67 addi r11,r4,THREAD_INFO_GAP 68 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4) 69 mr r1,r4 70 stw r10,8(r1) 71 stw r11,THREAD+KSP_LIMIT(r2) 72 bl __do_irq 73 lwz r10,8(r1) 74 lwz r1,0(r1) 75 lwz r0,4(r1) 76 stw r10,THREAD+KSP_LIMIT(r2) 77 mtlr r0 78 blr 79 80/* 81 * This returns the high 64 bits of the product of two 64-bit numbers. 82 */ 83_GLOBAL(mulhdu) 84 cmpwi r6,0 85 cmpwi cr1,r3,0 86 mr r10,r4 87 mulhwu r4,r4,r5 88 beq 1f 89 mulhwu r0,r10,r6 90 mullw r7,r10,r5 91 addc r7,r0,r7 92 addze r4,r4 931: beqlr cr1 /* all done if high part of A is 0 */ 94 mullw r9,r3,r5 95 mulhwu r10,r3,r5 96 beq 2f 97 mullw r0,r3,r6 98 mulhwu r8,r3,r6 99 addc r7,r0,r7 100 adde r4,r4,r8 101 addze r10,r10 1022: addc r4,r4,r9 103 addze r3,r10 104 blr 105 106/* 107 * reloc_got2 runs through the .got2 section adding an offset 108 * to each entry. 109 */ 110_GLOBAL(reloc_got2) 111 mflr r11 112 lis r7,__got2_start@ha 113 addi r7,r7,__got2_start@l 114 lis r8,__got2_end@ha 115 addi r8,r8,__got2_end@l 116 subf r8,r7,r8 117 srwi. r8,r8,2 118 beqlr 119 mtctr r8 120 bl 1f 1211: mflr r0 122 lis r4,1b@ha 123 addi r4,r4,1b@l 124 subf r0,r4,r0 125 add r7,r0,r7 1262: lwz r0,0(r7) 127 add r0,r0,r3 128 stw r0,0(r7) 129 addi r7,r7,4 130 bdnz 2b 131 mtlr r11 132 blr 133 134/* 135 * call_setup_cpu - call the setup_cpu function for this cpu 136 * r3 = data offset, r24 = cpu number 137 * 138 * Setup function is called with: 139 * r3 = data offset 140 * r4 = ptr to CPU spec (relocated) 141 */ 142_GLOBAL(call_setup_cpu) 143 addis r4,r3,cur_cpu_spec@ha 144 addi r4,r4,cur_cpu_spec@l 145 lwz r4,0(r4) 146 add r4,r4,r3 147 lwz r5,CPU_SPEC_SETUP(r4) 148 cmpwi 0,r5,0 149 add r5,r5,r3 150 beqlr 151 mtctr r5 152 bctr 153 154#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx) 155 156/* This gets called by via-pmu.c to switch the PLL selection 157 * on 750fx CPU. This function should really be moved to some 158 * other place (as most of the cpufreq code in via-pmu 159 */ 160_GLOBAL(low_choose_750fx_pll) 161 /* Clear MSR:EE */ 162 mfmsr r7 163 rlwinm r0,r7,0,17,15 164 mtmsr r0 165 166 /* If switching to PLL1, disable HID0:BTIC */ 167 cmplwi cr0,r3,0 168 beq 1f 169 mfspr r5,SPRN_HID0 170 rlwinm r5,r5,0,27,25 171 sync 172 mtspr SPRN_HID0,r5 173 isync 174 sync 175 1761: 177 /* Calc new HID1 value */ 178 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ 179 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ 180 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ 181 or r4,r4,r5 182 mtspr SPRN_HID1,r4 183 184 /* Store new HID1 image */ 185 CURRENT_THREAD_INFO(r6, r1) 186 lwz r6,TI_CPU(r6) 187 slwi r6,r6,2 188 addis r6,r6,nap_save_hid1@ha 189 stw r4,nap_save_hid1@l(r6) 190 191 /* If switching to PLL0, enable HID0:BTIC */ 192 cmplwi cr0,r3,0 193 bne 1f 194 mfspr r5,SPRN_HID0 195 ori r5,r5,HID0_BTIC 196 sync 197 mtspr SPRN_HID0,r5 198 isync 199 sync 200 2011: 202 /* Return */ 203 mtmsr r7 204 blr 205 206_GLOBAL(low_choose_7447a_dfs) 207 /* Clear MSR:EE */ 208 mfmsr r7 209 rlwinm r0,r7,0,17,15 210 mtmsr r0 211 212 /* Calc new HID1 value */ 213 mfspr r4,SPRN_HID1 214 insrwi r4,r3,1,9 /* insert parameter into bit 9 */ 215 sync 216 mtspr SPRN_HID1,r4 217 sync 218 isync 219 220 /* Return */ 221 mtmsr r7 222 blr 223 224#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */ 225 226/* 227 * complement mask on the msr then "or" some values on. 228 * _nmask_and_or_msr(nmask, value_to_or) 229 */ 230_GLOBAL(_nmask_and_or_msr) 231 mfmsr r0 /* Get current msr */ 232 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ 233 or r0,r0,r4 /* Or on the bits in r4 (second parm) */ 234 SYNC /* Some chip revs have problems here... */ 235 mtmsr r0 /* Update machine state */ 236 isync 237 blr /* Done */ 238 239#ifdef CONFIG_40x 240 241/* 242 * Do an IO access in real mode 243 */ 244_GLOBAL(real_readb) 245 mfmsr r7 246 ori r0,r7,MSR_DR 247 xori r0,r0,MSR_DR 248 sync 249 mtmsr r0 250 sync 251 isync 252 lbz r3,0(r3) 253 sync 254 mtmsr r7 255 sync 256 isync 257 blr 258 259 /* 260 * Do an IO access in real mode 261 */ 262_GLOBAL(real_writeb) 263 mfmsr r7 264 ori r0,r7,MSR_DR 265 xori r0,r0,MSR_DR 266 sync 267 mtmsr r0 268 sync 269 isync 270 stb r3,0(r4) 271 sync 272 mtmsr r7 273 sync 274 isync 275 blr 276 277#endif /* CONFIG_40x */ 278 279 280/* 281 * Flush instruction cache. 282 * This is a no-op on the 601. 283 */ 284#ifndef CONFIG_PPC_8xx 285_GLOBAL(flush_instruction_cache) 286#if defined(CONFIG_4xx) 287#ifdef CONFIG_403GCX 288 li r3, 512 289 mtctr r3 290 lis r4, KERNELBASE@h 2911: iccci 0, r4 292 addi r4, r4, 16 293 bdnz 1b 294#else 295 lis r3, KERNELBASE@h 296 iccci 0,r3 297#endif 298#elif CONFIG_FSL_BOOKE 299BEGIN_FTR_SECTION 300 mfspr r3,SPRN_L1CSR0 301 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC 302 /* msync; isync recommended here */ 303 mtspr SPRN_L1CSR0,r3 304 isync 305 blr 306END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) 307 mfspr r3,SPRN_L1CSR1 308 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR 309 mtspr SPRN_L1CSR1,r3 310#else 311 mfspr r3,SPRN_PVR 312 rlwinm r3,r3,16,16,31 313 cmpwi 0,r3,1 314 beqlr /* for 601, do nothing */ 315 /* 603/604 processor - use invalidate-all bit in HID0 */ 316 mfspr r3,SPRN_HID0 317 ori r3,r3,HID0_ICFI 318 mtspr SPRN_HID0,r3 319#endif /* CONFIG_4xx */ 320 isync 321 blr 322#endif /* CONFIG_PPC_8xx */ 323 324/* 325 * Write any modified data cache blocks out to memory 326 * and invalidate the corresponding instruction cache blocks. 327 * This is a no-op on the 601. 328 * 329 * flush_icache_range(unsigned long start, unsigned long stop) 330 */ 331_GLOBAL(flush_icache_range) 332BEGIN_FTR_SECTION 333 PURGE_PREFETCHED_INS 334 blr /* for 601, do nothing */ 335END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 336 rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT 337 subf r4,r3,r4 338 addi r4,r4,L1_CACHE_BYTES - 1 339 srwi. r4,r4,L1_CACHE_SHIFT 340 beqlr 341 mtctr r4 342 mr r6,r3 3431: dcbst 0,r3 344 addi r3,r3,L1_CACHE_BYTES 345 bdnz 1b 346 sync /* wait for dcbst's to get to ram */ 347#ifndef CONFIG_44x 348 mtctr r4 3492: icbi 0,r6 350 addi r6,r6,L1_CACHE_BYTES 351 bdnz 2b 352#else 353 /* Flash invalidate on 44x because we are passed kmapped addresses and 354 this doesn't work for userspace pages due to the virtually tagged 355 icache. Sigh. */ 356 iccci 0, r0 357#endif 358 sync /* additional sync needed on g4 */ 359 isync 360 blr 361_ASM_NOKPROBE_SYMBOL(flush_icache_range) 362 363/* 364 * Flush a particular page from the data cache to RAM. 365 * Note: this is necessary because the instruction cache does *not* 366 * snoop from the data cache. 367 * This is a no-op on the 601 which has a unified cache. 368 * 369 * void __flush_dcache_icache(void *page) 370 */ 371_GLOBAL(__flush_dcache_icache) 372BEGIN_FTR_SECTION 373 PURGE_PREFETCHED_INS 374 blr 375END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 376 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */ 377 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */ 378 mtctr r4 379 mr r6,r3 3800: dcbst 0,r3 /* Write line to ram */ 381 addi r3,r3,L1_CACHE_BYTES 382 bdnz 0b 383 sync 384#ifdef CONFIG_44x 385 /* We don't flush the icache on 44x. Those have a virtual icache 386 * and we don't have access to the virtual address here (it's 387 * not the page vaddr but where it's mapped in user space). The 388 * flushing of the icache on these is handled elsewhere, when 389 * a change in the address space occurs, before returning to 390 * user space 391 */ 392BEGIN_MMU_FTR_SECTION 393 blr 394END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x) 395#endif /* CONFIG_44x */ 396 mtctr r4 3971: icbi 0,r6 398 addi r6,r6,L1_CACHE_BYTES 399 bdnz 1b 400 sync 401 isync 402 blr 403 404#ifndef CONFIG_BOOKE 405/* 406 * Flush a particular page from the data cache to RAM, identified 407 * by its physical address. We turn off the MMU so we can just use 408 * the physical address (this may be a highmem page without a kernel 409 * mapping). 410 * 411 * void __flush_dcache_icache_phys(unsigned long physaddr) 412 */ 413_GLOBAL(__flush_dcache_icache_phys) 414BEGIN_FTR_SECTION 415 PURGE_PREFETCHED_INS 416 blr /* for 601, do nothing */ 417END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 418 mfmsr r10 419 rlwinm r0,r10,0,28,26 /* clear DR */ 420 mtmsr r0 421 isync 422 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */ 423 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */ 424 mtctr r4 425 mr r6,r3 4260: dcbst 0,r3 /* Write line to ram */ 427 addi r3,r3,L1_CACHE_BYTES 428 bdnz 0b 429 sync 430 mtctr r4 4311: icbi 0,r6 432 addi r6,r6,L1_CACHE_BYTES 433 bdnz 1b 434 sync 435 mtmsr r10 /* restore DR */ 436 isync 437 blr 438#endif /* CONFIG_BOOKE */ 439 440/* 441 * Copy a whole page. We use the dcbz instruction on the destination 442 * to reduce memory traffic (it eliminates the unnecessary reads of 443 * the destination into cache). This requires that the destination 444 * is cacheable. 445 */ 446#define COPY_16_BYTES \ 447 lwz r6,4(r4); \ 448 lwz r7,8(r4); \ 449 lwz r8,12(r4); \ 450 lwzu r9,16(r4); \ 451 stw r6,4(r3); \ 452 stw r7,8(r3); \ 453 stw r8,12(r3); \ 454 stwu r9,16(r3) 455 456_GLOBAL(copy_page) 457 addi r3,r3,-4 458 addi r4,r4,-4 459 460 li r5,4 461 462#if MAX_COPY_PREFETCH > 1 463 li r0,MAX_COPY_PREFETCH 464 li r11,4 465 mtctr r0 46611: dcbt r11,r4 467 addi r11,r11,L1_CACHE_BYTES 468 bdnz 11b 469#else /* MAX_COPY_PREFETCH == 1 */ 470 dcbt r5,r4 471 li r11,L1_CACHE_BYTES+4 472#endif /* MAX_COPY_PREFETCH */ 473 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH 474 crclr 4*cr0+eq 4752: 476 mtctr r0 4771: 478 dcbt r11,r4 479 dcbz r5,r3 480 COPY_16_BYTES 481#if L1_CACHE_BYTES >= 32 482 COPY_16_BYTES 483#if L1_CACHE_BYTES >= 64 484 COPY_16_BYTES 485 COPY_16_BYTES 486#if L1_CACHE_BYTES >= 128 487 COPY_16_BYTES 488 COPY_16_BYTES 489 COPY_16_BYTES 490 COPY_16_BYTES 491#endif 492#endif 493#endif 494 bdnz 1b 495 beqlr 496 crnot 4*cr0+eq,4*cr0+eq 497 li r0,MAX_COPY_PREFETCH 498 li r11,4 499 b 2b 500 501/* 502 * Extended precision shifts. 503 * 504 * Updated to be valid for shift counts from 0 to 63 inclusive. 505 * -- Gabriel 506 * 507 * R3/R4 has 64 bit value 508 * R5 has shift count 509 * result in R3/R4 510 * 511 * ashrdi3: arithmetic right shift (sign propagation) 512 * lshrdi3: logical right shift 513 * ashldi3: left shift 514 */ 515_GLOBAL(__ashrdi3) 516 subfic r6,r5,32 517 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 518 addi r7,r5,32 # could be xori, or addi with -32 519 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 520 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 521 sraw r7,r3,r7 # t2 = MSW >> (count-32) 522 or r4,r4,r6 # LSW |= t1 523 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 524 sraw r3,r3,r5 # MSW = MSW >> count 525 or r4,r4,r7 # LSW |= t2 526 blr 527 528_GLOBAL(__ashldi3) 529 subfic r6,r5,32 530 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count 531 addi r7,r5,32 # could be xori, or addi with -32 532 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) 533 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) 534 or r3,r3,r6 # MSW |= t1 535 slw r4,r4,r5 # LSW = LSW << count 536 or r3,r3,r7 # MSW |= t2 537 blr 538 539_GLOBAL(__lshrdi3) 540 subfic r6,r5,32 541 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 542 addi r7,r5,32 # could be xori, or addi with -32 543 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 544 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) 545 or r4,r4,r6 # LSW |= t1 546 srw r3,r3,r5 # MSW = MSW >> count 547 or r4,r4,r7 # LSW |= t2 548 blr 549 550/* 551 * 64-bit comparison: __cmpdi2(s64 a, s64 b) 552 * Returns 0 if a < b, 1 if a == b, 2 if a > b. 553 */ 554_GLOBAL(__cmpdi2) 555 cmpw r3,r5 556 li r3,1 557 bne 1f 558 cmplw r4,r6 559 beqlr 5601: li r3,0 561 bltlr 562 li r3,2 563 blr 564/* 565 * 64-bit comparison: __ucmpdi2(u64 a, u64 b) 566 * Returns 0 if a < b, 1 if a == b, 2 if a > b. 567 */ 568_GLOBAL(__ucmpdi2) 569 cmplw r3,r5 570 li r3,1 571 bne 1f 572 cmplw r4,r6 573 beqlr 5741: li r3,0 575 bltlr 576 li r3,2 577 blr 578 579_GLOBAL(__bswapdi2) 580 rotlwi r9,r4,8 581 rotlwi r10,r3,8 582 rlwimi r9,r4,24,0,7 583 rlwimi r10,r3,24,0,7 584 rlwimi r9,r4,24,16,23 585 rlwimi r10,r3,24,16,23 586 mr r3,r9 587 mr r4,r10 588 blr 589 590#ifdef CONFIG_SMP 591_GLOBAL(start_secondary_resume) 592 /* Reset stack */ 593 CURRENT_THREAD_INFO(r1, r1) 594 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 595 li r3,0 596 stw r3,0(r1) /* Zero the stack frame pointer */ 597 bl start_secondary 598 b . 599#endif /* CONFIG_SMP */ 600 601/* 602 * This routine is just here to keep GCC happy - sigh... 603 */ 604_GLOBAL(__main) 605 blr 606 607#ifdef CONFIG_KEXEC 608 /* 609 * Must be relocatable PIC code callable as a C function. 610 */ 611 .globl relocate_new_kernel 612relocate_new_kernel: 613 /* r3 = page_list */ 614 /* r4 = reboot_code_buffer */ 615 /* r5 = start_address */ 616 617#ifdef CONFIG_FSL_BOOKE 618 619 mr r29, r3 620 mr r30, r4 621 mr r31, r5 622 623#define ENTRY_MAPPING_KEXEC_SETUP 624#include "fsl_booke_entry_mapping.S" 625#undef ENTRY_MAPPING_KEXEC_SETUP 626 627 mr r3, r29 628 mr r4, r30 629 mr r5, r31 630 631 li r0, 0 632#elif defined(CONFIG_44x) 633 634 /* Save our parameters */ 635 mr r29, r3 636 mr r30, r4 637 mr r31, r5 638 639#ifdef CONFIG_PPC_47x 640 /* Check for 47x cores */ 641 mfspr r3,SPRN_PVR 642 srwi r3,r3,16 643 cmplwi cr0,r3,PVR_476FPE@h 644 beq setup_map_47x 645 cmplwi cr0,r3,PVR_476@h 646 beq setup_map_47x 647 cmplwi cr0,r3,PVR_476_ISS@h 648 beq setup_map_47x 649#endif /* CONFIG_PPC_47x */ 650 651/* 652 * Code for setting up 1:1 mapping for PPC440x for KEXEC 653 * 654 * We cannot switch off the MMU on PPC44x. 655 * So we: 656 * 1) Invalidate all the mappings except the one we are running from. 657 * 2) Create a tmp mapping for our code in the other address space(TS) and 658 * jump to it. Invalidate the entry we started in. 659 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS. 660 * 4) Jump to the 1:1 mapping in original TS. 661 * 5) Invalidate the tmp mapping. 662 * 663 * - Based on the kexec support code for FSL BookE 664 * 665 */ 666 667 /* 668 * Load the PID with kernel PID (0). 669 * Also load our MSR_IS and TID to MMUCR for TLB search. 670 */ 671 li r3, 0 672 mtspr SPRN_PID, r3 673 mfmsr r4 674 andi. r4,r4,MSR_IS@l 675 beq wmmucr 676 oris r3,r3,PPC44x_MMUCR_STS@h 677wmmucr: 678 mtspr SPRN_MMUCR,r3 679 sync 680 681 /* 682 * Invalidate all the TLB entries except the current entry 683 * where we are running from 684 */ 685 bl 0f /* Find our address */ 6860: mflr r5 /* Make it accessible */ 687 tlbsx r23,0,r5 /* Find entry we are in */ 688 li r4,0 /* Start at TLB entry 0 */ 689 li r3,0 /* Set PAGEID inval value */ 6901: cmpw r23,r4 /* Is this our entry? */ 691 beq skip /* If so, skip the inval */ 692 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ 693skip: 694 addi r4,r4,1 /* Increment */ 695 cmpwi r4,64 /* Are we done? */ 696 bne 1b /* If not, repeat */ 697 isync 698 699 /* Create a temp mapping and jump to it */ 700 andi. r6, r23, 1 /* Find the index to use */ 701 addi r24, r6, 1 /* r24 will contain 1 or 2 */ 702 703 mfmsr r9 /* get the MSR */ 704 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */ 705 xori r7, r5, 1 /* Use the other address space */ 706 707 /* Read the current mapping entries */ 708 tlbre r3, r23, PPC44x_TLB_PAGEID 709 tlbre r4, r23, PPC44x_TLB_XLAT 710 tlbre r5, r23, PPC44x_TLB_ATTRIB 711 712 /* Save our current XLAT entry */ 713 mr r25, r4 714 715 /* Extract the TLB PageSize */ 716 li r10, 1 /* r10 will hold PageSize */ 717 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */ 718 719 /* XXX: As of now we use 256M, 4K pages */ 720 cmpwi r11, PPC44x_TLB_256M 721 bne tlb_4k 722 rotlwi r10, r10, 28 /* r10 = 256M */ 723 b write_out 724tlb_4k: 725 cmpwi r11, PPC44x_TLB_4K 726 bne default 727 rotlwi r10, r10, 12 /* r10 = 4K */ 728 b write_out 729default: 730 rotlwi r10, r10, 10 /* r10 = 1K */ 731 732write_out: 733 /* 734 * Write out the tmp 1:1 mapping for this code in other address space 735 * Fixup EPN = RPN , TS=other address space 736 */ 737 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */ 738 739 /* Write out the tmp mapping entries */ 740 tlbwe r3, r24, PPC44x_TLB_PAGEID 741 tlbwe r4, r24, PPC44x_TLB_XLAT 742 tlbwe r5, r24, PPC44x_TLB_ATTRIB 743 744 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */ 745 not r10, r11 /* Mask for PageNum */ 746 747 /* Switch to other address space in MSR */ 748 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ 749 750 bl 1f 7511: mflr r8 752 addi r8, r8, (2f-1b) /* Find the target offset */ 753 754 /* Jump to the tmp mapping */ 755 mtspr SPRN_SRR0, r8 756 mtspr SPRN_SRR1, r9 757 rfi 758 7592: 760 /* Invalidate the entry we were executing from */ 761 li r3, 0 762 tlbwe r3, r23, PPC44x_TLB_PAGEID 763 764 /* attribute fields. rwx for SUPERVISOR mode */ 765 li r5, 0 766 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) 767 768 /* Create 1:1 mapping in 256M pages */ 769 xori r7, r7, 1 /* Revert back to Original TS */ 770 771 li r8, 0 /* PageNumber */ 772 li r6, 3 /* TLB Index, start at 3 */ 773 774next_tlb: 775 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */ 776 mr r4, r3 /* RPN = EPN */ 777 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */ 778 insrwi r3, r7, 1, 23 /* Set TS from r7 */ 779 780 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */ 781 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */ 782 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */ 783 784 addi r8, r8, 1 /* Increment PN */ 785 addi r6, r6, 1 /* Increment TLB Index */ 786 cmpwi r8, 8 /* Are we done ? */ 787 bne next_tlb 788 isync 789 790 /* Jump to the new mapping 1:1 */ 791 li r9,0 792 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ 793 794 bl 1f 7951: mflr r8 796 and r8, r8, r11 /* Get our offset within page */ 797 addi r8, r8, (2f-1b) 798 799 and r5, r25, r10 /* Get our target PageNum */ 800 or r8, r8, r5 /* Target jump address */ 801 802 mtspr SPRN_SRR0, r8 803 mtspr SPRN_SRR1, r9 804 rfi 8052: 806 /* Invalidate the tmp entry we used */ 807 li r3, 0 808 tlbwe r3, r24, PPC44x_TLB_PAGEID 809 sync 810 b ppc44x_map_done 811 812#ifdef CONFIG_PPC_47x 813 814 /* 1:1 mapping for 47x */ 815 816setup_map_47x: 817 818 /* 819 * Load the kernel pid (0) to PID and also to MMUCR[TID]. 820 * Also set the MSR IS->MMUCR STS 821 */ 822 li r3, 0 823 mtspr SPRN_PID, r3 /* Set PID */ 824 mfmsr r4 /* Get MSR */ 825 andi. r4, r4, MSR_IS@l /* TS=1? */ 826 beq 1f /* If not, leave STS=0 */ 827 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */ 8281: mtspr SPRN_MMUCR, r3 /* Put MMUCR */ 829 sync 830 831 /* Find the entry we are running from */ 832 bl 2f 8332: mflr r23 834 tlbsx r23, 0, r23 835 tlbre r24, r23, 0 /* TLB Word 0 */ 836 tlbre r25, r23, 1 /* TLB Word 1 */ 837 tlbre r26, r23, 2 /* TLB Word 2 */ 838 839 840 /* 841 * Invalidates all the tlb entries by writing to 256 RPNs(r4) 842 * of 4k page size in all 4 ways (0-3 in r3). 843 * This would invalidate the entire UTLB including the one we are 844 * running from. However the shadow TLB entries would help us 845 * to continue the execution, until we flush them (rfi/isync). 846 */ 847 addis r3, 0, 0x8000 /* specify the way */ 848 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */ 849 addi r5, 0, 0 850 b clear_utlb_entry 851 852 /* Align the loop to speed things up. from head_44x.S */ 853 .align 6 854 855clear_utlb_entry: 856 857 tlbwe r4, r3, 0 858 tlbwe r5, r3, 1 859 tlbwe r5, r3, 2 860 addis r3, r3, 0x2000 /* Increment the way */ 861 cmpwi r3, 0 862 bne clear_utlb_entry 863 addis r3, 0, 0x8000 864 addis r4, r4, 0x100 /* Increment the EPN */ 865 cmpwi r4, 0 866 bne clear_utlb_entry 867 868 /* Create the entries in the other address space */ 869 mfmsr r5 870 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */ 871 xori r7, r7, 1 /* r7 = !TS */ 872 873 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */ 874 875 /* 876 * write out the TLB entries for the tmp mapping 877 * Use way '0' so that we could easily invalidate it later. 878 */ 879 lis r3, 0x8000 /* Way '0' */ 880 881 tlbwe r24, r3, 0 882 tlbwe r25, r3, 1 883 tlbwe r26, r3, 2 884 885 /* Update the msr to the new TS */ 886 insrwi r5, r7, 1, 26 887 888 bl 1f 8891: mflr r6 890 addi r6, r6, (2f-1b) 891 892 mtspr SPRN_SRR0, r6 893 mtspr SPRN_SRR1, r5 894 rfi 895 896 /* 897 * Now we are in the tmp address space. 898 * Create a 1:1 mapping for 0-2GiB in the original TS. 899 */ 9002: 901 li r3, 0 902 li r4, 0 /* TLB Word 0 */ 903 li r5, 0 /* TLB Word 1 */ 904 li r6, 0 905 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */ 906 907 li r8, 0 /* PageIndex */ 908 909 xori r7, r7, 1 /* revert back to original TS */ 910 911write_utlb: 912 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */ 913 /* ERPN = 0 as we don't use memory above 2G */ 914 915 mr r4, r5 /* EPN = RPN */ 916 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M) 917 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */ 918 919 tlbwe r4, r3, 0 /* Write out the entries */ 920 tlbwe r5, r3, 1 921 tlbwe r6, r3, 2 922 addi r8, r8, 1 923 cmpwi r8, 8 /* Have we completed ? */ 924 bne write_utlb 925 926 /* make sure we complete the TLB write up */ 927 isync 928 929 /* 930 * Prepare to jump to the 1:1 mapping. 931 * 1) Extract page size of the tmp mapping 932 * DSIZ = TLB_Word0[22:27] 933 * 2) Calculate the physical address of the address 934 * to jump to. 935 */ 936 rlwinm r10, r24, 0, 22, 27 937 938 cmpwi r10, PPC47x_TLB0_4K 939 bne 0f 940 li r10, 0x1000 /* r10 = 4k */ 941 bl 1f 942 9430: 944 /* Defaults to 256M */ 945 lis r10, 0x1000 946 947 bl 1f 9481: mflr r4 949 addi r4, r4, (2f-1b) /* virtual address of 2f */ 950 951 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */ 952 not r10, r11 /* Pagemask = ~(offsetmask) */ 953 954 and r5, r25, r10 /* Physical page */ 955 and r6, r4, r11 /* offset within the current page */ 956 957 or r5, r5, r6 /* Physical address for 2f */ 958 959 /* Switch the TS in MSR to the original one */ 960 mfmsr r8 961 insrwi r8, r7, 1, 26 962 963 mtspr SPRN_SRR1, r8 964 mtspr SPRN_SRR0, r5 965 rfi 966 9672: 968 /* Invalidate the tmp mapping */ 969 lis r3, 0x8000 /* Way '0' */ 970 971 clrrwi r24, r24, 12 /* Clear the valid bit */ 972 tlbwe r24, r3, 0 973 tlbwe r25, r3, 1 974 tlbwe r26, r3, 2 975 976 /* Make sure we complete the TLB write and flush the shadow TLB */ 977 isync 978 979#endif 980 981ppc44x_map_done: 982 983 984 /* Restore the parameters */ 985 mr r3, r29 986 mr r4, r30 987 mr r5, r31 988 989 li r0, 0 990#else 991 li r0, 0 992 993 /* 994 * Set Machine Status Register to a known status, 995 * switch the MMU off and jump to 1: in a single step. 996 */ 997 998 mr r8, r0 999 ori r8, r8, MSR_RI|MSR_ME 1000 mtspr SPRN_SRR1, r8 1001 addi r8, r4, 1f - relocate_new_kernel 1002 mtspr SPRN_SRR0, r8 1003 sync 1004 rfi 1005 10061: 1007#endif 1008 /* from this point address translation is turned off */ 1009 /* and interrupts are disabled */ 1010 1011 /* set a new stack at the bottom of our page... */ 1012 /* (not really needed now) */ 1013 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */ 1014 stw r0, 0(r1) 1015 1016 /* Do the copies */ 1017 li r6, 0 /* checksum */ 1018 mr r0, r3 1019 b 1f 1020 10210: /* top, read another word for the indirection page */ 1022 lwzu r0, 4(r3) 1023 10241: 1025 /* is it a destination page? (r8) */ 1026 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ 1027 beq 2f 1028 1029 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ 1030 b 0b 1031 10322: /* is it an indirection page? (r3) */ 1033 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ 1034 beq 2f 1035 1036 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ 1037 subi r3, r3, 4 1038 b 0b 1039 10402: /* are we done? */ 1041 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ 1042 beq 2f 1043 b 3f 1044 10452: /* is it a source page? (r9) */ 1046 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ 1047 beq 0b 1048 1049 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ 1050 1051 li r7, PAGE_SIZE / 4 1052 mtctr r7 1053 subi r9, r9, 4 1054 subi r8, r8, 4 10559: 1056 lwzu r0, 4(r9) /* do the copy */ 1057 xor r6, r6, r0 1058 stwu r0, 4(r8) 1059 dcbst 0, r8 1060 sync 1061 icbi 0, r8 1062 bdnz 9b 1063 1064 addi r9, r9, 4 1065 addi r8, r8, 4 1066 b 0b 1067 10683: 1069 1070 /* To be certain of avoiding problems with self-modifying code 1071 * execute a serializing instruction here. 1072 */ 1073 isync 1074 sync 1075 1076 mfspr r3, SPRN_PIR /* current core we are running on */ 1077 mr r4, r5 /* load physical address of chunk called */ 1078 1079 /* jump to the entry point, usually the setup routine */ 1080 mtlr r5 1081 blrl 1082 10831: b 1b 1084 1085relocate_new_kernel_end: 1086 1087 .globl relocate_new_kernel_size 1088relocate_new_kernel_size: 1089 .long relocate_new_kernel_end - relocate_new_kernel 1090#endif 1091