xref: /linux/arch/powerpc/kernel/misc.S (revision 14b42963f64b98ab61fa9723c03d71aa5ef4f862)
1/*
2 * This file contains miscellaneous low-level functions.
3 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 *
8 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
9 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16#include <asm/ppc_asm.h>
17
18	.text
19
20#ifdef CONFIG_PPC64
21#define IN_SYNC		twi	0,r5,0; isync
22#define EIEIO_32
23#define SYNC_64		sync
24#else /* CONFIG_PPC32 */
25#define IN_SYNC
26#define EIEIO_32	eieio
27#define SYNC_64
28#endif
29/*
30 * Returns (address we are running at) - (address we were linked at)
31 * for use before the text and data are mapped to KERNELBASE.
32 */
33
34_GLOBAL(reloc_offset)
35	mflr	r0
36	bl	1f
371:	mflr	r3
38	LOAD_REG_IMMEDIATE(r4,1b)
39	subf	r3,r4,r3
40	mtlr	r0
41	blr
42
43/*
44 * add_reloc_offset(x) returns x + reloc_offset().
45 */
46_GLOBAL(add_reloc_offset)
47	mflr	r0
48	bl	1f
491:	mflr	r5
50	LOAD_REG_IMMEDIATE(r4,1b)
51	subf	r5,r4,r5
52	add	r3,r3,r5
53	mtlr	r0
54	blr
55
56/*
57 * I/O string operations
58 *
59 * insb(port, buf, len)
60 * outsb(port, buf, len)
61 * insw(port, buf, len)
62 * outsw(port, buf, len)
63 * insl(port, buf, len)
64 * outsl(port, buf, len)
65 * insw_ns(port, buf, len)
66 * outsw_ns(port, buf, len)
67 * insl_ns(port, buf, len)
68 * outsl_ns(port, buf, len)
69 *
70 * The *_ns versions don't do byte-swapping.
71 */
72_GLOBAL(_insb)
73	cmpwi	0,r5,0
74	mtctr	r5
75	subi	r4,r4,1
76	blelr-
7700:	lbz	r5,0(r3)
78	eieio
79	stbu	r5,1(r4)
80	bdnz	00b
81	IN_SYNC
82	blr
83
84_GLOBAL(_outsb)
85	cmpwi	0,r5,0
86	mtctr	r5
87	subi	r4,r4,1
88	blelr-
8900:	lbzu	r5,1(r4)
90	stb	r5,0(r3)
91	EIEIO_32
92	bdnz	00b
93	SYNC_64
94	blr
95
96_GLOBAL(_insw)
97	cmpwi	0,r5,0
98	mtctr	r5
99	subi	r4,r4,2
100	blelr-
10100:	lhbrx	r5,0,r3
102	eieio
103	sthu	r5,2(r4)
104	bdnz	00b
105	IN_SYNC
106	blr
107
108_GLOBAL(_outsw)
109	cmpwi	0,r5,0
110	mtctr	r5
111	subi	r4,r4,2
112	blelr-
11300:	lhzu	r5,2(r4)
114	EIEIO_32
115	sthbrx	r5,0,r3
116	bdnz	00b
117	SYNC_64
118	blr
119
120_GLOBAL(_insl)
121	cmpwi	0,r5,0
122	mtctr	r5
123	subi	r4,r4,4
124	blelr-
12500:	lwbrx	r5,0,r3
126	eieio
127	stwu	r5,4(r4)
128	bdnz	00b
129	IN_SYNC
130	blr
131
132_GLOBAL(_outsl)
133	cmpwi	0,r5,0
134	mtctr	r5
135	subi	r4,r4,4
136	blelr-
13700:	lwzu	r5,4(r4)
138	stwbrx	r5,0,r3
139	EIEIO_32
140	bdnz	00b
141	SYNC_64
142	blr
143
144#ifdef CONFIG_PPC32
145_GLOBAL(__ide_mm_insw)
146#endif
147_GLOBAL(_insw_ns)
148	cmpwi	0,r5,0
149	mtctr	r5
150	subi	r4,r4,2
151	blelr-
15200:	lhz	r5,0(r3)
153	eieio
154	sthu	r5,2(r4)
155	bdnz	00b
156	IN_SYNC
157	blr
158
159#ifdef CONFIG_PPC32
160_GLOBAL(__ide_mm_outsw)
161#endif
162_GLOBAL(_outsw_ns)
163	cmpwi	0,r5,0
164	mtctr	r5
165	subi	r4,r4,2
166	blelr-
16700:	lhzu	r5,2(r4)
168	sth	r5,0(r3)
169	EIEIO_32
170	bdnz	00b
171	SYNC_64
172	blr
173
174#ifdef CONFIG_PPC32
175_GLOBAL(__ide_mm_insl)
176#endif
177_GLOBAL(_insl_ns)
178	cmpwi	0,r5,0
179	mtctr	r5
180	subi	r4,r4,4
181	blelr-
18200:	lwz	r5,0(r3)
183	eieio
184	stwu	r5,4(r4)
185	bdnz	00b
186	IN_SYNC
187	blr
188
189#ifdef CONFIG_PPC32
190_GLOBAL(__ide_mm_outsl)
191#endif
192_GLOBAL(_outsl_ns)
193	cmpwi	0,r5,0
194	mtctr	r5
195	subi	r4,r4,4
196	blelr-
19700:	lwzu	r5,4(r4)
198	stw	r5,0(r3)
199	EIEIO_32
200	bdnz	00b
201	SYNC_64
202	blr
203
204