1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Machine check exception handling CPU-side for power7 and power8 4 * 5 * Copyright 2013 IBM Corporation 6 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> 7 */ 8 9 #undef DEBUG 10 #define pr_fmt(fmt) "mce_power: " fmt 11 12 #include <linux/types.h> 13 #include <linux/ptrace.h> 14 #include <asm/mmu.h> 15 #include <asm/mce.h> 16 #include <asm/machdep.h> 17 #include <asm/pgtable.h> 18 #include <asm/pte-walk.h> 19 #include <asm/sstep.h> 20 #include <asm/exception-64s.h> 21 22 /* 23 * Convert an address related to an mm to a PFN. NOTE: we are in real 24 * mode, we could potentially race with page table updates. 25 */ 26 unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr) 27 { 28 pte_t *ptep; 29 unsigned int shift; 30 unsigned long flags; 31 struct mm_struct *mm; 32 33 if (user_mode(regs)) 34 mm = current->mm; 35 else 36 mm = &init_mm; 37 38 local_irq_save(flags); 39 ptep = __find_linux_pte(mm->pgd, addr, NULL, &shift); 40 local_irq_restore(flags); 41 42 if (!ptep || pte_special(*ptep)) 43 return ULONG_MAX; 44 45 if (shift > PAGE_SHIFT) { 46 unsigned long rpnmask = (1ul << shift) - PAGE_SIZE; 47 48 return pte_pfn(__pte(pte_val(*ptep) | (addr & rpnmask))); 49 } 50 51 return pte_pfn(*ptep); 52 } 53 54 /* flush SLBs and reload */ 55 #ifdef CONFIG_PPC_BOOK3S_64 56 void flush_and_reload_slb(void) 57 { 58 /* Invalidate all SLBs */ 59 slb_flush_all_realmode(); 60 61 #ifdef CONFIG_KVM_BOOK3S_HANDLER 62 /* 63 * If machine check is hit when in guest or in transition, we will 64 * only flush the SLBs and continue. 65 */ 66 if (get_paca()->kvm_hstate.in_guest) 67 return; 68 #endif 69 if (early_radix_enabled()) 70 return; 71 72 /* 73 * This probably shouldn't happen, but it may be possible it's 74 * called in early boot before SLB shadows are allocated. 75 */ 76 if (!get_slb_shadow()) 77 return; 78 79 slb_restore_bolted_realmode(); 80 } 81 #endif 82 83 static void flush_erat(void) 84 { 85 #ifdef CONFIG_PPC_BOOK3S_64 86 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) { 87 flush_and_reload_slb(); 88 return; 89 } 90 #endif 91 asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory"); 92 } 93 94 #define MCE_FLUSH_SLB 1 95 #define MCE_FLUSH_TLB 2 96 #define MCE_FLUSH_ERAT 3 97 98 static int mce_flush(int what) 99 { 100 #ifdef CONFIG_PPC_BOOK3S_64 101 if (what == MCE_FLUSH_SLB) { 102 flush_and_reload_slb(); 103 return 1; 104 } 105 #endif 106 if (what == MCE_FLUSH_ERAT) { 107 flush_erat(); 108 return 1; 109 } 110 if (what == MCE_FLUSH_TLB) { 111 tlbiel_all(); 112 return 1; 113 } 114 115 return 0; 116 } 117 118 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) 119 120 struct mce_ierror_table { 121 unsigned long srr1_mask; 122 unsigned long srr1_value; 123 bool nip_valid; /* nip is a valid indicator of faulting address */ 124 unsigned int error_type; 125 unsigned int error_subtype; 126 unsigned int error_class; 127 unsigned int initiator; 128 unsigned int severity; 129 bool sync_error; 130 }; 131 132 static const struct mce_ierror_table mce_p7_ierror_table[] = { 133 { 0x00000000001c0000, 0x0000000000040000, true, 134 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 135 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 136 { 0x00000000001c0000, 0x0000000000080000, true, 137 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 138 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 139 { 0x00000000001c0000, 0x00000000000c0000, true, 140 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 141 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 142 { 0x00000000001c0000, 0x0000000000100000, true, 143 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */ 144 MCE_ECLASS_SOFT_INDETERMINATE, 145 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 146 { 0x00000000001c0000, 0x0000000000140000, true, 147 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 148 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 149 { 0x00000000001c0000, 0x0000000000180000, true, 150 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE, 151 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 152 { 0x00000000001c0000, 0x00000000001c0000, true, 153 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 154 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 155 { 0, 0, 0, 0, 0, 0, 0 } }; 156 157 static const struct mce_ierror_table mce_p8_ierror_table[] = { 158 { 0x00000000081c0000, 0x0000000000040000, true, 159 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 160 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 161 { 0x00000000081c0000, 0x0000000000080000, true, 162 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 163 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 164 { 0x00000000081c0000, 0x00000000000c0000, true, 165 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 166 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 167 { 0x00000000081c0000, 0x0000000000100000, true, 168 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 169 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 170 { 0x00000000081c0000, 0x0000000000140000, true, 171 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 172 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 173 { 0x00000000081c0000, 0x0000000000180000, true, 174 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, 175 MCE_ECLASS_HARDWARE, 176 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 177 { 0x00000000081c0000, 0x00000000001c0000, true, 178 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 179 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 180 { 0x00000000081c0000, 0x0000000008000000, true, 181 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE, 182 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 183 { 0x00000000081c0000, 0x0000000008040000, true, 184 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT, 185 MCE_ECLASS_HARDWARE, 186 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 187 { 0, 0, 0, 0, 0, 0, 0 } }; 188 189 static const struct mce_ierror_table mce_p9_ierror_table[] = { 190 { 0x00000000081c0000, 0x0000000000040000, true, 191 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 192 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 193 { 0x00000000081c0000, 0x0000000000080000, true, 194 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 195 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 196 { 0x00000000081c0000, 0x00000000000c0000, true, 197 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 198 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 199 { 0x00000000081c0000, 0x0000000000100000, true, 200 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 201 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 202 { 0x00000000081c0000, 0x0000000000140000, true, 203 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 204 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 205 { 0x00000000081c0000, 0x0000000000180000, true, 206 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE, 207 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 208 { 0x00000000081c0000, 0x00000000001c0000, true, 209 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN, MCE_ECLASS_SOFTWARE, 210 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 211 { 0x00000000081c0000, 0x0000000008000000, true, 212 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE, 213 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 214 { 0x00000000081c0000, 0x0000000008040000, true, 215 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT, 216 MCE_ECLASS_HARDWARE, 217 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 218 { 0x00000000081c0000, 0x00000000080c0000, true, 219 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH, MCE_ECLASS_SOFTWARE, 220 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 221 { 0x00000000081c0000, 0x0000000008100000, true, 222 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_SOFTWARE, 223 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 224 { 0x00000000081c0000, 0x0000000008140000, false, 225 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE, MCE_ECLASS_HARDWARE, 226 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */ 227 { 0x00000000081c0000, 0x0000000008180000, false, 228 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_STORE_TIMEOUT, 229 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */ 230 { 0x00000000081c0000, 0x00000000081c0000, true, MCE_ECLASS_HARDWARE, 231 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN, 232 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 233 { 0, 0, 0, 0, 0, 0, 0 } }; 234 235 struct mce_derror_table { 236 unsigned long dsisr_value; 237 bool dar_valid; /* dar is a valid indicator of faulting address */ 238 unsigned int error_type; 239 unsigned int error_subtype; 240 unsigned int error_class; 241 unsigned int initiator; 242 unsigned int severity; 243 bool sync_error; 244 }; 245 246 static const struct mce_derror_table mce_p7_derror_table[] = { 247 { 0x00008000, false, 248 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE, 249 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 250 { 0x00004000, true, 251 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 252 MCE_ECLASS_HARDWARE, 253 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 254 { 0x00000800, true, 255 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 256 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 257 { 0x00000400, true, 258 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 259 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 260 { 0x00000080, true, 261 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 262 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 263 { 0x00000100, true, 264 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 265 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 266 { 0x00000040, true, 267 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */ 268 MCE_ECLASS_HARD_INDETERMINATE, 269 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 270 { 0, false, 0, 0, 0, 0, 0 } }; 271 272 static const struct mce_derror_table mce_p8_derror_table[] = { 273 { 0x00008000, false, 274 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE, 275 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 276 { 0x00004000, true, 277 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 278 MCE_ECLASS_HARDWARE, 279 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 280 { 0x00002000, true, 281 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE, 282 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 283 { 0x00001000, true, 284 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT, 285 MCE_ECLASS_HARDWARE, 286 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 287 { 0x00000800, true, 288 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 289 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 290 { 0x00000400, true, 291 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 292 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 293 { 0x00000200, true, 294 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, /* SECONDARY ERAT */ 295 MCE_ECLASS_SOFT_INDETERMINATE, 296 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 297 { 0x00000080, true, 298 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */ 299 MCE_ECLASS_SOFT_INDETERMINATE, 300 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 301 { 0x00000100, true, 302 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 303 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 304 { 0, false, 0, 0, 0, 0, 0 } }; 305 306 static const struct mce_derror_table mce_p9_derror_table[] = { 307 { 0x00008000, false, 308 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE, 309 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 310 { 0x00004000, true, 311 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 312 MCE_ECLASS_HARDWARE, 313 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 314 { 0x00002000, true, 315 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE, 316 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 317 { 0x00001000, true, 318 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT, 319 MCE_ECLASS_HARDWARE, 320 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 321 { 0x00000800, true, 322 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 323 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 324 { 0x00000400, true, 325 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 326 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 327 { 0x00000200, false, 328 MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE, MCE_ECLASS_SOFTWARE, 329 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 330 { 0x00000080, true, 331 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */ 332 MCE_ECLASS_SOFT_INDETERMINATE, 333 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 334 { 0x00000100, true, 335 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 336 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 337 { 0x00000040, true, 338 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD, MCE_ECLASS_HARDWARE, 339 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 340 { 0x00000020, false, 341 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 342 MCE_ECLASS_HARDWARE, 343 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 344 { 0x00000010, false, 345 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN, 346 MCE_ECLASS_HARDWARE, 347 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 348 { 0x00000008, false, 349 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN, MCE_ECLASS_HARDWARE, 350 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 351 { 0, false, 0, 0, 0, 0, 0 } }; 352 353 static int mce_find_instr_ea_and_phys(struct pt_regs *regs, uint64_t *addr, 354 uint64_t *phys_addr) 355 { 356 /* 357 * Carefully look at the NIP to determine 358 * the instruction to analyse. Reading the NIP 359 * in real-mode is tricky and can lead to recursive 360 * faults 361 */ 362 int instr; 363 unsigned long pfn, instr_addr; 364 struct instruction_op op; 365 struct pt_regs tmp = *regs; 366 367 pfn = addr_to_pfn(regs, regs->nip); 368 if (pfn != ULONG_MAX) { 369 instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK); 370 instr = *(unsigned int *)(instr_addr); 371 if (!analyse_instr(&op, &tmp, instr)) { 372 pfn = addr_to_pfn(regs, op.ea); 373 *addr = op.ea; 374 *phys_addr = (pfn << PAGE_SHIFT); 375 return 0; 376 } 377 /* 378 * analyse_instr() might fail if the instruction 379 * is not a load/store, although this is unexpected 380 * for load/store errors or if we got the NIP 381 * wrong 382 */ 383 } 384 *addr = 0; 385 return -1; 386 } 387 388 static int mce_handle_ierror(struct pt_regs *regs, 389 const struct mce_ierror_table table[], 390 struct mce_error_info *mce_err, uint64_t *addr, 391 uint64_t *phys_addr) 392 { 393 uint64_t srr1 = regs->msr; 394 int handled = 0; 395 int i; 396 397 *addr = 0; 398 399 for (i = 0; table[i].srr1_mask; i++) { 400 if ((srr1 & table[i].srr1_mask) != table[i].srr1_value) 401 continue; 402 403 /* attempt to correct the error */ 404 switch (table[i].error_type) { 405 case MCE_ERROR_TYPE_SLB: 406 handled = mce_flush(MCE_FLUSH_SLB); 407 break; 408 case MCE_ERROR_TYPE_ERAT: 409 handled = mce_flush(MCE_FLUSH_ERAT); 410 break; 411 case MCE_ERROR_TYPE_TLB: 412 handled = mce_flush(MCE_FLUSH_TLB); 413 break; 414 } 415 416 /* now fill in mce_error_info */ 417 mce_err->error_type = table[i].error_type; 418 mce_err->error_class = table[i].error_class; 419 switch (table[i].error_type) { 420 case MCE_ERROR_TYPE_UE: 421 mce_err->u.ue_error_type = table[i].error_subtype; 422 break; 423 case MCE_ERROR_TYPE_SLB: 424 mce_err->u.slb_error_type = table[i].error_subtype; 425 break; 426 case MCE_ERROR_TYPE_ERAT: 427 mce_err->u.erat_error_type = table[i].error_subtype; 428 break; 429 case MCE_ERROR_TYPE_TLB: 430 mce_err->u.tlb_error_type = table[i].error_subtype; 431 break; 432 case MCE_ERROR_TYPE_USER: 433 mce_err->u.user_error_type = table[i].error_subtype; 434 break; 435 case MCE_ERROR_TYPE_RA: 436 mce_err->u.ra_error_type = table[i].error_subtype; 437 break; 438 case MCE_ERROR_TYPE_LINK: 439 mce_err->u.link_error_type = table[i].error_subtype; 440 break; 441 } 442 mce_err->sync_error = table[i].sync_error; 443 mce_err->severity = table[i].severity; 444 mce_err->initiator = table[i].initiator; 445 if (table[i].nip_valid) { 446 *addr = regs->nip; 447 if (mce_err->sync_error && 448 table[i].error_type == MCE_ERROR_TYPE_UE) { 449 unsigned long pfn; 450 451 if (get_paca()->in_mce < MAX_MCE_DEPTH) { 452 pfn = addr_to_pfn(regs, regs->nip); 453 if (pfn != ULONG_MAX) { 454 *phys_addr = 455 (pfn << PAGE_SHIFT); 456 } 457 } 458 } 459 } 460 return handled; 461 } 462 463 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN; 464 mce_err->error_class = MCE_ECLASS_UNKNOWN; 465 mce_err->severity = MCE_SEV_SEVERE; 466 mce_err->initiator = MCE_INITIATOR_CPU; 467 mce_err->sync_error = true; 468 469 return 0; 470 } 471 472 static int mce_handle_derror(struct pt_regs *regs, 473 const struct mce_derror_table table[], 474 struct mce_error_info *mce_err, uint64_t *addr, 475 uint64_t *phys_addr) 476 { 477 uint64_t dsisr = regs->dsisr; 478 int handled = 0; 479 int found = 0; 480 int i; 481 482 *addr = 0; 483 484 for (i = 0; table[i].dsisr_value; i++) { 485 if (!(dsisr & table[i].dsisr_value)) 486 continue; 487 488 /* attempt to correct the error */ 489 switch (table[i].error_type) { 490 case MCE_ERROR_TYPE_SLB: 491 if (mce_flush(MCE_FLUSH_SLB)) 492 handled = 1; 493 break; 494 case MCE_ERROR_TYPE_ERAT: 495 if (mce_flush(MCE_FLUSH_ERAT)) 496 handled = 1; 497 break; 498 case MCE_ERROR_TYPE_TLB: 499 if (mce_flush(MCE_FLUSH_TLB)) 500 handled = 1; 501 break; 502 } 503 504 /* 505 * Attempt to handle multiple conditions, but only return 506 * one. Ensure uncorrectable errors are first in the table 507 * to match. 508 */ 509 if (found) 510 continue; 511 512 /* now fill in mce_error_info */ 513 mce_err->error_type = table[i].error_type; 514 mce_err->error_class = table[i].error_class; 515 switch (table[i].error_type) { 516 case MCE_ERROR_TYPE_UE: 517 mce_err->u.ue_error_type = table[i].error_subtype; 518 break; 519 case MCE_ERROR_TYPE_SLB: 520 mce_err->u.slb_error_type = table[i].error_subtype; 521 break; 522 case MCE_ERROR_TYPE_ERAT: 523 mce_err->u.erat_error_type = table[i].error_subtype; 524 break; 525 case MCE_ERROR_TYPE_TLB: 526 mce_err->u.tlb_error_type = table[i].error_subtype; 527 break; 528 case MCE_ERROR_TYPE_USER: 529 mce_err->u.user_error_type = table[i].error_subtype; 530 break; 531 case MCE_ERROR_TYPE_RA: 532 mce_err->u.ra_error_type = table[i].error_subtype; 533 break; 534 case MCE_ERROR_TYPE_LINK: 535 mce_err->u.link_error_type = table[i].error_subtype; 536 break; 537 } 538 mce_err->sync_error = table[i].sync_error; 539 mce_err->severity = table[i].severity; 540 mce_err->initiator = table[i].initiator; 541 if (table[i].dar_valid) 542 *addr = regs->dar; 543 else if (mce_err->sync_error && 544 table[i].error_type == MCE_ERROR_TYPE_UE) { 545 /* 546 * We do a maximum of 4 nested MCE calls, see 547 * kernel/exception-64s.h 548 */ 549 if (get_paca()->in_mce < MAX_MCE_DEPTH) 550 mce_find_instr_ea_and_phys(regs, addr, 551 phys_addr); 552 } 553 found = 1; 554 } 555 556 if (found) 557 return handled; 558 559 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN; 560 mce_err->error_class = MCE_ECLASS_UNKNOWN; 561 mce_err->severity = MCE_SEV_SEVERE; 562 mce_err->initiator = MCE_INITIATOR_CPU; 563 mce_err->sync_error = true; 564 565 return 0; 566 } 567 568 static long mce_handle_ue_error(struct pt_regs *regs) 569 { 570 long handled = 0; 571 572 /* 573 * On specific SCOM read via MMIO we may get a machine check 574 * exception with SRR0 pointing inside opal. If that is the 575 * case OPAL may have recovery address to re-read SCOM data in 576 * different way and hence we can recover from this MC. 577 */ 578 579 if (ppc_md.mce_check_early_recovery) { 580 if (ppc_md.mce_check_early_recovery(regs)) 581 handled = 1; 582 } 583 return handled; 584 } 585 586 static long mce_handle_error(struct pt_regs *regs, 587 const struct mce_derror_table dtable[], 588 const struct mce_ierror_table itable[]) 589 { 590 struct mce_error_info mce_err = { 0 }; 591 uint64_t addr, phys_addr = ULONG_MAX; 592 uint64_t srr1 = regs->msr; 593 long handled; 594 595 if (SRR1_MC_LOADSTORE(srr1)) 596 handled = mce_handle_derror(regs, dtable, &mce_err, &addr, 597 &phys_addr); 598 else 599 handled = mce_handle_ierror(regs, itable, &mce_err, &addr, 600 &phys_addr); 601 602 if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE) 603 handled = mce_handle_ue_error(regs); 604 605 save_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr); 606 607 return handled; 608 } 609 610 long __machine_check_early_realmode_p7(struct pt_regs *regs) 611 { 612 /* P7 DD1 leaves top bits of DSISR undefined */ 613 regs->dsisr &= 0x0000ffff; 614 615 return mce_handle_error(regs, mce_p7_derror_table, mce_p7_ierror_table); 616 } 617 618 long __machine_check_early_realmode_p8(struct pt_regs *regs) 619 { 620 return mce_handle_error(regs, mce_p8_derror_table, mce_p8_ierror_table); 621 } 622 623 long __machine_check_early_realmode_p9(struct pt_regs *regs) 624 { 625 /* 626 * On POWER9 DD2.1 and below, it's possible to get a machine check 627 * caused by a paste instruction where only DSISR bit 25 is set. This 628 * will result in the MCE handler seeing an unknown event and the kernel 629 * crashing. An MCE that occurs like this is spurious, so we don't need 630 * to do anything in terms of servicing it. If there is something that 631 * needs to be serviced, the CPU will raise the MCE again with the 632 * correct DSISR so that it can be serviced properly. So detect this 633 * case and mark it as handled. 634 */ 635 if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000) 636 return 1; 637 638 return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table); 639 } 640