1 /* 2 * Machine check exception handling CPU-side for power7 and power8 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * Copyright 2013 IBM Corporation 19 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> 20 */ 21 22 #undef DEBUG 23 #define pr_fmt(fmt) "mce_power: " fmt 24 25 #include <linux/types.h> 26 #include <linux/ptrace.h> 27 #include <asm/mmu.h> 28 #include <asm/mce.h> 29 #include <asm/machdep.h> 30 31 static void flush_tlb_206(unsigned int num_sets, unsigned int action) 32 { 33 unsigned long rb; 34 unsigned int i; 35 36 switch (action) { 37 case TLB_INVAL_SCOPE_GLOBAL: 38 rb = TLBIEL_INVAL_SET; 39 break; 40 case TLB_INVAL_SCOPE_LPID: 41 rb = TLBIEL_INVAL_SET_LPID; 42 break; 43 default: 44 BUG(); 45 break; 46 } 47 48 asm volatile("ptesync" : : : "memory"); 49 for (i = 0; i < num_sets; i++) { 50 asm volatile("tlbiel %0" : : "r" (rb)); 51 rb += 1 << TLBIEL_INVAL_SET_SHIFT; 52 } 53 asm volatile("ptesync" : : : "memory"); 54 } 55 56 /* 57 * Generic routines to flush TLB on POWER processors. These routines 58 * are used as flush_tlb hook in the cpu_spec. 59 * 60 * action => TLB_INVAL_SCOPE_GLOBAL: Invalidate all TLBs. 61 * TLB_INVAL_SCOPE_LPID: Invalidate TLB for current LPID. 62 */ 63 void __flush_tlb_power7(unsigned int action) 64 { 65 flush_tlb_206(POWER7_TLB_SETS, action); 66 } 67 68 void __flush_tlb_power8(unsigned int action) 69 { 70 flush_tlb_206(POWER8_TLB_SETS, action); 71 } 72 73 void __flush_tlb_power9(unsigned int action) 74 { 75 unsigned int num_sets; 76 77 if (radix_enabled()) 78 num_sets = POWER9_TLB_SETS_RADIX; 79 else 80 num_sets = POWER9_TLB_SETS_HASH; 81 82 flush_tlb_206(num_sets, action); 83 } 84 85 86 /* flush SLBs and reload */ 87 #ifdef CONFIG_PPC_STD_MMU_64 88 static void flush_and_reload_slb(void) 89 { 90 struct slb_shadow *slb; 91 unsigned long i, n; 92 93 /* Invalidate all SLBs */ 94 asm volatile("slbmte %0,%0; slbia" : : "r" (0)); 95 96 #ifdef CONFIG_KVM_BOOK3S_HANDLER 97 /* 98 * If machine check is hit when in guest or in transition, we will 99 * only flush the SLBs and continue. 100 */ 101 if (get_paca()->kvm_hstate.in_guest) 102 return; 103 #endif 104 105 /* For host kernel, reload the SLBs from shadow SLB buffer. */ 106 slb = get_slb_shadow(); 107 if (!slb) 108 return; 109 110 n = min_t(u32, be32_to_cpu(slb->persistent), SLB_MIN_SIZE); 111 112 /* Load up the SLB entries from shadow SLB */ 113 for (i = 0; i < n; i++) { 114 unsigned long rb = be64_to_cpu(slb->save_area[i].esid); 115 unsigned long rs = be64_to_cpu(slb->save_area[i].vsid); 116 117 rb = (rb & ~0xFFFul) | i; 118 asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb)); 119 } 120 } 121 #endif 122 123 static void flush_erat(void) 124 { 125 asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); 126 } 127 128 #define MCE_FLUSH_SLB 1 129 #define MCE_FLUSH_TLB 2 130 #define MCE_FLUSH_ERAT 3 131 132 static int mce_flush(int what) 133 { 134 #ifdef CONFIG_PPC_STD_MMU_64 135 if (what == MCE_FLUSH_SLB) { 136 flush_and_reload_slb(); 137 return 1; 138 } 139 #endif 140 if (what == MCE_FLUSH_ERAT) { 141 flush_erat(); 142 return 1; 143 } 144 if (what == MCE_FLUSH_TLB) { 145 if (cur_cpu_spec && cur_cpu_spec->flush_tlb) { 146 cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL); 147 return 1; 148 } 149 } 150 151 return 0; 152 } 153 154 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) 155 156 struct mce_ierror_table { 157 unsigned long srr1_mask; 158 unsigned long srr1_value; 159 bool nip_valid; /* nip is a valid indicator of faulting address */ 160 unsigned int error_type; 161 unsigned int error_subtype; 162 unsigned int initiator; 163 unsigned int severity; 164 }; 165 166 static const struct mce_ierror_table mce_p7_ierror_table[] = { 167 { 0x00000000001c0000, 0x0000000000040000, true, 168 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, 169 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 170 { 0x00000000001c0000, 0x0000000000080000, true, 171 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, 172 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 173 { 0x00000000001c0000, 0x00000000000c0000, true, 174 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, 175 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 176 { 0x00000000001c0000, 0x0000000000100000, true, 177 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */ 178 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 179 { 0x00000000001c0000, 0x0000000000140000, true, 180 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, 181 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 182 { 0x00000000001c0000, 0x0000000000180000, true, 183 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, 184 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 185 { 0x00000000001c0000, 0x00000000001c0000, true, 186 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, 187 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 188 { 0, 0, 0, 0, 0, 0 } }; 189 190 static const struct mce_ierror_table mce_p8_ierror_table[] = { 191 { 0x00000000081c0000, 0x0000000000040000, true, 192 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, 193 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 194 { 0x00000000081c0000, 0x0000000000080000, true, 195 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, 196 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 197 { 0x00000000081c0000, 0x00000000000c0000, true, 198 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, 199 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 200 { 0x00000000081c0000, 0x0000000000100000, true, 201 MCE_ERROR_TYPE_ERAT,MCE_ERAT_ERROR_MULTIHIT, 202 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 203 { 0x00000000081c0000, 0x0000000000140000, true, 204 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, 205 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 206 { 0x00000000081c0000, 0x0000000000180000, true, 207 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, 208 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 209 { 0x00000000081c0000, 0x00000000001c0000, true, 210 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, 211 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 212 { 0x00000000081c0000, 0x0000000008000000, true, 213 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_IFETCH_TIMEOUT, 214 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 215 { 0x00000000081c0000, 0x0000000008040000, true, 216 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT, 217 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 218 { 0, 0, 0, 0, 0, 0 } }; 219 220 static const struct mce_ierror_table mce_p9_ierror_table[] = { 221 { 0x00000000081c0000, 0x0000000000040000, true, 222 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, 223 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 224 { 0x00000000081c0000, 0x0000000000080000, true, 225 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, 226 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 227 { 0x00000000081c0000, 0x00000000000c0000, true, 228 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, 229 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 230 { 0x00000000081c0000, 0x0000000000100000, true, 231 MCE_ERROR_TYPE_ERAT,MCE_ERAT_ERROR_MULTIHIT, 232 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 233 { 0x00000000081c0000, 0x0000000000140000, true, 234 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, 235 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 236 { 0x00000000081c0000, 0x0000000000180000, true, 237 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, 238 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 239 { 0x00000000081c0000, 0x00000000001c0000, true, 240 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN, 241 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 242 { 0x00000000081c0000, 0x0000000008000000, true, 243 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_IFETCH_TIMEOUT, 244 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 245 { 0x00000000081c0000, 0x0000000008040000, true, 246 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT, 247 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 248 { 0x00000000081c0000, 0x00000000080c0000, true, 249 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH, 250 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 251 { 0x00000000081c0000, 0x0000000008100000, true, 252 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH, 253 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 254 { 0x00000000081c0000, 0x0000000008140000, false, 255 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE, 256 MCE_INITIATOR_CPU, MCE_SEV_FATAL, }, /* ASYNC is fatal */ 257 { 0x00000000081c0000, 0x0000000008180000, false, 258 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_STORE_TIMEOUT, 259 MCE_INITIATOR_CPU, MCE_SEV_FATAL, }, /* ASYNC is fatal */ 260 { 0x00000000081c0000, 0x00000000081c0000, true, 261 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN, 262 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 263 { 0, 0, 0, 0, 0, 0 } }; 264 265 struct mce_derror_table { 266 unsigned long dsisr_value; 267 bool dar_valid; /* dar is a valid indicator of faulting address */ 268 unsigned int error_type; 269 unsigned int error_subtype; 270 unsigned int initiator; 271 unsigned int severity; 272 }; 273 274 static const struct mce_derror_table mce_p7_derror_table[] = { 275 { 0x00008000, false, 276 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, 277 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 278 { 0x00004000, true, 279 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 280 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 281 { 0x00000800, true, 282 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, 283 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 284 { 0x00000400, true, 285 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, 286 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 287 { 0x00000100, true, 288 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, 289 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 290 { 0x00000080, true, 291 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, 292 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 293 { 0x00000040, true, 294 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */ 295 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 296 { 0, false, 0, 0, 0, 0 } }; 297 298 static const struct mce_derror_table mce_p8_derror_table[] = { 299 { 0x00008000, false, 300 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, 301 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 302 { 0x00004000, true, 303 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 304 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 305 { 0x00002000, true, 306 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, 307 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 308 { 0x00001000, true, 309 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT, 310 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 311 { 0x00000800, true, 312 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, 313 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 314 { 0x00000400, true, 315 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, 316 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 317 { 0x00000200, true, 318 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, /* SECONDARY ERAT */ 319 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 320 { 0x00000100, true, 321 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, 322 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 323 { 0x00000080, true, 324 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, 325 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 326 { 0, false, 0, 0, 0, 0 } }; 327 328 static const struct mce_derror_table mce_p9_derror_table[] = { 329 { 0x00008000, false, 330 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, 331 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 332 { 0x00004000, true, 333 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 334 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 335 { 0x00002000, true, 336 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, 337 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 338 { 0x00001000, true, 339 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT, 340 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 341 { 0x00000800, true, 342 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, 343 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 344 { 0x00000400, true, 345 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, 346 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 347 { 0x00000200, false, 348 MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE, 349 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 350 { 0x00000100, true, 351 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, 352 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 353 { 0x00000080, true, 354 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, 355 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 356 { 0x00000040, true, 357 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD, 358 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 359 { 0x00000020, false, 360 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 361 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 362 { 0x00000010, false, 363 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN, 364 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 365 { 0x00000008, false, 366 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN, 367 MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, }, 368 { 0, false, 0, 0, 0, 0 } }; 369 370 static int mce_handle_ierror(struct pt_regs *regs, 371 const struct mce_ierror_table table[], 372 struct mce_error_info *mce_err, uint64_t *addr) 373 { 374 uint64_t srr1 = regs->msr; 375 int handled = 0; 376 int i; 377 378 *addr = 0; 379 380 for (i = 0; table[i].srr1_mask; i++) { 381 if ((srr1 & table[i].srr1_mask) != table[i].srr1_value) 382 continue; 383 384 /* attempt to correct the error */ 385 switch (table[i].error_type) { 386 case MCE_ERROR_TYPE_SLB: 387 handled = mce_flush(MCE_FLUSH_SLB); 388 break; 389 case MCE_ERROR_TYPE_ERAT: 390 handled = mce_flush(MCE_FLUSH_ERAT); 391 break; 392 case MCE_ERROR_TYPE_TLB: 393 handled = mce_flush(MCE_FLUSH_TLB); 394 break; 395 } 396 397 /* now fill in mce_error_info */ 398 mce_err->error_type = table[i].error_type; 399 switch (table[i].error_type) { 400 case MCE_ERROR_TYPE_UE: 401 mce_err->u.ue_error_type = table[i].error_subtype; 402 break; 403 case MCE_ERROR_TYPE_SLB: 404 mce_err->u.slb_error_type = table[i].error_subtype; 405 break; 406 case MCE_ERROR_TYPE_ERAT: 407 mce_err->u.erat_error_type = table[i].error_subtype; 408 break; 409 case MCE_ERROR_TYPE_TLB: 410 mce_err->u.tlb_error_type = table[i].error_subtype; 411 break; 412 case MCE_ERROR_TYPE_USER: 413 mce_err->u.user_error_type = table[i].error_subtype; 414 break; 415 case MCE_ERROR_TYPE_RA: 416 mce_err->u.ra_error_type = table[i].error_subtype; 417 break; 418 case MCE_ERROR_TYPE_LINK: 419 mce_err->u.link_error_type = table[i].error_subtype; 420 break; 421 } 422 mce_err->severity = table[i].severity; 423 mce_err->initiator = table[i].initiator; 424 if (table[i].nip_valid) 425 *addr = regs->nip; 426 return handled; 427 } 428 429 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN; 430 mce_err->severity = MCE_SEV_ERROR_SYNC; 431 mce_err->initiator = MCE_INITIATOR_CPU; 432 433 return 0; 434 } 435 436 static int mce_handle_derror(struct pt_regs *regs, 437 const struct mce_derror_table table[], 438 struct mce_error_info *mce_err, uint64_t *addr) 439 { 440 uint64_t dsisr = regs->dsisr; 441 int handled = 0; 442 int found = 0; 443 int i; 444 445 *addr = 0; 446 447 for (i = 0; table[i].dsisr_value; i++) { 448 if (!(dsisr & table[i].dsisr_value)) 449 continue; 450 451 /* attempt to correct the error */ 452 switch (table[i].error_type) { 453 case MCE_ERROR_TYPE_SLB: 454 if (mce_flush(MCE_FLUSH_SLB)) 455 handled = 1; 456 break; 457 case MCE_ERROR_TYPE_ERAT: 458 if (mce_flush(MCE_FLUSH_ERAT)) 459 handled = 1; 460 break; 461 case MCE_ERROR_TYPE_TLB: 462 if (mce_flush(MCE_FLUSH_TLB)) 463 handled = 1; 464 break; 465 } 466 467 /* 468 * Attempt to handle multiple conditions, but only return 469 * one. Ensure uncorrectable errors are first in the table 470 * to match. 471 */ 472 if (found) 473 continue; 474 475 /* now fill in mce_error_info */ 476 mce_err->error_type = table[i].error_type; 477 switch (table[i].error_type) { 478 case MCE_ERROR_TYPE_UE: 479 mce_err->u.ue_error_type = table[i].error_subtype; 480 break; 481 case MCE_ERROR_TYPE_SLB: 482 mce_err->u.slb_error_type = table[i].error_subtype; 483 break; 484 case MCE_ERROR_TYPE_ERAT: 485 mce_err->u.erat_error_type = table[i].error_subtype; 486 break; 487 case MCE_ERROR_TYPE_TLB: 488 mce_err->u.tlb_error_type = table[i].error_subtype; 489 break; 490 case MCE_ERROR_TYPE_USER: 491 mce_err->u.user_error_type = table[i].error_subtype; 492 break; 493 case MCE_ERROR_TYPE_RA: 494 mce_err->u.ra_error_type = table[i].error_subtype; 495 break; 496 case MCE_ERROR_TYPE_LINK: 497 mce_err->u.link_error_type = table[i].error_subtype; 498 break; 499 } 500 mce_err->severity = table[i].severity; 501 mce_err->initiator = table[i].initiator; 502 if (table[i].dar_valid) 503 *addr = regs->dar; 504 505 found = 1; 506 } 507 508 if (found) 509 return handled; 510 511 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN; 512 mce_err->severity = MCE_SEV_ERROR_SYNC; 513 mce_err->initiator = MCE_INITIATOR_CPU; 514 515 return 0; 516 } 517 518 static long mce_handle_ue_error(struct pt_regs *regs) 519 { 520 long handled = 0; 521 522 /* 523 * On specific SCOM read via MMIO we may get a machine check 524 * exception with SRR0 pointing inside opal. If that is the 525 * case OPAL may have recovery address to re-read SCOM data in 526 * different way and hence we can recover from this MC. 527 */ 528 529 if (ppc_md.mce_check_early_recovery) { 530 if (ppc_md.mce_check_early_recovery(regs)) 531 handled = 1; 532 } 533 return handled; 534 } 535 536 static long mce_handle_error(struct pt_regs *regs, 537 const struct mce_derror_table dtable[], 538 const struct mce_ierror_table itable[]) 539 { 540 struct mce_error_info mce_err = { 0 }; 541 uint64_t addr; 542 uint64_t srr1 = regs->msr; 543 long handled; 544 545 if (SRR1_MC_LOADSTORE(srr1)) 546 handled = mce_handle_derror(regs, dtable, &mce_err, &addr); 547 else 548 handled = mce_handle_ierror(regs, itable, &mce_err, &addr); 549 550 if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE) 551 handled = mce_handle_ue_error(regs); 552 553 save_mce_event(regs, handled, &mce_err, regs->nip, addr); 554 555 return handled; 556 } 557 558 long __machine_check_early_realmode_p7(struct pt_regs *regs) 559 { 560 /* P7 DD1 leaves top bits of DSISR undefined */ 561 regs->dsisr &= 0x0000ffff; 562 563 return mce_handle_error(regs, mce_p7_derror_table, mce_p7_ierror_table); 564 } 565 566 long __machine_check_early_realmode_p8(struct pt_regs *regs) 567 { 568 return mce_handle_error(regs, mce_p8_derror_table, mce_p8_ierror_table); 569 } 570 571 long __machine_check_early_realmode_p9(struct pt_regs *regs) 572 { 573 return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table); 574 } 575