1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 4 * 5 * Rewrite, cleanup, new allocation schemes, virtual merging: 6 * Copyright (C) 2004 Olof Johansson, IBM Corporation 7 * and Ben. Herrenschmidt, IBM Corporation 8 * 9 * Dynamic DMA mapping support, bus-independent parts. 10 */ 11 12 13 #include <linux/init.h> 14 #include <linux/types.h> 15 #include <linux/slab.h> 16 #include <linux/mm.h> 17 #include <linux/spinlock.h> 18 #include <linux/string.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/bitmap.h> 21 #include <linux/iommu-helper.h> 22 #include <linux/crash_dump.h> 23 #include <linux/hash.h> 24 #include <linux/fault-inject.h> 25 #include <linux/pci.h> 26 #include <linux/iommu.h> 27 #include <linux/sched.h> 28 #include <linux/debugfs.h> 29 #include <asm/io.h> 30 #include <asm/prom.h> 31 #include <asm/iommu.h> 32 #include <asm/pci-bridge.h> 33 #include <asm/machdep.h> 34 #include <asm/kdump.h> 35 #include <asm/fadump.h> 36 #include <asm/vio.h> 37 #include <asm/tce.h> 38 #include <asm/mmu_context.h> 39 40 #define DBG(...) 41 42 #ifdef CONFIG_IOMMU_DEBUGFS 43 static int iommu_debugfs_weight_get(void *data, u64 *val) 44 { 45 struct iommu_table *tbl = data; 46 *val = bitmap_weight(tbl->it_map, tbl->it_size); 47 return 0; 48 } 49 DEFINE_DEBUGFS_ATTRIBUTE(iommu_debugfs_fops_weight, iommu_debugfs_weight_get, NULL, "%llu\n"); 50 51 static void iommu_debugfs_add(struct iommu_table *tbl) 52 { 53 char name[10]; 54 struct dentry *liobn_entry; 55 56 sprintf(name, "%08lx", tbl->it_index); 57 liobn_entry = debugfs_create_dir(name, iommu_debugfs_dir); 58 59 debugfs_create_file_unsafe("weight", 0400, liobn_entry, tbl, &iommu_debugfs_fops_weight); 60 debugfs_create_ulong("it_size", 0400, liobn_entry, &tbl->it_size); 61 debugfs_create_ulong("it_page_shift", 0400, liobn_entry, &tbl->it_page_shift); 62 debugfs_create_ulong("it_reserved_start", 0400, liobn_entry, &tbl->it_reserved_start); 63 debugfs_create_ulong("it_reserved_end", 0400, liobn_entry, &tbl->it_reserved_end); 64 debugfs_create_ulong("it_indirect_levels", 0400, liobn_entry, &tbl->it_indirect_levels); 65 debugfs_create_ulong("it_level_size", 0400, liobn_entry, &tbl->it_level_size); 66 } 67 68 static void iommu_debugfs_del(struct iommu_table *tbl) 69 { 70 char name[10]; 71 struct dentry *liobn_entry; 72 73 sprintf(name, "%08lx", tbl->it_index); 74 liobn_entry = debugfs_lookup(name, iommu_debugfs_dir); 75 debugfs_remove(liobn_entry); 76 } 77 #else 78 static void iommu_debugfs_add(struct iommu_table *tbl){} 79 static void iommu_debugfs_del(struct iommu_table *tbl){} 80 #endif 81 82 static int novmerge; 83 84 static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int); 85 86 static int __init setup_iommu(char *str) 87 { 88 if (!strcmp(str, "novmerge")) 89 novmerge = 1; 90 else if (!strcmp(str, "vmerge")) 91 novmerge = 0; 92 return 1; 93 } 94 95 __setup("iommu=", setup_iommu); 96 97 static DEFINE_PER_CPU(unsigned int, iommu_pool_hash); 98 99 /* 100 * We precalculate the hash to avoid doing it on every allocation. 101 * 102 * The hash is important to spread CPUs across all the pools. For example, 103 * on a POWER7 with 4 way SMT we want interrupts on the primary threads and 104 * with 4 pools all primary threads would map to the same pool. 105 */ 106 static int __init setup_iommu_pool_hash(void) 107 { 108 unsigned int i; 109 110 for_each_possible_cpu(i) 111 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS); 112 113 return 0; 114 } 115 subsys_initcall(setup_iommu_pool_hash); 116 117 #ifdef CONFIG_FAIL_IOMMU 118 119 static DECLARE_FAULT_ATTR(fail_iommu); 120 121 static int __init setup_fail_iommu(char *str) 122 { 123 return setup_fault_attr(&fail_iommu, str); 124 } 125 __setup("fail_iommu=", setup_fail_iommu); 126 127 static bool should_fail_iommu(struct device *dev) 128 { 129 return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1); 130 } 131 132 static int __init fail_iommu_debugfs(void) 133 { 134 struct dentry *dir = fault_create_debugfs_attr("fail_iommu", 135 NULL, &fail_iommu); 136 137 return PTR_ERR_OR_ZERO(dir); 138 } 139 late_initcall(fail_iommu_debugfs); 140 141 static ssize_t fail_iommu_show(struct device *dev, 142 struct device_attribute *attr, char *buf) 143 { 144 return sprintf(buf, "%d\n", dev->archdata.fail_iommu); 145 } 146 147 static ssize_t fail_iommu_store(struct device *dev, 148 struct device_attribute *attr, const char *buf, 149 size_t count) 150 { 151 int i; 152 153 if (count > 0 && sscanf(buf, "%d", &i) > 0) 154 dev->archdata.fail_iommu = (i == 0) ? 0 : 1; 155 156 return count; 157 } 158 159 static DEVICE_ATTR_RW(fail_iommu); 160 161 static int fail_iommu_bus_notify(struct notifier_block *nb, 162 unsigned long action, void *data) 163 { 164 struct device *dev = data; 165 166 if (action == BUS_NOTIFY_ADD_DEVICE) { 167 if (device_create_file(dev, &dev_attr_fail_iommu)) 168 pr_warn("Unable to create IOMMU fault injection sysfs " 169 "entries\n"); 170 } else if (action == BUS_NOTIFY_DEL_DEVICE) { 171 device_remove_file(dev, &dev_attr_fail_iommu); 172 } 173 174 return 0; 175 } 176 177 static struct notifier_block fail_iommu_bus_notifier = { 178 .notifier_call = fail_iommu_bus_notify 179 }; 180 181 static int __init fail_iommu_setup(void) 182 { 183 #ifdef CONFIG_PCI 184 bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier); 185 #endif 186 #ifdef CONFIG_IBMVIO 187 bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier); 188 #endif 189 190 return 0; 191 } 192 /* 193 * Must execute after PCI and VIO subsystem have initialised but before 194 * devices are probed. 195 */ 196 arch_initcall(fail_iommu_setup); 197 #else 198 static inline bool should_fail_iommu(struct device *dev) 199 { 200 return false; 201 } 202 #endif 203 204 static unsigned long iommu_range_alloc(struct device *dev, 205 struct iommu_table *tbl, 206 unsigned long npages, 207 unsigned long *handle, 208 unsigned long mask, 209 unsigned int align_order) 210 { 211 unsigned long n, end, start; 212 unsigned long limit; 213 int largealloc = npages > 15; 214 int pass = 0; 215 unsigned long align_mask; 216 unsigned long flags; 217 unsigned int pool_nr; 218 struct iommu_pool *pool; 219 220 align_mask = (1ull << align_order) - 1; 221 222 /* This allocator was derived from x86_64's bit string search */ 223 224 /* Sanity check */ 225 if (unlikely(npages == 0)) { 226 if (printk_ratelimit()) 227 WARN_ON(1); 228 return DMA_MAPPING_ERROR; 229 } 230 231 if (should_fail_iommu(dev)) 232 return DMA_MAPPING_ERROR; 233 234 /* 235 * We don't need to disable preemption here because any CPU can 236 * safely use any IOMMU pool. 237 */ 238 pool_nr = raw_cpu_read(iommu_pool_hash) & (tbl->nr_pools - 1); 239 240 if (largealloc) 241 pool = &(tbl->large_pool); 242 else 243 pool = &(tbl->pools[pool_nr]); 244 245 spin_lock_irqsave(&(pool->lock), flags); 246 247 again: 248 if ((pass == 0) && handle && *handle && 249 (*handle >= pool->start) && (*handle < pool->end)) 250 start = *handle; 251 else 252 start = pool->hint; 253 254 limit = pool->end; 255 256 /* The case below can happen if we have a small segment appended 257 * to a large, or when the previous alloc was at the very end of 258 * the available space. If so, go back to the initial start. 259 */ 260 if (start >= limit) 261 start = pool->start; 262 263 if (limit + tbl->it_offset > mask) { 264 limit = mask - tbl->it_offset + 1; 265 /* If we're constrained on address range, first try 266 * at the masked hint to avoid O(n) search complexity, 267 * but on second pass, start at 0 in pool 0. 268 */ 269 if ((start & mask) >= limit || pass > 0) { 270 spin_unlock(&(pool->lock)); 271 pool = &(tbl->pools[0]); 272 spin_lock(&(pool->lock)); 273 start = pool->start; 274 } else { 275 start &= mask; 276 } 277 } 278 279 n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset, 280 dma_get_seg_boundary_nr_pages(dev, tbl->it_page_shift), 281 align_mask); 282 if (n == -1) { 283 if (likely(pass == 0)) { 284 /* First try the pool from the start */ 285 pool->hint = pool->start; 286 pass++; 287 goto again; 288 289 } else if (pass <= tbl->nr_pools) { 290 /* Now try scanning all the other pools */ 291 spin_unlock(&(pool->lock)); 292 pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1); 293 pool = &tbl->pools[pool_nr]; 294 spin_lock(&(pool->lock)); 295 pool->hint = pool->start; 296 pass++; 297 goto again; 298 299 } else { 300 /* Give up */ 301 spin_unlock_irqrestore(&(pool->lock), flags); 302 return DMA_MAPPING_ERROR; 303 } 304 } 305 306 end = n + npages; 307 308 /* Bump the hint to a new block for small allocs. */ 309 if (largealloc) { 310 /* Don't bump to new block to avoid fragmentation */ 311 pool->hint = end; 312 } else { 313 /* Overflow will be taken care of at the next allocation */ 314 pool->hint = (end + tbl->it_blocksize - 1) & 315 ~(tbl->it_blocksize - 1); 316 } 317 318 /* Update handle for SG allocations */ 319 if (handle) 320 *handle = end; 321 322 spin_unlock_irqrestore(&(pool->lock), flags); 323 324 return n; 325 } 326 327 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl, 328 void *page, unsigned int npages, 329 enum dma_data_direction direction, 330 unsigned long mask, unsigned int align_order, 331 unsigned long attrs) 332 { 333 unsigned long entry; 334 dma_addr_t ret = DMA_MAPPING_ERROR; 335 int build_fail; 336 337 entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order); 338 339 if (unlikely(entry == DMA_MAPPING_ERROR)) 340 return DMA_MAPPING_ERROR; 341 342 entry += tbl->it_offset; /* Offset into real TCE table */ 343 ret = entry << tbl->it_page_shift; /* Set the return dma address */ 344 345 /* Put the TCEs in the HW table */ 346 build_fail = tbl->it_ops->set(tbl, entry, npages, 347 (unsigned long)page & 348 IOMMU_PAGE_MASK(tbl), direction, attrs); 349 350 /* tbl->it_ops->set() only returns non-zero for transient errors. 351 * Clean up the table bitmap in this case and return 352 * DMA_MAPPING_ERROR. For all other errors the functionality is 353 * not altered. 354 */ 355 if (unlikely(build_fail)) { 356 __iommu_free(tbl, ret, npages); 357 return DMA_MAPPING_ERROR; 358 } 359 360 /* Flush/invalidate TLB caches if necessary */ 361 if (tbl->it_ops->flush) 362 tbl->it_ops->flush(tbl); 363 364 /* Make sure updates are seen by hardware */ 365 mb(); 366 367 return ret; 368 } 369 370 static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr, 371 unsigned int npages) 372 { 373 unsigned long entry, free_entry; 374 375 entry = dma_addr >> tbl->it_page_shift; 376 free_entry = entry - tbl->it_offset; 377 378 if (((free_entry + npages) > tbl->it_size) || 379 (entry < tbl->it_offset)) { 380 if (printk_ratelimit()) { 381 printk(KERN_INFO "iommu_free: invalid entry\n"); 382 printk(KERN_INFO "\tentry = 0x%lx\n", entry); 383 printk(KERN_INFO "\tdma_addr = 0x%llx\n", (u64)dma_addr); 384 printk(KERN_INFO "\tTable = 0x%llx\n", (u64)tbl); 385 printk(KERN_INFO "\tbus# = 0x%llx\n", (u64)tbl->it_busno); 386 printk(KERN_INFO "\tsize = 0x%llx\n", (u64)tbl->it_size); 387 printk(KERN_INFO "\tstartOff = 0x%llx\n", (u64)tbl->it_offset); 388 printk(KERN_INFO "\tindex = 0x%llx\n", (u64)tbl->it_index); 389 WARN_ON(1); 390 } 391 392 return false; 393 } 394 395 return true; 396 } 397 398 static struct iommu_pool *get_pool(struct iommu_table *tbl, 399 unsigned long entry) 400 { 401 struct iommu_pool *p; 402 unsigned long largepool_start = tbl->large_pool.start; 403 404 /* The large pool is the last pool at the top of the table */ 405 if (entry >= largepool_start) { 406 p = &tbl->large_pool; 407 } else { 408 unsigned int pool_nr = entry / tbl->poolsize; 409 410 BUG_ON(pool_nr > tbl->nr_pools); 411 p = &tbl->pools[pool_nr]; 412 } 413 414 return p; 415 } 416 417 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, 418 unsigned int npages) 419 { 420 unsigned long entry, free_entry; 421 unsigned long flags; 422 struct iommu_pool *pool; 423 424 entry = dma_addr >> tbl->it_page_shift; 425 free_entry = entry - tbl->it_offset; 426 427 pool = get_pool(tbl, free_entry); 428 429 if (!iommu_free_check(tbl, dma_addr, npages)) 430 return; 431 432 tbl->it_ops->clear(tbl, entry, npages); 433 434 spin_lock_irqsave(&(pool->lock), flags); 435 bitmap_clear(tbl->it_map, free_entry, npages); 436 spin_unlock_irqrestore(&(pool->lock), flags); 437 } 438 439 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, 440 unsigned int npages) 441 { 442 __iommu_free(tbl, dma_addr, npages); 443 444 /* Make sure TLB cache is flushed if the HW needs it. We do 445 * not do an mb() here on purpose, it is not needed on any of 446 * the current platforms. 447 */ 448 if (tbl->it_ops->flush) 449 tbl->it_ops->flush(tbl); 450 } 451 452 int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl, 453 struct scatterlist *sglist, int nelems, 454 unsigned long mask, enum dma_data_direction direction, 455 unsigned long attrs) 456 { 457 dma_addr_t dma_next = 0, dma_addr; 458 struct scatterlist *s, *outs, *segstart; 459 int outcount, incount, i, build_fail = 0; 460 unsigned int align; 461 unsigned long handle; 462 unsigned int max_seg_size; 463 464 BUG_ON(direction == DMA_NONE); 465 466 if ((nelems == 0) || !tbl) 467 return 0; 468 469 outs = s = segstart = &sglist[0]; 470 outcount = 1; 471 incount = nelems; 472 handle = 0; 473 474 /* Init first segment length for backout at failure */ 475 outs->dma_length = 0; 476 477 DBG("sg mapping %d elements:\n", nelems); 478 479 max_seg_size = dma_get_max_seg_size(dev); 480 for_each_sg(sglist, s, nelems, i) { 481 unsigned long vaddr, npages, entry, slen; 482 483 slen = s->length; 484 /* Sanity check */ 485 if (slen == 0) { 486 dma_next = 0; 487 continue; 488 } 489 /* Allocate iommu entries for that segment */ 490 vaddr = (unsigned long) sg_virt(s); 491 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl)); 492 align = 0; 493 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE && 494 (vaddr & ~PAGE_MASK) == 0) 495 align = PAGE_SHIFT - tbl->it_page_shift; 496 entry = iommu_range_alloc(dev, tbl, npages, &handle, 497 mask >> tbl->it_page_shift, align); 498 499 DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen); 500 501 /* Handle failure */ 502 if (unlikely(entry == DMA_MAPPING_ERROR)) { 503 if (!(attrs & DMA_ATTR_NO_WARN) && 504 printk_ratelimit()) 505 dev_info(dev, "iommu_alloc failed, tbl %p " 506 "vaddr %lx npages %lu\n", tbl, vaddr, 507 npages); 508 goto failure; 509 } 510 511 /* Convert entry to a dma_addr_t */ 512 entry += tbl->it_offset; 513 dma_addr = entry << tbl->it_page_shift; 514 dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl)); 515 516 DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n", 517 npages, entry, dma_addr); 518 519 /* Insert into HW table */ 520 build_fail = tbl->it_ops->set(tbl, entry, npages, 521 vaddr & IOMMU_PAGE_MASK(tbl), 522 direction, attrs); 523 if(unlikely(build_fail)) 524 goto failure; 525 526 /* If we are in an open segment, try merging */ 527 if (segstart != s) { 528 DBG(" - trying merge...\n"); 529 /* We cannot merge if: 530 * - allocated dma_addr isn't contiguous to previous allocation 531 */ 532 if (novmerge || (dma_addr != dma_next) || 533 (outs->dma_length + s->length > max_seg_size)) { 534 /* Can't merge: create a new segment */ 535 segstart = s; 536 outcount++; 537 outs = sg_next(outs); 538 DBG(" can't merge, new segment.\n"); 539 } else { 540 outs->dma_length += s->length; 541 DBG(" merged, new len: %ux\n", outs->dma_length); 542 } 543 } 544 545 if (segstart == s) { 546 /* This is a new segment, fill entries */ 547 DBG(" - filling new segment.\n"); 548 outs->dma_address = dma_addr; 549 outs->dma_length = slen; 550 } 551 552 /* Calculate next page pointer for contiguous check */ 553 dma_next = dma_addr + slen; 554 555 DBG(" - dma next is: %lx\n", dma_next); 556 } 557 558 /* Flush/invalidate TLB caches if necessary */ 559 if (tbl->it_ops->flush) 560 tbl->it_ops->flush(tbl); 561 562 DBG("mapped %d elements:\n", outcount); 563 564 /* For the sake of ppc_iommu_unmap_sg, we clear out the length in the 565 * next entry of the sglist if we didn't fill the list completely 566 */ 567 if (outcount < incount) { 568 outs = sg_next(outs); 569 outs->dma_address = DMA_MAPPING_ERROR; 570 outs->dma_length = 0; 571 } 572 573 /* Make sure updates are seen by hardware */ 574 mb(); 575 576 return outcount; 577 578 failure: 579 for_each_sg(sglist, s, nelems, i) { 580 if (s->dma_length != 0) { 581 unsigned long vaddr, npages; 582 583 vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl); 584 npages = iommu_num_pages(s->dma_address, s->dma_length, 585 IOMMU_PAGE_SIZE(tbl)); 586 __iommu_free(tbl, vaddr, npages); 587 s->dma_address = DMA_MAPPING_ERROR; 588 s->dma_length = 0; 589 } 590 if (s == outs) 591 break; 592 } 593 return 0; 594 } 595 596 597 void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist, 598 int nelems, enum dma_data_direction direction, 599 unsigned long attrs) 600 { 601 struct scatterlist *sg; 602 603 BUG_ON(direction == DMA_NONE); 604 605 if (!tbl) 606 return; 607 608 sg = sglist; 609 while (nelems--) { 610 unsigned int npages; 611 dma_addr_t dma_handle = sg->dma_address; 612 613 if (sg->dma_length == 0) 614 break; 615 npages = iommu_num_pages(dma_handle, sg->dma_length, 616 IOMMU_PAGE_SIZE(tbl)); 617 __iommu_free(tbl, dma_handle, npages); 618 sg = sg_next(sg); 619 } 620 621 /* Flush/invalidate TLBs if necessary. As for iommu_free(), we 622 * do not do an mb() here, the affected platforms do not need it 623 * when freeing. 624 */ 625 if (tbl->it_ops->flush) 626 tbl->it_ops->flush(tbl); 627 } 628 629 static void iommu_table_clear(struct iommu_table *tbl) 630 { 631 /* 632 * In case of firmware assisted dump system goes through clean 633 * reboot process at the time of system crash. Hence it's safe to 634 * clear the TCE entries if firmware assisted dump is active. 635 */ 636 if (!is_kdump_kernel() || is_fadump_active()) { 637 /* Clear the table in case firmware left allocations in it */ 638 tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size); 639 return; 640 } 641 642 #ifdef CONFIG_CRASH_DUMP 643 if (tbl->it_ops->get) { 644 unsigned long index, tceval, tcecount = 0; 645 646 /* Reserve the existing mappings left by the first kernel. */ 647 for (index = 0; index < tbl->it_size; index++) { 648 tceval = tbl->it_ops->get(tbl, index + tbl->it_offset); 649 /* 650 * Freed TCE entry contains 0x7fffffffffffffff on JS20 651 */ 652 if (tceval && (tceval != 0x7fffffffffffffffUL)) { 653 __set_bit(index, tbl->it_map); 654 tcecount++; 655 } 656 } 657 658 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) { 659 printk(KERN_WARNING "TCE table is full; freeing "); 660 printk(KERN_WARNING "%d entries for the kdump boot\n", 661 KDUMP_MIN_TCE_ENTRIES); 662 for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES; 663 index < tbl->it_size; index++) 664 __clear_bit(index, tbl->it_map); 665 } 666 } 667 #endif 668 } 669 670 static void iommu_table_reserve_pages(struct iommu_table *tbl, 671 unsigned long res_start, unsigned long res_end) 672 { 673 int i; 674 675 WARN_ON_ONCE(res_end < res_start); 676 /* 677 * Reserve page 0 so it will not be used for any mappings. 678 * This avoids buggy drivers that consider page 0 to be invalid 679 * to crash the machine or even lose data. 680 */ 681 if (tbl->it_offset == 0) 682 set_bit(0, tbl->it_map); 683 684 tbl->it_reserved_start = res_start; 685 tbl->it_reserved_end = res_end; 686 687 /* Check if res_start..res_end isn't empty and overlaps the table */ 688 if (res_start && res_end && 689 (tbl->it_offset + tbl->it_size < res_start || 690 res_end < tbl->it_offset)) 691 return; 692 693 for (i = tbl->it_reserved_start; i < tbl->it_reserved_end; ++i) 694 set_bit(i - tbl->it_offset, tbl->it_map); 695 } 696 697 static void iommu_table_release_pages(struct iommu_table *tbl) 698 { 699 int i; 700 701 /* 702 * In case we have reserved the first bit, we should not emit 703 * the warning below. 704 */ 705 if (tbl->it_offset == 0) 706 clear_bit(0, tbl->it_map); 707 708 for (i = tbl->it_reserved_start; i < tbl->it_reserved_end; ++i) 709 clear_bit(i - tbl->it_offset, tbl->it_map); 710 } 711 712 /* 713 * Build a iommu_table structure. This contains a bit map which 714 * is used to manage allocation of the tce space. 715 */ 716 struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid, 717 unsigned long res_start, unsigned long res_end) 718 { 719 unsigned long sz; 720 static int welcomed = 0; 721 struct page *page; 722 unsigned int i; 723 struct iommu_pool *p; 724 725 BUG_ON(!tbl->it_ops); 726 727 /* number of bytes needed for the bitmap */ 728 sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long); 729 730 page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz)); 731 if (!page) 732 panic("iommu_init_table: Can't allocate %ld bytes\n", sz); 733 tbl->it_map = page_address(page); 734 memset(tbl->it_map, 0, sz); 735 736 iommu_table_reserve_pages(tbl, res_start, res_end); 737 738 /* We only split the IOMMU table if we have 1GB or more of space */ 739 if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024)) 740 tbl->nr_pools = IOMMU_NR_POOLS; 741 else 742 tbl->nr_pools = 1; 743 744 /* We reserve the top 1/4 of the table for large allocations */ 745 tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools; 746 747 for (i = 0; i < tbl->nr_pools; i++) { 748 p = &tbl->pools[i]; 749 spin_lock_init(&(p->lock)); 750 p->start = tbl->poolsize * i; 751 p->hint = p->start; 752 p->end = p->start + tbl->poolsize; 753 } 754 755 p = &tbl->large_pool; 756 spin_lock_init(&(p->lock)); 757 p->start = tbl->poolsize * i; 758 p->hint = p->start; 759 p->end = tbl->it_size; 760 761 iommu_table_clear(tbl); 762 763 if (!welcomed) { 764 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n", 765 novmerge ? "disabled" : "enabled"); 766 welcomed = 1; 767 } 768 769 iommu_debugfs_add(tbl); 770 771 return tbl; 772 } 773 774 static void iommu_table_free(struct kref *kref) 775 { 776 unsigned long bitmap_sz; 777 unsigned int order; 778 struct iommu_table *tbl; 779 780 tbl = container_of(kref, struct iommu_table, it_kref); 781 782 if (tbl->it_ops->free) 783 tbl->it_ops->free(tbl); 784 785 if (!tbl->it_map) { 786 kfree(tbl); 787 return; 788 } 789 790 iommu_debugfs_del(tbl); 791 792 iommu_table_release_pages(tbl); 793 794 /* verify that table contains no entries */ 795 if (!bitmap_empty(tbl->it_map, tbl->it_size)) 796 pr_warn("%s: Unexpected TCEs\n", __func__); 797 798 /* calculate bitmap size in bytes */ 799 bitmap_sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long); 800 801 /* free bitmap */ 802 order = get_order(bitmap_sz); 803 free_pages((unsigned long) tbl->it_map, order); 804 805 /* free table */ 806 kfree(tbl); 807 } 808 809 struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl) 810 { 811 if (kref_get_unless_zero(&tbl->it_kref)) 812 return tbl; 813 814 return NULL; 815 } 816 EXPORT_SYMBOL_GPL(iommu_tce_table_get); 817 818 int iommu_tce_table_put(struct iommu_table *tbl) 819 { 820 if (WARN_ON(!tbl)) 821 return 0; 822 823 return kref_put(&tbl->it_kref, iommu_table_free); 824 } 825 EXPORT_SYMBOL_GPL(iommu_tce_table_put); 826 827 /* Creates TCEs for a user provided buffer. The user buffer must be 828 * contiguous real kernel storage (not vmalloc). The address passed here 829 * comprises a page address and offset into that page. The dma_addr_t 830 * returned will point to the same byte within the page as was passed in. 831 */ 832 dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl, 833 struct page *page, unsigned long offset, size_t size, 834 unsigned long mask, enum dma_data_direction direction, 835 unsigned long attrs) 836 { 837 dma_addr_t dma_handle = DMA_MAPPING_ERROR; 838 void *vaddr; 839 unsigned long uaddr; 840 unsigned int npages, align; 841 842 BUG_ON(direction == DMA_NONE); 843 844 vaddr = page_address(page) + offset; 845 uaddr = (unsigned long)vaddr; 846 847 if (tbl) { 848 npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl)); 849 align = 0; 850 if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE && 851 ((unsigned long)vaddr & ~PAGE_MASK) == 0) 852 align = PAGE_SHIFT - tbl->it_page_shift; 853 854 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction, 855 mask >> tbl->it_page_shift, align, 856 attrs); 857 if (dma_handle == DMA_MAPPING_ERROR) { 858 if (!(attrs & DMA_ATTR_NO_WARN) && 859 printk_ratelimit()) { 860 dev_info(dev, "iommu_alloc failed, tbl %p " 861 "vaddr %p npages %d\n", tbl, vaddr, 862 npages); 863 } 864 } else 865 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl)); 866 } 867 868 return dma_handle; 869 } 870 871 void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle, 872 size_t size, enum dma_data_direction direction, 873 unsigned long attrs) 874 { 875 unsigned int npages; 876 877 BUG_ON(direction == DMA_NONE); 878 879 if (tbl) { 880 npages = iommu_num_pages(dma_handle, size, 881 IOMMU_PAGE_SIZE(tbl)); 882 iommu_free(tbl, dma_handle, npages); 883 } 884 } 885 886 /* Allocates a contiguous real buffer and creates mappings over it. 887 * Returns the virtual address of the buffer and sets dma_handle 888 * to the dma address (mapping) of the first page. 889 */ 890 void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl, 891 size_t size, dma_addr_t *dma_handle, 892 unsigned long mask, gfp_t flag, int node) 893 { 894 void *ret = NULL; 895 dma_addr_t mapping; 896 unsigned int order; 897 unsigned int nio_pages, io_order; 898 struct page *page; 899 900 size = PAGE_ALIGN(size); 901 order = get_order(size); 902 903 /* 904 * Client asked for way too much space. This is checked later 905 * anyway. It is easier to debug here for the drivers than in 906 * the tce tables. 907 */ 908 if (order >= IOMAP_MAX_ORDER) { 909 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n", 910 size); 911 return NULL; 912 } 913 914 if (!tbl) 915 return NULL; 916 917 /* Alloc enough pages (and possibly more) */ 918 page = alloc_pages_node(node, flag, order); 919 if (!page) 920 return NULL; 921 ret = page_address(page); 922 memset(ret, 0, size); 923 924 /* Set up tces to cover the allocated range */ 925 nio_pages = size >> tbl->it_page_shift; 926 io_order = get_iommu_order(size, tbl); 927 mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL, 928 mask >> tbl->it_page_shift, io_order, 0); 929 if (mapping == DMA_MAPPING_ERROR) { 930 free_pages((unsigned long)ret, order); 931 return NULL; 932 } 933 *dma_handle = mapping; 934 return ret; 935 } 936 937 void iommu_free_coherent(struct iommu_table *tbl, size_t size, 938 void *vaddr, dma_addr_t dma_handle) 939 { 940 if (tbl) { 941 unsigned int nio_pages; 942 943 size = PAGE_ALIGN(size); 944 nio_pages = size >> tbl->it_page_shift; 945 iommu_free(tbl, dma_handle, nio_pages); 946 size = PAGE_ALIGN(size); 947 free_pages((unsigned long)vaddr, get_order(size)); 948 } 949 } 950 951 unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir) 952 { 953 switch (dir) { 954 case DMA_BIDIRECTIONAL: 955 return TCE_PCI_READ | TCE_PCI_WRITE; 956 case DMA_FROM_DEVICE: 957 return TCE_PCI_WRITE; 958 case DMA_TO_DEVICE: 959 return TCE_PCI_READ; 960 default: 961 return 0; 962 } 963 } 964 EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm); 965 966 #ifdef CONFIG_IOMMU_API 967 /* 968 * SPAPR TCE API 969 */ 970 static void group_release(void *iommu_data) 971 { 972 struct iommu_table_group *table_group = iommu_data; 973 974 table_group->group = NULL; 975 } 976 977 void iommu_register_group(struct iommu_table_group *table_group, 978 int pci_domain_number, unsigned long pe_num) 979 { 980 struct iommu_group *grp; 981 char *name; 982 983 grp = iommu_group_alloc(); 984 if (IS_ERR(grp)) { 985 pr_warn("powerpc iommu api: cannot create new group, err=%ld\n", 986 PTR_ERR(grp)); 987 return; 988 } 989 table_group->group = grp; 990 iommu_group_set_iommudata(grp, table_group, group_release); 991 name = kasprintf(GFP_KERNEL, "domain%d-pe%lx", 992 pci_domain_number, pe_num); 993 if (!name) 994 return; 995 iommu_group_set_name(grp, name); 996 kfree(name); 997 } 998 999 enum dma_data_direction iommu_tce_direction(unsigned long tce) 1000 { 1001 if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE)) 1002 return DMA_BIDIRECTIONAL; 1003 else if (tce & TCE_PCI_READ) 1004 return DMA_TO_DEVICE; 1005 else if (tce & TCE_PCI_WRITE) 1006 return DMA_FROM_DEVICE; 1007 else 1008 return DMA_NONE; 1009 } 1010 EXPORT_SYMBOL_GPL(iommu_tce_direction); 1011 1012 void iommu_flush_tce(struct iommu_table *tbl) 1013 { 1014 /* Flush/invalidate TLB caches if necessary */ 1015 if (tbl->it_ops->flush) 1016 tbl->it_ops->flush(tbl); 1017 1018 /* Make sure updates are seen by hardware */ 1019 mb(); 1020 } 1021 EXPORT_SYMBOL_GPL(iommu_flush_tce); 1022 1023 int iommu_tce_check_ioba(unsigned long page_shift, 1024 unsigned long offset, unsigned long size, 1025 unsigned long ioba, unsigned long npages) 1026 { 1027 unsigned long mask = (1UL << page_shift) - 1; 1028 1029 if (ioba & mask) 1030 return -EINVAL; 1031 1032 ioba >>= page_shift; 1033 if (ioba < offset) 1034 return -EINVAL; 1035 1036 if ((ioba + 1) > (offset + size)) 1037 return -EINVAL; 1038 1039 return 0; 1040 } 1041 EXPORT_SYMBOL_GPL(iommu_tce_check_ioba); 1042 1043 int iommu_tce_check_gpa(unsigned long page_shift, unsigned long gpa) 1044 { 1045 unsigned long mask = (1UL << page_shift) - 1; 1046 1047 if (gpa & mask) 1048 return -EINVAL; 1049 1050 return 0; 1051 } 1052 EXPORT_SYMBOL_GPL(iommu_tce_check_gpa); 1053 1054 extern long iommu_tce_xchg_no_kill(struct mm_struct *mm, 1055 struct iommu_table *tbl, 1056 unsigned long entry, unsigned long *hpa, 1057 enum dma_data_direction *direction) 1058 { 1059 long ret; 1060 unsigned long size = 0; 1061 1062 ret = tbl->it_ops->xchg_no_kill(tbl, entry, hpa, direction, false); 1063 if (!ret && ((*direction == DMA_FROM_DEVICE) || 1064 (*direction == DMA_BIDIRECTIONAL)) && 1065 !mm_iommu_is_devmem(mm, *hpa, tbl->it_page_shift, 1066 &size)) 1067 SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT)); 1068 1069 return ret; 1070 } 1071 EXPORT_SYMBOL_GPL(iommu_tce_xchg_no_kill); 1072 1073 void iommu_tce_kill(struct iommu_table *tbl, 1074 unsigned long entry, unsigned long pages) 1075 { 1076 if (tbl->it_ops->tce_kill) 1077 tbl->it_ops->tce_kill(tbl, entry, pages, false); 1078 } 1079 EXPORT_SYMBOL_GPL(iommu_tce_kill); 1080 1081 int iommu_take_ownership(struct iommu_table *tbl) 1082 { 1083 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3; 1084 int ret = 0; 1085 1086 /* 1087 * VFIO does not control TCE entries allocation and the guest 1088 * can write new TCEs on top of existing ones so iommu_tce_build() 1089 * must be able to release old pages. This functionality 1090 * requires exchange() callback defined so if it is not 1091 * implemented, we disallow taking ownership over the table. 1092 */ 1093 if (!tbl->it_ops->xchg_no_kill) 1094 return -EINVAL; 1095 1096 spin_lock_irqsave(&tbl->large_pool.lock, flags); 1097 for (i = 0; i < tbl->nr_pools; i++) 1098 spin_lock(&tbl->pools[i].lock); 1099 1100 iommu_table_release_pages(tbl); 1101 1102 if (!bitmap_empty(tbl->it_map, tbl->it_size)) { 1103 pr_err("iommu_tce: it_map is not empty"); 1104 ret = -EBUSY; 1105 /* Undo iommu_table_release_pages, i.e. restore bit#0, etc */ 1106 iommu_table_reserve_pages(tbl, tbl->it_reserved_start, 1107 tbl->it_reserved_end); 1108 } else { 1109 memset(tbl->it_map, 0xff, sz); 1110 } 1111 1112 for (i = 0; i < tbl->nr_pools; i++) 1113 spin_unlock(&tbl->pools[i].lock); 1114 spin_unlock_irqrestore(&tbl->large_pool.lock, flags); 1115 1116 return ret; 1117 } 1118 EXPORT_SYMBOL_GPL(iommu_take_ownership); 1119 1120 void iommu_release_ownership(struct iommu_table *tbl) 1121 { 1122 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3; 1123 1124 spin_lock_irqsave(&tbl->large_pool.lock, flags); 1125 for (i = 0; i < tbl->nr_pools; i++) 1126 spin_lock(&tbl->pools[i].lock); 1127 1128 memset(tbl->it_map, 0, sz); 1129 1130 iommu_table_reserve_pages(tbl, tbl->it_reserved_start, 1131 tbl->it_reserved_end); 1132 1133 for (i = 0; i < tbl->nr_pools; i++) 1134 spin_unlock(&tbl->pools[i].lock); 1135 spin_unlock_irqrestore(&tbl->large_pool.lock, flags); 1136 } 1137 EXPORT_SYMBOL_GPL(iommu_release_ownership); 1138 1139 int iommu_add_device(struct iommu_table_group *table_group, struct device *dev) 1140 { 1141 /* 1142 * The sysfs entries should be populated before 1143 * binding IOMMU group. If sysfs entries isn't 1144 * ready, we simply bail. 1145 */ 1146 if (!device_is_registered(dev)) 1147 return -ENOENT; 1148 1149 if (device_iommu_mapped(dev)) { 1150 pr_debug("%s: Skipping device %s with iommu group %d\n", 1151 __func__, dev_name(dev), 1152 iommu_group_id(dev->iommu_group)); 1153 return -EBUSY; 1154 } 1155 1156 pr_debug("%s: Adding %s to iommu group %d\n", 1157 __func__, dev_name(dev), iommu_group_id(table_group->group)); 1158 1159 return iommu_group_add_device(table_group->group, dev); 1160 } 1161 EXPORT_SYMBOL_GPL(iommu_add_device); 1162 1163 void iommu_del_device(struct device *dev) 1164 { 1165 /* 1166 * Some devices might not have IOMMU table and group 1167 * and we needn't detach them from the associated 1168 * IOMMU groups 1169 */ 1170 if (!device_iommu_mapped(dev)) { 1171 pr_debug("iommu_tce: skipping device %s with no tbl\n", 1172 dev_name(dev)); 1173 return; 1174 } 1175 1176 iommu_group_remove_device(dev); 1177 } 1178 EXPORT_SYMBOL_GPL(iommu_del_device); 1179 #endif /* CONFIG_IOMMU_API */ 1180