1/* 2 * This file contains the power_save function for 6xx & 7xxx CPUs 3 * rewritten in assembler 4 * 5 * Warning ! This code assumes that if your machine has a 750fx 6 * it will have PLL 1 set to low speed mode (used during NAP/DOZE). 7 * if this is not the case some additional changes will have to 8 * be done to check a runtime var (a bit like powersave-nap) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 */ 15 16#include <linux/config.h> 17#include <linux/threads.h> 18#include <asm/reg.h> 19#include <asm/page.h> 20#include <asm/cputable.h> 21#include <asm/thread_info.h> 22#include <asm/ppc_asm.h> 23#include <asm/asm-offsets.h> 24 25#undef DEBUG 26 27 .text 28 29/* 30 * Init idle, called at early CPU setup time from head.S for each CPU 31 * Make sure no rest of NAP mode remains in HID0, save default 32 * values for some CPU specific registers. Called with r24 33 * containing CPU number and r3 reloc offset 34 */ 35_GLOBAL(init_idle_6xx) 36BEGIN_FTR_SECTION 37 mfspr r4,SPRN_HID0 38 rlwinm r4,r4,0,10,8 /* Clear NAP */ 39 mtspr SPRN_HID0, r4 40 b 1f 41END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 42 blr 431: 44 slwi r5,r24,2 45 add r5,r5,r3 46BEGIN_FTR_SECTION 47 mfspr r4,SPRN_MSSCR0 48 addis r6,r5, nap_save_msscr0@ha 49 stw r4,nap_save_msscr0@l(r6) 50END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) 51BEGIN_FTR_SECTION 52 mfspr r4,SPRN_HID1 53 addis r6,r5,nap_save_hid1@ha 54 stw r4,nap_save_hid1@l(r6) 55END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) 56 blr 57 58/* 59 * Here is the power_save_6xx function. This could eventually be 60 * split into several functions & changing the function pointer 61 * depending on the various features. 62 */ 63_GLOBAL(ppc6xx_idle) 64 /* Check if we can nap or doze, put HID0 mask in r3 65 */ 66 lis r3, 0 67BEGIN_FTR_SECTION 68 lis r3,HID0_DOZE@h 69END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) 70BEGIN_FTR_SECTION 71 /* We must dynamically check for the NAP feature as it 72 * can be cleared by CPU init after the fixups are done 73 */ 74 lis r4,cur_cpu_spec@ha 75 lwz r4,cur_cpu_spec@l(r4) 76 lwz r4,CPU_SPEC_FEATURES(r4) 77 andi. r0,r4,CPU_FTR_CAN_NAP 78 beq 1f 79 /* Now check if user or arch enabled NAP mode */ 80 lis r4,powersave_nap@ha 81 lwz r4,powersave_nap@l(r4) 82 cmpwi 0,r4,0 83 beq 1f 84 lis r3,HID0_NAP@h 851: 86END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 87 cmpwi 0,r3,0 88 beqlr 89 90 /* Clear MSR:EE */ 91 mfmsr r7 92 rlwinm r0,r7,0,17,15 93 mtmsr r0 94 95 /* Check current_thread_info()->flags */ 96 rlwinm r4,r1,0,0,18 97 lwz r4,TI_FLAGS(r4) 98 andi. r0,r4,_TIF_NEED_RESCHED 99 beq 1f 100 mtmsr r7 /* out of line this ? */ 101 blr 1021: 103 /* Some pre-nap cleanups needed on some CPUs */ 104 andis. r0,r3,HID0_NAP@h 105 beq 2f 106BEGIN_FTR_SECTION 107 /* Disable L2 prefetch on some 745x and try to ensure 108 * L2 prefetch engines are idle. As explained by errata 109 * text, we can't be sure they are, we just hope very hard 110 * that well be enough (sic !). At least I noticed Apple 111 * doesn't even bother doing the dcbf's here... 112 */ 113 mfspr r4,SPRN_MSSCR0 114 rlwinm r4,r4,0,0,29 115 sync 116 mtspr SPRN_MSSCR0,r4 117 sync 118 isync 119 lis r4,KERNELBASE@h 120 dcbf 0,r4 121 dcbf 0,r4 122 dcbf 0,r4 123 dcbf 0,r4 124END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) 125#ifdef DEBUG 126 lis r6,nap_enter_count@ha 127 lwz r4,nap_enter_count@l(r6) 128 addi r4,r4,1 129 stw r4,nap_enter_count@l(r6) 130#endif 1312: 132BEGIN_FTR_SECTION 133 /* Go to low speed mode on some 750FX */ 134 lis r4,powersave_lowspeed@ha 135 lwz r4,powersave_lowspeed@l(r4) 136 cmpwi 0,r4,0 137 beq 1f 138 mfspr r4,SPRN_HID1 139 oris r4,r4,0x0001 140 mtspr SPRN_HID1,r4 1411: 142END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) 143 144 /* Go to NAP or DOZE now */ 145 mfspr r4,SPRN_HID0 146 lis r5,(HID0_NAP|HID0_SLEEP)@h 147BEGIN_FTR_SECTION 148 oris r5,r5,HID0_DOZE@h 149END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) 150 andc r4,r4,r5 151 or r4,r4,r3 152BEGIN_FTR_SECTION 153 oris r4,r4,HID0_DPM@h /* that should be done once for all */ 154END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM) 155 mtspr SPRN_HID0,r4 156BEGIN_FTR_SECTION 157 DSSALL 158 sync 159END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 160 ori r7,r7,MSR_EE /* Could be ommited (already set) */ 161 oris r7,r7,MSR_POW@h 162 sync 163 isync 164 mtmsr r7 165 isync 166 sync 167 blr 168 169/* 170 * Return from NAP/DOZE mode, restore some CPU specific registers, 171 * we are called with DR/IR still off and r2 containing physical 172 * address of current. 173 */ 174_GLOBAL(power_save_6xx_restore) 175 mfspr r11,SPRN_HID0 176 rlwinm. r11,r11,0,10,8 /* Clear NAP & copy NAP bit !state to cr1 EQ */ 177 cror 4*cr1+eq,4*cr0+eq,4*cr0+eq 178BEGIN_FTR_SECTION 179 rlwinm r11,r11,0,9,7 /* Clear DOZE */ 180END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) 181 mtspr SPRN_HID0, r11 182 183#ifdef DEBUG 184 beq cr1,1f 185 lis r11,(nap_return_count-KERNELBASE)@ha 186 lwz r9,nap_return_count@l(r11) 187 addi r9,r9,1 188 stw r9,nap_return_count@l(r11) 1891: 190#endif 191 192 rlwinm r9,r1,0,0,18 193 tophys(r9,r9) 194 lwz r11,TI_CPU(r9) 195 slwi r11,r11,2 196 /* Todo make sure all these are in the same page 197 * and load r22 (@ha part + CPU offset) only once 198 */ 199BEGIN_FTR_SECTION 200 beq cr1,1f 201 addis r9,r11,(nap_save_msscr0-KERNELBASE)@ha 202 lwz r9,nap_save_msscr0@l(r9) 203 mtspr SPRN_MSSCR0, r9 204 sync 205 isync 2061: 207END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) 208BEGIN_FTR_SECTION 209 addis r9,r11,(nap_save_hid1-KERNELBASE)@ha 210 lwz r9,nap_save_hid1@l(r9) 211 mtspr SPRN_HID1, r9 212END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) 213 b transfer_to_handler_cont 214 215 .data 216 217_GLOBAL(nap_save_msscr0) 218 .space 4*NR_CPUS 219 220_GLOBAL(nap_save_hid1) 221 .space 4*NR_CPUS 222 223_GLOBAL(powersave_nap) 224 .long 0 225_GLOBAL(powersave_lowspeed) 226 .long 0 227 228#ifdef DEBUG 229_GLOBAL(nap_enter_count) 230 .space 4 231_GLOBAL(nap_return_count) 232 .space 4 233#endif 234