xref: /linux/arch/powerpc/kernel/head_booke.h (revision 0b8061c340b643e01da431dd60c75a41bb1d31ec)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __HEAD_BOOKE_H__
3 #define __HEAD_BOOKE_H__
4 
5 #include <asm/ptrace.h>	/* for STACK_FRAME_REGS_MARKER */
6 #include <asm/kvm_asm.h>
7 #include <asm/kvm_booke_hv_asm.h>
8 
9 #ifdef __ASSEMBLY__
10 
11 /*
12  * Macros used for common Book-e exception handling
13  */
14 
15 #define SET_IVOR(vector_number, vector_label)		\
16 		li	r26,vector_label@l; 		\
17 		mtspr	SPRN_IVOR##vector_number,r26;	\
18 		sync
19 
20 #if (THREAD_SHIFT < 15)
21 #define ALLOC_STACK_FRAME(reg, val)			\
22 	addi reg,reg,val
23 #else
24 #define ALLOC_STACK_FRAME(reg, val)			\
25 	addis	reg,reg,val@ha;				\
26 	addi	reg,reg,val@l
27 #endif
28 
29 /*
30  * Macro used to get to thread save registers.
31  * Note that entries 0-3 are used for the prolog code, and the remaining
32  * entries are available for specific exception use in the event a handler
33  * requires more than 4 scratch registers.
34  */
35 #define THREAD_NORMSAVE(offset)	(THREAD_NORMSAVES + (offset * 4))
36 
37 #ifdef CONFIG_PPC_FSL_BOOK3E
38 #define BOOKE_CLEAR_BTB(reg)									\
39 START_BTB_FLUSH_SECTION								\
40 	BTB_FLUSH(reg)									\
41 END_BTB_FLUSH_SECTION
42 #else
43 #define BOOKE_CLEAR_BTB(reg)
44 #endif
45 
46 
47 #define NORMAL_EXCEPTION_PROLOG(intno)						     \
48 	mtspr	SPRN_SPRG_WSCRATCH0, r10;	/* save one register */	     \
49 	mfspr	r10, SPRN_SPRG_THREAD;					     \
50 	stw	r11, THREAD_NORMSAVE(0)(r10);				     \
51 	stw	r13, THREAD_NORMSAVE(2)(r10);				     \
52 	mfcr	r13;			/* save CR in r13 for now	   */\
53 	mfspr	r11, SPRN_SRR1;		                                     \
54 	DO_KVM	BOOKE_INTERRUPT_##intno SPRN_SRR1;			     \
55 	andi.	r11, r11, MSR_PR;	/* check whether user or kernel    */\
56 	mr	r11, r1;						     \
57 	beq	1f;							     \
58 	BOOKE_CLEAR_BTB(r11)						\
59 	/* if from user, start at top of this thread's kernel stack */       \
60 	lwz	r11, TASK_STACK - THREAD(r10);				     \
61 	ALLOC_STACK_FRAME(r11, THREAD_SIZE);				     \
62 1 :	subi	r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */     \
63 	stw	r13, _CCR(r11);		/* save various registers */	     \
64 	stw	r12,GPR12(r11);						     \
65 	stw	r9,GPR9(r11);						     \
66 	mfspr	r13, SPRN_SPRG_RSCRATCH0;				     \
67 	stw	r13, GPR10(r11);					     \
68 	lwz	r12, THREAD_NORMSAVE(0)(r10);				     \
69 	stw	r12,GPR11(r11);						     \
70 	lwz	r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */		     \
71 	mflr	r10;							     \
72 	stw	r10,_LINK(r11);						     \
73 	mfspr	r12,SPRN_SRR0;						     \
74 	stw	r1, GPR1(r11);						     \
75 	mfspr	r9,SPRN_SRR1;						     \
76 	stw	r1, 0(r11);						     \
77 	mr	r1, r11;						     \
78 	rlwinm	r9,r9,0,14,12;		/* clear MSR_WE (necessary?)	   */\
79 	stw	r0,GPR0(r11);						     \
80 	lis	r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
81 	addi	r10, r10, STACK_FRAME_REGS_MARKER@l;			     \
82 	stw	r10, 8(r11);						     \
83 	SAVE_4GPRS(3, r11);						     \
84 	SAVE_2GPRS(7, r11)
85 
86 .macro SYSCALL_ENTRY trapno intno srr1
87 	mfspr	r10, SPRN_SPRG_THREAD
88 #ifdef CONFIG_KVM_BOOKE_HV
89 BEGIN_FTR_SECTION
90 	mtspr	SPRN_SPRG_WSCRATCH0, r10
91 	stw	r11, THREAD_NORMSAVE(0)(r10)
92 	stw	r13, THREAD_NORMSAVE(2)(r10)
93 	mfcr	r13			/* save CR in r13 for now	   */
94 	mfspr	r11, SPRN_SRR1
95 	mtocrf	0x80, r11	/* check MSR[GS] without clobbering reg */
96 	bf	3, 1975f
97 	b	kvmppc_handler_\intno\()_\srr1
98 1975:
99 	mr	r12, r13
100 	lwz	r13, THREAD_NORMSAVE(2)(r10)
101 FTR_SECTION_ELSE
102 #endif
103 	mfcr	r12
104 #ifdef CONFIG_KVM_BOOKE_HV
105 ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
106 #endif
107 	mfspr	r9, SPRN_SRR1
108 	BOOKE_CLEAR_BTB(r11)
109 	lwz	r11, TASK_STACK - THREAD(r10)
110 	rlwinm	r12,r12,0,4,2	/* Clear SO bit in CR */
111 	ALLOC_STACK_FRAME(r11, THREAD_SIZE - INT_FRAME_SIZE)
112 	stw	r12, _CCR(r11)		/* save various registers */
113 	mflr	r12
114 	stw	r12,_LINK(r11)
115 	mfspr	r12,SPRN_SRR0
116 	stw	r1, GPR1(r11)
117 	stw	r1, 0(r11)
118 	mr	r1, r11
119 	stw	r12,_NIP(r11)
120 	rlwinm	r9,r9,0,14,12		/* clear MSR_WE (necessary?)	   */
121 	lis	r12, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
122 	stw	r2,GPR2(r11)
123 	addi	r12, r12, STACK_FRAME_REGS_MARKER@l
124 	stw	r9,_MSR(r11)
125 	li	r2, \trapno
126 	stw	r12, 8(r11)
127 	stw	r2,_TRAP(r11)
128 	SAVE_GPR(0, r11)
129 	SAVE_4GPRS(3, r11)
130 	SAVE_2GPRS(7, r11)
131 
132 	addi	r2,r10,-THREAD
133 	b	transfer_to_syscall	/* jump to handler */
134 .endm
135 
136 /* To handle the additional exception priority levels on 40x and Book-E
137  * processors we allocate a stack per additional priority level.
138  *
139  * On 40x critical is the only additional level
140  * On 44x/e500 we have critical and machine check
141  *
142  * Additionally we reserve a SPRG for each priority level so we can free up a
143  * GPR to use as the base for indirect access to the exception stacks.  This
144  * is necessary since the MMU is always on, for Book-E parts, and the stacks
145  * are offset from KERNELBASE.
146  *
147  * There is some space optimization to be had here if desired.  However
148  * to allow for a common kernel with support for debug exceptions either
149  * going to critical or their own debug level we aren't currently
150  * providing configurations that micro-optimize space usage.
151  */
152 
153 #define MC_STACK_BASE		mcheckirq_ctx
154 #define CRIT_STACK_BASE		critirq_ctx
155 
156 /* only on e500mc */
157 #define DBG_STACK_BASE		dbgirq_ctx
158 
159 #define EXC_LVL_FRAME_OVERHEAD	(THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
160 
161 #ifdef CONFIG_SMP
162 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)		\
163 	mfspr	r8,SPRN_PIR;				\
164 	slwi	r8,r8,2;				\
165 	addis	r8,r8,level##_STACK_BASE@ha;		\
166 	lwz	r8,level##_STACK_BASE@l(r8);		\
167 	addi	r8,r8,EXC_LVL_FRAME_OVERHEAD;
168 #else
169 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)		\
170 	lis	r8,level##_STACK_BASE@ha;		\
171 	lwz	r8,level##_STACK_BASE@l(r8);		\
172 	addi	r8,r8,EXC_LVL_FRAME_OVERHEAD;
173 #endif
174 
175 /*
176  * Exception prolog for critical/machine check exceptions.  This is a
177  * little different from the normal exception prolog above since a
178  * critical/machine check exception can potentially occur at any point
179  * during normal exception processing. Thus we cannot use the same SPRG
180  * registers as the normal prolog above. Instead we use a portion of the
181  * critical/machine check exception stack at low physical addresses.
182  */
183 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
184 	mtspr	SPRN_SPRG_WSCRATCH_##exc_level,r8;			     \
185 	BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
186 	stw	r9,GPR9(r8);		/* save various registers	   */\
187 	mfcr	r9;			/* save CR in r9 for now	   */\
188 	stw	r10,GPR10(r8);						     \
189 	stw	r11,GPR11(r8);						     \
190 	stw	r9,_CCR(r8);		/* save CR on stack		   */\
191 	mfspr	r11,exc_level_srr1;	/* check whether user or kernel    */\
192 	DO_KVM	BOOKE_INTERRUPT_##intno exc_level_srr1;		             \
193 	BOOKE_CLEAR_BTB(r10)						\
194 	andi.	r11,r11,MSR_PR;						     \
195 	mfspr	r11,SPRN_SPRG_THREAD;	/* if from user, start at top of   */\
196 	lwz	r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
197 	addi	r11,r11,EXC_LVL_FRAME_OVERHEAD;	/* allocate stack frame    */\
198 	beq	1f;							     \
199 	/* COMING FROM USER MODE */					     \
200 	stw	r9,_CCR(r11);		/* save CR			   */\
201 	lwz	r10,GPR10(r8);		/* copy regs from exception stack  */\
202 	lwz	r9,GPR9(r8);						     \
203 	stw	r10,GPR10(r11);						     \
204 	lwz	r10,GPR11(r8);						     \
205 	stw	r9,GPR9(r11);						     \
206 	stw	r10,GPR11(r11);						     \
207 	b	2f;							     \
208 	/* COMING FROM PRIV MODE */					     \
209 1:	mr	r11, r8;							     \
210 2:	mfspr	r8,SPRN_SPRG_RSCRATCH_##exc_level;			     \
211 	stw	r12,GPR12(r11);		/* save various registers	   */\
212 	mflr	r10;							     \
213 	stw	r10,_LINK(r11);						     \
214 	mfspr	r12,SPRN_DEAR;		/* save DEAR and ESR in the frame  */\
215 	stw	r12,_DEAR(r11);		/* since they may have had stuff   */\
216 	mfspr	r9,SPRN_ESR;		/* in them at the point where the  */\
217 	stw	r9,_ESR(r11);		/* exception was taken		   */\
218 	mfspr	r12,exc_level_srr0;					     \
219 	stw	r1,GPR1(r11);						     \
220 	mfspr	r9,exc_level_srr1;					     \
221 	stw	r1,0(r11);						     \
222 	mr	r1,r11;							     \
223 	rlwinm	r9,r9,0,14,12;		/* clear MSR_WE (necessary?)	   */\
224 	stw	r0,GPR0(r11);						     \
225 	SAVE_4GPRS(3, r11);						     \
226 	SAVE_2GPRS(7, r11)
227 
228 #define CRITICAL_EXCEPTION_PROLOG(intno) \
229 		EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
230 #define DEBUG_EXCEPTION_PROLOG \
231 		EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
232 #define MCHECK_EXCEPTION_PROLOG \
233 		EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
234 			SPRN_MCSRR0, SPRN_MCSRR1)
235 
236 /*
237  * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
238  * being delivered to the host.  This exception can only happen
239  * inside a KVM guest -- so we just handle up to the DO_KVM rather
240  * than try to fit this into one of the existing prolog macros.
241  */
242 #define GUEST_DOORBELL_EXCEPTION \
243 	START_EXCEPTION(GuestDoorbell);					     \
244 	mtspr	SPRN_SPRG_WSCRATCH0, r10;	/* save one register */	     \
245 	mfspr	r10, SPRN_SPRG_THREAD;					     \
246 	stw	r11, THREAD_NORMSAVE(0)(r10);				     \
247 	mfspr	r11, SPRN_SRR1;		                                     \
248 	stw	r13, THREAD_NORMSAVE(2)(r10);				     \
249 	mfcr	r13;			/* save CR in r13 for now	   */\
250 	DO_KVM	BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1;			     \
251 	trap
252 
253 /*
254  * Exception vectors.
255  */
256 #define	START_EXCEPTION(label)						     \
257         .align 5;              						     \
258 label:
259 
260 #define EXCEPTION(n, intno, label, hdlr, xfer)			\
261 	START_EXCEPTION(label);					\
262 	NORMAL_EXCEPTION_PROLOG(intno);				\
263 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
264 	xfer(n, hdlr)
265 
266 #define CRITICAL_EXCEPTION(n, intno, label, hdlr)			\
267 	START_EXCEPTION(label);						\
268 	CRITICAL_EXCEPTION_PROLOG(intno);				\
269 	addi	r3,r1,STACK_FRAME_OVERHEAD;				\
270 	EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
271 			  crit_transfer_to_handler, ret_from_crit_exc)
272 
273 #define MCHECK_EXCEPTION(n, label, hdlr)			\
274 	START_EXCEPTION(label);					\
275 	MCHECK_EXCEPTION_PROLOG;				\
276 	mfspr	r5,SPRN_ESR;					\
277 	stw	r5,_ESR(r11);					\
278 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
279 	EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
280 			  mcheck_transfer_to_handler, ret_from_mcheck_exc)
281 
282 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret)	\
283 	li	r10,trap;					\
284 	stw	r10,_TRAP(r11);					\
285 	lis	r10,msr@h;					\
286 	ori	r10,r10,msr@l;					\
287 	bl	tfer;		 				\
288 	.long	hdlr;						\
289 	.long	ret
290 
291 #define EXC_XFER_STD(n, hdlr)		\
292 	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, transfer_to_handler_full, \
293 			  ret_from_except_full)
294 
295 #define EXC_XFER_LITE(n, hdlr)		\
296 	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, transfer_to_handler, \
297 			  ret_from_except)
298 
299 /* Check for a single step debug exception while in an exception
300  * handler before state has been saved.  This is to catch the case
301  * where an instruction that we are trying to single step causes
302  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
303  * the exception handler generates a single step debug exception.
304  *
305  * If we get a debug trap on the first instruction of an exception handler,
306  * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
307  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
308  * The exception handler was handling a non-critical interrupt, so it will
309  * save (and later restore) the MSR via SPRN_CSRR1, which will still have
310  * the MSR_DE bit set.
311  */
312 #define DEBUG_DEBUG_EXCEPTION						      \
313 	START_EXCEPTION(DebugDebug);					      \
314 	DEBUG_EXCEPTION_PROLOG;						      \
315 									      \
316 	/*								      \
317 	 * If there is a single step or branch-taken exception in an	      \
318 	 * exception entry sequence, it was probably meant to apply to	      \
319 	 * the code where the exception occurred (since exception entry	      \
320 	 * doesn't turn off DE automatically).  We simulate the effect	      \
321 	 * of turning off DE on entry to an exception handler by turning      \
322 	 * off DE in the DSRR1 value and clearing the debug status.	      \
323 	 */								      \
324 	mfspr	r10,SPRN_DBSR;		/* check single-step/branch taken */  \
325 	andis.	r10,r10,(DBSR_IC|DBSR_BT)@h;				      \
326 	beq+	2f;							      \
327 									      \
328 	lis	r10,interrupt_base@h;	/* check if exception in vectors */   \
329 	ori	r10,r10,interrupt_base@l;				      \
330 	cmplw	r12,r10;						      \
331 	blt+	2f;			/* addr below exception vectors */    \
332 									      \
333 	lis	r10,interrupt_end@h;					      \
334 	ori	r10,r10,interrupt_end@l;				      \
335 	cmplw	r12,r10;						      \
336 	bgt+	2f;			/* addr above exception vectors */    \
337 									      \
338 	/* here it looks like we got an inappropriate debug exception. */     \
339 1:	rlwinm	r9,r9,0,~MSR_DE;	/* clear DE in the CDRR1 value */     \
340 	lis	r10,(DBSR_IC|DBSR_BT)@h;	/* clear the IC event */      \
341 	mtspr	SPRN_DBSR,r10;						      \
342 	/* restore state and get out */					      \
343 	lwz	r10,_CCR(r11);						      \
344 	lwz	r0,GPR0(r11);						      \
345 	lwz	r1,GPR1(r11);						      \
346 	mtcrf	0x80,r10;						      \
347 	mtspr	SPRN_DSRR0,r12;						      \
348 	mtspr	SPRN_DSRR1,r9;						      \
349 	lwz	r9,GPR9(r11);						      \
350 	lwz	r12,GPR12(r11);						      \
351 	mtspr	SPRN_SPRG_WSCRATCH_DBG,r8;				      \
352 	BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
353 	lwz	r10,GPR10(r8);						      \
354 	lwz	r11,GPR11(r8);						      \
355 	mfspr	r8,SPRN_SPRG_RSCRATCH_DBG;				      \
356 									      \
357 	PPC_RFDI;							      \
358 	b	.;							      \
359 									      \
360 	/* continue normal handling for a debug exception... */		      \
361 2:	mfspr	r4,SPRN_DBSR;						      \
362 	stw	r4,_ESR(r11);		/* DebugException takes DBSR in _ESR */\
363 	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
364 	EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), debug_transfer_to_handler, ret_from_debug_exc)
365 
366 #define DEBUG_CRIT_EXCEPTION						      \
367 	START_EXCEPTION(DebugCrit);					      \
368 	CRITICAL_EXCEPTION_PROLOG(DEBUG);				      \
369 									      \
370 	/*								      \
371 	 * If there is a single step or branch-taken exception in an	      \
372 	 * exception entry sequence, it was probably meant to apply to	      \
373 	 * the code where the exception occurred (since exception entry	      \
374 	 * doesn't turn off DE automatically).  We simulate the effect	      \
375 	 * of turning off DE on entry to an exception handler by turning      \
376 	 * off DE in the CSRR1 value and clearing the debug status.	      \
377 	 */								      \
378 	mfspr	r10,SPRN_DBSR;		/* check single-step/branch taken */  \
379 	andis.	r10,r10,(DBSR_IC|DBSR_BT)@h;				      \
380 	beq+	2f;							      \
381 									      \
382 	lis	r10,interrupt_base@h;	/* check if exception in vectors */   \
383 	ori	r10,r10,interrupt_base@l;				      \
384 	cmplw	r12,r10;						      \
385 	blt+	2f;			/* addr below exception vectors */    \
386 									      \
387 	lis	r10,interrupt_end@h;					      \
388 	ori	r10,r10,interrupt_end@l;				      \
389 	cmplw	r12,r10;						      \
390 	bgt+	2f;			/* addr above exception vectors */    \
391 									      \
392 	/* here it looks like we got an inappropriate debug exception. */     \
393 1:	rlwinm	r9,r9,0,~MSR_DE;	/* clear DE in the CSRR1 value */     \
394 	lis	r10,(DBSR_IC|DBSR_BT)@h;	/* clear the IC event */      \
395 	mtspr	SPRN_DBSR,r10;						      \
396 	/* restore state and get out */					      \
397 	lwz	r10,_CCR(r11);						      \
398 	lwz	r0,GPR0(r11);						      \
399 	lwz	r1,GPR1(r11);						      \
400 	mtcrf	0x80,r10;						      \
401 	mtspr	SPRN_CSRR0,r12;						      \
402 	mtspr	SPRN_CSRR1,r9;						      \
403 	lwz	r9,GPR9(r11);						      \
404 	lwz	r12,GPR12(r11);						      \
405 	mtspr	SPRN_SPRG_WSCRATCH_CRIT,r8;				      \
406 	BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
407 	lwz	r10,GPR10(r8);						      \
408 	lwz	r11,GPR11(r8);						      \
409 	mfspr	r8,SPRN_SPRG_RSCRATCH_CRIT;				      \
410 									      \
411 	rfci;								      \
412 	b	.;							      \
413 									      \
414 	/* continue normal handling for a critical exception... */	      \
415 2:	mfspr	r4,SPRN_DBSR;						      \
416 	stw	r4,_ESR(r11);		/* DebugException takes DBSR in _ESR */\
417 	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
418 	EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), crit_transfer_to_handler, ret_from_crit_exc)
419 
420 #define DATA_STORAGE_EXCEPTION						      \
421 	START_EXCEPTION(DataStorage)					      \
422 	NORMAL_EXCEPTION_PROLOG(DATA_STORAGE);		      \
423 	mfspr	r5,SPRN_ESR;		/* Grab the ESR and save it */	      \
424 	stw	r5,_ESR(r11);						      \
425 	mfspr	r4,SPRN_DEAR;		/* Grab the DEAR */		      \
426 	stw	r4, _DEAR(r11);						      \
427 	EXC_XFER_LITE(0x0300, handle_page_fault)
428 
429 #define INSTRUCTION_STORAGE_EXCEPTION					      \
430 	START_EXCEPTION(InstructionStorage)				      \
431 	NORMAL_EXCEPTION_PROLOG(INST_STORAGE);		      \
432 	mfspr	r5,SPRN_ESR;		/* Grab the ESR and save it */	      \
433 	stw	r5,_ESR(r11);						      \
434 	stw	r12, _DEAR(r11);	/* Pass SRR0 as arg2 */		      \
435 	EXC_XFER_LITE(0x0400, handle_page_fault)
436 
437 #define ALIGNMENT_EXCEPTION						      \
438 	START_EXCEPTION(Alignment)					      \
439 	NORMAL_EXCEPTION_PROLOG(ALIGNMENT);		      \
440 	mfspr   r4,SPRN_DEAR;           /* Grab the DEAR and save it */	      \
441 	stw     r4,_DEAR(r11);						      \
442 	addi    r3,r1,STACK_FRAME_OVERHEAD;				      \
443 	EXC_XFER_STD(0x0600, alignment_exception)
444 
445 #define PROGRAM_EXCEPTION						      \
446 	START_EXCEPTION(Program)					      \
447 	NORMAL_EXCEPTION_PROLOG(PROGRAM);		      \
448 	mfspr	r4,SPRN_ESR;		/* Grab the ESR and save it */	      \
449 	stw	r4,_ESR(r11);						      \
450 	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
451 	EXC_XFER_STD(0x0700, program_check_exception)
452 
453 #define DECREMENTER_EXCEPTION						      \
454 	START_EXCEPTION(Decrementer)					      \
455 	NORMAL_EXCEPTION_PROLOG(DECREMENTER);		      \
456 	lis     r0,TSR_DIS@h;           /* Setup the DEC interrupt mask */    \
457 	mtspr   SPRN_TSR,r0;		/* Clear the DEC interrupt */	      \
458 	addi    r3,r1,STACK_FRAME_OVERHEAD;				      \
459 	EXC_XFER_LITE(0x0900, timer_interrupt)
460 
461 #define FP_UNAVAILABLE_EXCEPTION					      \
462 	START_EXCEPTION(FloatingPointUnavailable)			      \
463 	NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL);		      \
464 	beq	1f;							      \
465 	bl	load_up_fpu;		/* if from user, just load it up */   \
466 	b	fast_exception_return;					      \
467 1:	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
468 	EXC_XFER_STD(0x800, kernel_fp_unavailable_exception)
469 
470 #else /* __ASSEMBLY__ */
471 struct exception_regs {
472 	unsigned long mas0;
473 	unsigned long mas1;
474 	unsigned long mas2;
475 	unsigned long mas3;
476 	unsigned long mas6;
477 	unsigned long mas7;
478 	unsigned long srr0;
479 	unsigned long srr1;
480 	unsigned long csrr0;
481 	unsigned long csrr1;
482 	unsigned long dsrr0;
483 	unsigned long dsrr1;
484 	unsigned long saved_ksp_limit;
485 };
486 
487 /* ensure this structure is always sized to a multiple of the stack alignment */
488 #define STACK_EXC_LVL_FRAME_SIZE	ALIGN(sizeof (struct exception_regs), 16)
489 
490 #endif /* __ASSEMBLY__ */
491 #endif /* __HEAD_BOOKE_H__ */
492