1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Low-level exception handlers and MMU support 8 * rewritten by Paul Mackerras. 9 * Copyright (C) 1996 Paul Mackerras. 10 * MPC8xx modifications by Dan Malek 11 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 12 * 13 * This file contains low-level support and setup for PowerPC 8xx 14 * embedded processors, including trap and interrupt dispatch. 15 */ 16 17#include <linux/init.h> 18#include <linux/magic.h> 19#include <linux/pgtable.h> 20#include <linux/sizes.h> 21#include <asm/processor.h> 22#include <asm/page.h> 23#include <asm/mmu.h> 24#include <asm/cache.h> 25#include <asm/cputable.h> 26#include <asm/thread_info.h> 27#include <asm/ppc_asm.h> 28#include <asm/asm-offsets.h> 29#include <asm/ptrace.h> 30#include <asm/export.h> 31#include <asm/code-patching-asm.h> 32 33#include "head_32.h" 34 35.macro compare_to_kernel_boundary scratch, addr 36#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 37/* By simply checking Address >= 0x80000000, we know if its a kernel address */ 38 not. \scratch, \addr 39#else 40 rlwinm \scratch, \addr, 16, 0xfff8 41 cmpli cr0, \scratch, PAGE_OFFSET@h 42#endif 43.endm 44 45/* 46 * Value for the bits that have fixed value in RPN entries. 47 * Also used for tagging DAR for DTLBerror. 48 */ 49#define RPN_PATTERN 0x00f0 50 51#define PAGE_SHIFT_512K 19 52#define PAGE_SHIFT_8M 23 53 54 __HEAD 55_ENTRY(_stext); 56_ENTRY(_start); 57 58/* MPC8xx 59 * This port was done on an MBX board with an 860. Right now I only 60 * support an ELF compressed (zImage) boot from EPPC-Bug because the 61 * code there loads up some registers before calling us: 62 * r3: ptr to board info data 63 * r4: initrd_start or if no initrd then 0 64 * r5: initrd_end - unused if r4 is 0 65 * r6: Start of command line string 66 * r7: End of command line string 67 * 68 * I decided to use conditional compilation instead of checking PVR and 69 * adding more processor specific branches around code I don't need. 70 * Since this is an embedded processor, I also appreciate any memory 71 * savings I can get. 72 * 73 * The MPC8xx does not have any BATs, but it supports large page sizes. 74 * We first initialize the MMU to support 8M byte pages, then load one 75 * entry into each of the instruction and data TLBs to map the first 76 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 77 * the "internal" processor registers before MMU_init is called. 78 * 79 * -- Dan 80 */ 81 .globl __start 82__start: 83 mr r31,r3 /* save device tree ptr */ 84 85 /* We have to turn on the MMU right away so we get cache modes 86 * set correctly. 87 */ 88 bl initial_mmu 89 90/* We now have the lower 8 Meg mapped into TLB entries, and the caches 91 * ready to work. 92 */ 93 94turn_on_mmu: 95 mfmsr r0 96 ori r0,r0,MSR_DR|MSR_IR 97 mtspr SPRN_SRR1,r0 98 lis r0,start_here@h 99 ori r0,r0,start_here@l 100 mtspr SPRN_SRR0,r0 101 rfi /* enables MMU */ 102 103 104#ifdef CONFIG_PERF_EVENTS 105 .align 4 106 107 .globl itlb_miss_counter 108itlb_miss_counter: 109 .space 4 110 111 .globl dtlb_miss_counter 112dtlb_miss_counter: 113 .space 4 114 115 .globl instruction_counter 116instruction_counter: 117 .space 4 118#endif 119 120/* System reset */ 121 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD) 122 123/* Machine check */ 124 . = 0x200 125MachineCheck: 126 EXCEPTION_PROLOG handle_dar_dsisr=1 127 save_dar_dsisr_on_stack r4, r5, r11 128 li r6, RPN_PATTERN 129 mtspr SPRN_DAR, r6 /* Tag DAR, to be used in DTLB Error */ 130 addi r3,r1,STACK_FRAME_OVERHEAD 131 EXC_XFER_STD(0x200, machine_check_exception) 132 133/* External interrupt */ 134 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 135 136/* Alignment exception */ 137 . = 0x600 138Alignment: 139 EXCEPTION_PROLOG handle_dar_dsisr=1 140 save_dar_dsisr_on_stack r4, r5, r11 141 li r6, RPN_PATTERN 142 mtspr SPRN_DAR, r6 /* Tag DAR, to be used in DTLB Error */ 143 addi r3,r1,STACK_FRAME_OVERHEAD 144 b .Lalignment_exception_ool 145 146/* Program check exception */ 147 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 148 149/* Decrementer */ 150 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 151 152 /* With VMAP_STACK there's not enough room for this at 0x600 */ 153 . = 0xa00 154.Lalignment_exception_ool: 155 EXC_XFER_STD(0x600, alignment_exception) 156 157/* System call */ 158 . = 0xc00 159SystemCall: 160 SYSCALL_ENTRY 0xc00 161 162/* Single step - not used on 601 */ 163 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 164 165/* On the MPC8xx, this is a software emulation interrupt. It occurs 166 * for all unimplemented and illegal instructions. 167 */ 168 EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD) 169 170 . = 0x1100 171/* 172 * For the MPC8xx, this is a software tablewalk to load the instruction 173 * TLB. The task switch loads the M_TWB register with the pointer to the first 174 * level table. 175 * If we discover there is no second level table (value is zero) or if there 176 * is an invalid pte, we load that into the TLB, which causes another fault 177 * into the TLB Error interrupt where we can handle such problems. 178 * We have to use the MD_xxx registers for the tablewalk because the 179 * equivalent MI_xxx registers only perform the attribute functions. 180 */ 181 182#ifdef CONFIG_8xx_CPU15 183#define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp) \ 184 addi tmp, addr, PAGE_SIZE; \ 185 tlbie tmp; \ 186 addi tmp, addr, -PAGE_SIZE; \ 187 tlbie tmp 188#else 189#define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp) 190#endif 191 192InstructionTLBMiss: 193 mtspr SPRN_SPRG_SCRATCH2, r10 194 mtspr SPRN_M_TW, r11 195 196 /* If we are faulting a kernel address, we have to use the 197 * kernel page tables. 198 */ 199 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 200 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11) 201 mtspr SPRN_MD_EPN, r10 202#ifdef CONFIG_MODULES 203 mfcr r11 204 compare_to_kernel_boundary r10, r10 205#endif 206 mfspr r10, SPRN_M_TWB /* Get level 1 table */ 207#ifdef CONFIG_MODULES 208 blt+ 3f 209 rlwinm r10, r10, 0, 20, 31 210 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha 2113: 212 mtcr r11 213#endif 214 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */ 215 mtspr SPRN_MD_TWC, r11 216 mfspr r10, SPRN_MD_TWC 217 lwz r10, 0(r10) /* Get the pte */ 218 rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED 219 rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K 220 mtspr SPRN_MI_TWC, r11 221 /* The Linux PTE won't go exactly into the MMU TLB. 222 * Software indicator bits 20 and 23 must be clear. 223 * Software indicator bits 22, 24, 25, 26, and 27 must be 224 * set. All other Linux PTE bits control the behavior 225 * of the MMU. 226 */ 227 rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */ 228 rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */ 229 ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */ 230 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 231 232 /* Restore registers */ 2330: mfspr r10, SPRN_SPRG_SCRATCH2 234 mfspr r11, SPRN_M_TW 235 rfi 236 patch_site 0b, patch__itlbmiss_exit_1 237 238#ifdef CONFIG_PERF_EVENTS 239 patch_site 0f, patch__itlbmiss_perf 2400: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) 241 addi r10, r10, 1 242 stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) 243 mfspr r10, SPRN_SPRG_SCRATCH2 244 mfspr r11, SPRN_M_TW 245 rfi 246#endif 247 248 . = 0x1200 249DataStoreTLBMiss: 250 mtspr SPRN_SPRG_SCRATCH2, r10 251 mtspr SPRN_M_TW, r11 252 mfcr r11 253 254 /* If we are faulting a kernel address, we have to use the 255 * kernel page tables. 256 */ 257 mfspr r10, SPRN_MD_EPN 258 compare_to_kernel_boundary r10, r10 259 mfspr r10, SPRN_M_TWB /* Get level 1 table */ 260 blt+ 3f 261 rlwinm r10, r10, 0, 20, 31 262 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha 2633: 264 mtcr r11 265 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */ 266 267 mtspr SPRN_MD_TWC, r11 268 mfspr r10, SPRN_MD_TWC 269 lwz r10, 0(r10) /* Get the pte */ 270 271 /* Insert Guarded and Accessed flags into the TWC from the Linux PTE. 272 * It is bit 27 of both the Linux PTE and the TWC (at least 273 * I got that right :-). It will be better when we can put 274 * this into the Linux pgd/pmd and load it in the operation 275 * above. 276 */ 277 rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED 278 rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K 279 mtspr SPRN_MD_TWC, r11 280 281 /* The Linux PTE won't go exactly into the MMU TLB. 282 * Software indicator bits 24, 25, 26, and 27 must be 283 * set. All other Linux PTE bits control the behavior 284 * of the MMU. 285 */ 286 li r11, RPN_PATTERN 287 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */ 288 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 289 mtspr SPRN_DAR, r11 /* Tag DAR */ 290 291 /* Restore registers */ 292 2930: mfspr r10, SPRN_SPRG_SCRATCH2 294 mfspr r11, SPRN_M_TW 295 rfi 296 patch_site 0b, patch__dtlbmiss_exit_1 297 298#ifdef CONFIG_PERF_EVENTS 299 patch_site 0f, patch__dtlbmiss_perf 3000: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) 301 addi r10, r10, 1 302 stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) 303 mfspr r10, SPRN_SPRG_SCRATCH2 304 mfspr r11, SPRN_M_TW 305 rfi 306#endif 307 308/* This is an instruction TLB error on the MPC8xx. This could be due 309 * to many reasons, such as executing guarded memory or illegal instruction 310 * addresses. There is nothing to do but handle a big time error fault. 311 */ 312 . = 0x1300 313InstructionTLBError: 314 EXCEPTION_PROLOG 315 mr r4,r12 316 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ 317 andis. r10,r9,SRR1_ISI_NOPT@h 318 beq+ .Litlbie 319 tlbie r4 320 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 321.Litlbie: 322 stw r4, _DAR(r11) 323 EXC_XFER_LITE(0x400, handle_page_fault) 324 325/* This is the data TLB error on the MPC8xx. This could be due to 326 * many reasons, including a dirty update to a pte. We bail out to 327 * a higher level function that can handle it. 328 */ 329 . = 0x1400 330DataTLBError: 331 EXCEPTION_PROLOG_0 handle_dar_dsisr=1 332 mfspr r11, SPRN_DAR 333 cmpwi cr1, r11, RPN_PATTERN 334 beq- cr1, FixupDAR /* must be a buggy dcbX, icbi insn. */ 335DARFixed:/* Return from dcbx instruction bug workaround */ 336#ifdef CONFIG_VMAP_STACK 337 li r11, RPN_PATTERN 338 mtspr SPRN_DAR, r11 /* Tag DAR, to be used in DTLB Error */ 339#endif 340 EXCEPTION_PROLOG_1 341 EXCEPTION_PROLOG_2 handle_dar_dsisr=1 342 get_and_save_dar_dsisr_on_stack r4, r5, r11 343 andis. r10,r5,DSISR_NOHPTE@h 344 beq+ .Ldtlbie 345 tlbie r4 346.Ldtlbie: 347#ifndef CONFIG_VMAP_STACK 348 li r10,RPN_PATTERN 349 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 350#endif 351 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 352 EXC_XFER_LITE(0x300, handle_page_fault) 353 354stack_overflow: 355 vmap_stack_overflow_exception 356 357/* On the MPC8xx, these next four traps are used for development 358 * support of breakpoints and such. Someday I will get around to 359 * using them. 360 */ 361do_databreakpoint: 362 EXCEPTION_PROLOG_1 363 EXCEPTION_PROLOG_2 handle_dar_dsisr=1 364 addi r3,r1,STACK_FRAME_OVERHEAD 365 mfspr r4,SPRN_BAR 366 stw r4,_DAR(r11) 367#ifdef CONFIG_VMAP_STACK 368 lwz r5,_DSISR(r11) 369#else 370 mfspr r5,SPRN_DSISR 371#endif 372 EXC_XFER_STD(0x1c00, do_break) 373 374 . = 0x1c00 375DataBreakpoint: 376 EXCEPTION_PROLOG_0 handle_dar_dsisr=1 377 mfspr r11, SPRN_SRR0 378 cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l 379 cmplwi cr7, r11, (.Litlbie - PAGE_OFFSET)@l 380 cror 4*cr1+eq, 4*cr1+eq, 4*cr7+eq 381 bne cr1, do_databreakpoint 382 mtcr r10 383 mfspr r10, SPRN_SPRG_SCRATCH0 384 mfspr r11, SPRN_SPRG_SCRATCH1 385 rfi 386 387#ifdef CONFIG_PERF_EVENTS 388 . = 0x1d00 389InstructionBreakpoint: 390 mtspr SPRN_SPRG_SCRATCH0, r10 391 lwz r10, (instruction_counter - PAGE_OFFSET)@l(0) 392 addi r10, r10, -1 393 stw r10, (instruction_counter - PAGE_OFFSET)@l(0) 394 lis r10, 0xffff 395 ori r10, r10, 0x01 396 mtspr SPRN_COUNTA, r10 397 mfspr r10, SPRN_SPRG_SCRATCH0 398 rfi 399#else 400 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD) 401#endif 402 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD) 403 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD) 404 405 . = 0x2000 406 407/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 408 * by decoding the registers used by the dcbx instruction and adding them. 409 * DAR is set to the calculated address. 410 */ 411FixupDAR:/* Entry point for dcbx workaround. */ 412 mtspr SPRN_M_TW, r10 413 /* fetch instruction from memory. */ 414 mfspr r10, SPRN_SRR0 415 mtspr SPRN_MD_EPN, r10 416 rlwinm r11, r10, 16, 0xfff8 417 cmpli cr1, r11, PAGE_OFFSET@h 418 mfspr r11, SPRN_M_TWB /* Get level 1 table */ 419 blt+ cr1, 3f 420 421 /* create physical page address from effective address */ 422 tophys(r11, r10) 423 mfspr r11, SPRN_M_TWB /* Get level 1 table */ 424 rlwinm r11, r11, 0, 20, 31 425 oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha 4263: 427 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 428 mtspr SPRN_MD_TWC, r11 429 mtcrf 0x01, r11 430 mfspr r11, SPRN_MD_TWC 431 lwz r11, 0(r11) /* Get the pte */ 432 bt 28,200f /* bit 28 = Large page (8M) */ 433 /* concat physical page address(r11) and page offset(r10) */ 434 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 435201: lwz r11,0(r11) 436/* Check if it really is a dcbx instruction. */ 437/* dcbt and dcbtst does not generate DTLB Misses/Errors, 438 * no need to include them here */ 439 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 440 rlwinm r10, r10, 0, 21, 5 441 cmpwi cr1, r10, 2028 /* Is dcbz? */ 442 beq+ cr1, 142f 443 cmpwi cr1, r10, 940 /* Is dcbi? */ 444 beq+ cr1, 142f 445 cmpwi cr1, r10, 108 /* Is dcbst? */ 446 beq+ cr1, 144f /* Fix up store bit! */ 447 cmpwi cr1, r10, 172 /* Is dcbf? */ 448 beq+ cr1, 142f 449 cmpwi cr1, r10, 1964 /* Is icbi? */ 450 beq+ cr1, 142f 451141: mfspr r10,SPRN_M_TW 452 b DARFixed /* Nope, go back to normal TLB processing */ 453 454200: 455 /* concat physical page address(r11) and page offset(r10) */ 456 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31 457 b 201b 458 459144: mfspr r10, SPRN_DSISR 460 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 461 mtspr SPRN_DSISR, r10 462142: /* continue, it was a dcbx, dcbi instruction. */ 463 mfctr r10 464 mtdar r10 /* save ctr reg in DAR */ 465 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 466 addi r10, r10, 150f@l /* add start of table */ 467 mtctr r10 /* load ctr with jump address */ 468 xor r10, r10, r10 /* sum starts at zero */ 469 bctr /* jump into table */ 470150: 471 add r10, r10, r0 ;b 151f 472 add r10, r10, r1 ;b 151f 473 add r10, r10, r2 ;b 151f 474 add r10, r10, r3 ;b 151f 475 add r10, r10, r4 ;b 151f 476 add r10, r10, r5 ;b 151f 477 add r10, r10, r6 ;b 151f 478 add r10, r10, r7 ;b 151f 479 add r10, r10, r8 ;b 151f 480 add r10, r10, r9 ;b 151f 481 mtctr r11 ;b 154f /* r10 needs special handling */ 482 mtctr r11 ;b 153f /* r11 needs special handling */ 483 add r10, r10, r12 ;b 151f 484 add r10, r10, r13 ;b 151f 485 add r10, r10, r14 ;b 151f 486 add r10, r10, r15 ;b 151f 487 add r10, r10, r16 ;b 151f 488 add r10, r10, r17 ;b 151f 489 add r10, r10, r18 ;b 151f 490 add r10, r10, r19 ;b 151f 491 add r10, r10, r20 ;b 151f 492 add r10, r10, r21 ;b 151f 493 add r10, r10, r22 ;b 151f 494 add r10, r10, r23 ;b 151f 495 add r10, r10, r24 ;b 151f 496 add r10, r10, r25 ;b 151f 497 add r10, r10, r26 ;b 151f 498 add r10, r10, r27 ;b 151f 499 add r10, r10, r28 ;b 151f 500 add r10, r10, r29 ;b 151f 501 add r10, r10, r30 ;b 151f 502 add r10, r10, r31 503151: 504 rlwinm r11,r11,19,24,28 /* offset into jump table for reg RA */ 505 cmpwi cr1, r11, 0 506 beq cr1, 152f /* if reg RA is zero, don't add it */ 507 addi r11, r11, 150b@l /* add start of table */ 508 mtctr r11 /* load ctr with jump address */ 509 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 510 bctr /* jump into table */ 511152: 512 mfdar r11 513 mtctr r11 /* restore ctr reg from DAR */ 514#ifdef CONFIG_VMAP_STACK 515 mfspr r11, SPRN_SPRG_THREAD 516 stw r10, DAR(r11) 517 mfspr r10, SPRN_DSISR 518 stw r10, DSISR(r11) 519#else 520 mtdar r10 /* save fault EA to DAR */ 521#endif 522 mfspr r10,SPRN_M_TW 523 b DARFixed /* Go back to normal TLB handling */ 524 525 /* special handling for r10,r11 since these are modified already */ 526153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 527 add r10, r10, r11 /* add it */ 528 mfctr r11 /* restore r11 */ 529 b 151b 530154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 531 add r10, r10, r11 /* add it */ 532 mfctr r11 /* restore r11 */ 533 b 151b 534 535/* 536 * This is where the main kernel code starts. 537 */ 538start_here: 539 /* ptr to current */ 540 lis r2,init_task@h 541 ori r2,r2,init_task@l 542 543 /* ptr to phys current thread */ 544 tophys(r4,r2) 545 addi r4,r4,THREAD /* init task's THREAD */ 546 mtspr SPRN_SPRG_THREAD,r4 547 548 /* stack */ 549 lis r1,init_thread_union@ha 550 addi r1,r1,init_thread_union@l 551 lis r0, STACK_END_MAGIC@h 552 ori r0, r0, STACK_END_MAGIC@l 553 stw r0, 0(r1) 554 li r0,0 555 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 556 557 lis r6, swapper_pg_dir@ha 558 tophys(r6,r6) 559 mtspr SPRN_M_TWB, r6 560 561 bl early_init /* We have to do this with MMU on */ 562 563/* 564 * Decide what sort of machine this is and initialize the MMU. 565 */ 566#ifdef CONFIG_KASAN 567 bl kasan_early_init 568#endif 569 li r3,0 570 mr r4,r31 571 bl machine_init 572 bl MMU_init 573 574/* 575 * Go back to running unmapped so we can load up new values 576 * and change to using our exception vectors. 577 * On the 8xx, all we have to do is invalidate the TLB to clear 578 * the old 8M byte TLB mappings and load the page table base register. 579 */ 580 /* The right way to do this would be to track it down through 581 * init's THREAD like the context switch code does, but this is 582 * easier......until someone changes init's static structures. 583 */ 584 lis r4,2f@h 585 ori r4,r4,2f@l 586 tophys(r4,r4) 587 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 588 mtspr SPRN_SRR0,r4 589 mtspr SPRN_SRR1,r3 590 rfi 591/* Load up the kernel context */ 5922: 593#ifdef CONFIG_PIN_TLB_IMMR 594 lis r0, MD_TWAM@h 595 oris r0, r0, 0x1f00 596 mtspr SPRN_MD_CTR, r0 597 LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID) 598 tlbie r0 599 mtspr SPRN_MD_EPN, r0 600 LOAD_REG_IMMEDIATE(r0, MD_SVALID | MD_PS512K | MD_GUARDED) 601 mtspr SPRN_MD_TWC, r0 602 mfspr r0, SPRN_IMMR 603 rlwinm r0, r0, 0, 0xfff80000 604 ori r0, r0, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \ 605 _PAGE_NO_CACHE | _PAGE_PRESENT 606 mtspr SPRN_MD_RPN, r0 607 lis r0, (MD_TWAM | MD_RSV4I)@h 608 mtspr SPRN_MD_CTR, r0 609#endif 610#if !defined(CONFIG_PIN_TLB_DATA) && !defined(CONFIG_PIN_TLB_IMMR) 611 lis r0, MD_TWAM@h 612 mtspr SPRN_MD_CTR, r0 613#endif 614 tlbia /* Clear all TLB entries */ 615 sync /* wait for tlbia/tlbie to finish */ 616 617 /* set up the PTE pointers for the Abatron bdiGDB. 618 */ 619 lis r5, abatron_pteptrs@h 620 ori r5, r5, abatron_pteptrs@l 621 stw r5, 0xf0(0) /* Must match your Abatron config file */ 622 tophys(r5,r5) 623 lis r6, swapper_pg_dir@h 624 ori r6, r6, swapper_pg_dir@l 625 stw r6, 0(r5) 626 627/* Now turn on the MMU for real! */ 628 li r4,MSR_KERNEL 629 lis r3,start_kernel@h 630 ori r3,r3,start_kernel@l 631 mtspr SPRN_SRR0,r3 632 mtspr SPRN_SRR1,r4 633 rfi /* enable MMU and jump to start_kernel */ 634 635/* Set up the initial MMU state so we can do the first level of 636 * kernel initialization. This maps the first 8 MBytes of memory 1:1 637 * virtual to physical. Also, set the cache mode since that is defined 638 * by TLB entries and perform any additional mapping (like of the IMMR). 639 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 640 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 641 * these mappings is mapped by page tables. 642 */ 643initial_mmu: 644 li r8, 0 645 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 646 lis r10, MD_TWAM@h 647 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 648 649 tlbia /* Invalidate all TLB entries */ 650 651 lis r8, MI_APG_INIT@h /* Set protection modes */ 652 ori r8, r8, MI_APG_INIT@l 653 mtspr SPRN_MI_AP, r8 654 lis r8, MD_APG_INIT@h 655 ori r8, r8, MD_APG_INIT@l 656 mtspr SPRN_MD_AP, r8 657 658 /* Map the lower RAM (up to 32 Mbytes) into the ITLB and DTLB */ 659 lis r8, MI_RSV4I@h 660 ori r8, r8, 0x1c00 661 oris r12, r10, MD_RSV4I@h 662 ori r12, r12, 0x1c00 663 li r9, 4 /* up to 4 pages of 8M */ 664 mtctr r9 665 lis r9, KERNELBASE@h /* Create vaddr for TLB */ 666 li r10, MI_PS8MEG | _PMD_ACCESSED | MI_SVALID 667 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 6681: 669 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 670 addi r8, r8, 0x100 671 ori r0, r9, MI_EVALID /* Mark it valid */ 672 mtspr SPRN_MI_EPN, r0 673 mtspr SPRN_MI_TWC, r10 674 mtspr SPRN_MI_RPN, r11 /* Store TLB entry */ 675 mtspr SPRN_MD_CTR, r12 676 addi r12, r12, 0x100 677 mtspr SPRN_MD_EPN, r0 678 mtspr SPRN_MD_TWC, r10 679 mtspr SPRN_MD_RPN, r11 680 addis r9, r9, 0x80 681 addis r11, r11, 0x80 682 683 bdnz 1b 684 685 /* Since the cache is enabled according to the information we 686 * just loaded into the TLB, invalidate and enable the caches here. 687 * We should probably check/set other modes....later. 688 */ 689 lis r8, IDC_INVALL@h 690 mtspr SPRN_IC_CST, r8 691 mtspr SPRN_DC_CST, r8 692 lis r8, IDC_ENABLE@h 693 mtspr SPRN_IC_CST, r8 694 mtspr SPRN_DC_CST, r8 695 /* Disable debug mode entry on breakpoints */ 696 mfspr r8, SPRN_DER 697#ifdef CONFIG_PERF_EVENTS 698 rlwinm r8, r8, 0, ~0xc 699#else 700 rlwinm r8, r8, 0, ~0x8 701#endif 702 mtspr SPRN_DER, r8 703 blr 704 705_GLOBAL(mmu_pin_tlb) 706 lis r9, (1f - PAGE_OFFSET)@h 707 ori r9, r9, (1f - PAGE_OFFSET)@l 708 mfmsr r10 709 mflr r11 710 li r12, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI) 711 rlwinm r0, r10, 0, ~MSR_RI 712 rlwinm r0, r0, 0, ~MSR_EE 713 mtmsr r0 714 isync 715 .align 4 716 mtspr SPRN_SRR0, r9 717 mtspr SPRN_SRR1, r12 718 rfi 7191: 720 li r5, 0 721 lis r6, MD_TWAM@h 722 mtspr SPRN_MI_CTR, r5 723 mtspr SPRN_MD_CTR, r6 724 tlbia 725 726 LOAD_REG_IMMEDIATE(r5, 28 << 8) 727 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET) 728 LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED) 729 LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT) 730 LOAD_REG_ADDR(r9, _sinittext) 731 li r0, 4 732 mtctr r0 733 7342: ori r0, r6, MI_EVALID 735 mtspr SPRN_MI_CTR, r5 736 mtspr SPRN_MI_EPN, r0 737 mtspr SPRN_MI_TWC, r7 738 mtspr SPRN_MI_RPN, r8 739 addi r5, r5, 0x100 740 addis r6, r6, SZ_8M@h 741 addis r8, r8, SZ_8M@h 742 cmplw r6, r9 743 bdnzt lt, 2b 744 lis r0, MI_RSV4I@h 745 mtspr SPRN_MI_CTR, r0 746 747 LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TWAM) 748#ifdef CONFIG_PIN_TLB_DATA 749 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET) 750 LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED) 751#ifdef CONFIG_PIN_TLB_IMMR 752 li r0, 3 753#else 754 li r0, 4 755#endif 756 mtctr r0 757 cmpwi r4, 0 758 beq 4f 759 LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT) 760 LOAD_REG_ADDR(r9, _sinittext) 761 7622: ori r0, r6, MD_EVALID 763 mtspr SPRN_MD_CTR, r5 764 mtspr SPRN_MD_EPN, r0 765 mtspr SPRN_MD_TWC, r7 766 mtspr SPRN_MD_RPN, r8 767 addi r5, r5, 0x100 768 addis r6, r6, SZ_8M@h 769 addis r8, r8, SZ_8M@h 770 cmplw r6, r9 771 bdnzt lt, 2b 772 7734: LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT) 7742: ori r0, r6, MD_EVALID 775 mtspr SPRN_MD_CTR, r5 776 mtspr SPRN_MD_EPN, r0 777 mtspr SPRN_MD_TWC, r7 778 mtspr SPRN_MD_RPN, r8 779 addi r5, r5, 0x100 780 addis r6, r6, SZ_8M@h 781 addis r8, r8, SZ_8M@h 782 cmplw r6, r3 783 bdnzt lt, 2b 784#endif 785#ifdef CONFIG_PIN_TLB_IMMR 786 LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID) 787 LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED | _PMD_ACCESSED) 788 mfspr r8, SPRN_IMMR 789 rlwinm r8, r8, 0, 0xfff80000 790 ori r8, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \ 791 _PAGE_NO_CACHE | _PAGE_PRESENT 792 mtspr SPRN_MD_CTR, r5 793 mtspr SPRN_MD_EPN, r0 794 mtspr SPRN_MD_TWC, r7 795 mtspr SPRN_MD_RPN, r8 796#endif 797#if defined(CONFIG_PIN_TLB_IMMR) || defined(CONFIG_PIN_TLB_DATA) 798 lis r0, (MD_RSV4I | MD_TWAM)@h 799 mtspr SPRN_MI_CTR, r0 800#endif 801 mtspr SPRN_SRR1, r10 802 mtspr SPRN_SRR0, r11 803 rfi 804 805/* 806 * We put a few things here that have to be page-aligned. 807 * This stuff goes at the beginning of the data segment, 808 * which is page-aligned. 809 */ 810 .data 811 .globl sdata 812sdata: 813 .globl empty_zero_page 814 .align PAGE_SHIFT 815empty_zero_page: 816 .space PAGE_SIZE 817EXPORT_SYMBOL(empty_zero_page) 818 819 .globl swapper_pg_dir 820swapper_pg_dir: 821 .space PGD_TABLE_SIZE 822 823/* Room for two PTE table poiners, usually the kernel and current user 824 * pointer to their respective root page table (pgdir). 825 */ 826 .globl abatron_pteptrs 827abatron_pteptrs: 828 .space 8 829