1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/ptrace.h> 33#include <asm/fixmap.h> 34 35/* Macro to make the code more readable. */ 36#ifdef CONFIG_8xx_CPU6 37#define SPRN_MI_TWC_ADDR 0x2b80 38#define SPRN_MI_RPN_ADDR 0x2d80 39#define SPRN_MD_TWC_ADDR 0x3b80 40#define SPRN_MD_RPN_ADDR 0x3d80 41 42#define MTSPR_CPU6(spr, reg, treg) \ 43 li treg, spr##_ADDR; \ 44 stw treg, 12(r0); \ 45 lwz treg, 12(r0); \ 46 mtspr spr, reg 47#else 48#define MTSPR_CPU6(spr, reg, treg) \ 49 mtspr spr, reg 50#endif 51 52/* Macro to test if an address is a kernel address */ 53#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 54#define IS_KERNEL(tmp, addr) \ 55 andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */ 56#define BRANCH_UNLESS_KERNEL(label) beq label 57#else 58#define IS_KERNEL(tmp, addr) \ 59 rlwinm tmp, addr, 16, 16, 31; \ 60 cmpli cr0, tmp, PAGE_OFFSET >> 16 61#define BRANCH_UNLESS_KERNEL(label) blt label 62#endif 63 64 65/* 66 * Value for the bits that have fixed value in RPN entries. 67 * Also used for tagging DAR for DTLBerror. 68 */ 69#ifdef CONFIG_PPC_16K_PAGES 70#define RPN_PATTERN (0x00f0 | MD_SPS16K) 71#else 72#define RPN_PATTERN 0x00f0 73#endif 74 75 __HEAD 76_ENTRY(_stext); 77_ENTRY(_start); 78 79/* MPC8xx 80 * This port was done on an MBX board with an 860. Right now I only 81 * support an ELF compressed (zImage) boot from EPPC-Bug because the 82 * code there loads up some registers before calling us: 83 * r3: ptr to board info data 84 * r4: initrd_start or if no initrd then 0 85 * r5: initrd_end - unused if r4 is 0 86 * r6: Start of command line string 87 * r7: End of command line string 88 * 89 * I decided to use conditional compilation instead of checking PVR and 90 * adding more processor specific branches around code I don't need. 91 * Since this is an embedded processor, I also appreciate any memory 92 * savings I can get. 93 * 94 * The MPC8xx does not have any BATs, but it supports large page sizes. 95 * We first initialize the MMU to support 8M byte pages, then load one 96 * entry into each of the instruction and data TLBs to map the first 97 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 98 * the "internal" processor registers before MMU_init is called. 99 * 100 * -- Dan 101 */ 102 .globl __start 103__start: 104 mr r31,r3 /* save device tree ptr */ 105 106 /* We have to turn on the MMU right away so we get cache modes 107 * set correctly. 108 */ 109 bl initial_mmu 110 111/* We now have the lower 8 Meg mapped into TLB entries, and the caches 112 * ready to work. 113 */ 114 115turn_on_mmu: 116 mfmsr r0 117 ori r0,r0,MSR_DR|MSR_IR 118 mtspr SPRN_SRR1,r0 119 lis r0,start_here@h 120 ori r0,r0,start_here@l 121 mtspr SPRN_SRR0,r0 122 SYNC 123 rfi /* enables MMU */ 124 125/* 126 * Exception entry code. This code runs with address translation 127 * turned off, i.e. using physical addresses. 128 * We assume sprg3 has the physical address of the current 129 * task's thread_struct. 130 */ 131#define EXCEPTION_PROLOG \ 132 EXCEPTION_PROLOG_0; \ 133 mfcr r10; \ 134 EXCEPTION_PROLOG_1; \ 135 EXCEPTION_PROLOG_2 136 137#define EXCEPTION_PROLOG_0 \ 138 mtspr SPRN_SPRG_SCRATCH0,r10; \ 139 mtspr SPRN_SPRG_SCRATCH1,r11 140 141#define EXCEPTION_PROLOG_1 \ 142 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 143 andi. r11,r11,MSR_PR; \ 144 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 145 beq 1f; \ 146 mfspr r11,SPRN_SPRG_THREAD; \ 147 lwz r11,THREAD_INFO-THREAD(r11); \ 148 addi r11,r11,THREAD_SIZE; \ 149 tophys(r11,r11); \ 1501: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 151 152 153#define EXCEPTION_PROLOG_2 \ 154 stw r10,_CCR(r11); /* save registers */ \ 155 stw r12,GPR12(r11); \ 156 stw r9,GPR9(r11); \ 157 mfspr r10,SPRN_SPRG_SCRATCH0; \ 158 stw r10,GPR10(r11); \ 159 mfspr r12,SPRN_SPRG_SCRATCH1; \ 160 stw r12,GPR11(r11); \ 161 mflr r10; \ 162 stw r10,_LINK(r11); \ 163 mfspr r12,SPRN_SRR0; \ 164 mfspr r9,SPRN_SRR1; \ 165 stw r1,GPR1(r11); \ 166 stw r1,0(r11); \ 167 tovirt(r1,r11); /* set new kernel sp */ \ 168 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 169 MTMSRD(r10); /* (except for mach check in rtas) */ \ 170 stw r0,GPR0(r11); \ 171 SAVE_4GPRS(3, r11); \ 172 SAVE_2GPRS(7, r11) 173 174/* 175 * Exception exit code. 176 */ 177#define EXCEPTION_EPILOG_0 \ 178 mfspr r10,SPRN_SPRG_SCRATCH0; \ 179 mfspr r11,SPRN_SPRG_SCRATCH1 180 181/* 182 * Note: code which follows this uses cr0.eq (set if from kernel), 183 * r11, r12 (SRR0), and r9 (SRR1). 184 * 185 * Note2: once we have set r1 we are in a position to take exceptions 186 * again, and we could thus set MSR:RI at that point. 187 */ 188 189/* 190 * Exception vectors. 191 */ 192#define EXCEPTION(n, label, hdlr, xfer) \ 193 . = n; \ 194label: \ 195 EXCEPTION_PROLOG; \ 196 addi r3,r1,STACK_FRAME_OVERHEAD; \ 197 xfer(n, hdlr) 198 199#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 200 li r10,trap; \ 201 stw r10,_TRAP(r11); \ 202 li r10,MSR_KERNEL; \ 203 copyee(r10, r9); \ 204 bl tfer; \ 205i##n: \ 206 .long hdlr; \ 207 .long ret 208 209#define COPY_EE(d, s) rlwimi d,s,0,16,16 210#define NOCOPY(d, s) 211 212#define EXC_XFER_STD(n, hdlr) \ 213 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 214 ret_from_except_full) 215 216#define EXC_XFER_LITE(n, hdlr) \ 217 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 218 ret_from_except) 219 220#define EXC_XFER_EE(n, hdlr) \ 221 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 222 ret_from_except_full) 223 224#define EXC_XFER_EE_LITE(n, hdlr) \ 225 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 226 ret_from_except) 227 228/* System reset */ 229 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) 230 231/* Machine check */ 232 . = 0x200 233MachineCheck: 234 EXCEPTION_PROLOG 235 mfspr r4,SPRN_DAR 236 stw r4,_DAR(r11) 237 li r5,RPN_PATTERN 238 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 239 mfspr r5,SPRN_DSISR 240 stw r5,_DSISR(r11) 241 addi r3,r1,STACK_FRAME_OVERHEAD 242 EXC_XFER_STD(0x200, machine_check_exception) 243 244/* Data access exception. 245 * This is "never generated" by the MPC8xx. 246 */ 247 . = 0x300 248DataAccess: 249 250/* Instruction access exception. 251 * This is "never generated" by the MPC8xx. 252 */ 253 . = 0x400 254InstructionAccess: 255 256/* External interrupt */ 257 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 258 259/* Alignment exception */ 260 . = 0x600 261Alignment: 262 EXCEPTION_PROLOG 263 mfspr r4,SPRN_DAR 264 stw r4,_DAR(r11) 265 li r5,RPN_PATTERN 266 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 267 mfspr r5,SPRN_DSISR 268 stw r5,_DSISR(r11) 269 addi r3,r1,STACK_FRAME_OVERHEAD 270 EXC_XFER_EE(0x600, alignment_exception) 271 272/* Program check exception */ 273 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 274 275/* No FPU on MPC8xx. This exception is not supposed to happen. 276*/ 277 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 278 279/* Decrementer */ 280 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 281 282 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 283 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 284 285/* System call */ 286 . = 0xc00 287SystemCall: 288 EXCEPTION_PROLOG 289 EXC_XFER_EE_LITE(0xc00, DoSyscall) 290 291/* Single step - not used on 601 */ 292 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 293 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 294 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 295 296/* On the MPC8xx, this is a software emulation interrupt. It occurs 297 * for all unimplemented and illegal instructions. 298 */ 299 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 300 301 . = 0x1100 302/* 303 * For the MPC8xx, this is a software tablewalk to load the instruction 304 * TLB. The task switch loads the M_TW register with the pointer to the first 305 * level table. 306 * If we discover there is no second level table (value is zero) or if there 307 * is an invalid pte, we load that into the TLB, which causes another fault 308 * into the TLB Error interrupt where we can handle such problems. 309 * We have to use the MD_xxx registers for the tablewalk because the 310 * equivalent MI_xxx registers only perform the attribute functions. 311 */ 312 313#ifdef CONFIG_8xx_CPU15 314#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ 315 addi tmp, addr, PAGE_SIZE; \ 316 tlbie tmp; \ 317 addi tmp, addr, -PAGE_SIZE; \ 318 tlbie tmp 319#else 320#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) 321#endif 322 323InstructionTLBMiss: 324#ifdef CONFIG_8xx_CPU6 325 mtspr SPRN_SPRG_SCRATCH2, r3 326#endif 327 EXCEPTION_PROLOG_0 328 329 /* If we are faulting a kernel address, we have to use the 330 * kernel page tables. 331 */ 332#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) 333 /* Only modules will cause ITLB Misses as we always 334 * pin the first 8MB of kernel memory */ 335 mfspr r11, SPRN_SRR0 /* Get effective address of fault */ 336 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11) 337 mfcr r10 338 IS_KERNEL(r11, r11) 339 mfspr r11, SPRN_M_TW /* Get level 1 table */ 340 BRANCH_UNLESS_KERNEL(3f) 341 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3423: 343 mtcr r10 344 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 345#else 346 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 347 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) 348 mfspr r11, SPRN_M_TW /* Get level 1 table base address */ 349#endif 350 /* Insert level 1 index */ 351 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 352 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 353 354 /* Extract level 2 index */ 355 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 356 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 357 lwz r10, 0(r10) /* Get the pte */ 358 359 /* Insert the APG into the TWC from the Linux PTE. */ 360 rlwimi r11, r10, 0, 25, 26 361 /* Load the MI_TWC with the attributes for this "segment." */ 362 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */ 363 364#ifdef CONFIG_SWAP 365 rlwinm r11, r10, 32-5, _PAGE_PRESENT 366 and r11, r11, r10 367 rlwimi r10, r11, 0, _PAGE_PRESENT 368#endif 369 li r11, RPN_PATTERN 370 /* The Linux PTE won't go exactly into the MMU TLB. 371 * Software indicator bits 20-23 and 28 must be clear. 372 * Software indicator bits 24, 25, 26, and 27 must be 373 * set. All other Linux PTE bits control the behavior 374 * of the MMU. 375 */ 376 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */ 377 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */ 378 379 /* Restore registers */ 380#ifdef CONFIG_8xx_CPU6 381 mfspr r3, SPRN_SPRG_SCRATCH2 382#endif 383 EXCEPTION_EPILOG_0 384 rfi 385 386/* 387 * Bottom part of DataStoreTLBMiss handler for IMMR area 388 * not enough space in the DataStoreTLBMiss area 389 */ 390DTLBMissIMMR: 391 mtcr r10 392 /* Set 512k byte guarded page and mark it valid */ 393 li r10, MD_PS512K | MD_GUARDED | MD_SVALID 394 MTSPR_CPU6(SPRN_MD_TWC, r10, r11) 395 mfspr r10, SPRN_IMMR /* Get current IMMR */ 396 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */ 397 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 398 _PAGE_PRESENT | _PAGE_NO_CACHE 399 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 400 401 li r11, RPN_PATTERN 402 mtspr SPRN_DAR, r11 /* Tag DAR */ 403 EXCEPTION_EPILOG_0 404 rfi 405 406 . = 0x1200 407DataStoreTLBMiss: 408 EXCEPTION_PROLOG_0 409 mfcr r10 410 411 /* If we are faulting a kernel address, we have to use the 412 * kernel page tables. 413 */ 414 mfspr r11, SPRN_MD_EPN 415 rlwinm r11, r11, 16, 0xfff8 416#ifndef CONFIG_PIN_TLB_IMMR 417 cmpli cr0, r11, VIRT_IMMR_BASE@h 418#endif 419 cmpli cr7, r11, PAGE_OFFSET@h 420#ifndef CONFIG_PIN_TLB_IMMR 421_ENTRY(DTLBMiss_jmp) 422 beq- DTLBMissIMMR 423#endif 424 bge- cr7, 4f 425 426 mfspr r11, SPRN_M_TW /* Get level 1 table */ 4273: 428 mtcr r10 429#ifdef CONFIG_8xx_CPU6 430 mtspr SPRN_SPRG_SCRATCH2, r3 431#endif 432 mfspr r10, SPRN_MD_EPN 433 434 /* Insert level 1 index */ 435 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 436 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 437 438 /* We have a pte table, so load fetch the pte from the table. 439 */ 440 /* Extract level 2 index */ 441 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 442 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 443 lwz r10, 0(r10) /* Get the pte */ 444 445 /* Insert the Guarded flag and APG into the TWC from the Linux PTE. 446 * It is bit 26-27 of both the Linux PTE and the TWC (at least 447 * I got that right :-). It will be better when we can put 448 * this into the Linux pgd/pmd and load it in the operation 449 * above. 450 */ 451 rlwimi r11, r10, 0, 26, 27 452 /* Insert the WriteThru flag into the TWC from the Linux PTE. 453 * It is bit 25 in the Linux PTE and bit 30 in the TWC 454 */ 455 rlwimi r11, r10, 32-5, 30, 30 456 MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 457 458 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 459 * We also need to know if the insn is a load/store, so: 460 * Clear _PAGE_PRESENT and load that which will 461 * trap into DTLB Error with store bit set accordinly. 462 */ 463 /* PRESENT=0x1, ACCESSED=0x20 464 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 465 * r10 = (r10 & ~PRESENT) | r11; 466 */ 467#ifdef CONFIG_SWAP 468 rlwinm r11, r10, 32-5, _PAGE_PRESENT 469 and r11, r11, r10 470 rlwimi r10, r11, 0, _PAGE_PRESENT 471#endif 472 /* The Linux PTE won't go exactly into the MMU TLB. 473 * Software indicator bits 22 and 28 must be clear. 474 * Software indicator bits 24, 25, 26, and 27 must be 475 * set. All other Linux PTE bits control the behavior 476 * of the MMU. 477 */ 478 li r11, RPN_PATTERN 479 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 480 rlwimi r10, r11, 0, 20, 20 /* clear 20 */ 481 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ 482 483 /* Restore registers */ 484#ifdef CONFIG_8xx_CPU6 485 mfspr r3, SPRN_SPRG_SCRATCH2 486#endif 487 mtspr SPRN_DAR, r11 /* Tag DAR */ 488 EXCEPTION_EPILOG_0 489 rfi 490 4914: 492_ENTRY(DTLBMiss_cmp) 493 cmpli cr0, r11, (PAGE_OFFSET + 0x1800000)@h 494 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 495 bge- 3b 496 497 mtcr r10 498 /* Set 8M byte page and mark it valid */ 499 li r10, MD_PS8MEG | MD_SVALID 500 MTSPR_CPU6(SPRN_MD_TWC, r10, r11) 501 mfspr r10, SPRN_MD_EPN 502 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 503 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 504 _PAGE_PRESENT 505 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 506 507 li r11, RPN_PATTERN 508 mtspr SPRN_DAR, r11 /* Tag DAR */ 509 EXCEPTION_EPILOG_0 510 rfi 511 512 513/* This is an instruction TLB error on the MPC8xx. This could be due 514 * to many reasons, such as executing guarded memory or illegal instruction 515 * addresses. There is nothing to do but handle a big time error fault. 516 */ 517 . = 0x1300 518InstructionTLBError: 519 EXCEPTION_PROLOG 520 mr r4,r12 521 mr r5,r9 522 andis. r10,r5,0x4000 523 beq+ 1f 524 tlbie r4 525 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 5261: EXC_XFER_LITE(0x400, handle_page_fault) 527 528/* This is the data TLB error on the MPC8xx. This could be due to 529 * many reasons, including a dirty update to a pte. We bail out to 530 * a higher level function that can handle it. 531 */ 532 . = 0x1400 533DataTLBError: 534 EXCEPTION_PROLOG_0 535 mfcr r10 536 537 mfspr r11, SPRN_DAR 538 cmpwi cr0, r11, RPN_PATTERN 539 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 540DARFixed:/* Return from dcbx instruction bug workaround */ 541 EXCEPTION_PROLOG_1 542 EXCEPTION_PROLOG_2 543 mfspr r5,SPRN_DSISR 544 stw r5,_DSISR(r11) 545 mfspr r4,SPRN_DAR 546 andis. r10,r5,0x4000 547 beq+ 1f 548 tlbie r4 5491: li r10,RPN_PATTERN 550 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 551 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 552 EXC_XFER_LITE(0x300, handle_page_fault) 553 554 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 555 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 556 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 557 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 558 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 559 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 560 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 561 562/* On the MPC8xx, these next four traps are used for development 563 * support of breakpoints and such. Someday I will get around to 564 * using them. 565 */ 566 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 567 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 568 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 569 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 570 571 . = 0x2000 572 573/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 574 * by decoding the registers used by the dcbx instruction and adding them. 575 * DAR is set to the calculated address. 576 */ 577 /* define if you don't want to use self modifying code */ 578#define NO_SELF_MODIFYING_CODE 579FixupDAR:/* Entry point for dcbx workaround. */ 580 mtspr SPRN_SPRG_SCRATCH2, r10 581 /* fetch instruction from memory. */ 582 mfspr r10, SPRN_SRR0 583 IS_KERNEL(r11, r10) 584 mfspr r11, SPRN_M_TW /* Get level 1 table */ 585 BRANCH_UNLESS_KERNEL(3f) 586 rlwinm r11, r10, 16, 0xfff8 587_ENTRY(FixupDAR_cmp) 588 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 589 blt- cr7, 200f 590 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 591 /* Insert level 1 index */ 5923: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 593 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 594 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */ 595 /* Insert level 2 index */ 596 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 597 lwz r11, 0(r11) /* Get the pte */ 598 /* concat physical page address(r11) and page offset(r10) */ 599 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 600201: lwz r11,0(r11) 601/* Check if it really is a dcbx instruction. */ 602/* dcbt and dcbtst does not generate DTLB Misses/Errors, 603 * no need to include them here */ 604 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 605 rlwinm r10, r10, 0, 21, 5 606 cmpwi cr0, r10, 2028 /* Is dcbz? */ 607 beq+ 142f 608 cmpwi cr0, r10, 940 /* Is dcbi? */ 609 beq+ 142f 610 cmpwi cr0, r10, 108 /* Is dcbst? */ 611 beq+ 144f /* Fix up store bit! */ 612 cmpwi cr0, r10, 172 /* Is dcbf? */ 613 beq+ 142f 614 cmpwi cr0, r10, 1964 /* Is icbi? */ 615 beq+ 142f 616141: mfspr r10,SPRN_SPRG_SCRATCH2 617 b DARFixed /* Nope, go back to normal TLB processing */ 618 619 /* create physical page address from effective address */ 620200: tophys(r11, r10) 621 b 201b 622 623144: mfspr r10, SPRN_DSISR 624 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 625 mtspr SPRN_DSISR, r10 626142: /* continue, it was a dcbx, dcbi instruction. */ 627#ifndef NO_SELF_MODIFYING_CODE 628 andis. r10,r11,0x1f /* test if reg RA is r0 */ 629 li r10,modified_instr@l 630 dcbtst r0,r10 /* touch for store */ 631 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 632 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 633 ori r11,r11,532 634 stw r11,0(r10) /* store add/and instruction */ 635 dcbf 0,r10 /* flush new instr. to memory. */ 636 icbi 0,r10 /* invalidate instr. cache line */ 637 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */ 638 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */ 639 isync /* Wait until new instr is loaded from memory */ 640modified_instr: 641 .space 4 /* this is where the add instr. is stored */ 642 bne+ 143f 643 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 644143: mtdar r10 /* store faulting EA in DAR */ 645 mfspr r10,SPRN_SPRG_SCRATCH2 646 b DARFixed /* Go back to normal TLB handling */ 647#else 648 mfctr r10 649 mtdar r10 /* save ctr reg in DAR */ 650 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 651 addi r10, r10, 150f@l /* add start of table */ 652 mtctr r10 /* load ctr with jump address */ 653 xor r10, r10, r10 /* sum starts at zero */ 654 bctr /* jump into table */ 655150: 656 add r10, r10, r0 ;b 151f 657 add r10, r10, r1 ;b 151f 658 add r10, r10, r2 ;b 151f 659 add r10, r10, r3 ;b 151f 660 add r10, r10, r4 ;b 151f 661 add r10, r10, r5 ;b 151f 662 add r10, r10, r6 ;b 151f 663 add r10, r10, r7 ;b 151f 664 add r10, r10, r8 ;b 151f 665 add r10, r10, r9 ;b 151f 666 mtctr r11 ;b 154f /* r10 needs special handling */ 667 mtctr r11 ;b 153f /* r11 needs special handling */ 668 add r10, r10, r12 ;b 151f 669 add r10, r10, r13 ;b 151f 670 add r10, r10, r14 ;b 151f 671 add r10, r10, r15 ;b 151f 672 add r10, r10, r16 ;b 151f 673 add r10, r10, r17 ;b 151f 674 add r10, r10, r18 ;b 151f 675 add r10, r10, r19 ;b 151f 676 add r10, r10, r20 ;b 151f 677 add r10, r10, r21 ;b 151f 678 add r10, r10, r22 ;b 151f 679 add r10, r10, r23 ;b 151f 680 add r10, r10, r24 ;b 151f 681 add r10, r10, r25 ;b 151f 682 add r10, r10, r26 ;b 151f 683 add r10, r10, r27 ;b 151f 684 add r10, r10, r28 ;b 151f 685 add r10, r10, r29 ;b 151f 686 add r10, r10, r30 ;b 151f 687 add r10, r10, r31 688151: 689 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 690 beq 152f /* if reg RA is zero, don't add it */ 691 addi r11, r11, 150b@l /* add start of table */ 692 mtctr r11 /* load ctr with jump address */ 693 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 694 bctr /* jump into table */ 695152: 696 mfdar r11 697 mtctr r11 /* restore ctr reg from DAR */ 698 mtdar r10 /* save fault EA to DAR */ 699 mfspr r10,SPRN_SPRG_SCRATCH2 700 b DARFixed /* Go back to normal TLB handling */ 701 702 /* special handling for r10,r11 since these are modified already */ 703153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 704 add r10, r10, r11 /* add it */ 705 mfctr r11 /* restore r11 */ 706 b 151b 707154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 708 add r10, r10, r11 /* add it */ 709 mfctr r11 /* restore r11 */ 710 b 151b 711#endif 712 713/* 714 * This is where the main kernel code starts. 715 */ 716start_here: 717 /* ptr to current */ 718 lis r2,init_task@h 719 ori r2,r2,init_task@l 720 721 /* ptr to phys current thread */ 722 tophys(r4,r2) 723 addi r4,r4,THREAD /* init task's THREAD */ 724 mtspr SPRN_SPRG_THREAD,r4 725 726 /* stack */ 727 lis r1,init_thread_union@ha 728 addi r1,r1,init_thread_union@l 729 li r0,0 730 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 731 732 bl early_init /* We have to do this with MMU on */ 733 734/* 735 * Decide what sort of machine this is and initialize the MMU. 736 */ 737 li r3,0 738 mr r4,r31 739 bl machine_init 740 bl MMU_init 741 742/* 743 * Go back to running unmapped so we can load up new values 744 * and change to using our exception vectors. 745 * On the 8xx, all we have to do is invalidate the TLB to clear 746 * the old 8M byte TLB mappings and load the page table base register. 747 */ 748 /* The right way to do this would be to track it down through 749 * init's THREAD like the context switch code does, but this is 750 * easier......until someone changes init's static structures. 751 */ 752 lis r6, swapper_pg_dir@ha 753 tophys(r6,r6) 754#ifdef CONFIG_8xx_CPU6 755 lis r4, cpu6_errata_word@h 756 ori r4, r4, cpu6_errata_word@l 757 li r3, 0x3f80 758 stw r3, 12(r4) 759 lwz r3, 12(r4) 760#endif 761 mtspr SPRN_M_TW, r6 762 lis r4,2f@h 763 ori r4,r4,2f@l 764 tophys(r4,r4) 765 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 766 mtspr SPRN_SRR0,r4 767 mtspr SPRN_SRR1,r3 768 rfi 769/* Load up the kernel context */ 7702: 771 SYNC /* Force all PTE updates to finish */ 772 tlbia /* Clear all TLB entries */ 773 sync /* wait for tlbia/tlbie to finish */ 774 TLBSYNC /* ... on all CPUs */ 775 776 /* set up the PTE pointers for the Abatron bdiGDB. 777 */ 778 tovirt(r6,r6) 779 lis r5, abatron_pteptrs@h 780 ori r5, r5, abatron_pteptrs@l 781 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 782 tophys(r5,r5) 783 stw r6, 0(r5) 784 785/* Now turn on the MMU for real! */ 786 li r4,MSR_KERNEL 787 lis r3,start_kernel@h 788 ori r3,r3,start_kernel@l 789 mtspr SPRN_SRR0,r3 790 mtspr SPRN_SRR1,r4 791 rfi /* enable MMU and jump to start_kernel */ 792 793/* Set up the initial MMU state so we can do the first level of 794 * kernel initialization. This maps the first 8 MBytes of memory 1:1 795 * virtual to physical. Also, set the cache mode since that is defined 796 * by TLB entries and perform any additional mapping (like of the IMMR). 797 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 798 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 799 * these mappings is mapped by page tables. 800 */ 801initial_mmu: 802 li r8, 0 803 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 804 lis r10, MD_RESETVAL@h 805#ifndef CONFIG_8xx_COPYBACK 806 oris r10, r10, MD_WTDEF@h 807#endif 808 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 809 810 tlbia /* Invalidate all TLB entries */ 811/* Always pin the first 8 MB ITLB to prevent ITLB 812 misses while mucking around with SRR0/SRR1 in asm 813*/ 814 lis r8, MI_RSV4I@h 815 ori r8, r8, 0x1c00 816 817 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 818 819#ifdef CONFIG_PIN_TLB 820 oris r10, r10, MD_RSV4I@h 821 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 822#endif 823 824 /* Now map the lower 8 Meg into the ITLB. */ 825 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 826 ori r8, r8, MI_EVALID /* Mark it valid */ 827 mtspr SPRN_MI_EPN, r8 828 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */ 829 ori r8, r8, MI_SVALID /* Make it valid */ 830 mtspr SPRN_MI_TWC, r8 831 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 832 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 833 834 lis r8, MI_APG_INIT@h /* Set protection modes */ 835 ori r8, r8, MI_APG_INIT@l 836 mtspr SPRN_MI_AP, r8 837 lis r8, MD_APG_INIT@h 838 ori r8, r8, MD_APG_INIT@l 839 mtspr SPRN_MD_AP, r8 840 841 /* Map a 512k page for the IMMR to get the processor 842 * internal registers (among other things). 843 */ 844#ifdef CONFIG_PIN_TLB_IMMR 845 ori r10, r10, 0x1c00 846 mtspr SPRN_MD_CTR, r10 847 848 mfspr r9, 638 /* Get current IMMR */ 849 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */ 850 851 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */ 852 ori r8, r8, MD_EVALID /* Mark it valid */ 853 mtspr SPRN_MD_EPN, r8 854 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */ 855 ori r8, r8, MD_SVALID /* Make it valid */ 856 mtspr SPRN_MD_TWC, r8 857 mr r8, r9 /* Create paddr for TLB */ 858 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 859 mtspr SPRN_MD_RPN, r8 860#endif 861 862 /* Since the cache is enabled according to the information we 863 * just loaded into the TLB, invalidate and enable the caches here. 864 * We should probably check/set other modes....later. 865 */ 866 lis r8, IDC_INVALL@h 867 mtspr SPRN_IC_CST, r8 868 mtspr SPRN_DC_CST, r8 869 lis r8, IDC_ENABLE@h 870 mtspr SPRN_IC_CST, r8 871#ifdef CONFIG_8xx_COPYBACK 872 mtspr SPRN_DC_CST, r8 873#else 874 /* For a debug option, I left this here to easily enable 875 * the write through cache mode 876 */ 877 lis r8, DC_SFWT@h 878 mtspr SPRN_DC_CST, r8 879 lis r8, IDC_ENABLE@h 880 mtspr SPRN_DC_CST, r8 881#endif 882 blr 883 884 885/* 886 * We put a few things here that have to be page-aligned. 887 * This stuff goes at the beginning of the data segment, 888 * which is page-aligned. 889 */ 890 .data 891 .globl sdata 892sdata: 893 .globl empty_zero_page 894 .align PAGE_SHIFT 895empty_zero_page: 896 .space PAGE_SIZE 897 898 .globl swapper_pg_dir 899swapper_pg_dir: 900 .space PGD_TABLE_SIZE 901 902/* Room for two PTE table poiners, usually the kernel and current user 903 * pointer to their respective root page table (pgdir). 904 */ 905abatron_pteptrs: 906 .space 8 907 908#ifdef CONFIG_8xx_CPU6 909 .globl cpu6_errata_word 910cpu6_errata_word: 911 .space 16 912#endif 913 914