1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/ptrace.h> 33#include <asm/fixmap.h> 34 35/* Macro to make the code more readable. */ 36#ifdef CONFIG_8xx_CPU6 37#define SPRN_MI_TWC_ADDR 0x2b80 38#define SPRN_MI_RPN_ADDR 0x2d80 39#define SPRN_MD_TWC_ADDR 0x3b80 40#define SPRN_MD_RPN_ADDR 0x3d80 41 42#define MTSPR_CPU6(spr, reg, treg) \ 43 li treg, spr##_ADDR; \ 44 stw treg, 12(r0); \ 45 lwz treg, 12(r0); \ 46 mtspr spr, reg 47#else 48#define MTSPR_CPU6(spr, reg, treg) \ 49 mtspr spr, reg 50#endif 51 52/* Macro to test if an address is a kernel address */ 53#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 54#define IS_KERNEL(tmp, addr) \ 55 andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */ 56#define BRANCH_UNLESS_KERNEL(label) beq label 57#else 58#define IS_KERNEL(tmp, addr) \ 59 rlwinm tmp, addr, 16, 16, 31; \ 60 cmpli cr0, tmp, PAGE_OFFSET >> 16 61#define BRANCH_UNLESS_KERNEL(label) blt label 62#endif 63 64 65/* 66 * Value for the bits that have fixed value in RPN entries. 67 * Also used for tagging DAR for DTLBerror. 68 */ 69#ifdef CONFIG_PPC_16K_PAGES 70#define RPN_PATTERN (0x00f0 | MD_SPS16K) 71#else 72#define RPN_PATTERN 0x00f0 73#endif 74 75 __HEAD 76_ENTRY(_stext); 77_ENTRY(_start); 78 79/* MPC8xx 80 * This port was done on an MBX board with an 860. Right now I only 81 * support an ELF compressed (zImage) boot from EPPC-Bug because the 82 * code there loads up some registers before calling us: 83 * r3: ptr to board info data 84 * r4: initrd_start or if no initrd then 0 85 * r5: initrd_end - unused if r4 is 0 86 * r6: Start of command line string 87 * r7: End of command line string 88 * 89 * I decided to use conditional compilation instead of checking PVR and 90 * adding more processor specific branches around code I don't need. 91 * Since this is an embedded processor, I also appreciate any memory 92 * savings I can get. 93 * 94 * The MPC8xx does not have any BATs, but it supports large page sizes. 95 * We first initialize the MMU to support 8M byte pages, then load one 96 * entry into each of the instruction and data TLBs to map the first 97 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 98 * the "internal" processor registers before MMU_init is called. 99 * 100 * -- Dan 101 */ 102 .globl __start 103__start: 104 mr r31,r3 /* save device tree ptr */ 105 106 /* We have to turn on the MMU right away so we get cache modes 107 * set correctly. 108 */ 109 bl initial_mmu 110 111/* We now have the lower 8 Meg mapped into TLB entries, and the caches 112 * ready to work. 113 */ 114 115turn_on_mmu: 116 mfmsr r0 117 ori r0,r0,MSR_DR|MSR_IR 118 mtspr SPRN_SRR1,r0 119 lis r0,start_here@h 120 ori r0,r0,start_here@l 121 mtspr SPRN_SRR0,r0 122 SYNC 123 rfi /* enables MMU */ 124 125/* 126 * Exception entry code. This code runs with address translation 127 * turned off, i.e. using physical addresses. 128 * We assume sprg3 has the physical address of the current 129 * task's thread_struct. 130 */ 131#define EXCEPTION_PROLOG \ 132 EXCEPTION_PROLOG_0; \ 133 mfcr r10; \ 134 EXCEPTION_PROLOG_1; \ 135 EXCEPTION_PROLOG_2 136 137#define EXCEPTION_PROLOG_0 \ 138 mtspr SPRN_SPRG_SCRATCH0,r10; \ 139 mtspr SPRN_SPRG_SCRATCH1,r11 140 141#define EXCEPTION_PROLOG_1 \ 142 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 143 andi. r11,r11,MSR_PR; \ 144 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 145 beq 1f; \ 146 mfspr r11,SPRN_SPRG_THREAD; \ 147 lwz r11,THREAD_INFO-THREAD(r11); \ 148 addi r11,r11,THREAD_SIZE; \ 149 tophys(r11,r11); \ 1501: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 151 152 153#define EXCEPTION_PROLOG_2 \ 154 CLR_TOP32(r11); \ 155 stw r10,_CCR(r11); /* save registers */ \ 156 stw r12,GPR12(r11); \ 157 stw r9,GPR9(r11); \ 158 mfspr r10,SPRN_SPRG_SCRATCH0; \ 159 stw r10,GPR10(r11); \ 160 mfspr r12,SPRN_SPRG_SCRATCH1; \ 161 stw r12,GPR11(r11); \ 162 mflr r10; \ 163 stw r10,_LINK(r11); \ 164 mfspr r12,SPRN_SRR0; \ 165 mfspr r9,SPRN_SRR1; \ 166 stw r1,GPR1(r11); \ 167 stw r1,0(r11); \ 168 tovirt(r1,r11); /* set new kernel sp */ \ 169 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 170 MTMSRD(r10); /* (except for mach check in rtas) */ \ 171 stw r0,GPR0(r11); \ 172 SAVE_4GPRS(3, r11); \ 173 SAVE_2GPRS(7, r11) 174 175/* 176 * Exception exit code. 177 */ 178#define EXCEPTION_EPILOG_0 \ 179 mfspr r10,SPRN_SPRG_SCRATCH0; \ 180 mfspr r11,SPRN_SPRG_SCRATCH1 181 182/* 183 * Note: code which follows this uses cr0.eq (set if from kernel), 184 * r11, r12 (SRR0), and r9 (SRR1). 185 * 186 * Note2: once we have set r1 we are in a position to take exceptions 187 * again, and we could thus set MSR:RI at that point. 188 */ 189 190/* 191 * Exception vectors. 192 */ 193#define EXCEPTION(n, label, hdlr, xfer) \ 194 . = n; \ 195label: \ 196 EXCEPTION_PROLOG; \ 197 addi r3,r1,STACK_FRAME_OVERHEAD; \ 198 xfer(n, hdlr) 199 200#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 201 li r10,trap; \ 202 stw r10,_TRAP(r11); \ 203 li r10,MSR_KERNEL; \ 204 copyee(r10, r9); \ 205 bl tfer; \ 206i##n: \ 207 .long hdlr; \ 208 .long ret 209 210#define COPY_EE(d, s) rlwimi d,s,0,16,16 211#define NOCOPY(d, s) 212 213#define EXC_XFER_STD(n, hdlr) \ 214 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 215 ret_from_except_full) 216 217#define EXC_XFER_LITE(n, hdlr) \ 218 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 219 ret_from_except) 220 221#define EXC_XFER_EE(n, hdlr) \ 222 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 223 ret_from_except_full) 224 225#define EXC_XFER_EE_LITE(n, hdlr) \ 226 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 227 ret_from_except) 228 229/* System reset */ 230 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) 231 232/* Machine check */ 233 . = 0x200 234MachineCheck: 235 EXCEPTION_PROLOG 236 mfspr r4,SPRN_DAR 237 stw r4,_DAR(r11) 238 li r5,RPN_PATTERN 239 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 240 mfspr r5,SPRN_DSISR 241 stw r5,_DSISR(r11) 242 addi r3,r1,STACK_FRAME_OVERHEAD 243 EXC_XFER_STD(0x200, machine_check_exception) 244 245/* Data access exception. 246 * This is "never generated" by the MPC8xx. 247 */ 248 . = 0x300 249DataAccess: 250 251/* Instruction access exception. 252 * This is "never generated" by the MPC8xx. 253 */ 254 . = 0x400 255InstructionAccess: 256 257/* External interrupt */ 258 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 259 260/* Alignment exception */ 261 . = 0x600 262Alignment: 263 EXCEPTION_PROLOG 264 mfspr r4,SPRN_DAR 265 stw r4,_DAR(r11) 266 li r5,RPN_PATTERN 267 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 268 mfspr r5,SPRN_DSISR 269 stw r5,_DSISR(r11) 270 addi r3,r1,STACK_FRAME_OVERHEAD 271 EXC_XFER_EE(0x600, alignment_exception) 272 273/* Program check exception */ 274 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 275 276/* No FPU on MPC8xx. This exception is not supposed to happen. 277*/ 278 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 279 280/* Decrementer */ 281 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 282 283 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 284 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 285 286/* System call */ 287 . = 0xc00 288SystemCall: 289 EXCEPTION_PROLOG 290 EXC_XFER_EE_LITE(0xc00, DoSyscall) 291 292/* Single step - not used on 601 */ 293 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 294 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 295 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 296 297/* On the MPC8xx, this is a software emulation interrupt. It occurs 298 * for all unimplemented and illegal instructions. 299 */ 300 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 301 302 . = 0x1100 303/* 304 * For the MPC8xx, this is a software tablewalk to load the instruction 305 * TLB. The task switch loads the M_TW register with the pointer to the first 306 * level table. 307 * If we discover there is no second level table (value is zero) or if there 308 * is an invalid pte, we load that into the TLB, which causes another fault 309 * into the TLB Error interrupt where we can handle such problems. 310 * We have to use the MD_xxx registers for the tablewalk because the 311 * equivalent MI_xxx registers only perform the attribute functions. 312 */ 313 314#ifdef CONFIG_8xx_CPU15 315#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ 316 addi tmp, addr, PAGE_SIZE; \ 317 tlbie tmp; \ 318 addi tmp, addr, -PAGE_SIZE; \ 319 tlbie tmp 320#else 321#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) 322#endif 323 324InstructionTLBMiss: 325#ifdef CONFIG_8xx_CPU6 326 mtspr SPRN_SPRG_SCRATCH2, r3 327#endif 328 EXCEPTION_PROLOG_0 329 330 /* If we are faulting a kernel address, we have to use the 331 * kernel page tables. 332 */ 333#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC) 334 /* Only modules will cause ITLB Misses as we always 335 * pin the first 8MB of kernel memory */ 336 mfspr r11, SPRN_SRR0 /* Get effective address of fault */ 337 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11) 338 mfcr r10 339 IS_KERNEL(r11, r11) 340 mfspr r11, SPRN_M_TW /* Get level 1 table */ 341 BRANCH_UNLESS_KERNEL(3f) 342 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3433: 344 mtcr r10 345 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 346#else 347 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 348 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) 349 mfspr r11, SPRN_M_TW /* Get level 1 table base address */ 350#endif 351 /* Insert level 1 index */ 352 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 353 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 354 355 /* Extract level 2 index */ 356 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 357 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 358 lwz r10, 0(r10) /* Get the pte */ 359 360 /* Insert the APG into the TWC from the Linux PTE. */ 361 rlwimi r11, r10, 0, 25, 26 362 /* Load the MI_TWC with the attributes for this "segment." */ 363 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */ 364 365#ifdef CONFIG_SWAP 366 rlwinm r11, r10, 32-5, _PAGE_PRESENT 367 and r11, r11, r10 368 rlwimi r10, r11, 0, _PAGE_PRESENT 369#endif 370 li r11, RPN_PATTERN 371 /* The Linux PTE won't go exactly into the MMU TLB. 372 * Software indicator bits 20-23 and 28 must be clear. 373 * Software indicator bits 24, 25, 26, and 27 must be 374 * set. All other Linux PTE bits control the behavior 375 * of the MMU. 376 */ 377 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */ 378 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */ 379 380 /* Restore registers */ 381#ifdef CONFIG_8xx_CPU6 382 mfspr r3, SPRN_SPRG_SCRATCH2 383#endif 384 EXCEPTION_EPILOG_0 385 rfi 386 387/* 388 * Bottom part of DataStoreTLBMiss handler for IMMR area 389 * not enough space in the DataStoreTLBMiss area 390 */ 391DTLBMissIMMR: 392 mtcr r10 393 /* Set 512k byte guarded page and mark it valid */ 394 li r10, MD_PS512K | MD_GUARDED | MD_SVALID 395 MTSPR_CPU6(SPRN_MD_TWC, r10, r11) 396 mfspr r10, SPRN_IMMR /* Get current IMMR */ 397 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */ 398 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 399 _PAGE_PRESENT | _PAGE_NO_CACHE 400 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 401 402 li r11, RPN_PATTERN 403 mtspr SPRN_DAR, r11 /* Tag DAR */ 404 EXCEPTION_EPILOG_0 405 rfi 406 407 . = 0x1200 408DataStoreTLBMiss: 409 EXCEPTION_PROLOG_0 410 mfcr r10 411 412 /* If we are faulting a kernel address, we have to use the 413 * kernel page tables. 414 */ 415 mfspr r11, SPRN_MD_EPN 416 rlwinm r11, r11, 16, 0xfff8 417#ifndef CONFIG_PIN_TLB_IMMR 418 cmpli cr0, r11, VIRT_IMMR_BASE@h 419#endif 420 cmpli cr7, r11, PAGE_OFFSET@h 421#ifndef CONFIG_PIN_TLB_IMMR 422_ENTRY(DTLBMiss_jmp) 423 beq- DTLBMissIMMR 424#endif 425 bge- cr7, 4f 426 427 mfspr r11, SPRN_M_TW /* Get level 1 table */ 4283: 429 mtcr r10 430#ifdef CONFIG_8xx_CPU6 431 mtspr SPRN_SPRG_SCRATCH2, r3 432#endif 433 mfspr r10, SPRN_MD_EPN 434 435 /* Insert level 1 index */ 436 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 437 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 438 439 /* We have a pte table, so load fetch the pte from the table. 440 */ 441 /* Extract level 2 index */ 442 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 443 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 444 lwz r10, 0(r10) /* Get the pte */ 445 446 /* Insert the Guarded flag and APG into the TWC from the Linux PTE. 447 * It is bit 26-27 of both the Linux PTE and the TWC (at least 448 * I got that right :-). It will be better when we can put 449 * this into the Linux pgd/pmd and load it in the operation 450 * above. 451 */ 452 rlwimi r11, r10, 0, 26, 27 453 /* Insert the WriteThru flag into the TWC from the Linux PTE. 454 * It is bit 25 in the Linux PTE and bit 30 in the TWC 455 */ 456 rlwimi r11, r10, 32-5, 30, 30 457 MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 458 459 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 460 * We also need to know if the insn is a load/store, so: 461 * Clear _PAGE_PRESENT and load that which will 462 * trap into DTLB Error with store bit set accordinly. 463 */ 464 /* PRESENT=0x1, ACCESSED=0x20 465 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 466 * r10 = (r10 & ~PRESENT) | r11; 467 */ 468#ifdef CONFIG_SWAP 469 rlwinm r11, r10, 32-5, _PAGE_PRESENT 470 and r11, r11, r10 471 rlwimi r10, r11, 0, _PAGE_PRESENT 472#endif 473 /* The Linux PTE won't go exactly into the MMU TLB. 474 * Software indicator bits 22 and 28 must be clear. 475 * Software indicator bits 24, 25, 26, and 27 must be 476 * set. All other Linux PTE bits control the behavior 477 * of the MMU. 478 */ 479 li r11, RPN_PATTERN 480 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 481 rlwimi r10, r11, 0, 20, 20 /* clear 20 */ 482 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ 483 484 /* Restore registers */ 485#ifdef CONFIG_8xx_CPU6 486 mfspr r3, SPRN_SPRG_SCRATCH2 487#endif 488 mtspr SPRN_DAR, r11 /* Tag DAR */ 489 EXCEPTION_EPILOG_0 490 rfi 491 4924: 493_ENTRY(DTLBMiss_cmp) 494 cmpli cr0, r11, (PAGE_OFFSET + 0x1800000)@h 495 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 496 bge- 3b 497 498 mtcr r10 499 /* Set 8M byte page and mark it valid */ 500 li r10, MD_PS8MEG | MD_SVALID 501 MTSPR_CPU6(SPRN_MD_TWC, r10, r11) 502 mfspr r10, SPRN_MD_EPN 503 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 504 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 505 _PAGE_PRESENT 506 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 507 508 li r11, RPN_PATTERN 509 mtspr SPRN_DAR, r11 /* Tag DAR */ 510 EXCEPTION_EPILOG_0 511 rfi 512 513 514/* This is an instruction TLB error on the MPC8xx. This could be due 515 * to many reasons, such as executing guarded memory or illegal instruction 516 * addresses. There is nothing to do but handle a big time error fault. 517 */ 518 . = 0x1300 519InstructionTLBError: 520 EXCEPTION_PROLOG 521 mr r4,r12 522 mr r5,r9 523 andis. r10,r5,0x4000 524 beq+ 1f 525 tlbie r4 526 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 5271: EXC_XFER_LITE(0x400, handle_page_fault) 528 529/* This is the data TLB error on the MPC8xx. This could be due to 530 * many reasons, including a dirty update to a pte. We bail out to 531 * a higher level function that can handle it. 532 */ 533 . = 0x1400 534DataTLBError: 535 EXCEPTION_PROLOG_0 536 mfcr r10 537 538 mfspr r11, SPRN_DAR 539 cmpwi cr0, r11, RPN_PATTERN 540 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 541DARFixed:/* Return from dcbx instruction bug workaround */ 542 EXCEPTION_PROLOG_1 543 EXCEPTION_PROLOG_2 544 mfspr r5,SPRN_DSISR 545 stw r5,_DSISR(r11) 546 mfspr r4,SPRN_DAR 547 andis. r10,r5,0x4000 548 beq+ 1f 549 tlbie r4 5501: li r10,RPN_PATTERN 551 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 552 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 553 EXC_XFER_LITE(0x300, handle_page_fault) 554 555 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 556 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 557 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 558 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 559 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 560 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 561 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 562 563/* On the MPC8xx, these next four traps are used for development 564 * support of breakpoints and such. Someday I will get around to 565 * using them. 566 */ 567 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 568 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 569 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 570 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 571 572 . = 0x2000 573 574/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 575 * by decoding the registers used by the dcbx instruction and adding them. 576 * DAR is set to the calculated address. 577 */ 578 /* define if you don't want to use self modifying code */ 579#define NO_SELF_MODIFYING_CODE 580FixupDAR:/* Entry point for dcbx workaround. */ 581 mtspr SPRN_SPRG_SCRATCH2, r10 582 /* fetch instruction from memory. */ 583 mfspr r10, SPRN_SRR0 584 IS_KERNEL(r11, r10) 585 mfspr r11, SPRN_M_TW /* Get level 1 table */ 586 BRANCH_UNLESS_KERNEL(3f) 587 rlwinm r11, r10, 16, 0xfff8 588_ENTRY(FixupDAR_cmp) 589 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 590 blt- cr7, 200f 591 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 592 /* Insert level 1 index */ 5933: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 594 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 595 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */ 596 /* Insert level 2 index */ 597 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 598 lwz r11, 0(r11) /* Get the pte */ 599 /* concat physical page address(r11) and page offset(r10) */ 600 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 601201: lwz r11,0(r11) 602/* Check if it really is a dcbx instruction. */ 603/* dcbt and dcbtst does not generate DTLB Misses/Errors, 604 * no need to include them here */ 605 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 606 rlwinm r10, r10, 0, 21, 5 607 cmpwi cr0, r10, 2028 /* Is dcbz? */ 608 beq+ 142f 609 cmpwi cr0, r10, 940 /* Is dcbi? */ 610 beq+ 142f 611 cmpwi cr0, r10, 108 /* Is dcbst? */ 612 beq+ 144f /* Fix up store bit! */ 613 cmpwi cr0, r10, 172 /* Is dcbf? */ 614 beq+ 142f 615 cmpwi cr0, r10, 1964 /* Is icbi? */ 616 beq+ 142f 617141: mfspr r10,SPRN_SPRG_SCRATCH2 618 b DARFixed /* Nope, go back to normal TLB processing */ 619 620 /* create physical page address from effective address */ 621200: tophys(r11, r10) 622 b 201b 623 624144: mfspr r10, SPRN_DSISR 625 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 626 mtspr SPRN_DSISR, r10 627142: /* continue, it was a dcbx, dcbi instruction. */ 628#ifndef NO_SELF_MODIFYING_CODE 629 andis. r10,r11,0x1f /* test if reg RA is r0 */ 630 li r10,modified_instr@l 631 dcbtst r0,r10 /* touch for store */ 632 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 633 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 634 ori r11,r11,532 635 stw r11,0(r10) /* store add/and instruction */ 636 dcbf 0,r10 /* flush new instr. to memory. */ 637 icbi 0,r10 /* invalidate instr. cache line */ 638 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */ 639 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */ 640 isync /* Wait until new instr is loaded from memory */ 641modified_instr: 642 .space 4 /* this is where the add instr. is stored */ 643 bne+ 143f 644 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 645143: mtdar r10 /* store faulting EA in DAR */ 646 mfspr r10,SPRN_SPRG_SCRATCH2 647 b DARFixed /* Go back to normal TLB handling */ 648#else 649 mfctr r10 650 mtdar r10 /* save ctr reg in DAR */ 651 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 652 addi r10, r10, 150f@l /* add start of table */ 653 mtctr r10 /* load ctr with jump address */ 654 xor r10, r10, r10 /* sum starts at zero */ 655 bctr /* jump into table */ 656150: 657 add r10, r10, r0 ;b 151f 658 add r10, r10, r1 ;b 151f 659 add r10, r10, r2 ;b 151f 660 add r10, r10, r3 ;b 151f 661 add r10, r10, r4 ;b 151f 662 add r10, r10, r5 ;b 151f 663 add r10, r10, r6 ;b 151f 664 add r10, r10, r7 ;b 151f 665 add r10, r10, r8 ;b 151f 666 add r10, r10, r9 ;b 151f 667 mtctr r11 ;b 154f /* r10 needs special handling */ 668 mtctr r11 ;b 153f /* r11 needs special handling */ 669 add r10, r10, r12 ;b 151f 670 add r10, r10, r13 ;b 151f 671 add r10, r10, r14 ;b 151f 672 add r10, r10, r15 ;b 151f 673 add r10, r10, r16 ;b 151f 674 add r10, r10, r17 ;b 151f 675 add r10, r10, r18 ;b 151f 676 add r10, r10, r19 ;b 151f 677 add r10, r10, r20 ;b 151f 678 add r10, r10, r21 ;b 151f 679 add r10, r10, r22 ;b 151f 680 add r10, r10, r23 ;b 151f 681 add r10, r10, r24 ;b 151f 682 add r10, r10, r25 ;b 151f 683 add r10, r10, r26 ;b 151f 684 add r10, r10, r27 ;b 151f 685 add r10, r10, r28 ;b 151f 686 add r10, r10, r29 ;b 151f 687 add r10, r10, r30 ;b 151f 688 add r10, r10, r31 689151: 690 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 691 beq 152f /* if reg RA is zero, don't add it */ 692 addi r11, r11, 150b@l /* add start of table */ 693 mtctr r11 /* load ctr with jump address */ 694 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 695 bctr /* jump into table */ 696152: 697 mfdar r11 698 mtctr r11 /* restore ctr reg from DAR */ 699 mtdar r10 /* save fault EA to DAR */ 700 mfspr r10,SPRN_SPRG_SCRATCH2 701 b DARFixed /* Go back to normal TLB handling */ 702 703 /* special handling for r10,r11 since these are modified already */ 704153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 705 add r10, r10, r11 /* add it */ 706 mfctr r11 /* restore r11 */ 707 b 151b 708154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 709 add r10, r10, r11 /* add it */ 710 mfctr r11 /* restore r11 */ 711 b 151b 712#endif 713 714/* 715 * This is where the main kernel code starts. 716 */ 717start_here: 718 /* ptr to current */ 719 lis r2,init_task@h 720 ori r2,r2,init_task@l 721 722 /* ptr to phys current thread */ 723 tophys(r4,r2) 724 addi r4,r4,THREAD /* init task's THREAD */ 725 mtspr SPRN_SPRG_THREAD,r4 726 727 /* stack */ 728 lis r1,init_thread_union@ha 729 addi r1,r1,init_thread_union@l 730 li r0,0 731 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 732 733 bl early_init /* We have to do this with MMU on */ 734 735/* 736 * Decide what sort of machine this is and initialize the MMU. 737 */ 738 li r3,0 739 mr r4,r31 740 bl machine_init 741 bl MMU_init 742 743/* 744 * Go back to running unmapped so we can load up new values 745 * and change to using our exception vectors. 746 * On the 8xx, all we have to do is invalidate the TLB to clear 747 * the old 8M byte TLB mappings and load the page table base register. 748 */ 749 /* The right way to do this would be to track it down through 750 * init's THREAD like the context switch code does, but this is 751 * easier......until someone changes init's static structures. 752 */ 753 lis r6, swapper_pg_dir@ha 754 tophys(r6,r6) 755#ifdef CONFIG_8xx_CPU6 756 lis r4, cpu6_errata_word@h 757 ori r4, r4, cpu6_errata_word@l 758 li r3, 0x3f80 759 stw r3, 12(r4) 760 lwz r3, 12(r4) 761#endif 762 mtspr SPRN_M_TW, r6 763 lis r4,2f@h 764 ori r4,r4,2f@l 765 tophys(r4,r4) 766 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 767 mtspr SPRN_SRR0,r4 768 mtspr SPRN_SRR1,r3 769 rfi 770/* Load up the kernel context */ 7712: 772 SYNC /* Force all PTE updates to finish */ 773 tlbia /* Clear all TLB entries */ 774 sync /* wait for tlbia/tlbie to finish */ 775 TLBSYNC /* ... on all CPUs */ 776 777 /* set up the PTE pointers for the Abatron bdiGDB. 778 */ 779 tovirt(r6,r6) 780 lis r5, abatron_pteptrs@h 781 ori r5, r5, abatron_pteptrs@l 782 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 783 tophys(r5,r5) 784 stw r6, 0(r5) 785 786/* Now turn on the MMU for real! */ 787 li r4,MSR_KERNEL 788 lis r3,start_kernel@h 789 ori r3,r3,start_kernel@l 790 mtspr SPRN_SRR0,r3 791 mtspr SPRN_SRR1,r4 792 rfi /* enable MMU and jump to start_kernel */ 793 794/* Set up the initial MMU state so we can do the first level of 795 * kernel initialization. This maps the first 8 MBytes of memory 1:1 796 * virtual to physical. Also, set the cache mode since that is defined 797 * by TLB entries and perform any additional mapping (like of the IMMR). 798 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 799 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 800 * these mappings is mapped by page tables. 801 */ 802initial_mmu: 803 li r8, 0 804 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 805 lis r10, MD_RESETVAL@h 806#ifndef CONFIG_8xx_COPYBACK 807 oris r10, r10, MD_WTDEF@h 808#endif 809 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 810 811 tlbia /* Invalidate all TLB entries */ 812/* Always pin the first 8 MB ITLB to prevent ITLB 813 misses while mucking around with SRR0/SRR1 in asm 814*/ 815 lis r8, MI_RSV4I@h 816 ori r8, r8, 0x1c00 817 818 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 819 820#ifdef CONFIG_PIN_TLB 821 oris r10, r10, MD_RSV4I@h 822 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 823#endif 824 825 /* Now map the lower 8 Meg into the ITLB. */ 826 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 827 ori r8, r8, MI_EVALID /* Mark it valid */ 828 mtspr SPRN_MI_EPN, r8 829 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */ 830 ori r8, r8, MI_SVALID /* Make it valid */ 831 mtspr SPRN_MI_TWC, r8 832 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 833 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 834 835 lis r8, MI_APG_INIT@h /* Set protection modes */ 836 ori r8, r8, MI_APG_INIT@l 837 mtspr SPRN_MI_AP, r8 838 lis r8, MD_APG_INIT@h 839 ori r8, r8, MD_APG_INIT@l 840 mtspr SPRN_MD_AP, r8 841 842 /* Map a 512k page for the IMMR to get the processor 843 * internal registers (among other things). 844 */ 845#ifdef CONFIG_PIN_TLB_IMMR 846 ori r10, r10, 0x1c00 847 mtspr SPRN_MD_CTR, r10 848 849 mfspr r9, 638 /* Get current IMMR */ 850 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */ 851 852 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */ 853 ori r8, r8, MD_EVALID /* Mark it valid */ 854 mtspr SPRN_MD_EPN, r8 855 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */ 856 ori r8, r8, MD_SVALID /* Make it valid */ 857 mtspr SPRN_MD_TWC, r8 858 mr r8, r9 /* Create paddr for TLB */ 859 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 860 mtspr SPRN_MD_RPN, r8 861#endif 862 863 /* Since the cache is enabled according to the information we 864 * just loaded into the TLB, invalidate and enable the caches here. 865 * We should probably check/set other modes....later. 866 */ 867 lis r8, IDC_INVALL@h 868 mtspr SPRN_IC_CST, r8 869 mtspr SPRN_DC_CST, r8 870 lis r8, IDC_ENABLE@h 871 mtspr SPRN_IC_CST, r8 872#ifdef CONFIG_8xx_COPYBACK 873 mtspr SPRN_DC_CST, r8 874#else 875 /* For a debug option, I left this here to easily enable 876 * the write through cache mode 877 */ 878 lis r8, DC_SFWT@h 879 mtspr SPRN_DC_CST, r8 880 lis r8, IDC_ENABLE@h 881 mtspr SPRN_DC_CST, r8 882#endif 883 blr 884 885 886/* 887 * We put a few things here that have to be page-aligned. 888 * This stuff goes at the beginning of the data segment, 889 * which is page-aligned. 890 */ 891 .data 892 .globl sdata 893sdata: 894 .globl empty_zero_page 895 .align PAGE_SHIFT 896empty_zero_page: 897 .space PAGE_SIZE 898 899 .globl swapper_pg_dir 900swapper_pg_dir: 901 .space PGD_TABLE_SIZE 902 903/* Room for two PTE table poiners, usually the kernel and current user 904 * pointer to their respective root page table (pgdir). 905 */ 906abatron_pteptrs: 907 .space 8 908 909#ifdef CONFIG_8xx_CPU6 910 .globl cpu6_errata_word 911cpu6_errata_word: 912 .space 16 913#endif 914 915