1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * 6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8 * Adapted for Power Macintosh by Paul Mackerras. 9 * Low-level exception handlers and MMU support 10 * rewritten by Paul Mackerras. 11 * Copyright (C) 1996 Paul Mackerras. 12 * 13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 15 * 16 * This file contains the entry point for the 64-bit kernel along 17 * with some early initialization code common to all 64-bit powerpc 18 * variants. 19 */ 20 21#include <linux/linkage.h> 22#include <linux/threads.h> 23#include <linux/init.h> 24#include <asm/reg.h> 25#include <asm/page.h> 26#include <asm/mmu.h> 27#include <asm/ppc_asm.h> 28#include <asm/head-64.h> 29#include <asm/asm-offsets.h> 30#include <asm/bug.h> 31#include <asm/cputable.h> 32#include <asm/setup.h> 33#include <asm/hvcall.h> 34#include <asm/thread_info.h> 35#include <asm/firmware.h> 36#include <asm/page_64.h> 37#include <asm/irqflags.h> 38#include <asm/kvm_book3s_asm.h> 39#include <asm/ptrace.h> 40#include <asm/hw_irq.h> 41#include <asm/cputhreads.h> 42#include <asm/ppc-opcode.h> 43#include <asm/feature-fixups.h> 44#ifdef CONFIG_PPC_BOOK3S 45#include <asm/exception-64s.h> 46#else 47#include <asm/exception-64e.h> 48#endif 49 50/* The physical memory is laid out such that the secondary processor 51 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 52 * using the layout described in exceptions-64s.S 53 */ 54 55/* 56 * Entering into this code we make the following assumptions: 57 * 58 * For pSeries or server processors: 59 * 1. The MMU is off & open firmware is running in real mode. 60 * 2. The primary CPU enters at __start. 61 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary 62 * CPUs will enter as directed by "start-cpu" RTAS call, which is 63 * generic_secondary_smp_init, with PIR in r3. 64 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as 65 * directed by the "start-cpu" RTS call, with PIR in r3. 66 * -or- For OPAL entry: 67 * 1. The MMU is off, processor in HV mode. 68 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base 69 * in r8, and entry in r9 for debugging purposes. 70 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which 71 * is at generic_secondary_smp_init, with PIR in r3. 72 * 73 * For Book3E processors: 74 * 1. The MMU is on running in AS0 in a state defined in ePAPR 75 * 2. The kernel is entered at __start 76 */ 77 78/* 79 * boot_from_prom and prom_init run at the physical address. Everything 80 * after prom and kexec entry run at the virtual address (PAGE_OFFSET). 81 * Secondaries run at the virtual address from generic_secondary_common_init 82 * onward. 83 */ 84 85OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) 86USE_FIXED_SECTION(first_256B) 87 /* 88 * Offsets are relative from the start of fixed section, and 89 * first_256B starts at 0. Offsets are a bit easier to use here 90 * than the fixed section entry macros. 91 */ 92 . = 0x0 93_GLOBAL(__start) 94 /* NOP this out unconditionally */ 95BEGIN_FTR_SECTION 96 FIXUP_ENDIAN 97 b __start_initialization_multiplatform 98END_FTR_SECTION(0, 1) 99 100 /* Catch branch to 0 in real mode */ 101 trap 102 103 /* Secondary processors spin on this value until it becomes non-zero. 104 * When non-zero, it contains the real address of the function the cpu 105 * should jump to. 106 */ 107 .balign 8 108 .globl __secondary_hold_spinloop 109__secondary_hold_spinloop: 110 .8byte 0x0 111 112 /* Secondary processors write this value with their cpu # */ 113 /* after they enter the spin loop immediately below. */ 114 .globl __secondary_hold_acknowledge 115__secondary_hold_acknowledge: 116 .8byte 0x0 117 118#ifdef CONFIG_RELOCATABLE 119 /* This flag is set to 1 by a loader if the kernel should run 120 * at the loaded address instead of the linked address. This 121 * is used by kexec-tools to keep the kdump kernel in the 122 * crash_kernel region. The loader is responsible for 123 * observing the alignment requirement. 124 */ 125 126#ifdef CONFIG_RELOCATABLE_TEST 127#define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */ 128#else 129#define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */ 130#endif 131 132 /* Do not move this variable as kexec-tools knows about it. */ 133 . = 0x5c 134 .globl __run_at_load 135__run_at_load: 136DEFINE_FIXED_SYMBOL(__run_at_load, first_256B) 137 .long RUN_AT_LOAD_DEFAULT 138#endif 139 140 . = 0x60 141/* 142 * The following code is used to hold secondary processors 143 * in a spin loop after they have entered the kernel, but 144 * before the bulk of the kernel has been relocated. This code 145 * is relocated to physical address 0x60 before prom_init is run. 146 * All of it must fit below the first exception vector at 0x100. 147 * Use .globl here not _GLOBAL because we want __secondary_hold 148 * to be the actual text address, not a descriptor. 149 */ 150 .globl __secondary_hold 151__secondary_hold: 152 FIXUP_ENDIAN 153#ifndef CONFIG_PPC_BOOK3E_64 154 mfmsr r24 155 ori r24,r24,MSR_RI 156 mtmsrd r24 /* RI on */ 157#endif 158 /* Grab our physical cpu number */ 159 mr r24,r3 160 /* stash r4 for book3e */ 161 mr r25,r4 162 163 /* Tell the master cpu we're here */ 164 /* Relocation is off & we are located at an address less */ 165 /* than 0x100, so only need to grab low order offset. */ 166 std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0) 167 sync 168 169 /* All secondary cpus wait here until told to start. */ 170100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(0) 171 cmpdi 0,r12,0 172 beq 100b 173 174#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 175#ifdef CONFIG_PPC_BOOK3E_64 176 tovirt(r12,r12) 177#endif 178 mtctr r12 179 mr r3,r24 180 /* 181 * it may be the case that other platforms have r4 right to 182 * begin with, this gives us some safety in case it is not 183 */ 184#ifdef CONFIG_PPC_BOOK3E_64 185 mr r4,r25 186#else 187 li r4,0 188#endif 189 /* Make sure that patched code is visible */ 190 isync 191 bctr 192#else 1930: trap 194 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 195#endif 196CLOSE_FIXED_SECTION(first_256B) 197 198/* 199 * On server, we include the exception vectors code here as it 200 * relies on absolute addressing which is only possible within 201 * this compilation unit 202 */ 203#ifdef CONFIG_PPC_BOOK3S 204#include "exceptions-64s.S" 205#else 206OPEN_TEXT_SECTION(0x100) 207#endif 208 209USE_TEXT_SECTION() 210 211#include "interrupt_64.S" 212 213#ifdef CONFIG_PPC_BOOK3E_64 214/* 215 * The booting_thread_hwid holds the thread id we want to boot in cpu 216 * hotplug case. It is set by cpu hotplug code, and is invalid by default. 217 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] 218 * bit field. 219 */ 220 .globl booting_thread_hwid 221booting_thread_hwid: 222 .long INVALID_THREAD_HWID 223 .align 3 224/* 225 * start a thread in the same core 226 * input parameters: 227 * r3 = the thread physical id 228 * r4 = the entry point where thread starts 229 */ 230_GLOBAL(book3e_start_thread) 231 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) 232 cmpwi r3, 0 233 beq 10f 234 cmpwi r3, 1 235 beq 11f 236 /* If the thread id is invalid, just exit. */ 237 b 13f 23810: 239 MTTMR(TMRN_IMSR0, 5) 240 MTTMR(TMRN_INIA0, 4) 241 b 12f 24211: 243 MTTMR(TMRN_IMSR1, 5) 244 MTTMR(TMRN_INIA1, 4) 24512: 246 isync 247 li r6, 1 248 sld r6, r6, r3 249 mtspr SPRN_TENS, r6 25013: 251 blr 252 253/* 254 * stop a thread in the same core 255 * input parameter: 256 * r3 = the thread physical id 257 */ 258_GLOBAL(book3e_stop_thread) 259 cmpwi r3, 0 260 beq 10f 261 cmpwi r3, 1 262 beq 10f 263 /* If the thread id is invalid, just exit. */ 264 b 13f 26510: 266 li r4, 1 267 sld r4, r4, r3 268 mtspr SPRN_TENC, r4 26913: 270 blr 271 272_GLOBAL(fsl_secondary_thread_init) 273 mfspr r4,SPRN_BUCSR 274 275 /* Enable branch prediction */ 276 lis r3,BUCSR_INIT@h 277 ori r3,r3,BUCSR_INIT@l 278 mtspr SPRN_BUCSR,r3 279 isync 280 281 /* 282 * Fix PIR to match the linear numbering in the device tree. 283 * 284 * On e6500, the reset value of PIR uses the low three bits for 285 * the thread within a core, and the upper bits for the core 286 * number. There are two threads per core, so shift everything 287 * but the low bit right by two bits so that the cpu numbering is 288 * continuous. 289 * 290 * If the old value of BUCSR is non-zero, this thread has run 291 * before. Thus, we assume we are coming from kexec or a similar 292 * scenario, and PIR is already set to the correct value. This 293 * is a bit of a hack, but there are limited opportunities for 294 * getting information into the thread and the alternatives 295 * seemed like they'd be overkill. We can't tell just by looking 296 * at the old PIR value which state it's in, since the same value 297 * could be valid for one thread out of reset and for a different 298 * thread in Linux. 299 */ 300 301 mfspr r3, SPRN_PIR 302 cmpwi r4,0 303 bne 1f 304 rlwimi r3, r3, 30, 2, 30 305 mtspr SPRN_PIR, r3 3061: 307 mr r24,r3 308 309 /* turn on 64-bit mode */ 310 bl enable_64b_mode 311 312 /* Book3E initialization */ 313 mr r3,r24 314 bl book3e_secondary_thread_init 315 bl relative_toc 316 317 b generic_secondary_common_init 318 319#endif /* CONFIG_PPC_BOOK3E_64 */ 320 321/* 322 * On pSeries and most other platforms, secondary processors spin 323 * in the following code. 324 * At entry, r3 = this processor's number (physical cpu id) 325 * 326 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 327 * this core already exists (setup via some other mechanism such 328 * as SCOM before entry). 329 */ 330_GLOBAL(generic_secondary_smp_init) 331 FIXUP_ENDIAN 332 333 li r13,0 334 335 /* Poison TOC */ 336 li r2,-1 337 338 mr r24,r3 339 mr r25,r4 340 341 /* turn on 64-bit mode */ 342 bl enable_64b_mode 343 344#ifdef CONFIG_PPC_BOOK3E_64 345 /* Book3E initialization */ 346 mr r3,r24 347 mr r4,r25 348 bl book3e_secondary_core_init 349 /* Now NIA and r2 are relocated to PAGE_OFFSET if not already */ 350/* 351 * After common core init has finished, check if the current thread is the 352 * one we wanted to boot. If not, start the specified thread and stop the 353 * current thread. 354 */ 355 LOAD_REG_ADDR(r4, booting_thread_hwid) 356 lwz r3, 0(r4) 357 li r5, INVALID_THREAD_HWID 358 cmpw r3, r5 359 beq 20f 360 361 /* 362 * The value of booting_thread_hwid has been stored in r3, 363 * so make it invalid. 364 */ 365 stw r5, 0(r4) 366 367 /* 368 * Get the current thread id and check if it is the one we wanted. 369 * If not, start the one specified in booting_thread_hwid and stop 370 * the current thread. 371 */ 372 mfspr r8, SPRN_TIR 373 cmpw r3, r8 374 beq 20f 375 376 /* start the specified thread */ 377 LOAD_REG_ADDR(r5, DOTSYM(fsl_secondary_thread_init)) 378 bl book3e_start_thread 379 380 /* stop the current thread */ 381 mr r3, r8 382 bl book3e_stop_thread 38310: 384 b 10b 38520: 386#else 387 /* Now the MMU is off, can branch to our PAGE_OFFSET address */ 388 bcl 20,31,$+4 3891: mflr r11 390 addi r11,r11,(2f - 1b) 391 tovirt(r11, r11) 392 mtctr r11 393 bctr 3942: 395 bl relative_toc 396#endif 397 398generic_secondary_common_init: 399 /* Set up a paca value for this processor. Since we have the 400 * physical cpu id in r24, we need to search the pacas to find 401 * which logical id maps to our physical one. 402 */ 403#ifndef CONFIG_SMP 404 b kexec_wait /* wait for next kernel if !SMP */ 405#else 406 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */ 407 ld r8,0(r8) /* Get base vaddr of array */ 408#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS) 409 LOAD_REG_IMMEDIATE(r7, NR_CPUS) 410#else 411 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 412 lwz r7,0(r7) /* also the max paca allocated */ 413#endif 414 li r5,0 /* logical cpu id */ 4151: 416 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */ 417 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */ 418 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 419 cmpw r6,r24 /* Compare to our id */ 420 beq 2f 421 addi r5,r5,1 422 cmpw r5,r7 /* Check if more pacas exist */ 423 blt 1b 424 425 mr r3,r24 /* not found, copy phys to r3 */ 426 b kexec_wait /* next kernel might do better */ 427 4282: SET_PACA(r13) 429#ifdef CONFIG_PPC_BOOK3E_64 430 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 431 mtspr SPRN_SPRG_TLB_EXFRAME,r12 432#endif 433 434 /* From now on, r24 is expected to be logical cpuid */ 435 mr r24,r5 436 437 /* Create a temp kernel stack for use before relocation is on. */ 438 ld r1,PACAEMERGSP(r13) 439 subi r1,r1,STACK_FRAME_MIN_SIZE 440 441 /* See if we need to call a cpu state restore handler */ 442 LOAD_REG_ADDR(r23, cur_cpu_spec) 443 ld r23,0(r23) 444 ld r12,CPU_SPEC_RESTORE(r23) 445 cmpdi 0,r12,0 446 beq 3f 447#ifdef CONFIG_PPC64_ELF_ABI_V1 448 ld r12,0(r12) 449#endif 450 mtctr r12 451 bctrl 452 4533: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 454 lwarx r4,0,r3 455 subi r4,r4,1 456 stwcx. r4,0,r3 457 bne 3b 458 isync 459 4604: HMT_LOW 461 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 462 /* start. */ 463 cmpwi 0,r23,0 464 beq 4b /* Loop until told to go */ 465 466 sync /* order paca.run and cur_cpu_spec */ 467 isync /* In case code patching happened */ 468 469 b __secondary_start 470#endif /* SMP */ 471 472/* 473 * Turn the MMU off. 474 * Assumes we're mapped EA == RA if the MMU is on. 475 */ 476#ifdef CONFIG_PPC_BOOK3S 477SYM_FUNC_START_LOCAL(__mmu_off) 478 mfmsr r3 479 andi. r0,r3,MSR_IR|MSR_DR 480 beqlr 481 mflr r4 482 andc r3,r3,r0 483 mtspr SPRN_SRR0,r4 484 mtspr SPRN_SRR1,r3 485 sync 486 rfid 487 b . /* prevent speculative execution */ 488SYM_FUNC_END(__mmu_off) 489 490SYM_FUNC_START_LOCAL(start_initialization_book3s) 491 mflr r25 492 493 /* Setup some critical 970 SPRs before switching MMU off */ 494 mfspr r0,SPRN_PVR 495 srwi r0,r0,16 496 cmpwi r0,0x39 /* 970 */ 497 beq 1f 498 cmpwi r0,0x3c /* 970FX */ 499 beq 1f 500 cmpwi r0,0x44 /* 970MP */ 501 beq 1f 502 cmpwi r0,0x45 /* 970GX */ 503 bne 2f 5041: bl __cpu_preinit_ppc970 5052: 506 507 /* Switch off MMU if not already off */ 508 bl __mmu_off 509 510 /* Now the MMU is off, can return to our PAGE_OFFSET address */ 511 tovirt(r25,r25) 512 mtlr r25 513 blr 514SYM_FUNC_END(start_initialization_book3s) 515#endif 516 517/* 518 * Here is our main kernel entry point. We support currently 2 kind of entries 519 * depending on the value of r5. 520 * 521 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 522 * in r3...r7 523 * 524 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 525 * DT block, r4 is a physical pointer to the kernel itself 526 * 527 */ 528__start_initialization_multiplatform: 529 /* Make sure we are running in 64 bits mode */ 530 bl enable_64b_mode 531 532 /* Zero r13 (paca) so early program check / mce don't use it */ 533 li r13,0 534 535 /* Poison TOC */ 536 li r2,-1 537 538 /* 539 * Are we booted from a PROM Of-type client-interface ? 540 */ 541 cmpldi cr0,r5,0 542 beq 1f 543 b __boot_from_prom /* yes -> prom */ 5441: 545 /* Save parameters */ 546 mr r31,r3 547 mr r30,r4 548#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 549 /* Save OPAL entry */ 550 mr r28,r8 551 mr r29,r9 552#endif 553 554 /* Get TOC pointer (current runtime address) */ 555 bl relative_toc 556 557 /* These functions return to the virtual (PAGE_OFFSET) address */ 558#ifdef CONFIG_PPC_BOOK3E_64 559 bl start_initialization_book3e 560#else 561 bl start_initialization_book3s 562#endif /* CONFIG_PPC_BOOK3E_64 */ 563 564 /* Get TOC pointer, virtual */ 565 bl relative_toc 566 567 /* find out where we are now */ 568 569 /* OPAL doesn't pass base address in r4, have to derive it. */ 570 bcl 20,31,$+4 5710: mflr r26 /* r26 = runtime addr here */ 572 addis r26,r26,(_stext - 0b)@ha 573 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 574 575 b __after_prom_start 576 577__REF 578__boot_from_prom: 579#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 580 /* Get TOC pointer, non-virtual */ 581 bl relative_toc 582 583 /* find out where we are now */ 584 bcl 20,31,$+4 5850: mflr r26 /* r26 = runtime addr here */ 586 addis r26,r26,(_stext - 0b)@ha 587 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 588 589 /* Save parameters */ 590 mr r31,r3 591 mr r30,r4 592 mr r29,r5 593 mr r28,r6 594 mr r27,r7 595 596 /* 597 * Align the stack to 16-byte boundary 598 * Depending on the size and layout of the ELF sections in the initial 599 * boot binary, the stack pointer may be unaligned on PowerMac 600 */ 601 rldicr r1,r1,0,59 602 603#ifdef CONFIG_RELOCATABLE 604 /* Relocate code for where we are now */ 605 mr r3,r26 606 bl relocate 607#endif 608 609 /* Restore parameters */ 610 mr r3,r31 611 mr r4,r30 612 mr r5,r29 613 mr r6,r28 614 mr r7,r27 615 616 /* Do all of the interaction with OF client interface */ 617 mr r8,r26 618 bl CFUNC(prom_init) 619#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 620 621 /* We never return. We also hit that trap if trying to boot 622 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 623 trap 624 .previous 625 626__after_prom_start: 627#ifdef CONFIG_RELOCATABLE 628 /* process relocations for the final address of the kernel */ 629 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 630 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 631 mr r25,r26 /* then use current kernel base */ 632 beq 1f 633 LOAD_REG_IMMEDIATE(r25, PAGE_OFFSET) /* else use static kernel base */ 6341: mr r3,r25 635 bl relocate 636#if defined(CONFIG_PPC_BOOK3E_64) 637 /* IVPR needs to be set after relocation. */ 638 bl init_core_book3e 639#endif 640#endif 641 642/* 643 * We need to run with _stext at physical address PHYSICAL_START. 644 * This will leave some code in the first 256B of 645 * real memory, which are reserved for software use. 646 * 647 * Note: This process overwrites the OF exception vectors. 648 */ 649 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET) 650 mr r4,r26 /* Load the virtual source address into r4 */ 651 cmpld r3,r4 /* Check if source == dest */ 652 beq 9f /* If so skip the copy */ 653 li r6,0x100 /* Start offset, the first 0x100 */ 654 /* bytes were copied earlier. */ 655 656#ifdef CONFIG_RELOCATABLE 657/* 658 * Check if the kernel has to be running as relocatable kernel based on the 659 * variable __run_at_load, if it is set the kernel is treated as relocatable 660 * kernel, otherwise it will be moved to PHYSICAL_START 661 */ 662 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 663 cmplwi cr0,r7,1 664 bne 3f 665 666#ifdef CONFIG_PPC_BOOK3E_64 667 LOAD_REG_ADDR(r5, __end_interrupts) 668 LOAD_REG_ADDR(r11, _stext) 669 sub r5,r5,r11 670#else 671 /* just copy interrupts */ 672 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) 673#endif 674 b 5f 6753: 676#endif 677 /* # bytes of memory to copy */ 678 lis r5,(ABS_ADDR(copy_to_here, text))@ha 679 addi r5,r5,(ABS_ADDR(copy_to_here, text))@l 680 681 bl copy_and_flush /* copy the first n bytes */ 682 /* this includes the code being */ 683 /* executed here. */ 684 /* Jump to the copy of this code that we just made */ 685 addis r8,r3,(ABS_ADDR(4f, text))@ha 686 addi r12,r8,(ABS_ADDR(4f, text))@l 687 mtctr r12 688 bctr 689 690.balign 8 691p_end: .8byte _end - copy_to_here 692 6934: 694 /* 695 * Now copy the rest of the kernel up to _end, add 696 * _end - copy_to_here to the copy limit and run again. 697 */ 698 addis r8,r26,(ABS_ADDR(p_end, text))@ha 699 ld r8,(ABS_ADDR(p_end, text))@l(r8) 700 add r5,r5,r8 7015: bl copy_and_flush /* copy the rest */ 702 7039: b start_here_multiplatform 704 705/* 706 * Copy routine used to copy the kernel to start at physical address 0 707 * and flush and invalidate the caches as needed. 708 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 709 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 710 * 711 * Note: this routine *only* clobbers r0, r6 and lr 712 */ 713_GLOBAL(copy_and_flush) 714 addi r5,r5,-8 715 addi r6,r6,-8 7164: li r0,8 /* r0 is the number of 8-byte words */ 717 /* to copy per cache sync iteration. */ 718 /* 8 words * 8 bytes = 64 bytes. 64B is */ 719 /* the current default cache line size. */ 720 /* This is a loop count, not a byte */ 721 /* count. Increasing it may skip */ 722 /* dcbst/icbi for lines in between and */ 723 /* leave stale instructions in icache. */ 724 /* This results in extra cache line */ 725 /* flushes but operation is correct. */ 726 /* Can't get cache line size from NACA */ 727 /* as it is being moved too. */ 728 729 mtctr r0 /* put # words/line in ctr */ 7303: addi r6,r6,8 /* copy a cache line */ 731 ldx r0,r6,r4 732 stdx r0,r6,r3 733 bdnz 3b 734 dcbst r6,r3 /* write it to memory */ 735 sync 736 icbi r6,r3 /* flush the icache line */ 737 cmpld 0,r6,r5 738 blt 4b 739 sync 740 addi r5,r5,8 741 addi r6,r6,8 742 isync 743 blr 744 745_ASM_NOKPROBE_SYMBOL(copy_and_flush); /* Called in real mode */ 746 747.align 8 748copy_to_here: 749 750#ifdef CONFIG_SMP 751#ifdef CONFIG_PPC_PMAC 752/* 753 * On PowerMac, secondary processors starts from the reset vector, which 754 * is temporarily turned into a call to one of the functions below. 755 */ 756 .section ".text"; 757 .align 2 ; 758 759 .globl __secondary_start_pmac_0 760__secondary_start_pmac_0: 761 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 762 li r24,0 763 b 1f 764 li r24,1 765 b 1f 766 li r24,2 767 b 1f 768 li r24,3 7691: 770 771_GLOBAL(pmac_secondary_start) 772 /* turn on 64-bit mode */ 773 bl enable_64b_mode 774 775 li r0,0 776 mfspr r3,SPRN_HID4 777 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 778 sync 779 mtspr SPRN_HID4,r3 780 isync 781 sync 782 slbia 783 784 /* Branch to our PAGE_OFFSET address */ 785 bcl 20,31,$+4 7861: mflr r11 787 addi r11,r11,(2f - 1b) 788 tovirt(r11, r11) 789 mtctr r11 790 bctr 7912: 792 bl relative_toc 793 794 /* Copy some CPU settings from CPU 0 */ 795 bl __restore_cpu_ppc970 796 797 /* pSeries do that early though I don't think we really need it */ 798 mfmsr r3 799 ori r3,r3,MSR_RI 800 mtmsrd r3 /* RI on */ 801 802 /* Set up a paca value for this processor. */ 803 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */ 804 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */ 805 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */ 806 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */ 807 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 808 809 /* Mark interrupts soft and hard disabled (they might be enabled 810 * in the PACA when doing hotplug) 811 */ 812 li r0,IRQS_DISABLED 813 stb r0,PACAIRQSOFTMASK(r13) 814 li r0,PACA_IRQ_HARD_DIS 815 stb r0,PACAIRQHAPPENED(r13) 816 817 /* Create a temp kernel stack for use before relocation is on. */ 818 ld r1,PACAEMERGSP(r13) 819 subi r1,r1,STACK_FRAME_MIN_SIZE 820 821 b __secondary_start 822 823#endif /* CONFIG_PPC_PMAC */ 824 825/* 826 * This function is called after the master CPU has released the 827 * secondary processors. The execution environment is relocation off. 828 * The paca for this processor has the following fields initialized at 829 * this point: 830 * 1. Processor number 831 * 2. Segment table pointer (virtual address) 832 * On entry the following are set: 833 * r1 = stack pointer (real addr of temp stack) 834 * r24 = cpu# (in Linux terms) 835 * r13 = paca virtual address 836 * SPRG_PACA = paca virtual address 837 */ 838 .section ".text"; 839 .align 2 ; 840 841 .globl __secondary_start 842__secondary_start: 843 /* Set thread priority to MEDIUM */ 844 HMT_MEDIUM 845 846 /* 847 * Do early setup for this CPU, in particular initialising the MMU so we 848 * can turn it on below. This is a call to C, which is OK, we're still 849 * running on the emergency stack. 850 */ 851 bl CFUNC(early_setup_secondary) 852 853 /* 854 * The primary has initialized our kernel stack for us in the paca, grab 855 * it and put it in r1. We must *not* use it until we turn on the MMU 856 * below, because it may not be inside the RMO. 857 */ 858 ld r1, PACAKSAVE(r13) 859 860 /* Clear backchain so we get nice backtraces */ 861 li r7,0 862 mtlr r7 863 864 /* Mark interrupts soft and hard disabled (they might be enabled 865 * in the PACA when doing hotplug) 866 */ 867 li r7,IRQS_DISABLED 868 stb r7,PACAIRQSOFTMASK(r13) 869 li r0,PACA_IRQ_HARD_DIS 870 stb r0,PACAIRQHAPPENED(r13) 871 872 /* enable MMU and jump to start_secondary */ 873 LOAD_REG_ADDR(r3, start_secondary_prolog) 874 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 875 876 mtspr SPRN_SRR0,r3 877 mtspr SPRN_SRR1,r4 878 RFI_TO_KERNEL 879 b . /* prevent speculative execution */ 880 881/* 882 * Running with relocation on at this point. All we want to do is 883 * zero the stack back-chain pointer and get the TOC virtual address 884 * before going into C code. 885 */ 886start_secondary_prolog: 887 LOAD_PACA_TOC() 888 li r3,0 889 std r3,0(r1) /* Zero the stack frame pointer */ 890 bl CFUNC(start_secondary) 891 b . 892/* 893 * Reset stack pointer and call start_secondary 894 * to continue with online operation when woken up 895 * from cede in cpu offline. 896 */ 897_GLOBAL(start_secondary_resume) 898 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 899 li r3,0 900 std r3,0(r1) /* Zero the stack frame pointer */ 901 bl CFUNC(start_secondary) 902 b . 903#endif 904 905/* 906 * This subroutine clobbers r11 and r12 907 */ 908SYM_FUNC_START_LOCAL(enable_64b_mode) 909 mfmsr r11 /* grab the current MSR */ 910#ifdef CONFIG_PPC_BOOK3E_64 911 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 912 mtmsr r11 913#else /* CONFIG_PPC_BOOK3E_64 */ 914 LOAD_REG_IMMEDIATE(r12, MSR_64BIT) 915 or r11,r11,r12 916 mtmsrd r11 917 isync 918#endif 919 blr 920SYM_FUNC_END(enable_64b_mode) 921 922/* 923 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 924 * by the toolchain). It computes the correct value for wherever we 925 * are running at the moment, using position-independent code. 926 * 927 * Note: The compiler constructs pointers using offsets from the 928 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 929 * the MMU is on we need our TOC to be a virtual address otherwise 930 * these pointers will be real addresses which may get stored and 931 * accessed later with the MMU on. We branch to the virtual address 932 * while still in real mode then call relative_toc again to handle 933 * this. 934 */ 935_GLOBAL(relative_toc) 936#ifdef CONFIG_PPC_KERNEL_PCREL 937 tdnei r2,-1 938 blr 939#else 940 mflr r0 941 bcl 20,31,$+4 9420: mflr r11 943 ld r2,(p_toc - 0b)(r11) 944 add r2,r2,r11 945 mtlr r0 946 blr 947 948.balign 8 949p_toc: .8byte .TOC. - 0b 950#endif 951 952/* 953 * This is where the main kernel code starts. 954 */ 955__REF 956start_here_multiplatform: 957 /* Adjust TOC for moved kernel. Could adjust when moving it instead. */ 958 bl relative_toc 959 960 /* Clear out the BSS. It may have been done in prom_init, 961 * already but that's irrelevant since prom_init will soon 962 * be detached from the kernel completely. Besides, we need 963 * to clear it now for kexec-style entry. 964 */ 965 LOAD_REG_ADDR(r11,__bss_stop) 966 LOAD_REG_ADDR(r8,__bss_start) 967 sub r11,r11,r8 /* bss size */ 968 addi r11,r11,7 /* round up to an even double word */ 969 srdi. r11,r11,3 /* shift right by 3 */ 970 beq 4f 971 addi r8,r8,-8 972 li r0,0 973 mtctr r11 /* zero this many doublewords */ 9743: stdu r0,8(r8) 975 bdnz 3b 9764: 977 978#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 979 /* Setup OPAL entry */ 980 LOAD_REG_ADDR(r11, opal) 981 std r28,0(r11); 982 std r29,8(r11); 983#endif 984 985#ifndef CONFIG_PPC_BOOK3E_64 986 mfmsr r6 987 ori r6,r6,MSR_RI 988 mtmsrd r6 /* RI on */ 989#endif 990 991#ifdef CONFIG_RELOCATABLE 992 /* Save the physical address we're running at in kernstart_addr */ 993 LOAD_REG_ADDR(r4, kernstart_addr) 994 clrldi r0,r25,2 995 std r0,0(r4) 996#endif 997 998 /* set up a stack pointer */ 999 LOAD_REG_ADDR(r3,init_thread_union) 1000 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE) 1001 add r1,r3,r1 1002 li r0,0 1003 stdu r0,-STACK_FRAME_MIN_SIZE(r1) 1004 1005 /* 1006 * Do very early kernel initializations, including initial hash table 1007 * and SLB setup before we turn on relocation. 1008 */ 1009 1010#ifdef CONFIG_KASAN 1011 bl CFUNC(kasan_early_init) 1012#endif 1013 /* Restore parameters passed from prom_init/kexec */ 1014 mr r3,r31 1015 LOAD_REG_ADDR(r12, DOTSYM(early_setup)) 1016 mtctr r12 1017 bctrl /* also sets r13 and SPRG_PACA */ 1018 1019 LOAD_REG_ADDR(r3, start_here_common) 1020 ld r4,PACAKMSR(r13) 1021 mtspr SPRN_SRR0,r3 1022 mtspr SPRN_SRR1,r4 1023 RFI_TO_KERNEL 1024 b . /* prevent speculative execution */ 1025 1026 /* This is where all platforms converge execution */ 1027 1028start_here_common: 1029 /* relocation is on at this point */ 1030 std r1,PACAKSAVE(r13) 1031 1032 /* Load the TOC (virtual address) */ 1033 LOAD_PACA_TOC() 1034 1035 /* Mark interrupts soft and hard disabled (they might be enabled 1036 * in the PACA when doing hotplug) 1037 */ 1038 li r0,IRQS_DISABLED 1039 stb r0,PACAIRQSOFTMASK(r13) 1040 li r0,PACA_IRQ_HARD_DIS 1041 stb r0,PACAIRQHAPPENED(r13) 1042 1043 /* Generic kernel entry */ 1044 bl CFUNC(start_kernel) 1045 1046 /* Not reached */ 10470: trap 1048 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 1049 .previous 1050