1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the entry point for the 64-bit kernel along 16 * with some early initialization code common to all 64-bit powerpc 17 * variants. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 25#include <linux/threads.h> 26#include <asm/reg.h> 27#include <asm/page.h> 28#include <asm/mmu.h> 29#include <asm/ppc_asm.h> 30#include <asm/asm-offsets.h> 31#include <asm/bug.h> 32#include <asm/cputable.h> 33#include <asm/setup.h> 34#include <asm/hvcall.h> 35#include <asm/iseries/lpar_map.h> 36#include <asm/thread_info.h> 37#include <asm/firmware.h> 38#include <asm/page_64.h> 39#include <asm/irqflags.h> 40#include <asm/kvm_book3s_asm.h> 41#include <asm/ptrace.h> 42 43/* The physical memory is laid out such that the secondary processor 44 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 45 * using the layout described in exceptions-64s.S 46 */ 47 48/* 49 * Entering into this code we make the following assumptions: 50 * 51 * For pSeries or server processors: 52 * 1. The MMU is off & open firmware is running in real mode. 53 * 2. The kernel is entered at __start 54 * -or- For OPAL entry: 55 * 1. The MMU is off, processor in HV mode, primary CPU enters at 0 56 * with device-tree in gpr3. We also get OPAL base in r8 and 57 * entry in r9 for debugging purposes 58 * 2. Secondary processors enter at 0x60 with PIR in gpr3 59 * 60 * For iSeries: 61 * 1. The MMU is on (as it always is for iSeries) 62 * 2. The kernel is entered at system_reset_iSeries 63 * 64 * For Book3E processors: 65 * 1. The MMU is on running in AS0 in a state defined in ePAPR 66 * 2. The kernel is entered at __start 67 */ 68 69 .text 70 .globl _stext 71_stext: 72_GLOBAL(__start) 73 /* NOP this out unconditionally */ 74BEGIN_FTR_SECTION 75 b .__start_initialization_multiplatform 76END_FTR_SECTION(0, 1) 77 78 /* Catch branch to 0 in real mode */ 79 trap 80 81 /* Secondary processors spin on this value until it becomes nonzero. 82 * When it does it contains the real address of the descriptor 83 * of the function that the cpu should jump to to continue 84 * initialization. 85 */ 86 .globl __secondary_hold_spinloop 87__secondary_hold_spinloop: 88 .llong 0x0 89 90 /* Secondary processors write this value with their cpu # */ 91 /* after they enter the spin loop immediately below. */ 92 .globl __secondary_hold_acknowledge 93__secondary_hold_acknowledge: 94 .llong 0x0 95 96#ifdef CONFIG_PPC_ISERIES 97 /* 98 * At offset 0x20, there is a pointer to iSeries LPAR data. 99 * This is required by the hypervisor 100 */ 101 . = 0x20 102 .llong hvReleaseData-KERNELBASE 103#endif /* CONFIG_PPC_ISERIES */ 104 105#ifdef CONFIG_RELOCATABLE 106 /* This flag is set to 1 by a loader if the kernel should run 107 * at the loaded address instead of the linked address. This 108 * is used by kexec-tools to keep the the kdump kernel in the 109 * crash_kernel region. The loader is responsible for 110 * observing the alignment requirement. 111 */ 112 /* Do not move this variable as kexec-tools knows about it. */ 113 . = 0x5c 114 .globl __run_at_load 115__run_at_load: 116 .long 0x72756e30 /* "run0" -- relocate to 0 by default */ 117#endif 118 119 . = 0x60 120/* 121 * The following code is used to hold secondary processors 122 * in a spin loop after they have entered the kernel, but 123 * before the bulk of the kernel has been relocated. This code 124 * is relocated to physical address 0x60 before prom_init is run. 125 * All of it must fit below the first exception vector at 0x100. 126 * Use .globl here not _GLOBAL because we want __secondary_hold 127 * to be the actual text address, not a descriptor. 128 */ 129 .globl __secondary_hold 130__secondary_hold: 131#ifndef CONFIG_PPC_BOOK3E 132 mfmsr r24 133 ori r24,r24,MSR_RI 134 mtmsrd r24 /* RI on */ 135#endif 136 /* Grab our physical cpu number */ 137 mr r24,r3 138 139 /* Tell the master cpu we're here */ 140 /* Relocation is off & we are located at an address less */ 141 /* than 0x100, so only need to grab low order offset. */ 142 std r24,__secondary_hold_acknowledge-_stext(0) 143 sync 144 145 /* All secondary cpus wait here until told to start. */ 146100: ld r4,__secondary_hold_spinloop-_stext(0) 147 cmpdi 0,r4,0 148 beq 100b 149 150#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 151 ld r4,0(r4) /* deref function descriptor */ 152 mtctr r4 153 mr r3,r24 154 li r4,0 155 /* Make sure that patched code is visible */ 156 isync 157 bctr 158#else 159 BUG_OPCODE 160#endif 161 162/* This value is used to mark exception frames on the stack. */ 163 .section ".toc","aw" 164exception_marker: 165 .tc ID_72656773_68657265[TC],0x7265677368657265 166 .text 167 168/* 169 * On server, we include the exception vectors code here as it 170 * relies on absolute addressing which is only possible within 171 * this compilation unit 172 */ 173#ifdef CONFIG_PPC_BOOK3S 174#include "exceptions-64s.S" 175#endif 176 177_GLOBAL(generic_secondary_thread_init) 178 mr r24,r3 179 180 /* turn on 64-bit mode */ 181 bl .enable_64b_mode 182 183 /* get a valid TOC pointer, wherever we're mapped at */ 184 bl .relative_toc 185 186#ifdef CONFIG_PPC_BOOK3E 187 /* Book3E initialization */ 188 mr r3,r24 189 bl .book3e_secondary_thread_init 190#endif 191 b generic_secondary_common_init 192 193/* 194 * On pSeries and most other platforms, secondary processors spin 195 * in the following code. 196 * At entry, r3 = this processor's number (physical cpu id) 197 * 198 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 199 * this core already exists (setup via some other mechanism such 200 * as SCOM before entry). 201 */ 202_GLOBAL(generic_secondary_smp_init) 203 mr r24,r3 204 mr r25,r4 205 206 /* turn on 64-bit mode */ 207 bl .enable_64b_mode 208 209 /* get a valid TOC pointer, wherever we're mapped at */ 210 bl .relative_toc 211 212#ifdef CONFIG_PPC_BOOK3E 213 /* Book3E initialization */ 214 mr r3,r24 215 mr r4,r25 216 bl .book3e_secondary_core_init 217#endif 218 219generic_secondary_common_init: 220 /* Set up a paca value for this processor. Since we have the 221 * physical cpu id in r24, we need to search the pacas to find 222 * which logical id maps to our physical one. 223 */ 224 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ 225 ld r13,0(r13) /* Get base vaddr of paca array */ 226#ifndef CONFIG_SMP 227 addi r13,r13,PACA_SIZE /* know r13 if used accidentally */ 228 b .kexec_wait /* wait for next kernel if !SMP */ 229#else 230 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 231 lwz r7,0(r7) /* also the max paca allocated */ 232 li r5,0 /* logical cpu id */ 2331: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 234 cmpw r6,r24 /* Compare to our id */ 235 beq 2f 236 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 237 addi r5,r5,1 238 cmpw r5,r7 /* Check if more pacas exist */ 239 blt 1b 240 241 mr r3,r24 /* not found, copy phys to r3 */ 242 b .kexec_wait /* next kernel might do better */ 243 2442: SET_PACA(r13) 245#ifdef CONFIG_PPC_BOOK3E 246 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 247 mtspr SPRN_SPRG_TLB_EXFRAME,r12 248#endif 249 250 /* From now on, r24 is expected to be logical cpuid */ 251 mr r24,r5 252 253 /* See if we need to call a cpu state restore handler */ 254 LOAD_REG_ADDR(r23, cur_cpu_spec) 255 ld r23,0(r23) 256 ld r23,CPU_SPEC_RESTORE(r23) 257 cmpdi 0,r23,0 258 beq 3f 259 ld r23,0(r23) 260 mtctr r23 261 bctrl 262 2633: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 264 lwarx r4,0,r3 265 subi r4,r4,1 266 stwcx. r4,0,r3 267 bne 3b 268 isync 269 2704: HMT_LOW 271 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 272 /* start. */ 273 cmpwi 0,r23,0 274 beq 4b /* Loop until told to go */ 275 276 sync /* order paca.run and cur_cpu_spec */ 277 isync /* In case code patching happened */ 278 279 /* Create a temp kernel stack for use before relocation is on. */ 280 ld r1,PACAEMERGSP(r13) 281 subi r1,r1,STACK_FRAME_OVERHEAD 282 283 b __secondary_start 284#endif /* SMP */ 285 286/* 287 * Turn the MMU off. 288 * Assumes we're mapped EA == RA if the MMU is on. 289 */ 290#ifdef CONFIG_PPC_BOOK3S 291_STATIC(__mmu_off) 292 mfmsr r3 293 andi. r0,r3,MSR_IR|MSR_DR 294 beqlr 295 mflr r4 296 andc r3,r3,r0 297 mtspr SPRN_SRR0,r4 298 mtspr SPRN_SRR1,r3 299 sync 300 rfid 301 b . /* prevent speculative execution */ 302#endif 303 304 305/* 306 * Here is our main kernel entry point. We support currently 2 kind of entries 307 * depending on the value of r5. 308 * 309 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 310 * in r3...r7 311 * 312 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 313 * DT block, r4 is a physical pointer to the kernel itself 314 * 315 */ 316_GLOBAL(__start_initialization_multiplatform) 317 /* Make sure we are running in 64 bits mode */ 318 bl .enable_64b_mode 319 320 /* Get TOC pointer (current runtime address) */ 321 bl .relative_toc 322 323 /* find out where we are now */ 324 bcl 20,31,$+4 3250: mflr r26 /* r26 = runtime addr here */ 326 addis r26,r26,(_stext - 0b)@ha 327 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 328 329 /* 330 * Are we booted from a PROM Of-type client-interface ? 331 */ 332 cmpldi cr0,r5,0 333 beq 1f 334 b .__boot_from_prom /* yes -> prom */ 3351: 336 /* Save parameters */ 337 mr r31,r3 338 mr r30,r4 339#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 340 /* Save OPAL entry */ 341 mr r28,r8 342 mr r29,r9 343#endif 344 345#ifdef CONFIG_PPC_BOOK3E 346 bl .start_initialization_book3e 347 b .__after_prom_start 348#else 349 /* Setup some critical 970 SPRs before switching MMU off */ 350 mfspr r0,SPRN_PVR 351 srwi r0,r0,16 352 cmpwi r0,0x39 /* 970 */ 353 beq 1f 354 cmpwi r0,0x3c /* 970FX */ 355 beq 1f 356 cmpwi r0,0x44 /* 970MP */ 357 beq 1f 358 cmpwi r0,0x45 /* 970GX */ 359 bne 2f 3601: bl .__cpu_preinit_ppc970 3612: 362 363 /* Switch off MMU if not already off */ 364 bl .__mmu_off 365 b .__after_prom_start 366#endif /* CONFIG_PPC_BOOK3E */ 367 368_INIT_STATIC(__boot_from_prom) 369#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 370 /* Save parameters */ 371 mr r31,r3 372 mr r30,r4 373 mr r29,r5 374 mr r28,r6 375 mr r27,r7 376 377 /* 378 * Align the stack to 16-byte boundary 379 * Depending on the size and layout of the ELF sections in the initial 380 * boot binary, the stack pointer may be unaligned on PowerMac 381 */ 382 rldicr r1,r1,0,59 383 384#ifdef CONFIG_RELOCATABLE 385 /* Relocate code for where we are now */ 386 mr r3,r26 387 bl .relocate 388#endif 389 390 /* Restore parameters */ 391 mr r3,r31 392 mr r4,r30 393 mr r5,r29 394 mr r6,r28 395 mr r7,r27 396 397 /* Do all of the interaction with OF client interface */ 398 mr r8,r26 399 bl .prom_init 400#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 401 402 /* We never return. We also hit that trap if trying to boot 403 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 404 trap 405 406_STATIC(__after_prom_start) 407#ifdef CONFIG_RELOCATABLE 408 /* process relocations for the final address of the kernel */ 409 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 410 sldi r25,r25,32 411 lwz r7,__run_at_load-_stext(r26) 412 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 413 bne 1f 414 add r25,r25,r26 4151: mr r3,r25 416 bl .relocate 417#endif 418 419/* 420 * We need to run with _stext at physical address PHYSICAL_START. 421 * This will leave some code in the first 256B of 422 * real memory, which are reserved for software use. 423 * 424 * Note: This process overwrites the OF exception vectors. 425 */ 426 li r3,0 /* target addr */ 427#ifdef CONFIG_PPC_BOOK3E 428 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 429#endif 430 mr. r4,r26 /* In some cases the loader may */ 431 beq 9f /* have already put us at zero */ 432 li r6,0x100 /* Start offset, the first 0x100 */ 433 /* bytes were copied earlier. */ 434#ifdef CONFIG_PPC_BOOK3E 435 tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */ 436#endif 437 438#ifdef CONFIG_CRASH_DUMP 439/* 440 * Check if the kernel has to be running as relocatable kernel based on the 441 * variable __run_at_load, if it is set the kernel is treated as relocatable 442 * kernel, otherwise it will be moved to PHYSICAL_START 443 */ 444 lwz r7,__run_at_load-_stext(r26) 445 cmplwi cr0,r7,1 446 bne 3f 447 448 li r5,__end_interrupts - _stext /* just copy interrupts */ 449 b 5f 4503: 451#endif 452 lis r5,(copy_to_here - _stext)@ha 453 addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ 454 455 bl .copy_and_flush /* copy the first n bytes */ 456 /* this includes the code being */ 457 /* executed here. */ 458 addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ 459 addi r8,r8,(4f - _stext)@l /* that we just made */ 460 mtctr r8 461 bctr 462 463p_end: .llong _end - _stext 464 4654: /* Now copy the rest of the kernel up to _end */ 466 addis r5,r26,(p_end - _stext)@ha 467 ld r5,(p_end - _stext)@l(r5) /* get _end */ 4685: bl .copy_and_flush /* copy the rest */ 469 4709: b .start_here_multiplatform 471 472/* 473 * Copy routine used to copy the kernel to start at physical address 0 474 * and flush and invalidate the caches as needed. 475 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 476 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 477 * 478 * Note: this routine *only* clobbers r0, r6 and lr 479 */ 480_GLOBAL(copy_and_flush) 481 addi r5,r5,-8 482 addi r6,r6,-8 4834: li r0,8 /* Use the smallest common */ 484 /* denominator cache line */ 485 /* size. This results in */ 486 /* extra cache line flushes */ 487 /* but operation is correct. */ 488 /* Can't get cache line size */ 489 /* from NACA as it is being */ 490 /* moved too. */ 491 492 mtctr r0 /* put # words/line in ctr */ 4933: addi r6,r6,8 /* copy a cache line */ 494 ldx r0,r6,r4 495 stdx r0,r6,r3 496 bdnz 3b 497 dcbst r6,r3 /* write it to memory */ 498 sync 499 icbi r6,r3 /* flush the icache line */ 500 cmpld 0,r6,r5 501 blt 4b 502 sync 503 addi r5,r5,8 504 addi r6,r6,8 505 blr 506 507.align 8 508copy_to_here: 509 510#ifdef CONFIG_SMP 511#ifdef CONFIG_PPC_PMAC 512/* 513 * On PowerMac, secondary processors starts from the reset vector, which 514 * is temporarily turned into a call to one of the functions below. 515 */ 516 .section ".text"; 517 .align 2 ; 518 519 .globl __secondary_start_pmac_0 520__secondary_start_pmac_0: 521 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 522 li r24,0 523 b 1f 524 li r24,1 525 b 1f 526 li r24,2 527 b 1f 528 li r24,3 5291: 530 531_GLOBAL(pmac_secondary_start) 532 /* turn on 64-bit mode */ 533 bl .enable_64b_mode 534 535 li r0,0 536 mfspr r3,SPRN_HID4 537 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 538 sync 539 mtspr SPRN_HID4,r3 540 isync 541 sync 542 slbia 543 544 /* get TOC pointer (real address) */ 545 bl .relative_toc 546 547 /* Copy some CPU settings from CPU 0 */ 548 bl .__restore_cpu_ppc970 549 550 /* pSeries do that early though I don't think we really need it */ 551 mfmsr r3 552 ori r3,r3,MSR_RI 553 mtmsrd r3 /* RI on */ 554 555 /* Set up a paca value for this processor. */ 556 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ 557 ld r4,0(r4) /* Get base vaddr of paca array */ 558 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 559 add r13,r13,r4 /* for this processor. */ 560 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 561 562 /* Mark interrupts soft and hard disabled (they might be enabled 563 * in the PACA when doing hotplug) 564 */ 565 li r0,0 566 stb r0,PACASOFTIRQEN(r13) 567 stb r0,PACAHARDIRQEN(r13) 568 569 /* Create a temp kernel stack for use before relocation is on. */ 570 ld r1,PACAEMERGSP(r13) 571 subi r1,r1,STACK_FRAME_OVERHEAD 572 573 b __secondary_start 574 575#endif /* CONFIG_PPC_PMAC */ 576 577/* 578 * This function is called after the master CPU has released the 579 * secondary processors. The execution environment is relocation off. 580 * The paca for this processor has the following fields initialized at 581 * this point: 582 * 1. Processor number 583 * 2. Segment table pointer (virtual address) 584 * On entry the following are set: 585 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 586 * r24 = cpu# (in Linux terms) 587 * r13 = paca virtual address 588 * SPRG_PACA = paca virtual address 589 */ 590 .section ".text"; 591 .align 2 ; 592 593 .globl __secondary_start 594__secondary_start: 595 /* Set thread priority to MEDIUM */ 596 HMT_MEDIUM 597 598 /* Initialize the kernel stack. Just a repeat for iSeries. */ 599 LOAD_REG_ADDR(r3, current_set) 600 sldi r28,r24,3 /* get current_set[cpu#] */ 601 ldx r14,r3,r28 602 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD 603 std r14,PACAKSAVE(r13) 604 605 /* Do early setup for that CPU (stab, slb, hash table pointer) */ 606 bl .early_setup_secondary 607 608 /* 609 * setup the new stack pointer, but *don't* use this until 610 * translation is on. 611 */ 612 mr r1, r14 613 614 /* Clear backchain so we get nice backtraces */ 615 li r7,0 616 mtlr r7 617 618 /* enable MMU and jump to start_secondary */ 619 LOAD_REG_ADDR(r3, .start_secondary_prolog) 620 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 621#ifdef CONFIG_PPC_ISERIES 622BEGIN_FW_FTR_SECTION 623 ori r4,r4,MSR_EE 624 li r8,1 625 stb r8,PACAHARDIRQEN(r13) 626END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 627#endif 628BEGIN_FW_FTR_SECTION 629 stb r7,PACAHARDIRQEN(r13) 630END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 631 stb r7,PACASOFTIRQEN(r13) 632 633 mtspr SPRN_SRR0,r3 634 mtspr SPRN_SRR1,r4 635 RFI 636 b . /* prevent speculative execution */ 637 638/* 639 * Running with relocation on at this point. All we want to do is 640 * zero the stack back-chain pointer and get the TOC virtual address 641 * before going into C code. 642 */ 643_GLOBAL(start_secondary_prolog) 644 ld r2,PACATOC(r13) 645 li r3,0 646 std r3,0(r1) /* Zero the stack frame pointer */ 647 bl .start_secondary 648 b . 649/* 650 * Reset stack pointer and call start_secondary 651 * to continue with online operation when woken up 652 * from cede in cpu offline. 653 */ 654_GLOBAL(start_secondary_resume) 655 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 656 li r3,0 657 std r3,0(r1) /* Zero the stack frame pointer */ 658 bl .start_secondary 659 b . 660#endif 661 662/* 663 * This subroutine clobbers r11 and r12 664 */ 665_GLOBAL(enable_64b_mode) 666 mfmsr r11 /* grab the current MSR */ 667#ifdef CONFIG_PPC_BOOK3E 668 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 669 mtmsr r11 670#else /* CONFIG_PPC_BOOK3E */ 671 li r12,(MSR_64BIT | MSR_ISF)@highest 672 sldi r12,r12,48 673 or r11,r11,r12 674 mtmsrd r11 675 isync 676#endif 677 blr 678 679/* 680 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 681 * by the toolchain). It computes the correct value for wherever we 682 * are running at the moment, using position-independent code. 683 */ 684_GLOBAL(relative_toc) 685 mflr r0 686 bcl 20,31,$+4 6870: mflr r11 688 ld r2,(p_toc - 0b)(r11) 689 add r2,r2,r11 690 mtlr r0 691 blr 692 693p_toc: .llong __toc_start + 0x8000 - 0b 694 695/* 696 * This is where the main kernel code starts. 697 */ 698_INIT_STATIC(start_here_multiplatform) 699 /* set up the TOC (real address) */ 700 bl .relative_toc 701 702 /* Clear out the BSS. It may have been done in prom_init, 703 * already but that's irrelevant since prom_init will soon 704 * be detached from the kernel completely. Besides, we need 705 * to clear it now for kexec-style entry. 706 */ 707 LOAD_REG_ADDR(r11,__bss_stop) 708 LOAD_REG_ADDR(r8,__bss_start) 709 sub r11,r11,r8 /* bss size */ 710 addi r11,r11,7 /* round up to an even double word */ 711 srdi. r11,r11,3 /* shift right by 3 */ 712 beq 4f 713 addi r8,r8,-8 714 li r0,0 715 mtctr r11 /* zero this many doublewords */ 7163: stdu r0,8(r8) 717 bdnz 3b 7184: 719 720#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 721 /* Setup OPAL entry */ 722 std r28,0(r11); 723 std r29,8(r11); 724#endif 725 726#ifndef CONFIG_PPC_BOOK3E 727 mfmsr r6 728 ori r6,r6,MSR_RI 729 mtmsrd r6 /* RI on */ 730#endif 731 732#ifdef CONFIG_RELOCATABLE 733 /* Save the physical address we're running at in kernstart_addr */ 734 LOAD_REG_ADDR(r4, kernstart_addr) 735 clrldi r0,r25,2 736 std r0,0(r4) 737#endif 738 739 /* The following gets the stack set up with the regs */ 740 /* pointing to the real addr of the kernel stack. This is */ 741 /* all done to support the C function call below which sets */ 742 /* up the htab. This is done because we have relocated the */ 743 /* kernel but are still running in real mode. */ 744 745 LOAD_REG_ADDR(r3,init_thread_union) 746 747 /* set up a stack pointer */ 748 addi r1,r3,THREAD_SIZE 749 li r0,0 750 stdu r0,-STACK_FRAME_OVERHEAD(r1) 751 752 /* Do very early kernel initializations, including initial hash table, 753 * stab and slb setup before we turn on relocation. */ 754 755 /* Restore parameters passed from prom_init/kexec */ 756 mr r3,r31 757 bl .early_setup /* also sets r13 and SPRG_PACA */ 758 759 LOAD_REG_ADDR(r3, .start_here_common) 760 ld r4,PACAKMSR(r13) 761 mtspr SPRN_SRR0,r3 762 mtspr SPRN_SRR1,r4 763 RFI 764 b . /* prevent speculative execution */ 765 766 /* This is where all platforms converge execution */ 767_INIT_GLOBAL(start_here_common) 768 /* relocation is on at this point */ 769 std r1,PACAKSAVE(r13) 770 771 /* Load the TOC (virtual address) */ 772 ld r2,PACATOC(r13) 773 774 bl .setup_system 775 776 /* Load up the kernel context */ 7775: 778 li r5,0 779 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ 780#ifdef CONFIG_PPC_ISERIES 781BEGIN_FW_FTR_SECTION 782 mfmsr r5 783 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/ 784 mtmsrd r5 785 li r5,1 786END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 787#endif 788 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */ 789 790 bl .start_kernel 791 792 /* Not reached */ 793 BUG_OPCODE 794 795/* 796 * We put a few things here that have to be page-aligned. 797 * This stuff goes at the beginning of the bss, which is page-aligned. 798 */ 799 .section ".bss" 800 801 .align PAGE_SHIFT 802 803 .globl empty_zero_page 804empty_zero_page: 805 .space PAGE_SIZE 806 807 .globl swapper_pg_dir 808swapper_pg_dir: 809 .space PGD_TABLE_SIZE 810