1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * 6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8 * Adapted for Power Macintosh by Paul Mackerras. 9 * Low-level exception handlers and MMU support 10 * rewritten by Paul Mackerras. 11 * Copyright (C) 1996 Paul Mackerras. 12 * 13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 15 * 16 * This file contains the entry point for the 64-bit kernel along 17 * with some early initialization code common to all 64-bit powerpc 18 * variants. 19 */ 20 21#include <linux/threads.h> 22#include <linux/init.h> 23#include <asm/reg.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/ppc_asm.h> 27#include <asm/head-64.h> 28#include <asm/asm-offsets.h> 29#include <asm/bug.h> 30#include <asm/cputable.h> 31#include <asm/setup.h> 32#include <asm/hvcall.h> 33#include <asm/thread_info.h> 34#include <asm/firmware.h> 35#include <asm/page_64.h> 36#include <asm/irqflags.h> 37#include <asm/kvm_book3s_asm.h> 38#include <asm/ptrace.h> 39#include <asm/hw_irq.h> 40#include <asm/cputhreads.h> 41#include <asm/ppc-opcode.h> 42#include <asm/export.h> 43#include <asm/feature-fixups.h> 44#ifdef CONFIG_PPC_BOOK3S 45#include <asm/exception-64s.h> 46#else 47#include <asm/exception-64e.h> 48#endif 49 50/* The physical memory is laid out such that the secondary processor 51 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 52 * using the layout described in exceptions-64s.S 53 */ 54 55/* 56 * Entering into this code we make the following assumptions: 57 * 58 * For pSeries or server processors: 59 * 1. The MMU is off & open firmware is running in real mode. 60 * 2. The primary CPU enters at __start. 61 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary 62 * CPUs will enter as directed by "start-cpu" RTAS call, which is 63 * generic_secondary_smp_init, with PIR in r3. 64 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as 65 * directed by the "start-cpu" RTS call, with PIR in r3. 66 * -or- For OPAL entry: 67 * 1. The MMU is off, processor in HV mode. 68 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base 69 * in r8, and entry in r9 for debugging purposes. 70 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which 71 * is at generic_secondary_smp_init, with PIR in r3. 72 * 73 * For Book3E processors: 74 * 1. The MMU is on running in AS0 in a state defined in ePAPR 75 * 2. The kernel is entered at __start 76 */ 77 78OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) 79USE_FIXED_SECTION(first_256B) 80 /* 81 * Offsets are relative from the start of fixed section, and 82 * first_256B starts at 0. Offsets are a bit easier to use here 83 * than the fixed section entry macros. 84 */ 85 . = 0x0 86_GLOBAL(__start) 87 /* NOP this out unconditionally */ 88BEGIN_FTR_SECTION 89 FIXUP_ENDIAN 90 b __start_initialization_multiplatform 91END_FTR_SECTION(0, 1) 92 93 /* Catch branch to 0 in real mode */ 94 trap 95 96 /* Secondary processors spin on this value until it becomes non-zero. 97 * When non-zero, it contains the real address of the function the cpu 98 * should jump to. 99 */ 100 .balign 8 101 .globl __secondary_hold_spinloop 102__secondary_hold_spinloop: 103 .8byte 0x0 104 105 /* Secondary processors write this value with their cpu # */ 106 /* after they enter the spin loop immediately below. */ 107 .globl __secondary_hold_acknowledge 108__secondary_hold_acknowledge: 109 .8byte 0x0 110 111#ifdef CONFIG_RELOCATABLE 112 /* This flag is set to 1 by a loader if the kernel should run 113 * at the loaded address instead of the linked address. This 114 * is used by kexec-tools to keep the the kdump kernel in the 115 * crash_kernel region. The loader is responsible for 116 * observing the alignment requirement. 117 */ 118 119#ifdef CONFIG_RELOCATABLE_TEST 120#define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */ 121#else 122#define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */ 123#endif 124 125 /* Do not move this variable as kexec-tools knows about it. */ 126 . = 0x5c 127 .globl __run_at_load 128__run_at_load: 129DEFINE_FIXED_SYMBOL(__run_at_load) 130 .long RUN_AT_LOAD_DEFAULT 131#endif 132 133 . = 0x60 134/* 135 * The following code is used to hold secondary processors 136 * in a spin loop after they have entered the kernel, but 137 * before the bulk of the kernel has been relocated. This code 138 * is relocated to physical address 0x60 before prom_init is run. 139 * All of it must fit below the first exception vector at 0x100. 140 * Use .globl here not _GLOBAL because we want __secondary_hold 141 * to be the actual text address, not a descriptor. 142 */ 143 .globl __secondary_hold 144__secondary_hold: 145 FIXUP_ENDIAN 146#ifndef CONFIG_PPC_BOOK3E 147 mfmsr r24 148 ori r24,r24,MSR_RI 149 mtmsrd r24 /* RI on */ 150#endif 151 /* Grab our physical cpu number */ 152 mr r24,r3 153 /* stash r4 for book3e */ 154 mr r25,r4 155 156 /* Tell the master cpu we're here */ 157 /* Relocation is off & we are located at an address less */ 158 /* than 0x100, so only need to grab low order offset. */ 159 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0) 160 sync 161 162 li r26,0 163#ifdef CONFIG_PPC_BOOK3E 164 tovirt(r26,r26) 165#endif 166 /* All secondary cpus wait here until told to start. */ 167100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26) 168 cmpdi 0,r12,0 169 beq 100b 170 171#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 172#ifdef CONFIG_PPC_BOOK3E 173 tovirt(r12,r12) 174#endif 175 mtctr r12 176 mr r3,r24 177 /* 178 * it may be the case that other platforms have r4 right to 179 * begin with, this gives us some safety in case it is not 180 */ 181#ifdef CONFIG_PPC_BOOK3E 182 mr r4,r25 183#else 184 li r4,0 185#endif 186 /* Make sure that patched code is visible */ 187 isync 188 bctr 189#else 1900: trap 191 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 192#endif 193CLOSE_FIXED_SECTION(first_256B) 194 195/* This value is used to mark exception frames on the stack. */ 196 .section ".toc","aw" 197exception_marker: 198 .tc ID_72656773_68657265[TC],0x7265677368657265 199 .previous 200 201/* 202 * On server, we include the exception vectors code here as it 203 * relies on absolute addressing which is only possible within 204 * this compilation unit 205 */ 206#ifdef CONFIG_PPC_BOOK3S 207#include "exceptions-64s.S" 208#else 209OPEN_TEXT_SECTION(0x100) 210#endif 211 212USE_TEXT_SECTION() 213 214#ifdef CONFIG_PPC_BOOK3E 215/* 216 * The booting_thread_hwid holds the thread id we want to boot in cpu 217 * hotplug case. It is set by cpu hotplug code, and is invalid by default. 218 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] 219 * bit field. 220 */ 221 .globl booting_thread_hwid 222booting_thread_hwid: 223 .long INVALID_THREAD_HWID 224 .align 3 225/* 226 * start a thread in the same core 227 * input parameters: 228 * r3 = the thread physical id 229 * r4 = the entry point where thread starts 230 */ 231_GLOBAL(book3e_start_thread) 232 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) 233 cmpwi r3, 0 234 beq 10f 235 cmpwi r3, 1 236 beq 11f 237 /* If the thread id is invalid, just exit. */ 238 b 13f 23910: 240 MTTMR(TMRN_IMSR0, 5) 241 MTTMR(TMRN_INIA0, 4) 242 b 12f 24311: 244 MTTMR(TMRN_IMSR1, 5) 245 MTTMR(TMRN_INIA1, 4) 24612: 247 isync 248 li r6, 1 249 sld r6, r6, r3 250 mtspr SPRN_TENS, r6 25113: 252 blr 253 254/* 255 * stop a thread in the same core 256 * input parameter: 257 * r3 = the thread physical id 258 */ 259_GLOBAL(book3e_stop_thread) 260 cmpwi r3, 0 261 beq 10f 262 cmpwi r3, 1 263 beq 10f 264 /* If the thread id is invalid, just exit. */ 265 b 13f 26610: 267 li r4, 1 268 sld r4, r4, r3 269 mtspr SPRN_TENC, r4 27013: 271 blr 272 273_GLOBAL(fsl_secondary_thread_init) 274 mfspr r4,SPRN_BUCSR 275 276 /* Enable branch prediction */ 277 lis r3,BUCSR_INIT@h 278 ori r3,r3,BUCSR_INIT@l 279 mtspr SPRN_BUCSR,r3 280 isync 281 282 /* 283 * Fix PIR to match the linear numbering in the device tree. 284 * 285 * On e6500, the reset value of PIR uses the low three bits for 286 * the thread within a core, and the upper bits for the core 287 * number. There are two threads per core, so shift everything 288 * but the low bit right by two bits so that the cpu numbering is 289 * continuous. 290 * 291 * If the old value of BUCSR is non-zero, this thread has run 292 * before. Thus, we assume we are coming from kexec or a similar 293 * scenario, and PIR is already set to the correct value. This 294 * is a bit of a hack, but there are limited opportunities for 295 * getting information into the thread and the alternatives 296 * seemed like they'd be overkill. We can't tell just by looking 297 * at the old PIR value which state it's in, since the same value 298 * could be valid for one thread out of reset and for a different 299 * thread in Linux. 300 */ 301 302 mfspr r3, SPRN_PIR 303 cmpwi r4,0 304 bne 1f 305 rlwimi r3, r3, 30, 2, 30 306 mtspr SPRN_PIR, r3 3071: 308 mr r24,r3 309 310 /* turn on 64-bit mode */ 311 bl enable_64b_mode 312 313 /* get a valid TOC pointer, wherever we're mapped at */ 314 bl relative_toc 315 tovirt(r2,r2) 316 317 /* Book3E initialization */ 318 mr r3,r24 319 bl book3e_secondary_thread_init 320 b generic_secondary_common_init 321 322#endif /* CONFIG_PPC_BOOK3E */ 323 324/* 325 * On pSeries and most other platforms, secondary processors spin 326 * in the following code. 327 * At entry, r3 = this processor's number (physical cpu id) 328 * 329 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 330 * this core already exists (setup via some other mechanism such 331 * as SCOM before entry). 332 */ 333_GLOBAL(generic_secondary_smp_init) 334 FIXUP_ENDIAN 335 mr r24,r3 336 mr r25,r4 337 338 /* turn on 64-bit mode */ 339 bl enable_64b_mode 340 341 /* get a valid TOC pointer, wherever we're mapped at */ 342 bl relative_toc 343 tovirt(r2,r2) 344 345#ifdef CONFIG_PPC_BOOK3E 346 /* Book3E initialization */ 347 mr r3,r24 348 mr r4,r25 349 bl book3e_secondary_core_init 350 351/* 352 * After common core init has finished, check if the current thread is the 353 * one we wanted to boot. If not, start the specified thread and stop the 354 * current thread. 355 */ 356 LOAD_REG_ADDR(r4, booting_thread_hwid) 357 lwz r3, 0(r4) 358 li r5, INVALID_THREAD_HWID 359 cmpw r3, r5 360 beq 20f 361 362 /* 363 * The value of booting_thread_hwid has been stored in r3, 364 * so make it invalid. 365 */ 366 stw r5, 0(r4) 367 368 /* 369 * Get the current thread id and check if it is the one we wanted. 370 * If not, start the one specified in booting_thread_hwid and stop 371 * the current thread. 372 */ 373 mfspr r8, SPRN_TIR 374 cmpw r3, r8 375 beq 20f 376 377 /* start the specified thread */ 378 LOAD_REG_ADDR(r5, fsl_secondary_thread_init) 379 ld r4, 0(r5) 380 bl book3e_start_thread 381 382 /* stop the current thread */ 383 mr r3, r8 384 bl book3e_stop_thread 38510: 386 b 10b 38720: 388#endif 389 390generic_secondary_common_init: 391 /* Set up a paca value for this processor. Since we have the 392 * physical cpu id in r24, we need to search the pacas to find 393 * which logical id maps to our physical one. 394 */ 395#ifndef CONFIG_SMP 396 b kexec_wait /* wait for next kernel if !SMP */ 397#else 398 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */ 399 ld r8,0(r8) /* Get base vaddr of array */ 400 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 401 lwz r7,0(r7) /* also the max paca allocated */ 402 li r5,0 /* logical cpu id */ 4031: 404 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */ 405 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */ 406 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 407 cmpw r6,r24 /* Compare to our id */ 408 beq 2f 409 addi r5,r5,1 410 cmpw r5,r7 /* Check if more pacas exist */ 411 blt 1b 412 413 mr r3,r24 /* not found, copy phys to r3 */ 414 b kexec_wait /* next kernel might do better */ 415 4162: SET_PACA(r13) 417#ifdef CONFIG_PPC_BOOK3E 418 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 419 mtspr SPRN_SPRG_TLB_EXFRAME,r12 420#endif 421 422 /* From now on, r24 is expected to be logical cpuid */ 423 mr r24,r5 424 425 /* Create a temp kernel stack for use before relocation is on. */ 426 ld r1,PACAEMERGSP(r13) 427 subi r1,r1,STACK_FRAME_OVERHEAD 428 429 /* See if we need to call a cpu state restore handler */ 430 LOAD_REG_ADDR(r23, cur_cpu_spec) 431 ld r23,0(r23) 432 ld r12,CPU_SPEC_RESTORE(r23) 433 cmpdi 0,r12,0 434 beq 3f 435#ifdef PPC64_ELF_ABI_v1 436 ld r12,0(r12) 437#endif 438 mtctr r12 439 bctrl 440 4413: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 442 lwarx r4,0,r3 443 subi r4,r4,1 444 stwcx. r4,0,r3 445 bne 3b 446 isync 447 4484: HMT_LOW 449 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 450 /* start. */ 451 cmpwi 0,r23,0 452 beq 4b /* Loop until told to go */ 453 454 sync /* order paca.run and cur_cpu_spec */ 455 isync /* In case code patching happened */ 456 457 b __secondary_start 458#endif /* SMP */ 459 460/* 461 * Turn the MMU off. 462 * Assumes we're mapped EA == RA if the MMU is on. 463 */ 464#ifdef CONFIG_PPC_BOOK3S 465__mmu_off: 466 mfmsr r3 467 andi. r0,r3,MSR_IR|MSR_DR 468 beqlr 469 mflr r4 470 andc r3,r3,r0 471 mtspr SPRN_SRR0,r4 472 mtspr SPRN_SRR1,r3 473 sync 474 rfid 475 b . /* prevent speculative execution */ 476#endif 477 478 479/* 480 * Here is our main kernel entry point. We support currently 2 kind of entries 481 * depending on the value of r5. 482 * 483 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 484 * in r3...r7 485 * 486 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 487 * DT block, r4 is a physical pointer to the kernel itself 488 * 489 */ 490__start_initialization_multiplatform: 491 /* Make sure we are running in 64 bits mode */ 492 bl enable_64b_mode 493 494 /* Get TOC pointer (current runtime address) */ 495 bl relative_toc 496 497 /* find out where we are now */ 498 bcl 20,31,$+4 4990: mflr r26 /* r26 = runtime addr here */ 500 addis r26,r26,(_stext - 0b)@ha 501 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 502 503 /* 504 * Are we booted from a PROM Of-type client-interface ? 505 */ 506 cmpldi cr0,r5,0 507 beq 1f 508 b __boot_from_prom /* yes -> prom */ 5091: 510 /* Save parameters */ 511 mr r31,r3 512 mr r30,r4 513#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 514 /* Save OPAL entry */ 515 mr r28,r8 516 mr r29,r9 517#endif 518 519#ifdef CONFIG_PPC_BOOK3E 520 bl start_initialization_book3e 521 b __after_prom_start 522#else 523 /* Setup some critical 970 SPRs before switching MMU off */ 524 mfspr r0,SPRN_PVR 525 srwi r0,r0,16 526 cmpwi r0,0x39 /* 970 */ 527 beq 1f 528 cmpwi r0,0x3c /* 970FX */ 529 beq 1f 530 cmpwi r0,0x44 /* 970MP */ 531 beq 1f 532 cmpwi r0,0x45 /* 970GX */ 533 bne 2f 5341: bl __cpu_preinit_ppc970 5352: 536 537 /* Switch off MMU if not already off */ 538 bl __mmu_off 539 b __after_prom_start 540#endif /* CONFIG_PPC_BOOK3E */ 541 542__REF 543__boot_from_prom: 544#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 545 /* Save parameters */ 546 mr r31,r3 547 mr r30,r4 548 mr r29,r5 549 mr r28,r6 550 mr r27,r7 551 552 /* 553 * Align the stack to 16-byte boundary 554 * Depending on the size and layout of the ELF sections in the initial 555 * boot binary, the stack pointer may be unaligned on PowerMac 556 */ 557 rldicr r1,r1,0,59 558 559#ifdef CONFIG_RELOCATABLE 560 /* Relocate code for where we are now */ 561 mr r3,r26 562 bl relocate 563#endif 564 565 /* Restore parameters */ 566 mr r3,r31 567 mr r4,r30 568 mr r5,r29 569 mr r6,r28 570 mr r7,r27 571 572 /* Do all of the interaction with OF client interface */ 573 mr r8,r26 574 bl prom_init 575#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 576 577 /* We never return. We also hit that trap if trying to boot 578 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 579 trap 580 .previous 581 582__after_prom_start: 583#ifdef CONFIG_RELOCATABLE 584 /* process relocations for the final address of the kernel */ 585 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 586 sldi r25,r25,32 587#if defined(CONFIG_PPC_BOOK3E) 588 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 589#endif 590 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 591#if defined(CONFIG_PPC_BOOK3E) 592 tophys(r26,r26) 593#endif 594 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 595 bne 1f 596 add r25,r25,r26 5971: mr r3,r25 598 bl relocate 599#if defined(CONFIG_PPC_BOOK3E) 600 /* IVPR needs to be set after relocation. */ 601 bl init_core_book3e 602#endif 603#endif 604 605/* 606 * We need to run with _stext at physical address PHYSICAL_START. 607 * This will leave some code in the first 256B of 608 * real memory, which are reserved for software use. 609 * 610 * Note: This process overwrites the OF exception vectors. 611 */ 612 li r3,0 /* target addr */ 613#ifdef CONFIG_PPC_BOOK3E 614 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 615#endif 616 mr. r4,r26 /* In some cases the loader may */ 617#if defined(CONFIG_PPC_BOOK3E) 618 tovirt(r4,r4) 619#endif 620 beq 9f /* have already put us at zero */ 621 li r6,0x100 /* Start offset, the first 0x100 */ 622 /* bytes were copied earlier. */ 623 624#ifdef CONFIG_RELOCATABLE 625/* 626 * Check if the kernel has to be running as relocatable kernel based on the 627 * variable __run_at_load, if it is set the kernel is treated as relocatable 628 * kernel, otherwise it will be moved to PHYSICAL_START 629 */ 630#if defined(CONFIG_PPC_BOOK3E) 631 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 632#endif 633 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 634 cmplwi cr0,r7,1 635 bne 3f 636 637#ifdef CONFIG_PPC_BOOK3E 638 LOAD_REG_ADDR(r5, __end_interrupts) 639 LOAD_REG_ADDR(r11, _stext) 640 sub r5,r5,r11 641#else 642 /* just copy interrupts */ 643 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) 644#endif 645 b 5f 6463: 647#endif 648 /* # bytes of memory to copy */ 649 lis r5,(ABS_ADDR(copy_to_here))@ha 650 addi r5,r5,(ABS_ADDR(copy_to_here))@l 651 652 bl copy_and_flush /* copy the first n bytes */ 653 /* this includes the code being */ 654 /* executed here. */ 655 /* Jump to the copy of this code that we just made */ 656 addis r8,r3,(ABS_ADDR(4f))@ha 657 addi r12,r8,(ABS_ADDR(4f))@l 658 mtctr r12 659 bctr 660 661.balign 8 662p_end: .8byte _end - copy_to_here 663 6644: 665 /* 666 * Now copy the rest of the kernel up to _end, add 667 * _end - copy_to_here to the copy limit and run again. 668 */ 669 addis r8,r26,(ABS_ADDR(p_end))@ha 670 ld r8,(ABS_ADDR(p_end))@l(r8) 671 add r5,r5,r8 6725: bl copy_and_flush /* copy the rest */ 673 6749: b start_here_multiplatform 675 676/* 677 * Copy routine used to copy the kernel to start at physical address 0 678 * and flush and invalidate the caches as needed. 679 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 680 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 681 * 682 * Note: this routine *only* clobbers r0, r6 and lr 683 */ 684_GLOBAL(copy_and_flush) 685 addi r5,r5,-8 686 addi r6,r6,-8 6874: li r0,8 /* Use the smallest common */ 688 /* denominator cache line */ 689 /* size. This results in */ 690 /* extra cache line flushes */ 691 /* but operation is correct. */ 692 /* Can't get cache line size */ 693 /* from NACA as it is being */ 694 /* moved too. */ 695 696 mtctr r0 /* put # words/line in ctr */ 6973: addi r6,r6,8 /* copy a cache line */ 698 ldx r0,r6,r4 699 stdx r0,r6,r3 700 bdnz 3b 701 dcbst r6,r3 /* write it to memory */ 702 sync 703 icbi r6,r3 /* flush the icache line */ 704 cmpld 0,r6,r5 705 blt 4b 706 sync 707 addi r5,r5,8 708 addi r6,r6,8 709 isync 710 blr 711 712.align 8 713copy_to_here: 714 715#ifdef CONFIG_SMP 716#ifdef CONFIG_PPC_PMAC 717/* 718 * On PowerMac, secondary processors starts from the reset vector, which 719 * is temporarily turned into a call to one of the functions below. 720 */ 721 .section ".text"; 722 .align 2 ; 723 724 .globl __secondary_start_pmac_0 725__secondary_start_pmac_0: 726 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 727 li r24,0 728 b 1f 729 li r24,1 730 b 1f 731 li r24,2 732 b 1f 733 li r24,3 7341: 735 736_GLOBAL(pmac_secondary_start) 737 /* turn on 64-bit mode */ 738 bl enable_64b_mode 739 740 li r0,0 741 mfspr r3,SPRN_HID4 742 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 743 sync 744 mtspr SPRN_HID4,r3 745 isync 746 sync 747 slbia 748 749 /* get TOC pointer (real address) */ 750 bl relative_toc 751 tovirt(r2,r2) 752 753 /* Copy some CPU settings from CPU 0 */ 754 bl __restore_cpu_ppc970 755 756 /* pSeries do that early though I don't think we really need it */ 757 mfmsr r3 758 ori r3,r3,MSR_RI 759 mtmsrd r3 /* RI on */ 760 761 /* Set up a paca value for this processor. */ 762 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */ 763 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */ 764 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */ 765 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */ 766 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 767 768 /* Mark interrupts soft and hard disabled (they might be enabled 769 * in the PACA when doing hotplug) 770 */ 771 li r0,IRQS_DISABLED 772 stb r0,PACAIRQSOFTMASK(r13) 773 li r0,PACA_IRQ_HARD_DIS 774 stb r0,PACAIRQHAPPENED(r13) 775 776 /* Create a temp kernel stack for use before relocation is on. */ 777 ld r1,PACAEMERGSP(r13) 778 subi r1,r1,STACK_FRAME_OVERHEAD 779 780 b __secondary_start 781 782#endif /* CONFIG_PPC_PMAC */ 783 784/* 785 * This function is called after the master CPU has released the 786 * secondary processors. The execution environment is relocation off. 787 * The paca for this processor has the following fields initialized at 788 * this point: 789 * 1. Processor number 790 * 2. Segment table pointer (virtual address) 791 * On entry the following are set: 792 * r1 = stack pointer (real addr of temp stack) 793 * r24 = cpu# (in Linux terms) 794 * r13 = paca virtual address 795 * SPRG_PACA = paca virtual address 796 */ 797 .section ".text"; 798 .align 2 ; 799 800 .globl __secondary_start 801__secondary_start: 802 /* Set thread priority to MEDIUM */ 803 HMT_MEDIUM 804 805 /* 806 * Do early setup for this CPU, in particular initialising the MMU so we 807 * can turn it on below. This is a call to C, which is OK, we're still 808 * running on the emergency stack. 809 */ 810 bl early_setup_secondary 811 812 /* 813 * The primary has initialized our kernel stack for us in the paca, grab 814 * it and put it in r1. We must *not* use it until we turn on the MMU 815 * below, because it may not be inside the RMO. 816 */ 817 ld r1, PACAKSAVE(r13) 818 819 /* Clear backchain so we get nice backtraces */ 820 li r7,0 821 mtlr r7 822 823 /* Mark interrupts soft and hard disabled (they might be enabled 824 * in the PACA when doing hotplug) 825 */ 826 li r7,IRQS_DISABLED 827 stb r7,PACAIRQSOFTMASK(r13) 828 li r0,PACA_IRQ_HARD_DIS 829 stb r0,PACAIRQHAPPENED(r13) 830 831 /* enable MMU and jump to start_secondary */ 832 LOAD_REG_ADDR(r3, start_secondary_prolog) 833 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 834 835 mtspr SPRN_SRR0,r3 836 mtspr SPRN_SRR1,r4 837 RFI_TO_KERNEL 838 b . /* prevent speculative execution */ 839 840/* 841 * Running with relocation on at this point. All we want to do is 842 * zero the stack back-chain pointer and get the TOC virtual address 843 * before going into C code. 844 */ 845start_secondary_prolog: 846 ld r2,PACATOC(r13) 847 li r3,0 848 std r3,0(r1) /* Zero the stack frame pointer */ 849 bl start_secondary 850 b . 851/* 852 * Reset stack pointer and call start_secondary 853 * to continue with online operation when woken up 854 * from cede in cpu offline. 855 */ 856_GLOBAL(start_secondary_resume) 857 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 858 li r3,0 859 std r3,0(r1) /* Zero the stack frame pointer */ 860 bl start_secondary 861 b . 862#endif 863 864/* 865 * This subroutine clobbers r11 and r12 866 */ 867enable_64b_mode: 868 mfmsr r11 /* grab the current MSR */ 869#ifdef CONFIG_PPC_BOOK3E 870 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 871 mtmsr r11 872#else /* CONFIG_PPC_BOOK3E */ 873 LOAD_REG_IMMEDIATE(r12, MSR_64BIT) 874 or r11,r11,r12 875 mtmsrd r11 876 isync 877#endif 878 blr 879 880/* 881 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 882 * by the toolchain). It computes the correct value for wherever we 883 * are running at the moment, using position-independent code. 884 * 885 * Note: The compiler constructs pointers using offsets from the 886 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 887 * the MMU is on we need our TOC to be a virtual address otherwise 888 * these pointers will be real addresses which may get stored and 889 * accessed later with the MMU on. We use tovirt() at the call 890 * sites to handle this. 891 */ 892_GLOBAL(relative_toc) 893 mflr r0 894 bcl 20,31,$+4 8950: mflr r11 896 ld r2,(p_toc - 0b)(r11) 897 add r2,r2,r11 898 mtlr r0 899 blr 900 901.balign 8 902p_toc: .8byte __toc_start + 0x8000 - 0b 903 904/* 905 * This is where the main kernel code starts. 906 */ 907__REF 908start_here_multiplatform: 909 /* set up the TOC */ 910 bl relative_toc 911 tovirt(r2,r2) 912 913 /* Clear out the BSS. It may have been done in prom_init, 914 * already but that's irrelevant since prom_init will soon 915 * be detached from the kernel completely. Besides, we need 916 * to clear it now for kexec-style entry. 917 */ 918 LOAD_REG_ADDR(r11,__bss_stop) 919 LOAD_REG_ADDR(r8,__bss_start) 920 sub r11,r11,r8 /* bss size */ 921 addi r11,r11,7 /* round up to an even double word */ 922 srdi. r11,r11,3 /* shift right by 3 */ 923 beq 4f 924 addi r8,r8,-8 925 li r0,0 926 mtctr r11 /* zero this many doublewords */ 9273: stdu r0,8(r8) 928 bdnz 3b 9294: 930 931#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 932 /* Setup OPAL entry */ 933 LOAD_REG_ADDR(r11, opal) 934 std r28,0(r11); 935 std r29,8(r11); 936#endif 937 938#ifndef CONFIG_PPC_BOOK3E 939 mfmsr r6 940 ori r6,r6,MSR_RI 941 mtmsrd r6 /* RI on */ 942#endif 943 944#ifdef CONFIG_RELOCATABLE 945 /* Save the physical address we're running at in kernstart_addr */ 946 LOAD_REG_ADDR(r4, kernstart_addr) 947 clrldi r0,r25,2 948 std r0,0(r4) 949#endif 950 951 /* set up a stack pointer */ 952 LOAD_REG_ADDR(r3,init_thread_union) 953 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE) 954 add r1,r3,r1 955 li r0,0 956 stdu r0,-STACK_FRAME_OVERHEAD(r1) 957 958 /* 959 * Do very early kernel initializations, including initial hash table 960 * and SLB setup before we turn on relocation. 961 */ 962 963 /* Restore parameters passed from prom_init/kexec */ 964 mr r3,r31 965 LOAD_REG_ADDR(r12, DOTSYM(early_setup)) 966 mtctr r12 967 bctrl /* also sets r13 and SPRG_PACA */ 968 969 LOAD_REG_ADDR(r3, start_here_common) 970 ld r4,PACAKMSR(r13) 971 mtspr SPRN_SRR0,r3 972 mtspr SPRN_SRR1,r4 973 RFI_TO_KERNEL 974 b . /* prevent speculative execution */ 975 976 /* This is where all platforms converge execution */ 977 978start_here_common: 979 /* relocation is on at this point */ 980 std r1,PACAKSAVE(r13) 981 982 /* Load the TOC (virtual address) */ 983 ld r2,PACATOC(r13) 984 985 /* Mark interrupts soft and hard disabled (they might be enabled 986 * in the PACA when doing hotplug) 987 */ 988 li r0,IRQS_DISABLED 989 stb r0,PACAIRQSOFTMASK(r13) 990 li r0,PACA_IRQ_HARD_DIS 991 stb r0,PACAIRQHAPPENED(r13) 992 993 /* Generic kernel entry */ 994 bl start_kernel 995 996 /* Not reached */ 9970: trap 998 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 999 .previous 1000 1001/* 1002 * We put a few things here that have to be page-aligned. 1003 * This stuff goes at the beginning of the bss, which is page-aligned. 1004 */ 1005 .section ".bss" 1006/* 1007 * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K. 1008 * We will need to find a better way to fix this 1009 */ 1010 .align 16 1011 1012 .globl swapper_pg_dir 1013swapper_pg_dir: 1014 .space PGD_TABLE_SIZE 1015 1016 .globl empty_zero_page 1017empty_zero_page: 1018 .space PAGE_SIZE 1019EXPORT_SYMBOL(empty_zero_page) 1020