1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the low-level support and setup for the 16 * PowerPC-64 platform, including trap and interrupt dispatch. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License 20 * as published by the Free Software Foundation; either version 21 * 2 of the License, or (at your option) any later version. 22 */ 23 24#include <linux/threads.h> 25#include <asm/reg.h> 26#include <asm/page.h> 27#include <asm/mmu.h> 28#include <asm/ppc_asm.h> 29#include <asm/asm-offsets.h> 30#include <asm/bug.h> 31#include <asm/cputable.h> 32#include <asm/setup.h> 33#include <asm/hvcall.h> 34#include <asm/iseries/lpar_map.h> 35#include <asm/thread_info.h> 36#include <asm/firmware.h> 37 38#define DO_SOFT_DISABLE 39 40/* 41 * We layout physical memory as follows: 42 * 0x0000 - 0x00ff : Secondary processor spin code 43 * 0x0100 - 0x2fff : pSeries Interrupt prologs 44 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs 45 * 0x6000 - 0x6fff : Initial (CPU0) segment table 46 * 0x7000 - 0x7fff : FWNMI data area 47 * 0x8000 - : Early init and support code 48 */ 49 50/* 51 * SPRG Usage 52 * 53 * Register Definition 54 * 55 * SPRG0 reserved for hypervisor 56 * SPRG1 temp - used to save gpr 57 * SPRG2 temp - used to save gpr 58 * SPRG3 virt addr of paca 59 */ 60 61/* 62 * Entering into this code we make the following assumptions: 63 * For pSeries: 64 * 1. The MMU is off & open firmware is running in real mode. 65 * 2. The kernel is entered at __start 66 * 67 * For iSeries: 68 * 1. The MMU is on (as it always is for iSeries) 69 * 2. The kernel is entered at system_reset_iSeries 70 */ 71 72 .text 73 .globl _stext 74_stext: 75_GLOBAL(__start) 76 /* NOP this out unconditionally */ 77BEGIN_FTR_SECTION 78 b .__start_initialization_multiplatform 79END_FTR_SECTION(0, 1) 80 81 /* Catch branch to 0 in real mode */ 82 trap 83 84 /* Secondary processors spin on this value until it goes to 1. */ 85 .globl __secondary_hold_spinloop 86__secondary_hold_spinloop: 87 .llong 0x0 88 89 /* Secondary processors write this value with their cpu # */ 90 /* after they enter the spin loop immediately below. */ 91 .globl __secondary_hold_acknowledge 92__secondary_hold_acknowledge: 93 .llong 0x0 94 95#ifdef CONFIG_PPC_ISERIES 96 /* 97 * At offset 0x20, there is a pointer to iSeries LPAR data. 98 * This is required by the hypervisor 99 */ 100 . = 0x20 101 .llong hvReleaseData-KERNELBASE 102#endif /* CONFIG_PPC_ISERIES */ 103 104 . = 0x60 105/* 106 * The following code is used on pSeries to hold secondary processors 107 * in a spin loop after they have been freed from OpenFirmware, but 108 * before the bulk of the kernel has been relocated. This code 109 * is relocated to physical address 0x60 before prom_init is run. 110 * All of it must fit below the first exception vector at 0x100. 111 */ 112_GLOBAL(__secondary_hold) 113 mfmsr r24 114 ori r24,r24,MSR_RI 115 mtmsrd r24 /* RI on */ 116 117 /* Grab our physical cpu number */ 118 mr r24,r3 119 120 /* Tell the master cpu we're here */ 121 /* Relocation is off & we are located at an address less */ 122 /* than 0x100, so only need to grab low order offset. */ 123 std r24,__secondary_hold_acknowledge@l(0) 124 sync 125 126 /* All secondary cpus wait here until told to start. */ 127100: ld r4,__secondary_hold_spinloop@l(0) 128 cmpdi 0,r4,1 129 bne 100b 130 131#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 132 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init) 133 mtctr r4 134 mr r3,r24 135 bctr 136#else 137 BUG_OPCODE 138#endif 139 140/* This value is used to mark exception frames on the stack. */ 141 .section ".toc","aw" 142exception_marker: 143 .tc ID_72656773_68657265[TC],0x7265677368657265 144 .text 145 146/* 147 * The following macros define the code that appears as 148 * the prologue to each of the exception handlers. They 149 * are split into two parts to allow a single kernel binary 150 * to be used for pSeries and iSeries. 151 * LOL. One day... - paulus 152 */ 153 154/* 155 * We make as much of the exception code common between native 156 * exception handlers (including pSeries LPAR) and iSeries LPAR 157 * implementations as possible. 158 */ 159 160/* 161 * This is the start of the interrupt handlers for pSeries 162 * This code runs with relocation off. 163 */ 164#define EX_R9 0 165#define EX_R10 8 166#define EX_R11 16 167#define EX_R12 24 168#define EX_R13 32 169#define EX_SRR0 40 170#define EX_DAR 48 171#define EX_DSISR 56 172#define EX_CCR 60 173#define EX_R3 64 174#define EX_LR 72 175 176/* 177 * We're short on space and time in the exception prolog, so we can't 178 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the 179 * low halfword of the address, but for Kdump we need the whole low 180 * word. 181 */ 182#ifdef CONFIG_CRASH_DUMP 183#define LOAD_HANDLER(reg, label) \ 184 oris reg,reg,(label)@h; /* virt addr of handler ... */ \ 185 ori reg,reg,(label)@l; /* .. and the rest */ 186#else 187#define LOAD_HANDLER(reg, label) \ 188 ori reg,reg,(label)@l; /* virt addr of handler ... */ 189#endif 190 191/* 192 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode. 193 * The firmware calls the registered system_reset_fwnmi and 194 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run 195 * a 32bit application at the time of the event. 196 * This firmware bug is present on POWER4 and JS20. 197 */ 198#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \ 199 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 200 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 201 std r10,area+EX_R10(r13); \ 202 std r11,area+EX_R11(r13); \ 203 std r12,area+EX_R12(r13); \ 204 mfspr r9,SPRN_SPRG1; \ 205 std r9,area+EX_R13(r13); \ 206 mfcr r9; \ 207 clrrdi r12,r13,32; /* get high part of &label */ \ 208 mfmsr r10; \ 209 /* force 64bit mode */ \ 210 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \ 211 rldimi r10,r11,61,0; /* insert into top 3 bits */ \ 212 /* done 64bit mode */ \ 213 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 214 LOAD_HANDLER(r12,label) \ 215 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 216 mtspr SPRN_SRR0,r12; \ 217 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 218 mtspr SPRN_SRR1,r10; \ 219 rfid; \ 220 b . /* prevent speculative execution */ 221 222#define EXCEPTION_PROLOG_PSERIES(area, label) \ 223 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 224 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 225 std r10,area+EX_R10(r13); \ 226 std r11,area+EX_R11(r13); \ 227 std r12,area+EX_R12(r13); \ 228 mfspr r9,SPRN_SPRG1; \ 229 std r9,area+EX_R13(r13); \ 230 mfcr r9; \ 231 clrrdi r12,r13,32; /* get high part of &label */ \ 232 mfmsr r10; \ 233 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 234 LOAD_HANDLER(r12,label) \ 235 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 236 mtspr SPRN_SRR0,r12; \ 237 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 238 mtspr SPRN_SRR1,r10; \ 239 rfid; \ 240 b . /* prevent speculative execution */ 241 242/* 243 * This is the start of the interrupt handlers for iSeries 244 * This code runs with relocation on. 245 */ 246#define EXCEPTION_PROLOG_ISERIES_1(area) \ 247 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 248 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 249 std r10,area+EX_R10(r13); \ 250 std r11,area+EX_R11(r13); \ 251 std r12,area+EX_R12(r13); \ 252 mfspr r9,SPRN_SPRG1; \ 253 std r9,area+EX_R13(r13); \ 254 mfcr r9 255 256#define EXCEPTION_PROLOG_ISERIES_2 \ 257 mfmsr r10; \ 258 ld r12,PACALPPACAPTR(r13); \ 259 ld r11,LPPACASRR0(r12); \ 260 ld r12,LPPACASRR1(r12); \ 261 ori r10,r10,MSR_RI; \ 262 mtmsrd r10,1 263 264/* 265 * The common exception prolog is used for all except a few exceptions 266 * such as a segment miss on a kernel address. We have to be prepared 267 * to take another exception from the point where we first touch the 268 * kernel stack onwards. 269 * 270 * On entry r13 points to the paca, r9-r13 are saved in the paca, 271 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 272 * SRR1, and relocation is on. 273 */ 274#define EXCEPTION_PROLOG_COMMON(n, area) \ 275 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 276 mr r10,r1; /* Save r1 */ \ 277 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 278 beq- 1f; \ 279 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 2801: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ 281 bge- cr1,bad_stack; /* abort if it is */ \ 282 std r9,_CCR(r1); /* save CR in stackframe */ \ 283 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 284 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 285 std r10,0(r1); /* make stack chain pointer */ \ 286 std r0,GPR0(r1); /* save r0 in stackframe */ \ 287 std r10,GPR1(r1); /* save r1 in stackframe */ \ 288 ACCOUNT_CPU_USER_ENTRY(r9, r10); \ 289 std r2,GPR2(r1); /* save r2 in stackframe */ \ 290 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 291 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 292 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 293 ld r10,area+EX_R10(r13); \ 294 std r9,GPR9(r1); \ 295 std r10,GPR10(r1); \ 296 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 297 ld r10,area+EX_R12(r13); \ 298 ld r11,area+EX_R13(r13); \ 299 std r9,GPR11(r1); \ 300 std r10,GPR12(r1); \ 301 std r11,GPR13(r1); \ 302 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 303 mflr r9; /* save LR in stackframe */ \ 304 std r9,_LINK(r1); \ 305 mfctr r10; /* save CTR in stackframe */ \ 306 std r10,_CTR(r1); \ 307 lbz r10,PACASOFTIRQEN(r13); \ 308 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 309 std r10,SOFTE(r1); \ 310 std r11,_XER(r1); \ 311 li r9,(n)+1; \ 312 std r9,_TRAP(r1); /* set trap number */ \ 313 li r10,0; \ 314 ld r11,exception_marker@toc(r2); \ 315 std r10,RESULT(r1); /* clear regs->result */ \ 316 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 317 318/* 319 * Exception vectors. 320 */ 321#define STD_EXCEPTION_PSERIES(n, label) \ 322 . = n; \ 323 .globl label##_pSeries; \ 324label##_pSeries: \ 325 HMT_MEDIUM; \ 326 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 327 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 328 329#define HSTD_EXCEPTION_PSERIES(n, label) \ 330 . = n; \ 331 .globl label##_pSeries; \ 332label##_pSeries: \ 333 HMT_MEDIUM; \ 334 mtspr SPRN_SPRG1,r20; /* save r20 */ \ 335 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \ 336 mtspr SPRN_SRR0,r20; \ 337 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \ 338 mtspr SPRN_SRR1,r20; \ 339 mfspr r20,SPRN_SPRG1; /* restore r20 */ \ 340 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 341 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 342 343 344#define MASKABLE_EXCEPTION_PSERIES(n, label) \ 345 . = n; \ 346 .globl label##_pSeries; \ 347label##_pSeries: \ 348 HMT_MEDIUM; \ 349 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 350 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 351 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ 352 std r10,PACA_EXGEN+EX_R10(r13); \ 353 lbz r10,PACASOFTIRQEN(r13); \ 354 mfcr r9; \ 355 cmpwi r10,0; \ 356 beq masked_interrupt; \ 357 mfspr r10,SPRN_SPRG1; \ 358 std r10,PACA_EXGEN+EX_R13(r13); \ 359 std r11,PACA_EXGEN+EX_R11(r13); \ 360 std r12,PACA_EXGEN+EX_R12(r13); \ 361 clrrdi r12,r13,32; /* get high part of &label */ \ 362 mfmsr r10; \ 363 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 364 LOAD_HANDLER(r12,label##_common) \ 365 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 366 mtspr SPRN_SRR0,r12; \ 367 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 368 mtspr SPRN_SRR1,r10; \ 369 rfid; \ 370 b . /* prevent speculative execution */ 371 372#define STD_EXCEPTION_ISERIES(n, label, area) \ 373 .globl label##_iSeries; \ 374label##_iSeries: \ 375 HMT_MEDIUM; \ 376 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 377 EXCEPTION_PROLOG_ISERIES_1(area); \ 378 EXCEPTION_PROLOG_ISERIES_2; \ 379 b label##_common 380 381#define MASKABLE_EXCEPTION_ISERIES(n, label) \ 382 .globl label##_iSeries; \ 383label##_iSeries: \ 384 HMT_MEDIUM; \ 385 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 386 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ 387 lbz r10,PACASOFTIRQEN(r13); \ 388 cmpwi 0,r10,0; \ 389 beq- label##_iSeries_masked; \ 390 EXCEPTION_PROLOG_ISERIES_2; \ 391 b label##_common; \ 392 393#ifdef CONFIG_PPC_ISERIES 394#define DISABLE_INTS \ 395 li r11,0; \ 396 stb r11,PACASOFTIRQEN(r13); \ 397BEGIN_FW_FTR_SECTION; \ 398 stb r11,PACAHARDIRQEN(r13); \ 399END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \ 400BEGIN_FW_FTR_SECTION; \ 401 mfmsr r10; \ 402 ori r10,r10,MSR_EE; \ 403 mtmsrd r10,1; \ 404END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 405 406#else 407#define DISABLE_INTS \ 408 li r11,0; \ 409 stb r11,PACASOFTIRQEN(r13); \ 410 stb r11,PACAHARDIRQEN(r13) 411 412#endif /* CONFIG_PPC_ISERIES */ 413 414#define ENABLE_INTS \ 415 ld r12,_MSR(r1); \ 416 mfmsr r11; \ 417 rlwimi r11,r12,0,MSR_EE; \ 418 mtmsrd r11,1 419 420#define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 421 .align 7; \ 422 .globl label##_common; \ 423label##_common: \ 424 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 425 DISABLE_INTS; \ 426 bl .save_nvgprs; \ 427 addi r3,r1,STACK_FRAME_OVERHEAD; \ 428 bl hdlr; \ 429 b .ret_from_except 430 431/* 432 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 433 * in the idle task and therefore need the special idle handling. 434 */ 435#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \ 436 .align 7; \ 437 .globl label##_common; \ 438label##_common: \ 439 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 440 FINISH_NAP; \ 441 DISABLE_INTS; \ 442 bl .save_nvgprs; \ 443 addi r3,r1,STACK_FRAME_OVERHEAD; \ 444 bl hdlr; \ 445 b .ret_from_except 446 447#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ 448 .align 7; \ 449 .globl label##_common; \ 450label##_common: \ 451 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 452 FINISH_NAP; \ 453 DISABLE_INTS; \ 454 bl .ppc64_runlatch_on; \ 455 addi r3,r1,STACK_FRAME_OVERHEAD; \ 456 bl hdlr; \ 457 b .ret_from_except_lite 458 459/* 460 * When the idle code in power4_idle puts the CPU into NAP mode, 461 * it has to do so in a loop, and relies on the external interrupt 462 * and decrementer interrupt entry code to get it out of the loop. 463 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 464 * to signal that it is in the loop and needs help to get out. 465 */ 466#ifdef CONFIG_PPC_970_NAP 467#define FINISH_NAP \ 468BEGIN_FTR_SECTION \ 469 clrrdi r11,r1,THREAD_SHIFT; \ 470 ld r9,TI_LOCAL_FLAGS(r11); \ 471 andi. r10,r9,_TLF_NAPPING; \ 472 bnel power4_fixup_nap; \ 473END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 474#else 475#define FINISH_NAP 476#endif 477 478/* 479 * Start of pSeries system interrupt routines 480 */ 481 . = 0x100 482 .globl __start_interrupts 483__start_interrupts: 484 485 STD_EXCEPTION_PSERIES(0x100, system_reset) 486 487 . = 0x200 488_machine_check_pSeries: 489 HMT_MEDIUM 490 mtspr SPRN_SPRG1,r13 /* save r13 */ 491 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 492 493 . = 0x300 494 .globl data_access_pSeries 495data_access_pSeries: 496 HMT_MEDIUM 497 mtspr SPRN_SPRG1,r13 498BEGIN_FTR_SECTION 499 mtspr SPRN_SPRG2,r12 500 mfspr r13,SPRN_DAR 501 mfspr r12,SPRN_DSISR 502 srdi r13,r13,60 503 rlwimi r13,r12,16,0x20 504 mfcr r12 505 cmpwi r13,0x2c 506 beq do_stab_bolted_pSeries 507 mtcrf 0x80,r12 508 mfspr r12,SPRN_SPRG2 509END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 510 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 511 512 . = 0x380 513 .globl data_access_slb_pSeries 514data_access_slb_pSeries: 515 HMT_MEDIUM 516 mtspr SPRN_SPRG1,r13 517 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 518 std r3,PACA_EXSLB+EX_R3(r13) 519 mfspr r3,SPRN_DAR 520 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 521 mfcr r9 522#ifdef __DISABLED__ 523 /* Keep that around for when we re-implement dynamic VSIDs */ 524 cmpdi r3,0 525 bge slb_miss_user_pseries 526#endif /* __DISABLED__ */ 527 std r10,PACA_EXSLB+EX_R10(r13) 528 std r11,PACA_EXSLB+EX_R11(r13) 529 std r12,PACA_EXSLB+EX_R12(r13) 530 mfspr r10,SPRN_SPRG1 531 std r10,PACA_EXSLB+EX_R13(r13) 532 mfspr r12,SPRN_SRR1 /* and SRR1 */ 533 b .slb_miss_realmode /* Rel. branch works in real mode */ 534 535 STD_EXCEPTION_PSERIES(0x400, instruction_access) 536 537 . = 0x480 538 .globl instruction_access_slb_pSeries 539instruction_access_slb_pSeries: 540 HMT_MEDIUM 541 mtspr SPRN_SPRG1,r13 542 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 543 std r3,PACA_EXSLB+EX_R3(r13) 544 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 545 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 546 mfcr r9 547#ifdef __DISABLED__ 548 /* Keep that around for when we re-implement dynamic VSIDs */ 549 cmpdi r3,0 550 bge slb_miss_user_pseries 551#endif /* __DISABLED__ */ 552 std r10,PACA_EXSLB+EX_R10(r13) 553 std r11,PACA_EXSLB+EX_R11(r13) 554 std r12,PACA_EXSLB+EX_R12(r13) 555 mfspr r10,SPRN_SPRG1 556 std r10,PACA_EXSLB+EX_R13(r13) 557 mfspr r12,SPRN_SRR1 /* and SRR1 */ 558 b .slb_miss_realmode /* Rel. branch works in real mode */ 559 560 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt) 561 STD_EXCEPTION_PSERIES(0x600, alignment) 562 STD_EXCEPTION_PSERIES(0x700, program_check) 563 STD_EXCEPTION_PSERIES(0x800, fp_unavailable) 564 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer) 565 STD_EXCEPTION_PSERIES(0xa00, trap_0a) 566 STD_EXCEPTION_PSERIES(0xb00, trap_0b) 567 568 . = 0xc00 569 .globl system_call_pSeries 570system_call_pSeries: 571 HMT_MEDIUM 572 mr r9,r13 573 mfmsr r10 574 mfspr r13,SPRN_SPRG3 575 mfspr r11,SPRN_SRR0 576 clrrdi r12,r13,32 577 oris r12,r12,system_call_common@h 578 ori r12,r12,system_call_common@l 579 mtspr SPRN_SRR0,r12 580 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 581 mfspr r12,SPRN_SRR1 582 mtspr SPRN_SRR1,r10 583 rfid 584 b . /* prevent speculative execution */ 585 586 STD_EXCEPTION_PSERIES(0xd00, single_step) 587 STD_EXCEPTION_PSERIES(0xe00, trap_0e) 588 589 /* We need to deal with the Altivec unavailable exception 590 * here which is at 0xf20, thus in the middle of the 591 * prolog code of the PerformanceMonitor one. A little 592 * trickery is thus necessary 593 */ 594 . = 0xf00 595 b performance_monitor_pSeries 596 597 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) 598 599#ifdef CONFIG_CBE_RAS 600 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) 601#endif /* CONFIG_CBE_RAS */ 602 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) 603#ifdef CONFIG_CBE_RAS 604 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance) 605#endif /* CONFIG_CBE_RAS */ 606 STD_EXCEPTION_PSERIES(0x1700, altivec_assist) 607#ifdef CONFIG_CBE_RAS 608 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal) 609#endif /* CONFIG_CBE_RAS */ 610 611 . = 0x3000 612 613/*** pSeries interrupt support ***/ 614 615 /* moved from 0xf00 */ 616 STD_EXCEPTION_PSERIES(., performance_monitor) 617 618/* 619 * An interrupt came in while soft-disabled; clear EE in SRR1, 620 * clear paca->hard_enabled and return. 621 */ 622masked_interrupt: 623 stb r10,PACAHARDIRQEN(r13) 624 mtcrf 0x80,r9 625 ld r9,PACA_EXGEN+EX_R9(r13) 626 mfspr r10,SPRN_SRR1 627 rldicl r10,r10,48,1 /* clear MSR_EE */ 628 rotldi r10,r10,16 629 mtspr SPRN_SRR1,r10 630 ld r10,PACA_EXGEN+EX_R10(r13) 631 mfspr r13,SPRN_SPRG1 632 rfid 633 b . 634 635 .align 7 636do_stab_bolted_pSeries: 637 mtcrf 0x80,r12 638 mfspr r12,SPRN_SPRG2 639 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) 640 641/* 642 * We have some room here we use that to put 643 * the peries slb miss user trampoline code so it's reasonably 644 * away from slb_miss_user_common to avoid problems with rfid 645 * 646 * This is used for when the SLB miss handler has to go virtual, 647 * which doesn't happen for now anymore but will once we re-implement 648 * dynamic VSIDs for shared page tables 649 */ 650#ifdef __DISABLED__ 651slb_miss_user_pseries: 652 std r10,PACA_EXGEN+EX_R10(r13) 653 std r11,PACA_EXGEN+EX_R11(r13) 654 std r12,PACA_EXGEN+EX_R12(r13) 655 mfspr r10,SPRG1 656 ld r11,PACA_EXSLB+EX_R9(r13) 657 ld r12,PACA_EXSLB+EX_R3(r13) 658 std r10,PACA_EXGEN+EX_R13(r13) 659 std r11,PACA_EXGEN+EX_R9(r13) 660 std r12,PACA_EXGEN+EX_R3(r13) 661 clrrdi r12,r13,32 662 mfmsr r10 663 mfspr r11,SRR0 /* save SRR0 */ 664 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ 665 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 666 mtspr SRR0,r12 667 mfspr r12,SRR1 /* and SRR1 */ 668 mtspr SRR1,r10 669 rfid 670 b . /* prevent spec. execution */ 671#endif /* __DISABLED__ */ 672 673/* 674 * Vectors for the FWNMI option. Share common code. 675 */ 676 .globl system_reset_fwnmi 677 .align 7 678system_reset_fwnmi: 679 HMT_MEDIUM 680 mtspr SPRN_SPRG1,r13 /* save r13 */ 681 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common) 682 683 .globl machine_check_fwnmi 684 .align 7 685machine_check_fwnmi: 686 HMT_MEDIUM 687 mtspr SPRN_SPRG1,r13 /* save r13 */ 688 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common) 689 690#ifdef CONFIG_PPC_ISERIES 691/*** ISeries-LPAR interrupt handlers ***/ 692 693 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) 694 695 .globl data_access_iSeries 696data_access_iSeries: 697 mtspr SPRN_SPRG1,r13 698BEGIN_FTR_SECTION 699 mtspr SPRN_SPRG2,r12 700 mfspr r13,SPRN_DAR 701 mfspr r12,SPRN_DSISR 702 srdi r13,r13,60 703 rlwimi r13,r12,16,0x20 704 mfcr r12 705 cmpwi r13,0x2c 706 beq .do_stab_bolted_iSeries 707 mtcrf 0x80,r12 708 mfspr r12,SPRN_SPRG2 709END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 710 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) 711 EXCEPTION_PROLOG_ISERIES_2 712 b data_access_common 713 714.do_stab_bolted_iSeries: 715 mtcrf 0x80,r12 716 mfspr r12,SPRN_SPRG2 717 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) 718 EXCEPTION_PROLOG_ISERIES_2 719 b .do_stab_bolted 720 721 .globl data_access_slb_iSeries 722data_access_slb_iSeries: 723 mtspr SPRN_SPRG1,r13 /* save r13 */ 724 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 725 std r3,PACA_EXSLB+EX_R3(r13) 726 mfspr r3,SPRN_DAR 727 std r9,PACA_EXSLB+EX_R9(r13) 728 mfcr r9 729#ifdef __DISABLED__ 730 cmpdi r3,0 731 bge slb_miss_user_iseries 732#endif 733 std r10,PACA_EXSLB+EX_R10(r13) 734 std r11,PACA_EXSLB+EX_R11(r13) 735 std r12,PACA_EXSLB+EX_R12(r13) 736 mfspr r10,SPRN_SPRG1 737 std r10,PACA_EXSLB+EX_R13(r13) 738 ld r12,PACALPPACAPTR(r13) 739 ld r12,LPPACASRR1(r12) 740 b .slb_miss_realmode 741 742 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) 743 744 .globl instruction_access_slb_iSeries 745instruction_access_slb_iSeries: 746 mtspr SPRN_SPRG1,r13 /* save r13 */ 747 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 748 std r3,PACA_EXSLB+EX_R3(r13) 749 ld r3,PACALPPACAPTR(r13) 750 ld r3,LPPACASRR0(r3) /* get SRR0 value */ 751 std r9,PACA_EXSLB+EX_R9(r13) 752 mfcr r9 753#ifdef __DISABLED__ 754 cmpdi r3,0 755 bge .slb_miss_user_iseries 756#endif 757 std r10,PACA_EXSLB+EX_R10(r13) 758 std r11,PACA_EXSLB+EX_R11(r13) 759 std r12,PACA_EXSLB+EX_R12(r13) 760 mfspr r10,SPRN_SPRG1 761 std r10,PACA_EXSLB+EX_R13(r13) 762 ld r12,PACALPPACAPTR(r13) 763 ld r12,LPPACASRR1(r12) 764 b .slb_miss_realmode 765 766#ifdef __DISABLED__ 767slb_miss_user_iseries: 768 std r10,PACA_EXGEN+EX_R10(r13) 769 std r11,PACA_EXGEN+EX_R11(r13) 770 std r12,PACA_EXGEN+EX_R12(r13) 771 mfspr r10,SPRG1 772 ld r11,PACA_EXSLB+EX_R9(r13) 773 ld r12,PACA_EXSLB+EX_R3(r13) 774 std r10,PACA_EXGEN+EX_R13(r13) 775 std r11,PACA_EXGEN+EX_R9(r13) 776 std r12,PACA_EXGEN+EX_R3(r13) 777 EXCEPTION_PROLOG_ISERIES_2 778 b slb_miss_user_common 779#endif 780 781 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) 782 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) 783 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) 784 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) 785 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) 786 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) 787 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) 788 789 .globl system_call_iSeries 790system_call_iSeries: 791 mr r9,r13 792 mfspr r13,SPRN_SPRG3 793 EXCEPTION_PROLOG_ISERIES_2 794 b system_call_common 795 796 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) 797 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) 798 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) 799 800 .globl system_reset_iSeries 801system_reset_iSeries: 802 mfspr r13,SPRN_SPRG3 /* Get paca address */ 803 mfmsr r24 804 ori r24,r24,MSR_RI 805 mtmsrd r24 /* RI on */ 806 lhz r24,PACAPACAINDEX(r13) /* Get processor # */ 807 cmpwi 0,r24,0 /* Are we processor 0? */ 808 beq .__start_initialization_iSeries /* Start up the first processor */ 809 mfspr r4,SPRN_CTRLF 810 li r5,CTRL_RUNLATCH /* Turn off the run light */ 811 andc r4,r4,r5 812 mtspr SPRN_CTRLT,r4 813 8141: 815 HMT_LOW 816#ifdef CONFIG_SMP 817 lbz r23,PACAPROCSTART(r13) /* Test if this processor 818 * should start */ 819 sync 820 LOAD_REG_IMMEDIATE(r3,current_set) 821 sldi r28,r24,3 /* get current_set[cpu#] */ 822 ldx r3,r3,r28 823 addi r1,r3,THREAD_SIZE 824 subi r1,r1,STACK_FRAME_OVERHEAD 825 826 cmpwi 0,r23,0 827 beq iSeries_secondary_smp_loop /* Loop until told to go */ 828 bne __secondary_start /* Loop until told to go */ 829iSeries_secondary_smp_loop: 830 /* Let the Hypervisor know we are alive */ 831 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ 832 lis r3,0x8002 833 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ 834#else /* CONFIG_SMP */ 835 /* Yield the processor. This is required for non-SMP kernels 836 which are running on multi-threaded machines. */ 837 lis r3,0x8000 838 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ 839 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ 840 li r4,0 /* "yield timed" */ 841 li r5,-1 /* "yield forever" */ 842#endif /* CONFIG_SMP */ 843 li r0,-1 /* r0=-1 indicates a Hypervisor call */ 844 sc /* Invoke the hypervisor via a system call */ 845 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ 846 b 1b /* If SMP not configured, secondaries 847 * loop forever */ 848 849decrementer_iSeries_masked: 850 /* We may not have a valid TOC pointer in here. */ 851 li r11,1 852 ld r12,PACALPPACAPTR(r13) 853 stb r11,LPPACADECRINT(r12) 854 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy) 855 lwz r12,0(r12) 856 mtspr SPRN_DEC,r12 857 /* fall through */ 858 859hardware_interrupt_iSeries_masked: 860 mtcrf 0x80,r9 /* Restore regs */ 861 ld r12,PACALPPACAPTR(r13) 862 ld r11,LPPACASRR0(r12) 863 ld r12,LPPACASRR1(r12) 864 mtspr SPRN_SRR0,r11 865 mtspr SPRN_SRR1,r12 866 ld r9,PACA_EXGEN+EX_R9(r13) 867 ld r10,PACA_EXGEN+EX_R10(r13) 868 ld r11,PACA_EXGEN+EX_R11(r13) 869 ld r12,PACA_EXGEN+EX_R12(r13) 870 ld r13,PACA_EXGEN+EX_R13(r13) 871 rfid 872 b . /* prevent speculative execution */ 873#endif /* CONFIG_PPC_ISERIES */ 874 875/*** Common interrupt handlers ***/ 876 877 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) 878 879 /* 880 * Machine check is different because we use a different 881 * save area: PACA_EXMC instead of PACA_EXGEN. 882 */ 883 .align 7 884 .globl machine_check_common 885machine_check_common: 886 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 887 FINISH_NAP 888 DISABLE_INTS 889 bl .save_nvgprs 890 addi r3,r1,STACK_FRAME_OVERHEAD 891 bl .machine_check_exception 892 b .ret_from_except 893 894 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) 895 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) 896 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) 897 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) 898 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) 899 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) 900 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) 901#ifdef CONFIG_ALTIVEC 902 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) 903#else 904 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) 905#endif 906#ifdef CONFIG_CBE_RAS 907 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) 908 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) 909 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) 910#endif /* CONFIG_CBE_RAS */ 911 912/* 913 * Here we have detected that the kernel stack pointer is bad. 914 * R9 contains the saved CR, r13 points to the paca, 915 * r10 contains the (bad) kernel stack pointer, 916 * r11 and r12 contain the saved SRR0 and SRR1. 917 * We switch to using an emergency stack, save the registers there, 918 * and call kernel_bad_stack(), which panics. 919 */ 920bad_stack: 921 ld r1,PACAEMERGSP(r13) 922 subi r1,r1,64+INT_FRAME_SIZE 923 std r9,_CCR(r1) 924 std r10,GPR1(r1) 925 std r11,_NIP(r1) 926 std r12,_MSR(r1) 927 mfspr r11,SPRN_DAR 928 mfspr r12,SPRN_DSISR 929 std r11,_DAR(r1) 930 std r12,_DSISR(r1) 931 mflr r10 932 mfctr r11 933 mfxer r12 934 std r10,_LINK(r1) 935 std r11,_CTR(r1) 936 std r12,_XER(r1) 937 SAVE_GPR(0,r1) 938 SAVE_GPR(2,r1) 939 SAVE_4GPRS(3,r1) 940 SAVE_2GPRS(7,r1) 941 SAVE_10GPRS(12,r1) 942 SAVE_10GPRS(22,r1) 943 addi r11,r1,INT_FRAME_SIZE 944 std r11,0(r1) 945 li r12,0 946 std r12,0(r11) 947 ld r2,PACATOC(r13) 9481: addi r3,r1,STACK_FRAME_OVERHEAD 949 bl .kernel_bad_stack 950 b 1b 951 952/* 953 * Return from an exception with minimal checks. 954 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. 955 * If interrupts have been enabled, or anything has been 956 * done that might have changed the scheduling status of 957 * any task or sent any task a signal, you should use 958 * ret_from_except or ret_from_except_lite instead of this. 959 */ 960fast_exc_return_irq: /* restores irq state too */ 961 ld r3,SOFTE(r1) 962 ld r12,_MSR(r1) 963 stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */ 964 rldicl r4,r12,49,63 /* get MSR_EE to LSB */ 965 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ 966 b 1f 967 968 .globl fast_exception_return 969fast_exception_return: 970 ld r12,_MSR(r1) 9711: ld r11,_NIP(r1) 972 andi. r3,r12,MSR_RI /* check if RI is set */ 973 beq- unrecov_fer 974 975#ifdef CONFIG_VIRT_CPU_ACCOUNTING 976 andi. r3,r12,MSR_PR 977 beq 2f 978 ACCOUNT_CPU_USER_EXIT(r3, r4) 9792: 980#endif 981 982 ld r3,_CCR(r1) 983 ld r4,_LINK(r1) 984 ld r5,_CTR(r1) 985 ld r6,_XER(r1) 986 mtcr r3 987 mtlr r4 988 mtctr r5 989 mtxer r6 990 REST_GPR(0, r1) 991 REST_8GPRS(2, r1) 992 993 mfmsr r10 994 rldicl r10,r10,48,1 /* clear EE */ 995 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ 996 mtmsrd r10,1 997 998 mtspr SPRN_SRR1,r12 999 mtspr SPRN_SRR0,r11 1000 REST_4GPRS(10, r1) 1001 ld r1,GPR1(r1) 1002 rfid 1003 b . /* prevent speculative execution */ 1004 1005unrecov_fer: 1006 bl .save_nvgprs 10071: addi r3,r1,STACK_FRAME_OVERHEAD 1008 bl .unrecoverable_exception 1009 b 1b 1010 1011/* 1012 * Here r13 points to the paca, r9 contains the saved CR, 1013 * SRR0 and SRR1 are saved in r11 and r12, 1014 * r9 - r13 are saved in paca->exgen. 1015 */ 1016 .align 7 1017 .globl data_access_common 1018data_access_common: 1019 mfspr r10,SPRN_DAR 1020 std r10,PACA_EXGEN+EX_DAR(r13) 1021 mfspr r10,SPRN_DSISR 1022 stw r10,PACA_EXGEN+EX_DSISR(r13) 1023 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 1024 ld r3,PACA_EXGEN+EX_DAR(r13) 1025 lwz r4,PACA_EXGEN+EX_DSISR(r13) 1026 li r5,0x300 1027 b .do_hash_page /* Try to handle as hpte fault */ 1028 1029 .align 7 1030 .globl instruction_access_common 1031instruction_access_common: 1032 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 1033 ld r3,_NIP(r1) 1034 andis. r4,r12,0x5820 1035 li r5,0x400 1036 b .do_hash_page /* Try to handle as hpte fault */ 1037 1038/* 1039 * Here is the common SLB miss user that is used when going to virtual 1040 * mode for SLB misses, that is currently not used 1041 */ 1042#ifdef __DISABLED__ 1043 .align 7 1044 .globl slb_miss_user_common 1045slb_miss_user_common: 1046 mflr r10 1047 std r3,PACA_EXGEN+EX_DAR(r13) 1048 stw r9,PACA_EXGEN+EX_CCR(r13) 1049 std r10,PACA_EXGEN+EX_LR(r13) 1050 std r11,PACA_EXGEN+EX_SRR0(r13) 1051 bl .slb_allocate_user 1052 1053 ld r10,PACA_EXGEN+EX_LR(r13) 1054 ld r3,PACA_EXGEN+EX_R3(r13) 1055 lwz r9,PACA_EXGEN+EX_CCR(r13) 1056 ld r11,PACA_EXGEN+EX_SRR0(r13) 1057 mtlr r10 1058 beq- slb_miss_fault 1059 1060 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 1061 beq- unrecov_user_slb 1062 mfmsr r10 1063 1064.machine push 1065.machine "power4" 1066 mtcrf 0x80,r9 1067.machine pop 1068 1069 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ 1070 mtmsrd r10,1 1071 1072 mtspr SRR0,r11 1073 mtspr SRR1,r12 1074 1075 ld r9,PACA_EXGEN+EX_R9(r13) 1076 ld r10,PACA_EXGEN+EX_R10(r13) 1077 ld r11,PACA_EXGEN+EX_R11(r13) 1078 ld r12,PACA_EXGEN+EX_R12(r13) 1079 ld r13,PACA_EXGEN+EX_R13(r13) 1080 rfid 1081 b . 1082 1083slb_miss_fault: 1084 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) 1085 ld r4,PACA_EXGEN+EX_DAR(r13) 1086 li r5,0 1087 std r4,_DAR(r1) 1088 std r5,_DSISR(r1) 1089 b handle_page_fault 1090 1091unrecov_user_slb: 1092 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) 1093 DISABLE_INTS 1094 bl .save_nvgprs 10951: addi r3,r1,STACK_FRAME_OVERHEAD 1096 bl .unrecoverable_exception 1097 b 1b 1098 1099#endif /* __DISABLED__ */ 1100 1101 1102/* 1103 * r13 points to the PACA, r9 contains the saved CR, 1104 * r12 contain the saved SRR1, SRR0 is still ready for return 1105 * r3 has the faulting address 1106 * r9 - r13 are saved in paca->exslb. 1107 * r3 is saved in paca->slb_r3 1108 * We assume we aren't going to take any exceptions during this procedure. 1109 */ 1110_GLOBAL(slb_miss_realmode) 1111 mflr r10 1112 1113 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 1114 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 1115 1116 bl .slb_allocate_realmode 1117 1118 /* All done -- return from exception. */ 1119 1120 ld r10,PACA_EXSLB+EX_LR(r13) 1121 ld r3,PACA_EXSLB+EX_R3(r13) 1122 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 1123#ifdef CONFIG_PPC_ISERIES 1124BEGIN_FW_FTR_SECTION 1125 ld r11,PACALPPACAPTR(r13) 1126 ld r11,LPPACASRR0(r11) /* get SRR0 value */ 1127END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1128#endif /* CONFIG_PPC_ISERIES */ 1129 1130 mtlr r10 1131 1132 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 1133 beq- unrecov_slb 1134 1135.machine push 1136.machine "power4" 1137 mtcrf 0x80,r9 1138 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 1139.machine pop 1140 1141#ifdef CONFIG_PPC_ISERIES 1142BEGIN_FW_FTR_SECTION 1143 mtspr SPRN_SRR0,r11 1144 mtspr SPRN_SRR1,r12 1145END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1146#endif /* CONFIG_PPC_ISERIES */ 1147 ld r9,PACA_EXSLB+EX_R9(r13) 1148 ld r10,PACA_EXSLB+EX_R10(r13) 1149 ld r11,PACA_EXSLB+EX_R11(r13) 1150 ld r12,PACA_EXSLB+EX_R12(r13) 1151 ld r13,PACA_EXSLB+EX_R13(r13) 1152 rfid 1153 b . /* prevent speculative execution */ 1154 1155unrecov_slb: 1156 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 1157 DISABLE_INTS 1158 bl .save_nvgprs 11591: addi r3,r1,STACK_FRAME_OVERHEAD 1160 bl .unrecoverable_exception 1161 b 1b 1162 1163 .align 7 1164 .globl hardware_interrupt_common 1165 .globl hardware_interrupt_entry 1166hardware_interrupt_common: 1167 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) 1168 FINISH_NAP 1169hardware_interrupt_entry: 1170 DISABLE_INTS 1171 bl .ppc64_runlatch_on 1172 addi r3,r1,STACK_FRAME_OVERHEAD 1173 bl .do_IRQ 1174 b .ret_from_except_lite 1175 1176#ifdef CONFIG_PPC_970_NAP 1177power4_fixup_nap: 1178 andc r9,r9,r10 1179 std r9,TI_LOCAL_FLAGS(r11) 1180 ld r10,_LINK(r1) /* make idle task do the */ 1181 std r10,_NIP(r1) /* equivalent of a blr */ 1182 blr 1183#endif 1184 1185 .align 7 1186 .globl alignment_common 1187alignment_common: 1188 mfspr r10,SPRN_DAR 1189 std r10,PACA_EXGEN+EX_DAR(r13) 1190 mfspr r10,SPRN_DSISR 1191 stw r10,PACA_EXGEN+EX_DSISR(r13) 1192 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 1193 ld r3,PACA_EXGEN+EX_DAR(r13) 1194 lwz r4,PACA_EXGEN+EX_DSISR(r13) 1195 std r3,_DAR(r1) 1196 std r4,_DSISR(r1) 1197 bl .save_nvgprs 1198 addi r3,r1,STACK_FRAME_OVERHEAD 1199 ENABLE_INTS 1200 bl .alignment_exception 1201 b .ret_from_except 1202 1203 .align 7 1204 .globl program_check_common 1205program_check_common: 1206 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 1207 bl .save_nvgprs 1208 addi r3,r1,STACK_FRAME_OVERHEAD 1209 ENABLE_INTS 1210 bl .program_check_exception 1211 b .ret_from_except 1212 1213 .align 7 1214 .globl fp_unavailable_common 1215fp_unavailable_common: 1216 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 1217 bne 1f /* if from user, just load it up */ 1218 bl .save_nvgprs 1219 addi r3,r1,STACK_FRAME_OVERHEAD 1220 ENABLE_INTS 1221 bl .kernel_fp_unavailable_exception 1222 BUG_OPCODE 12231: b .load_up_fpu 1224 1225 .align 7 1226 .globl altivec_unavailable_common 1227altivec_unavailable_common: 1228 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1229#ifdef CONFIG_ALTIVEC 1230BEGIN_FTR_SECTION 1231 bne .load_up_altivec /* if from user, just load it up */ 1232END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1233#endif 1234 bl .save_nvgprs 1235 addi r3,r1,STACK_FRAME_OVERHEAD 1236 ENABLE_INTS 1237 bl .altivec_unavailable_exception 1238 b .ret_from_except 1239 1240#ifdef CONFIG_ALTIVEC 1241/* 1242 * load_up_altivec(unused, unused, tsk) 1243 * Disable VMX for the task which had it previously, 1244 * and save its vector registers in its thread_struct. 1245 * Enables the VMX for use in the kernel on return. 1246 * On SMP we know the VMX is free, since we give it up every 1247 * switch (ie, no lazy save of the vector registers). 1248 * On entry: r13 == 'current' && last_task_used_altivec != 'current' 1249 */ 1250_STATIC(load_up_altivec) 1251 mfmsr r5 /* grab the current MSR */ 1252 oris r5,r5,MSR_VEC@h 1253 mtmsrd r5 /* enable use of VMX now */ 1254 isync 1255 1256/* 1257 * For SMP, we don't do lazy VMX switching because it just gets too 1258 * horrendously complex, especially when a task switches from one CPU 1259 * to another. Instead we call giveup_altvec in switch_to. 1260 * VRSAVE isn't dealt with here, that is done in the normal context 1261 * switch code. Note that we could rely on vrsave value to eventually 1262 * avoid saving all of the VREGs here... 1263 */ 1264#ifndef CONFIG_SMP 1265 ld r3,last_task_used_altivec@got(r2) 1266 ld r4,0(r3) 1267 cmpdi 0,r4,0 1268 beq 1f 1269 /* Save VMX state to last_task_used_altivec's THREAD struct */ 1270 addi r4,r4,THREAD 1271 SAVE_32VRS(0,r5,r4) 1272 mfvscr vr0 1273 li r10,THREAD_VSCR 1274 stvx vr0,r10,r4 1275 /* Disable VMX for last_task_used_altivec */ 1276 ld r5,PT_REGS(r4) 1277 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1278 lis r6,MSR_VEC@h 1279 andc r4,r4,r6 1280 std r4,_MSR-STACK_FRAME_OVERHEAD(r5) 12811: 1282#endif /* CONFIG_SMP */ 1283 /* Hack: if we get an altivec unavailable trap with VRSAVE 1284 * set to all zeros, we assume this is a broken application 1285 * that fails to set it properly, and thus we switch it to 1286 * all 1's 1287 */ 1288 mfspr r4,SPRN_VRSAVE 1289 cmpdi 0,r4,0 1290 bne+ 1f 1291 li r4,-1 1292 mtspr SPRN_VRSAVE,r4 12931: 1294 /* enable use of VMX after return */ 1295 ld r4,PACACURRENT(r13) 1296 addi r5,r4,THREAD /* Get THREAD */ 1297 oris r12,r12,MSR_VEC@h 1298 std r12,_MSR(r1) 1299 li r4,1 1300 li r10,THREAD_VSCR 1301 stw r4,THREAD_USED_VR(r5) 1302 lvx vr0,r10,r5 1303 mtvscr vr0 1304 REST_32VRS(0,r4,r5) 1305#ifndef CONFIG_SMP 1306 /* Update last_task_used_math to 'current' */ 1307 subi r4,r5,THREAD /* Back to 'current' */ 1308 std r4,0(r3) 1309#endif /* CONFIG_SMP */ 1310 /* restore registers and return */ 1311 b fast_exception_return 1312#endif /* CONFIG_ALTIVEC */ 1313 1314/* 1315 * Hash table stuff 1316 */ 1317 .align 7 1318_GLOBAL(do_hash_page) 1319 std r3,_DAR(r1) 1320 std r4,_DSISR(r1) 1321 1322 andis. r0,r4,0xa450 /* weird error? */ 1323 bne- handle_page_fault /* if not, try to insert a HPTE */ 1324BEGIN_FTR_SECTION 1325 andis. r0,r4,0x0020 /* Is it a segment table fault? */ 1326 bne- do_ste_alloc /* If so handle it */ 1327END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 1328 1329 /* 1330 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are 1331 * accessing a userspace segment (even from the kernel). We assume 1332 * kernel addresses always have the high bit set. 1333 */ 1334 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ 1335 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ 1336 orc r0,r12,r0 /* MSR_PR | ~high_bit */ 1337 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ 1338 ori r4,r4,1 /* add _PAGE_PRESENT */ 1339 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ 1340 1341 /* 1342 * On iSeries, we soft-disable interrupts here, then 1343 * hard-enable interrupts so that the hash_page code can spin on 1344 * the hash_table_lock without problems on a shared processor. 1345 */ 1346 DISABLE_INTS 1347 1348 /* 1349 * r3 contains the faulting address 1350 * r4 contains the required access permissions 1351 * r5 contains the trap number 1352 * 1353 * at return r3 = 0 for success 1354 */ 1355 bl .hash_page /* build HPTE if possible */ 1356 cmpdi r3,0 /* see if hash_page succeeded */ 1357 1358#ifdef DO_SOFT_DISABLE 1359BEGIN_FW_FTR_SECTION 1360 /* 1361 * If we had interrupts soft-enabled at the point where the 1362 * DSI/ISI occurred, and an interrupt came in during hash_page, 1363 * handle it now. 1364 * We jump to ret_from_except_lite rather than fast_exception_return 1365 * because ret_from_except_lite will check for and handle pending 1366 * interrupts if necessary. 1367 */ 1368 beq 13f 1369END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1370#endif 1371BEGIN_FW_FTR_SECTION 1372 /* 1373 * Here we have interrupts hard-disabled, so it is sufficient 1374 * to restore paca->{soft,hard}_enable and get out. 1375 */ 1376 beq fast_exc_return_irq /* Return from exception on success */ 1377END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1378 1379 /* For a hash failure, we don't bother re-enabling interrupts */ 1380 ble- 12f 1381 1382 /* 1383 * hash_page couldn't handle it, set soft interrupt enable back 1384 * to what it was before the trap. Note that .local_irq_restore 1385 * handles any interrupts pending at this point. 1386 */ 1387 ld r3,SOFTE(r1) 1388 bl .local_irq_restore 1389 b 11f 1390 1391/* Here we have a page fault that hash_page can't handle. */ 1392handle_page_fault: 1393 ENABLE_INTS 139411: ld r4,_DAR(r1) 1395 ld r5,_DSISR(r1) 1396 addi r3,r1,STACK_FRAME_OVERHEAD 1397 bl .do_page_fault 1398 cmpdi r3,0 1399 beq+ 13f 1400 bl .save_nvgprs 1401 mr r5,r3 1402 addi r3,r1,STACK_FRAME_OVERHEAD 1403 lwz r4,_DAR(r1) 1404 bl .bad_page_fault 1405 b .ret_from_except 1406 140713: b .ret_from_except_lite 1408 1409/* We have a page fault that hash_page could handle but HV refused 1410 * the PTE insertion 1411 */ 141212: bl .save_nvgprs 1413 addi r3,r1,STACK_FRAME_OVERHEAD 1414 lwz r4,_DAR(r1) 1415 bl .low_hash_fault 1416 b .ret_from_except 1417 1418 /* here we have a segment miss */ 1419do_ste_alloc: 1420 bl .ste_allocate /* try to insert stab entry */ 1421 cmpdi r3,0 1422 bne- handle_page_fault 1423 b fast_exception_return 1424 1425/* 1426 * r13 points to the PACA, r9 contains the saved CR, 1427 * r11 and r12 contain the saved SRR0 and SRR1. 1428 * r9 - r13 are saved in paca->exslb. 1429 * We assume we aren't going to take any exceptions during this procedure. 1430 * We assume (DAR >> 60) == 0xc. 1431 */ 1432 .align 7 1433_GLOBAL(do_stab_bolted) 1434 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 1435 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ 1436 1437 /* Hash to the primary group */ 1438 ld r10,PACASTABVIRT(r13) 1439 mfspr r11,SPRN_DAR 1440 srdi r11,r11,28 1441 rldimi r10,r11,7,52 /* r10 = first ste of the group */ 1442 1443 /* Calculate VSID */ 1444 /* This is a kernel address, so protovsid = ESID */ 1445 ASM_VSID_SCRAMBLE(r11, r9) 1446 rldic r9,r11,12,16 /* r9 = vsid << 12 */ 1447 1448 /* Search the primary group for a free entry */ 14491: ld r11,0(r10) /* Test valid bit of the current ste */ 1450 andi. r11,r11,0x80 1451 beq 2f 1452 addi r10,r10,16 1453 andi. r11,r10,0x70 1454 bne 1b 1455 1456 /* Stick for only searching the primary group for now. */ 1457 /* At least for now, we use a very simple random castout scheme */ 1458 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ 1459 mftb r11 1460 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ 1461 ori r11,r11,0x10 1462 1463 /* r10 currently points to an ste one past the group of interest */ 1464 /* make it point to the randomly selected entry */ 1465 subi r10,r10,128 1466 or r10,r10,r11 /* r10 is the entry to invalidate */ 1467 1468 isync /* mark the entry invalid */ 1469 ld r11,0(r10) 1470 rldicl r11,r11,56,1 /* clear the valid bit */ 1471 rotldi r11,r11,8 1472 std r11,0(r10) 1473 sync 1474 1475 clrrdi r11,r11,28 /* Get the esid part of the ste */ 1476 slbie r11 1477 14782: std r9,8(r10) /* Store the vsid part of the ste */ 1479 eieio 1480 1481 mfspr r11,SPRN_DAR /* Get the new esid */ 1482 clrrdi r11,r11,28 /* Permits a full 32b of ESID */ 1483 ori r11,r11,0x90 /* Turn on valid and kp */ 1484 std r11,0(r10) /* Put new entry back into the stab */ 1485 1486 sync 1487 1488 /* All done -- return from exception. */ 1489 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 1490 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ 1491 1492 andi. r10,r12,MSR_RI 1493 beq- unrecov_slb 1494 1495 mtcrf 0x80,r9 /* restore CR */ 1496 1497 mfmsr r10 1498 clrrdi r10,r10,2 1499 mtmsrd r10,1 1500 1501 mtspr SPRN_SRR0,r11 1502 mtspr SPRN_SRR1,r12 1503 ld r9,PACA_EXSLB+EX_R9(r13) 1504 ld r10,PACA_EXSLB+EX_R10(r13) 1505 ld r11,PACA_EXSLB+EX_R11(r13) 1506 ld r12,PACA_EXSLB+EX_R12(r13) 1507 ld r13,PACA_EXSLB+EX_R13(r13) 1508 rfid 1509 b . /* prevent speculative execution */ 1510 1511/* 1512 * Space for CPU0's segment table. 1513 * 1514 * On iSeries, the hypervisor must fill in at least one entry before 1515 * we get control (with relocate on). The address is give to the hv 1516 * as a page number (see xLparMap in lpardata.c), so this must be at a 1517 * fixed address (the linker can't compute (u64)&initial_stab >> 1518 * PAGE_SHIFT). 1519 */ 1520 . = STAB0_OFFSET /* 0x6000 */ 1521 .globl initial_stab 1522initial_stab: 1523 .space 4096 1524 1525/* 1526 * Data area reserved for FWNMI option. 1527 * This address (0x7000) is fixed by the RPA. 1528 */ 1529 .= 0x7000 1530 .globl fwnmi_data_area 1531fwnmi_data_area: 1532 1533 /* iSeries does not use the FWNMI stuff, so it is safe to put 1534 * this here, even if we later allow kernels that will boot on 1535 * both pSeries and iSeries */ 1536#ifdef CONFIG_PPC_ISERIES 1537 . = LPARMAP_PHYS 1538#include "lparmap.s" 1539/* 1540 * This ".text" is here for old compilers that generate a trailing 1541 * .note section when compiling .c files to .s 1542 */ 1543 .text 1544#endif /* CONFIG_PPC_ISERIES */ 1545 1546 . = 0x8000 1547 1548/* 1549 * On pSeries and most other platforms, secondary processors spin 1550 * in the following code. 1551 * At entry, r3 = this processor's number (physical cpu id) 1552 */ 1553_GLOBAL(generic_secondary_smp_init) 1554 mr r24,r3 1555 1556 /* turn on 64-bit mode */ 1557 bl .enable_64b_mode 1558 isync 1559 1560 /* Set up a paca value for this processor. Since we have the 1561 * physical cpu id in r24, we need to search the pacas to find 1562 * which logical id maps to our physical one. 1563 */ 1564 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */ 1565 li r5,0 /* logical cpu id */ 15661: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 1567 cmpw r6,r24 /* Compare to our id */ 1568 beq 2f 1569 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 1570 addi r5,r5,1 1571 cmpwi r5,NR_CPUS 1572 blt 1b 1573 1574 mr r3,r24 /* not found, copy phys to r3 */ 1575 b .kexec_wait /* next kernel might do better */ 1576 15772: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1578 /* From now on, r24 is expected to be logical cpuid */ 1579 mr r24,r5 15803: HMT_LOW 1581 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 1582 /* start. */ 1583 sync 1584 1585#ifndef CONFIG_SMP 1586 b 3b /* Never go on non-SMP */ 1587#else 1588 cmpwi 0,r23,0 1589 beq 3b /* Loop until told to go */ 1590 1591 /* See if we need to call a cpu state restore handler */ 1592 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec) 1593 ld r23,0(r23) 1594 ld r23,CPU_SPEC_RESTORE(r23) 1595 cmpdi 0,r23,0 1596 beq 4f 1597 ld r23,0(r23) 1598 mtctr r23 1599 bctrl 1600 16014: /* Create a temp kernel stack for use before relocation is on. */ 1602 ld r1,PACAEMERGSP(r13) 1603 subi r1,r1,STACK_FRAME_OVERHEAD 1604 1605 b __secondary_start 1606#endif 1607 1608#ifdef CONFIG_PPC_ISERIES 1609_STATIC(__start_initialization_iSeries) 1610 /* Clear out the BSS */ 1611 LOAD_REG_IMMEDIATE(r11,__bss_stop) 1612 LOAD_REG_IMMEDIATE(r8,__bss_start) 1613 sub r11,r11,r8 /* bss size */ 1614 addi r11,r11,7 /* round up to an even double word */ 1615 rldicl. r11,r11,61,3 /* shift right by 3 */ 1616 beq 4f 1617 addi r8,r8,-8 1618 li r0,0 1619 mtctr r11 /* zero this many doublewords */ 16203: stdu r0,8(r8) 1621 bdnz 3b 16224: 1623 LOAD_REG_IMMEDIATE(r1,init_thread_union) 1624 addi r1,r1,THREAD_SIZE 1625 li r0,0 1626 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1627 1628 LOAD_REG_IMMEDIATE(r2,__toc_start) 1629 addi r2,r2,0x4000 1630 addi r2,r2,0x4000 1631 1632 bl .iSeries_early_setup 1633 bl .early_setup 1634 1635 /* relocation is on at this point */ 1636 1637 b .start_here_common 1638#endif /* CONFIG_PPC_ISERIES */ 1639 1640 1641_STATIC(__mmu_off) 1642 mfmsr r3 1643 andi. r0,r3,MSR_IR|MSR_DR 1644 beqlr 1645 andc r3,r3,r0 1646 mtspr SPRN_SRR0,r4 1647 mtspr SPRN_SRR1,r3 1648 sync 1649 rfid 1650 b . /* prevent speculative execution */ 1651 1652 1653/* 1654 * Here is our main kernel entry point. We support currently 2 kind of entries 1655 * depending on the value of r5. 1656 * 1657 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 1658 * in r3...r7 1659 * 1660 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 1661 * DT block, r4 is a physical pointer to the kernel itself 1662 * 1663 */ 1664_GLOBAL(__start_initialization_multiplatform) 1665 /* 1666 * Are we booted from a PROM Of-type client-interface ? 1667 */ 1668 cmpldi cr0,r5,0 1669 bne .__boot_from_prom /* yes -> prom */ 1670 1671 /* Save parameters */ 1672 mr r31,r3 1673 mr r30,r4 1674 1675 /* Make sure we are running in 64 bits mode */ 1676 bl .enable_64b_mode 1677 1678 /* Setup some critical 970 SPRs before switching MMU off */ 1679 mfspr r0,SPRN_PVR 1680 srwi r0,r0,16 1681 cmpwi r0,0x39 /* 970 */ 1682 beq 1f 1683 cmpwi r0,0x3c /* 970FX */ 1684 beq 1f 1685 cmpwi r0,0x44 /* 970MP */ 1686 beq 1f 1687 cmpwi r0,0x45 /* 970GX */ 1688 bne 2f 16891: bl .__cpu_preinit_ppc970 16902: 1691 1692 /* Switch off MMU if not already */ 1693 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE) 1694 add r4,r4,r30 1695 bl .__mmu_off 1696 b .__after_prom_start 1697 1698_STATIC(__boot_from_prom) 1699 /* Save parameters */ 1700 mr r31,r3 1701 mr r30,r4 1702 mr r29,r5 1703 mr r28,r6 1704 mr r27,r7 1705 1706 /* 1707 * Align the stack to 16-byte boundary 1708 * Depending on the size and layout of the ELF sections in the initial 1709 * boot binary, the stack pointer will be unalignet on PowerMac 1710 */ 1711 rldicr r1,r1,0,59 1712 1713 /* Make sure we are running in 64 bits mode */ 1714 bl .enable_64b_mode 1715 1716 /* put a relocation offset into r3 */ 1717 bl .reloc_offset 1718 1719 LOAD_REG_IMMEDIATE(r2,__toc_start) 1720 addi r2,r2,0x4000 1721 addi r2,r2,0x4000 1722 1723 /* Relocate the TOC from a virt addr to a real addr */ 1724 add r2,r2,r3 1725 1726 /* Restore parameters */ 1727 mr r3,r31 1728 mr r4,r30 1729 mr r5,r29 1730 mr r6,r28 1731 mr r7,r27 1732 1733 /* Do all of the interaction with OF client interface */ 1734 bl .prom_init 1735 /* We never return */ 1736 trap 1737 1738/* 1739 * At this point, r3 contains the physical address we are running at, 1740 * returned by prom_init() 1741 */ 1742_STATIC(__after_prom_start) 1743 1744/* 1745 * We need to run with __start at physical address PHYSICAL_START. 1746 * This will leave some code in the first 256B of 1747 * real memory, which are reserved for software use. 1748 * The remainder of the first page is loaded with the fixed 1749 * interrupt vectors. The next two pages are filled with 1750 * unknown exception placeholders. 1751 * 1752 * Note: This process overwrites the OF exception vectors. 1753 * r26 == relocation offset 1754 * r27 == KERNELBASE 1755 */ 1756 bl .reloc_offset 1757 mr r26,r3 1758 LOAD_REG_IMMEDIATE(r27, KERNELBASE) 1759 1760 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */ 1761 1762 // XXX FIXME: Use phys returned by OF (r30) 1763 add r4,r27,r26 /* source addr */ 1764 /* current address of _start */ 1765 /* i.e. where we are running */ 1766 /* the source addr */ 1767 1768 cmpdi r4,0 /* In some cases the loader may */ 1769 beq .start_here_multiplatform /* have already put us at zero */ 1770 /* so we can skip the copy. */ 1771 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */ 1772 sub r5,r5,r27 1773 1774 li r6,0x100 /* Start offset, the first 0x100 */ 1775 /* bytes were copied earlier. */ 1776 1777 bl .copy_and_flush /* copy the first n bytes */ 1778 /* this includes the code being */ 1779 /* executed here. */ 1780 1781 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */ 1782 mtctr r0 /* that we just made/relocated */ 1783 bctr 1784 17854: LOAD_REG_IMMEDIATE(r5,klimit) 1786 add r5,r5,r26 1787 ld r5,0(r5) /* get the value of klimit */ 1788 sub r5,r5,r27 1789 bl .copy_and_flush /* copy the rest */ 1790 b .start_here_multiplatform 1791 1792/* 1793 * Copy routine used to copy the kernel to start at physical address 0 1794 * and flush and invalidate the caches as needed. 1795 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 1796 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 1797 * 1798 * Note: this routine *only* clobbers r0, r6 and lr 1799 */ 1800_GLOBAL(copy_and_flush) 1801 addi r5,r5,-8 1802 addi r6,r6,-8 18034: li r0,8 /* Use the smallest common */ 1804 /* denominator cache line */ 1805 /* size. This results in */ 1806 /* extra cache line flushes */ 1807 /* but operation is correct. */ 1808 /* Can't get cache line size */ 1809 /* from NACA as it is being */ 1810 /* moved too. */ 1811 1812 mtctr r0 /* put # words/line in ctr */ 18133: addi r6,r6,8 /* copy a cache line */ 1814 ldx r0,r6,r4 1815 stdx r0,r6,r3 1816 bdnz 3b 1817 dcbst r6,r3 /* write it to memory */ 1818 sync 1819 icbi r6,r3 /* flush the icache line */ 1820 cmpld 0,r6,r5 1821 blt 4b 1822 sync 1823 addi r5,r5,8 1824 addi r6,r6,8 1825 blr 1826 1827.align 8 1828copy_to_here: 1829 1830#ifdef CONFIG_SMP 1831#ifdef CONFIG_PPC_PMAC 1832/* 1833 * On PowerMac, secondary processors starts from the reset vector, which 1834 * is temporarily turned into a call to one of the functions below. 1835 */ 1836 .section ".text"; 1837 .align 2 ; 1838 1839 .globl __secondary_start_pmac_0 1840__secondary_start_pmac_0: 1841 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 1842 li r24,0 1843 b 1f 1844 li r24,1 1845 b 1f 1846 li r24,2 1847 b 1f 1848 li r24,3 18491: 1850 1851_GLOBAL(pmac_secondary_start) 1852 /* turn on 64-bit mode */ 1853 bl .enable_64b_mode 1854 isync 1855 1856 /* Copy some CPU settings from CPU 0 */ 1857 bl .__restore_cpu_ppc970 1858 1859 /* pSeries do that early though I don't think we really need it */ 1860 mfmsr r3 1861 ori r3,r3,MSR_RI 1862 mtmsrd r3 /* RI on */ 1863 1864 /* Set up a paca value for this processor. */ 1865 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */ 1866 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 1867 add r13,r13,r4 /* for this processor. */ 1868 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1869 1870 /* Create a temp kernel stack for use before relocation is on. */ 1871 ld r1,PACAEMERGSP(r13) 1872 subi r1,r1,STACK_FRAME_OVERHEAD 1873 1874 b __secondary_start 1875 1876#endif /* CONFIG_PPC_PMAC */ 1877 1878/* 1879 * This function is called after the master CPU has released the 1880 * secondary processors. The execution environment is relocation off. 1881 * The paca for this processor has the following fields initialized at 1882 * this point: 1883 * 1. Processor number 1884 * 2. Segment table pointer (virtual address) 1885 * On entry the following are set: 1886 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 1887 * r24 = cpu# (in Linux terms) 1888 * r13 = paca virtual address 1889 * SPRG3 = paca virtual address 1890 */ 1891__secondary_start: 1892 /* Set thread priority to MEDIUM */ 1893 HMT_MEDIUM 1894 1895 /* Load TOC */ 1896 ld r2,PACATOC(r13) 1897 1898 /* Do early setup for that CPU (stab, slb, hash table pointer) */ 1899 bl .early_setup_secondary 1900 1901 /* Initialize the kernel stack. Just a repeat for iSeries. */ 1902 LOAD_REG_ADDR(r3, current_set) 1903 sldi r28,r24,3 /* get current_set[cpu#] */ 1904 ldx r1,r3,r28 1905 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1906 std r1,PACAKSAVE(r13) 1907 1908 /* Clear backchain so we get nice backtraces */ 1909 li r7,0 1910 mtlr r7 1911 1912 /* enable MMU and jump to start_secondary */ 1913 LOAD_REG_ADDR(r3, .start_secondary_prolog) 1914 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 1915#ifdef CONFIG_PPC_ISERIES 1916BEGIN_FW_FTR_SECTION 1917 ori r4,r4,MSR_EE 1918END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1919#endif 1920BEGIN_FW_FTR_SECTION 1921 stb r7,PACASOFTIRQEN(r13) 1922 stb r7,PACAHARDIRQEN(r13) 1923END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1924 1925 mtspr SPRN_SRR0,r3 1926 mtspr SPRN_SRR1,r4 1927 rfid 1928 b . /* prevent speculative execution */ 1929 1930/* 1931 * Running with relocation on at this point. All we want to do is 1932 * zero the stack back-chain pointer before going into C code. 1933 */ 1934_GLOBAL(start_secondary_prolog) 1935 li r3,0 1936 std r3,0(r1) /* Zero the stack frame pointer */ 1937 bl .start_secondary 1938 b . 1939#endif 1940 1941/* 1942 * This subroutine clobbers r11 and r12 1943 */ 1944_GLOBAL(enable_64b_mode) 1945 mfmsr r11 /* grab the current MSR */ 1946 li r12,1 1947 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) 1948 or r11,r11,r12 1949 li r12,1 1950 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) 1951 or r11,r11,r12 1952 mtmsrd r11 1953 isync 1954 blr 1955 1956/* 1957 * This is where the main kernel code starts. 1958 */ 1959_STATIC(start_here_multiplatform) 1960 /* get a new offset, now that the kernel has moved. */ 1961 bl .reloc_offset 1962 mr r26,r3 1963 1964 /* Clear out the BSS. It may have been done in prom_init, 1965 * already but that's irrelevant since prom_init will soon 1966 * be detached from the kernel completely. Besides, we need 1967 * to clear it now for kexec-style entry. 1968 */ 1969 LOAD_REG_IMMEDIATE(r11,__bss_stop) 1970 LOAD_REG_IMMEDIATE(r8,__bss_start) 1971 sub r11,r11,r8 /* bss size */ 1972 addi r11,r11,7 /* round up to an even double word */ 1973 rldicl. r11,r11,61,3 /* shift right by 3 */ 1974 beq 4f 1975 addi r8,r8,-8 1976 li r0,0 1977 mtctr r11 /* zero this many doublewords */ 19783: stdu r0,8(r8) 1979 bdnz 3b 19804: 1981 1982 mfmsr r6 1983 ori r6,r6,MSR_RI 1984 mtmsrd r6 /* RI on */ 1985 1986 /* The following gets the stack and TOC set up with the regs */ 1987 /* pointing to the real addr of the kernel stack. This is */ 1988 /* all done to support the C function call below which sets */ 1989 /* up the htab. This is done because we have relocated the */ 1990 /* kernel but are still running in real mode. */ 1991 1992 LOAD_REG_IMMEDIATE(r3,init_thread_union) 1993 add r3,r3,r26 1994 1995 /* set up a stack pointer (physical address) */ 1996 addi r1,r3,THREAD_SIZE 1997 li r0,0 1998 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1999 2000 /* set up the TOC (physical address) */ 2001 LOAD_REG_IMMEDIATE(r2,__toc_start) 2002 addi r2,r2,0x4000 2003 addi r2,r2,0x4000 2004 add r2,r2,r26 2005 2006 /* Do very early kernel initializations, including initial hash table, 2007 * stab and slb setup before we turn on relocation. */ 2008 2009 /* Restore parameters passed from prom_init/kexec */ 2010 mr r3,r31 2011 bl .early_setup 2012 2013 LOAD_REG_IMMEDIATE(r3, .start_here_common) 2014 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 2015 mtspr SPRN_SRR0,r3 2016 mtspr SPRN_SRR1,r4 2017 rfid 2018 b . /* prevent speculative execution */ 2019 2020 /* This is where all platforms converge execution */ 2021_STATIC(start_here_common) 2022 /* relocation is on at this point */ 2023 2024 /* The following code sets up the SP and TOC now that we are */ 2025 /* running with translation enabled. */ 2026 2027 LOAD_REG_IMMEDIATE(r3,init_thread_union) 2028 2029 /* set up the stack */ 2030 addi r1,r3,THREAD_SIZE 2031 li r0,0 2032 stdu r0,-STACK_FRAME_OVERHEAD(r1) 2033 2034 /* ptr to current */ 2035 LOAD_REG_IMMEDIATE(r4, init_task) 2036 std r4,PACACURRENT(r13) 2037 2038 /* Load the TOC */ 2039 ld r2,PACATOC(r13) 2040 std r1,PACAKSAVE(r13) 2041 2042 bl .setup_system 2043 2044 /* Load up the kernel context */ 20455: 2046 li r5,0 2047 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ 2048#ifdef CONFIG_PPC_ISERIES 2049BEGIN_FW_FTR_SECTION 2050 mfmsr r5 2051 ori r5,r5,MSR_EE /* Hard Enabled */ 2052 mtmsrd r5 2053END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 2054#endif 2055BEGIN_FW_FTR_SECTION 2056 stb r5,PACAHARDIRQEN(r13) 2057END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 2058 2059 bl .start_kernel 2060 2061 /* Not reached */ 2062 BUG_OPCODE 2063 2064/* 2065 * We put a few things here that have to be page-aligned. 2066 * This stuff goes at the beginning of the bss, which is page-aligned. 2067 */ 2068 .section ".bss" 2069 2070 .align PAGE_SHIFT 2071 2072 .globl empty_zero_page 2073empty_zero_page: 2074 .space PAGE_SIZE 2075 2076 .globl swapper_pg_dir 2077swapper_pg_dir: 2078 .space PAGE_SIZE 2079 2080/* 2081 * This space gets a copy of optional info passed to us by the bootstrap 2082 * Used to pass parameters into the kernel like root=/dev/sda1, etc. 2083 */ 2084 .globl cmd_line 2085cmd_line: 2086 .space COMMAND_LINE_SIZE 2087