1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the low-level support and setup for the 16 * PowerPC-64 platform, including trap and interrupt dispatch. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License 20 * as published by the Free Software Foundation; either version 21 * 2 of the License, or (at your option) any later version. 22 */ 23 24#include <linux/threads.h> 25#include <asm/reg.h> 26#include <asm/page.h> 27#include <asm/mmu.h> 28#include <asm/ppc_asm.h> 29#include <asm/asm-offsets.h> 30#include <asm/bug.h> 31#include <asm/cputable.h> 32#include <asm/setup.h> 33#include <asm/hvcall.h> 34#include <asm/iseries/lpar_map.h> 35#include <asm/thread_info.h> 36#include <asm/firmware.h> 37#include <asm/page_64.h> 38#include <asm/exception.h> 39#include <asm/irqflags.h> 40 41/* 42 * We layout physical memory as follows: 43 * 0x0000 - 0x00ff : Secondary processor spin code 44 * 0x0100 - 0x2fff : pSeries Interrupt prologs 45 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs 46 * 0x6000 - 0x6fff : Initial (CPU0) segment table 47 * 0x7000 - 0x7fff : FWNMI data area 48 * 0x8000 - : Early init and support code 49 */ 50 51/* 52 * SPRG Usage 53 * 54 * Register Definition 55 * 56 * SPRG0 reserved for hypervisor 57 * SPRG1 temp - used to save gpr 58 * SPRG2 temp - used to save gpr 59 * SPRG3 virt addr of paca 60 */ 61 62/* 63 * Entering into this code we make the following assumptions: 64 * For pSeries: 65 * 1. The MMU is off & open firmware is running in real mode. 66 * 2. The kernel is entered at __start 67 * 68 * For iSeries: 69 * 1. The MMU is on (as it always is for iSeries) 70 * 2. The kernel is entered at system_reset_iSeries 71 */ 72 73 .text 74 .globl _stext 75_stext: 76_GLOBAL(__start) 77 /* NOP this out unconditionally */ 78BEGIN_FTR_SECTION 79 b .__start_initialization_multiplatform 80END_FTR_SECTION(0, 1) 81 82 /* Catch branch to 0 in real mode */ 83 trap 84 85 /* Secondary processors spin on this value until it becomes nonzero. 86 * When it does it contains the real address of the descriptor 87 * of the function that the cpu should jump to to continue 88 * initialization. 89 */ 90 .globl __secondary_hold_spinloop 91__secondary_hold_spinloop: 92 .llong 0x0 93 94 /* Secondary processors write this value with their cpu # */ 95 /* after they enter the spin loop immediately below. */ 96 .globl __secondary_hold_acknowledge 97__secondary_hold_acknowledge: 98 .llong 0x0 99 100#ifdef CONFIG_PPC_ISERIES 101 /* 102 * At offset 0x20, there is a pointer to iSeries LPAR data. 103 * This is required by the hypervisor 104 */ 105 . = 0x20 106 .llong hvReleaseData-KERNELBASE 107#endif /* CONFIG_PPC_ISERIES */ 108 109 . = 0x60 110/* 111 * The following code is used to hold secondary processors 112 * in a spin loop after they have entered the kernel, but 113 * before the bulk of the kernel has been relocated. This code 114 * is relocated to physical address 0x60 before prom_init is run. 115 * All of it must fit below the first exception vector at 0x100. 116 * Use .globl here not _GLOBAL because we want __secondary_hold 117 * to be the actual text address, not a descriptor. 118 */ 119 .globl __secondary_hold 120__secondary_hold: 121 mfmsr r24 122 ori r24,r24,MSR_RI 123 mtmsrd r24 /* RI on */ 124 125 /* Grab our physical cpu number */ 126 mr r24,r3 127 128 /* Tell the master cpu we're here */ 129 /* Relocation is off & we are located at an address less */ 130 /* than 0x100, so only need to grab low order offset. */ 131 std r24,__secondary_hold_acknowledge-_stext(0) 132 sync 133 134 /* All secondary cpus wait here until told to start. */ 135100: ld r4,__secondary_hold_spinloop-_stext(0) 136 cmpdi 0,r4,0 137 beq 100b 138 139#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 140 ld r4,0(r4) /* deref function descriptor */ 141 mtctr r4 142 mr r3,r24 143 bctr 144#else 145 BUG_OPCODE 146#endif 147 148/* This value is used to mark exception frames on the stack. */ 149 .section ".toc","aw" 150exception_marker: 151 .tc ID_72656773_68657265[TC],0x7265677368657265 152 .text 153 154/* 155 * This is the start of the interrupt handlers for pSeries 156 * This code runs with relocation off. 157 * Code from here to __end_interrupts gets copied down to real 158 * address 0x100 when we are running a relocatable kernel. 159 * Therefore any relative branches in this section must only 160 * branch to labels in this section. 161 */ 162 . = 0x100 163 .globl __start_interrupts 164__start_interrupts: 165 166 STD_EXCEPTION_PSERIES(0x100, system_reset) 167 168 . = 0x200 169_machine_check_pSeries: 170 HMT_MEDIUM 171 mtspr SPRN_SPRG1,r13 /* save r13 */ 172 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 173 174 . = 0x300 175 .globl data_access_pSeries 176data_access_pSeries: 177 HMT_MEDIUM 178 mtspr SPRN_SPRG1,r13 179BEGIN_FTR_SECTION 180 mtspr SPRN_SPRG2,r12 181 mfspr r13,SPRN_DAR 182 mfspr r12,SPRN_DSISR 183 srdi r13,r13,60 184 rlwimi r13,r12,16,0x20 185 mfcr r12 186 cmpwi r13,0x2c 187 beq do_stab_bolted_pSeries 188 mtcrf 0x80,r12 189 mfspr r12,SPRN_SPRG2 190END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 191 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 192 193 . = 0x380 194 .globl data_access_slb_pSeries 195data_access_slb_pSeries: 196 HMT_MEDIUM 197 mtspr SPRN_SPRG1,r13 198 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 199 std r3,PACA_EXSLB+EX_R3(r13) 200 mfspr r3,SPRN_DAR 201 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 202 mfcr r9 203#ifdef __DISABLED__ 204 /* Keep that around for when we re-implement dynamic VSIDs */ 205 cmpdi r3,0 206 bge slb_miss_user_pseries 207#endif /* __DISABLED__ */ 208 std r10,PACA_EXSLB+EX_R10(r13) 209 std r11,PACA_EXSLB+EX_R11(r13) 210 std r12,PACA_EXSLB+EX_R12(r13) 211 mfspr r10,SPRN_SPRG1 212 std r10,PACA_EXSLB+EX_R13(r13) 213 mfspr r12,SPRN_SRR1 /* and SRR1 */ 214#ifndef CONFIG_RELOCATABLE 215 b .slb_miss_realmode 216#else 217 /* 218 * We can't just use a direct branch to .slb_miss_realmode 219 * because the distance from here to there depends on where 220 * the kernel ends up being put. 221 */ 222 mfctr r11 223 ld r10,PACAKBASE(r13) 224 LOAD_HANDLER(r10, .slb_miss_realmode) 225 mtctr r10 226 bctr 227#endif 228 229 STD_EXCEPTION_PSERIES(0x400, instruction_access) 230 231 . = 0x480 232 .globl instruction_access_slb_pSeries 233instruction_access_slb_pSeries: 234 HMT_MEDIUM 235 mtspr SPRN_SPRG1,r13 236 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 237 std r3,PACA_EXSLB+EX_R3(r13) 238 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 239 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 240 mfcr r9 241#ifdef __DISABLED__ 242 /* Keep that around for when we re-implement dynamic VSIDs */ 243 cmpdi r3,0 244 bge slb_miss_user_pseries 245#endif /* __DISABLED__ */ 246 std r10,PACA_EXSLB+EX_R10(r13) 247 std r11,PACA_EXSLB+EX_R11(r13) 248 std r12,PACA_EXSLB+EX_R12(r13) 249 mfspr r10,SPRN_SPRG1 250 std r10,PACA_EXSLB+EX_R13(r13) 251 mfspr r12,SPRN_SRR1 /* and SRR1 */ 252#ifndef CONFIG_RELOCATABLE 253 b .slb_miss_realmode 254#else 255 mfctr r11 256 ld r10,PACAKBASE(r13) 257 LOAD_HANDLER(r10, .slb_miss_realmode) 258 mtctr r10 259 bctr 260#endif 261 262 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt) 263 STD_EXCEPTION_PSERIES(0x600, alignment) 264 STD_EXCEPTION_PSERIES(0x700, program_check) 265 STD_EXCEPTION_PSERIES(0x800, fp_unavailable) 266 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer) 267 STD_EXCEPTION_PSERIES(0xa00, trap_0a) 268 STD_EXCEPTION_PSERIES(0xb00, trap_0b) 269 270 . = 0xc00 271 .globl system_call_pSeries 272system_call_pSeries: 273 HMT_MEDIUM 274BEGIN_FTR_SECTION 275 cmpdi r0,0x1ebe 276 beq- 1f 277END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) 278 mr r9,r13 279 mfspr r13,SPRN_SPRG3 280 mfspr r11,SPRN_SRR0 281 ld r12,PACAKBASE(r13) 282 ld r10,PACAKMSR(r13) 283 LOAD_HANDLER(r12, system_call_entry) 284 mtspr SPRN_SRR0,r12 285 mfspr r12,SPRN_SRR1 286 mtspr SPRN_SRR1,r10 287 rfid 288 b . /* prevent speculative execution */ 289 290/* Fast LE/BE switch system call */ 2911: mfspr r12,SPRN_SRR1 292 xori r12,r12,MSR_LE 293 mtspr SPRN_SRR1,r12 294 rfid /* return to userspace */ 295 b . 296 297 STD_EXCEPTION_PSERIES(0xd00, single_step) 298 STD_EXCEPTION_PSERIES(0xe00, trap_0e) 299 300 /* We need to deal with the Altivec unavailable exception 301 * here which is at 0xf20, thus in the middle of the 302 * prolog code of the PerformanceMonitor one. A little 303 * trickery is thus necessary 304 */ 305 . = 0xf00 306 b performance_monitor_pSeries 307 308 . = 0xf20 309 b altivec_unavailable_pSeries 310 311 . = 0xf40 312 b vsx_unavailable_pSeries 313 314#ifdef CONFIG_CBE_RAS 315 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) 316#endif /* CONFIG_CBE_RAS */ 317 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) 318#ifdef CONFIG_CBE_RAS 319 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance) 320#endif /* CONFIG_CBE_RAS */ 321 STD_EXCEPTION_PSERIES(0x1700, altivec_assist) 322#ifdef CONFIG_CBE_RAS 323 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal) 324#endif /* CONFIG_CBE_RAS */ 325 326 . = 0x3000 327 328/*** pSeries interrupt support ***/ 329 330 /* moved from 0xf00 */ 331 STD_EXCEPTION_PSERIES(., performance_monitor) 332 STD_EXCEPTION_PSERIES(., altivec_unavailable) 333 STD_EXCEPTION_PSERIES(., vsx_unavailable) 334 335/* 336 * An interrupt came in while soft-disabled; clear EE in SRR1, 337 * clear paca->hard_enabled and return. 338 */ 339masked_interrupt: 340 stb r10,PACAHARDIRQEN(r13) 341 mtcrf 0x80,r9 342 ld r9,PACA_EXGEN+EX_R9(r13) 343 mfspr r10,SPRN_SRR1 344 rldicl r10,r10,48,1 /* clear MSR_EE */ 345 rotldi r10,r10,16 346 mtspr SPRN_SRR1,r10 347 ld r10,PACA_EXGEN+EX_R10(r13) 348 mfspr r13,SPRN_SPRG1 349 rfid 350 b . 351 352 .align 7 353do_stab_bolted_pSeries: 354 mtcrf 0x80,r12 355 mfspr r12,SPRN_SPRG2 356 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) 357 358#ifdef CONFIG_PPC_PSERIES 359/* 360 * Vectors for the FWNMI option. Share common code. 361 */ 362 .globl system_reset_fwnmi 363 .align 7 364system_reset_fwnmi: 365 HMT_MEDIUM 366 mtspr SPRN_SPRG1,r13 /* save r13 */ 367 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) 368 369 .globl machine_check_fwnmi 370 .align 7 371machine_check_fwnmi: 372 HMT_MEDIUM 373 mtspr SPRN_SPRG1,r13 /* save r13 */ 374 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 375 376#endif /* CONFIG_PPC_PSERIES */ 377 378#ifdef __DISABLED__ 379/* 380 * This is used for when the SLB miss handler has to go virtual, 381 * which doesn't happen for now anymore but will once we re-implement 382 * dynamic VSIDs for shared page tables 383 */ 384slb_miss_user_pseries: 385 std r10,PACA_EXGEN+EX_R10(r13) 386 std r11,PACA_EXGEN+EX_R11(r13) 387 std r12,PACA_EXGEN+EX_R12(r13) 388 mfspr r10,SPRG1 389 ld r11,PACA_EXSLB+EX_R9(r13) 390 ld r12,PACA_EXSLB+EX_R3(r13) 391 std r10,PACA_EXGEN+EX_R13(r13) 392 std r11,PACA_EXGEN+EX_R9(r13) 393 std r12,PACA_EXGEN+EX_R3(r13) 394 clrrdi r12,r13,32 395 mfmsr r10 396 mfspr r11,SRR0 /* save SRR0 */ 397 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ 398 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 399 mtspr SRR0,r12 400 mfspr r12,SRR1 /* and SRR1 */ 401 mtspr SRR1,r10 402 rfid 403 b . /* prevent spec. execution */ 404#endif /* __DISABLED__ */ 405 406 .align 7 407 .globl __end_interrupts 408__end_interrupts: 409 410/* 411 * Code from here down to __end_handlers is invoked from the 412 * exception prologs above. Because the prologs assemble the 413 * addresses of these handlers using the LOAD_HANDLER macro, 414 * which uses an addi instruction, these handlers must be in 415 * the first 32k of the kernel image. 416 */ 417 418/*** Common interrupt handlers ***/ 419 420 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) 421 422 /* 423 * Machine check is different because we use a different 424 * save area: PACA_EXMC instead of PACA_EXGEN. 425 */ 426 .align 7 427 .globl machine_check_common 428machine_check_common: 429 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 430 FINISH_NAP 431 DISABLE_INTS 432 bl .save_nvgprs 433 addi r3,r1,STACK_FRAME_OVERHEAD 434 bl .machine_check_exception 435 b .ret_from_except 436 437 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) 438 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) 439 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) 440 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) 441 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) 442 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) 443 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) 444#ifdef CONFIG_ALTIVEC 445 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) 446#else 447 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) 448#endif 449#ifdef CONFIG_CBE_RAS 450 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) 451 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) 452 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) 453#endif /* CONFIG_CBE_RAS */ 454 455 .align 7 456system_call_entry: 457 b system_call_common 458 459/* 460 * Here we have detected that the kernel stack pointer is bad. 461 * R9 contains the saved CR, r13 points to the paca, 462 * r10 contains the (bad) kernel stack pointer, 463 * r11 and r12 contain the saved SRR0 and SRR1. 464 * We switch to using an emergency stack, save the registers there, 465 * and call kernel_bad_stack(), which panics. 466 */ 467bad_stack: 468 ld r1,PACAEMERGSP(r13) 469 subi r1,r1,64+INT_FRAME_SIZE 470 std r9,_CCR(r1) 471 std r10,GPR1(r1) 472 std r11,_NIP(r1) 473 std r12,_MSR(r1) 474 mfspr r11,SPRN_DAR 475 mfspr r12,SPRN_DSISR 476 std r11,_DAR(r1) 477 std r12,_DSISR(r1) 478 mflr r10 479 mfctr r11 480 mfxer r12 481 std r10,_LINK(r1) 482 std r11,_CTR(r1) 483 std r12,_XER(r1) 484 SAVE_GPR(0,r1) 485 SAVE_GPR(2,r1) 486 SAVE_4GPRS(3,r1) 487 SAVE_2GPRS(7,r1) 488 SAVE_10GPRS(12,r1) 489 SAVE_10GPRS(22,r1) 490 lhz r12,PACA_TRAP_SAVE(r13) 491 std r12,_TRAP(r1) 492 addi r11,r1,INT_FRAME_SIZE 493 std r11,0(r1) 494 li r12,0 495 std r12,0(r11) 496 ld r2,PACATOC(r13) 4971: addi r3,r1,STACK_FRAME_OVERHEAD 498 bl .kernel_bad_stack 499 b 1b 500 501/* 502 * Here r13 points to the paca, r9 contains the saved CR, 503 * SRR0 and SRR1 are saved in r11 and r12, 504 * r9 - r13 are saved in paca->exgen. 505 */ 506 .align 7 507 .globl data_access_common 508data_access_common: 509 mfspr r10,SPRN_DAR 510 std r10,PACA_EXGEN+EX_DAR(r13) 511 mfspr r10,SPRN_DSISR 512 stw r10,PACA_EXGEN+EX_DSISR(r13) 513 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 514 ld r3,PACA_EXGEN+EX_DAR(r13) 515 lwz r4,PACA_EXGEN+EX_DSISR(r13) 516 li r5,0x300 517 b .do_hash_page /* Try to handle as hpte fault */ 518 519 .align 7 520 .globl instruction_access_common 521instruction_access_common: 522 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 523 ld r3,_NIP(r1) 524 andis. r4,r12,0x5820 525 li r5,0x400 526 b .do_hash_page /* Try to handle as hpte fault */ 527 528/* 529 * Here is the common SLB miss user that is used when going to virtual 530 * mode for SLB misses, that is currently not used 531 */ 532#ifdef __DISABLED__ 533 .align 7 534 .globl slb_miss_user_common 535slb_miss_user_common: 536 mflr r10 537 std r3,PACA_EXGEN+EX_DAR(r13) 538 stw r9,PACA_EXGEN+EX_CCR(r13) 539 std r10,PACA_EXGEN+EX_LR(r13) 540 std r11,PACA_EXGEN+EX_SRR0(r13) 541 bl .slb_allocate_user 542 543 ld r10,PACA_EXGEN+EX_LR(r13) 544 ld r3,PACA_EXGEN+EX_R3(r13) 545 lwz r9,PACA_EXGEN+EX_CCR(r13) 546 ld r11,PACA_EXGEN+EX_SRR0(r13) 547 mtlr r10 548 beq- slb_miss_fault 549 550 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 551 beq- unrecov_user_slb 552 mfmsr r10 553 554.machine push 555.machine "power4" 556 mtcrf 0x80,r9 557.machine pop 558 559 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ 560 mtmsrd r10,1 561 562 mtspr SRR0,r11 563 mtspr SRR1,r12 564 565 ld r9,PACA_EXGEN+EX_R9(r13) 566 ld r10,PACA_EXGEN+EX_R10(r13) 567 ld r11,PACA_EXGEN+EX_R11(r13) 568 ld r12,PACA_EXGEN+EX_R12(r13) 569 ld r13,PACA_EXGEN+EX_R13(r13) 570 rfid 571 b . 572 573slb_miss_fault: 574 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) 575 ld r4,PACA_EXGEN+EX_DAR(r13) 576 li r5,0 577 std r4,_DAR(r1) 578 std r5,_DSISR(r1) 579 b handle_page_fault 580 581unrecov_user_slb: 582 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) 583 DISABLE_INTS 584 bl .save_nvgprs 5851: addi r3,r1,STACK_FRAME_OVERHEAD 586 bl .unrecoverable_exception 587 b 1b 588 589#endif /* __DISABLED__ */ 590 591 592/* 593 * r13 points to the PACA, r9 contains the saved CR, 594 * r12 contain the saved SRR1, SRR0 is still ready for return 595 * r3 has the faulting address 596 * r9 - r13 are saved in paca->exslb. 597 * r3 is saved in paca->slb_r3 598 * We assume we aren't going to take any exceptions during this procedure. 599 */ 600_GLOBAL(slb_miss_realmode) 601 mflr r10 602#ifdef CONFIG_RELOCATABLE 603 mtctr r11 604#endif 605 606 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 607 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 608 609 bl .slb_allocate_realmode 610 611 /* All done -- return from exception. */ 612 613 ld r10,PACA_EXSLB+EX_LR(r13) 614 ld r3,PACA_EXSLB+EX_R3(r13) 615 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 616#ifdef CONFIG_PPC_ISERIES 617BEGIN_FW_FTR_SECTION 618 ld r11,PACALPPACAPTR(r13) 619 ld r11,LPPACASRR0(r11) /* get SRR0 value */ 620END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 621#endif /* CONFIG_PPC_ISERIES */ 622 623 mtlr r10 624 625 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 626 beq- 2f 627 628.machine push 629.machine "power4" 630 mtcrf 0x80,r9 631 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 632.machine pop 633 634#ifdef CONFIG_PPC_ISERIES 635BEGIN_FW_FTR_SECTION 636 mtspr SPRN_SRR0,r11 637 mtspr SPRN_SRR1,r12 638END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 639#endif /* CONFIG_PPC_ISERIES */ 640 ld r9,PACA_EXSLB+EX_R9(r13) 641 ld r10,PACA_EXSLB+EX_R10(r13) 642 ld r11,PACA_EXSLB+EX_R11(r13) 643 ld r12,PACA_EXSLB+EX_R12(r13) 644 ld r13,PACA_EXSLB+EX_R13(r13) 645 rfid 646 b . /* prevent speculative execution */ 647 6482: 649#ifdef CONFIG_PPC_ISERIES 650BEGIN_FW_FTR_SECTION 651 b unrecov_slb 652END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 653#endif /* CONFIG_PPC_ISERIES */ 654 mfspr r11,SPRN_SRR0 655 ld r10,PACAKBASE(r13) 656 LOAD_HANDLER(r10,unrecov_slb) 657 mtspr SPRN_SRR0,r10 658 ld r10,PACAKMSR(r13) 659 mtspr SPRN_SRR1,r10 660 rfid 661 b . 662 663unrecov_slb: 664 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 665 DISABLE_INTS 666 bl .save_nvgprs 6671: addi r3,r1,STACK_FRAME_OVERHEAD 668 bl .unrecoverable_exception 669 b 1b 670 671 .align 7 672 .globl hardware_interrupt_common 673 .globl hardware_interrupt_entry 674hardware_interrupt_common: 675 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) 676 FINISH_NAP 677hardware_interrupt_entry: 678 DISABLE_INTS 679BEGIN_FTR_SECTION 680 bl .ppc64_runlatch_on 681END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 682 addi r3,r1,STACK_FRAME_OVERHEAD 683 bl .do_IRQ 684 b .ret_from_except_lite 685 686#ifdef CONFIG_PPC_970_NAP 687power4_fixup_nap: 688 andc r9,r9,r10 689 std r9,TI_LOCAL_FLAGS(r11) 690 ld r10,_LINK(r1) /* make idle task do the */ 691 std r10,_NIP(r1) /* equivalent of a blr */ 692 blr 693#endif 694 695 .align 7 696 .globl alignment_common 697alignment_common: 698 mfspr r10,SPRN_DAR 699 std r10,PACA_EXGEN+EX_DAR(r13) 700 mfspr r10,SPRN_DSISR 701 stw r10,PACA_EXGEN+EX_DSISR(r13) 702 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 703 ld r3,PACA_EXGEN+EX_DAR(r13) 704 lwz r4,PACA_EXGEN+EX_DSISR(r13) 705 std r3,_DAR(r1) 706 std r4,_DSISR(r1) 707 bl .save_nvgprs 708 addi r3,r1,STACK_FRAME_OVERHEAD 709 ENABLE_INTS 710 bl .alignment_exception 711 b .ret_from_except 712 713 .align 7 714 .globl program_check_common 715program_check_common: 716 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 717 bl .save_nvgprs 718 addi r3,r1,STACK_FRAME_OVERHEAD 719 ENABLE_INTS 720 bl .program_check_exception 721 b .ret_from_except 722 723 .align 7 724 .globl fp_unavailable_common 725fp_unavailable_common: 726 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 727 bne 1f /* if from user, just load it up */ 728 bl .save_nvgprs 729 addi r3,r1,STACK_FRAME_OVERHEAD 730 ENABLE_INTS 731 bl .kernel_fp_unavailable_exception 732 BUG_OPCODE 7331: bl .load_up_fpu 734 b fast_exception_return 735 736 .align 7 737 .globl altivec_unavailable_common 738altivec_unavailable_common: 739 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 740#ifdef CONFIG_ALTIVEC 741BEGIN_FTR_SECTION 742 beq 1f 743 bl .load_up_altivec 744 b fast_exception_return 7451: 746END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 747#endif 748 bl .save_nvgprs 749 addi r3,r1,STACK_FRAME_OVERHEAD 750 ENABLE_INTS 751 bl .altivec_unavailable_exception 752 b .ret_from_except 753 754 .align 7 755 .globl vsx_unavailable_common 756vsx_unavailable_common: 757 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) 758#ifdef CONFIG_VSX 759BEGIN_FTR_SECTION 760 bne .load_up_vsx 7611: 762END_FTR_SECTION_IFSET(CPU_FTR_VSX) 763#endif 764 bl .save_nvgprs 765 addi r3,r1,STACK_FRAME_OVERHEAD 766 ENABLE_INTS 767 bl .vsx_unavailable_exception 768 b .ret_from_except 769 770 .align 7 771 .globl __end_handlers 772__end_handlers: 773 774/* 775 * Return from an exception with minimal checks. 776 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. 777 * If interrupts have been enabled, or anything has been 778 * done that might have changed the scheduling status of 779 * any task or sent any task a signal, you should use 780 * ret_from_except or ret_from_except_lite instead of this. 781 */ 782fast_exc_return_irq: /* restores irq state too */ 783 ld r3,SOFTE(r1) 784 TRACE_AND_RESTORE_IRQ(r3); 785 ld r12,_MSR(r1) 786 rldicl r4,r12,49,63 /* get MSR_EE to LSB */ 787 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ 788 b 1f 789 790 .globl fast_exception_return 791fast_exception_return: 792 ld r12,_MSR(r1) 7931: ld r11,_NIP(r1) 794 andi. r3,r12,MSR_RI /* check if RI is set */ 795 beq- unrecov_fer 796 797#ifdef CONFIG_VIRT_CPU_ACCOUNTING 798 andi. r3,r12,MSR_PR 799 beq 2f 800 ACCOUNT_CPU_USER_EXIT(r3, r4) 8012: 802#endif 803 804 ld r3,_CCR(r1) 805 ld r4,_LINK(r1) 806 ld r5,_CTR(r1) 807 ld r6,_XER(r1) 808 mtcr r3 809 mtlr r4 810 mtctr r5 811 mtxer r6 812 REST_GPR(0, r1) 813 REST_8GPRS(2, r1) 814 815 mfmsr r10 816 rldicl r10,r10,48,1 /* clear EE */ 817 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ 818 mtmsrd r10,1 819 820 mtspr SPRN_SRR1,r12 821 mtspr SPRN_SRR0,r11 822 REST_4GPRS(10, r1) 823 ld r1,GPR1(r1) 824 rfid 825 b . /* prevent speculative execution */ 826 827unrecov_fer: 828 bl .save_nvgprs 8291: addi r3,r1,STACK_FRAME_OVERHEAD 830 bl .unrecoverable_exception 831 b 1b 832 833#ifdef CONFIG_ALTIVEC 834/* 835 * load_up_altivec(unused, unused, tsk) 836 * Disable VMX for the task which had it previously, 837 * and save its vector registers in its thread_struct. 838 * Enables the VMX for use in the kernel on return. 839 * On SMP we know the VMX is free, since we give it up every 840 * switch (ie, no lazy save of the vector registers). 841 * On entry: r13 == 'current' && last_task_used_altivec != 'current' 842 */ 843_STATIC(load_up_altivec) 844 mfmsr r5 /* grab the current MSR */ 845 oris r5,r5,MSR_VEC@h 846 mtmsrd r5 /* enable use of VMX now */ 847 isync 848 849/* 850 * For SMP, we don't do lazy VMX switching because it just gets too 851 * horrendously complex, especially when a task switches from one CPU 852 * to another. Instead we call giveup_altvec in switch_to. 853 * VRSAVE isn't dealt with here, that is done in the normal context 854 * switch code. Note that we could rely on vrsave value to eventually 855 * avoid saving all of the VREGs here... 856 */ 857#ifndef CONFIG_SMP 858 ld r3,last_task_used_altivec@got(r2) 859 ld r4,0(r3) 860 cmpdi 0,r4,0 861 beq 1f 862 /* Save VMX state to last_task_used_altivec's THREAD struct */ 863 addi r4,r4,THREAD 864 SAVE_32VRS(0,r5,r4) 865 mfvscr vr0 866 li r10,THREAD_VSCR 867 stvx vr0,r10,r4 868 /* Disable VMX for last_task_used_altivec */ 869 ld r5,PT_REGS(r4) 870 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) 871 lis r6,MSR_VEC@h 872 andc r4,r4,r6 873 std r4,_MSR-STACK_FRAME_OVERHEAD(r5) 8741: 875#endif /* CONFIG_SMP */ 876 /* Hack: if we get an altivec unavailable trap with VRSAVE 877 * set to all zeros, we assume this is a broken application 878 * that fails to set it properly, and thus we switch it to 879 * all 1's 880 */ 881 mfspr r4,SPRN_VRSAVE 882 cmpdi 0,r4,0 883 bne+ 1f 884 li r4,-1 885 mtspr SPRN_VRSAVE,r4 8861: 887 /* enable use of VMX after return */ 888 ld r4,PACACURRENT(r13) 889 addi r5,r4,THREAD /* Get THREAD */ 890 oris r12,r12,MSR_VEC@h 891 std r12,_MSR(r1) 892 li r4,1 893 li r10,THREAD_VSCR 894 stw r4,THREAD_USED_VR(r5) 895 lvx vr0,r10,r5 896 mtvscr vr0 897 REST_32VRS(0,r4,r5) 898#ifndef CONFIG_SMP 899 /* Update last_task_used_math to 'current' */ 900 subi r4,r5,THREAD /* Back to 'current' */ 901 std r4,0(r3) 902#endif /* CONFIG_SMP */ 903 /* restore registers and return */ 904 blr 905#endif /* CONFIG_ALTIVEC */ 906 907#ifdef CONFIG_VSX 908/* 909 * load_up_vsx(unused, unused, tsk) 910 * Disable VSX for the task which had it previously, 911 * and save its vector registers in its thread_struct. 912 * Reuse the fp and vsx saves, but first check to see if they have 913 * been saved already. 914 * On entry: r13 == 'current' && last_task_used_vsx != 'current' 915 */ 916_STATIC(load_up_vsx) 917/* Load FP and VSX registers if they haven't been done yet */ 918 andi. r5,r12,MSR_FP 919 beql+ load_up_fpu /* skip if already loaded */ 920 andis. r5,r12,MSR_VEC@h 921 beql+ load_up_altivec /* skip if already loaded */ 922 923#ifndef CONFIG_SMP 924 ld r3,last_task_used_vsx@got(r2) 925 ld r4,0(r3) 926 cmpdi 0,r4,0 927 beq 1f 928 /* Disable VSX for last_task_used_vsx */ 929 addi r4,r4,THREAD 930 ld r5,PT_REGS(r4) 931 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) 932 lis r6,MSR_VSX@h 933 andc r6,r4,r6 934 std r6,_MSR-STACK_FRAME_OVERHEAD(r5) 9351: 936#endif /* CONFIG_SMP */ 937 ld r4,PACACURRENT(r13) 938 addi r4,r4,THREAD /* Get THREAD */ 939 li r6,1 940 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */ 941 /* enable use of VSX after return */ 942 oris r12,r12,MSR_VSX@h 943 std r12,_MSR(r1) 944#ifndef CONFIG_SMP 945 /* Update last_task_used_math to 'current' */ 946 ld r4,PACACURRENT(r13) 947 std r4,0(r3) 948#endif /* CONFIG_SMP */ 949 b fast_exception_return 950#endif /* CONFIG_VSX */ 951 952/* 953 * Hash table stuff 954 */ 955 .align 7 956_STATIC(do_hash_page) 957 std r3,_DAR(r1) 958 std r4,_DSISR(r1) 959 960 andis. r0,r4,0xa450 /* weird error? */ 961 bne- handle_page_fault /* if not, try to insert a HPTE */ 962BEGIN_FTR_SECTION 963 andis. r0,r4,0x0020 /* Is it a segment table fault? */ 964 bne- do_ste_alloc /* If so handle it */ 965END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 966 967 /* 968 * On iSeries, we soft-disable interrupts here, then 969 * hard-enable interrupts so that the hash_page code can spin on 970 * the hash_table_lock without problems on a shared processor. 971 */ 972 DISABLE_INTS 973 974 /* 975 * Currently, trace_hardirqs_off() will be called by DISABLE_INTS 976 * and will clobber volatile registers when irq tracing is enabled 977 * so we need to reload them. It may be possible to be smarter here 978 * and move the irq tracing elsewhere but let's keep it simple for 979 * now 980 */ 981#ifdef CONFIG_TRACE_IRQFLAGS 982 ld r3,_DAR(r1) 983 ld r4,_DSISR(r1) 984 ld r5,_TRAP(r1) 985 ld r12,_MSR(r1) 986 clrrdi r5,r5,4 987#endif /* CONFIG_TRACE_IRQFLAGS */ 988 /* 989 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are 990 * accessing a userspace segment (even from the kernel). We assume 991 * kernel addresses always have the high bit set. 992 */ 993 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ 994 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ 995 orc r0,r12,r0 /* MSR_PR | ~high_bit */ 996 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ 997 ori r4,r4,1 /* add _PAGE_PRESENT */ 998 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ 999 1000 /* 1001 * r3 contains the faulting address 1002 * r4 contains the required access permissions 1003 * r5 contains the trap number 1004 * 1005 * at return r3 = 0 for success 1006 */ 1007 bl .hash_page /* build HPTE if possible */ 1008 cmpdi r3,0 /* see if hash_page succeeded */ 1009 1010BEGIN_FW_FTR_SECTION 1011 /* 1012 * If we had interrupts soft-enabled at the point where the 1013 * DSI/ISI occurred, and an interrupt came in during hash_page, 1014 * handle it now. 1015 * We jump to ret_from_except_lite rather than fast_exception_return 1016 * because ret_from_except_lite will check for and handle pending 1017 * interrupts if necessary. 1018 */ 1019 beq 13f 1020END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1021 1022BEGIN_FW_FTR_SECTION 1023 /* 1024 * Here we have interrupts hard-disabled, so it is sufficient 1025 * to restore paca->{soft,hard}_enable and get out. 1026 */ 1027 beq fast_exc_return_irq /* Return from exception on success */ 1028END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1029 1030 /* For a hash failure, we don't bother re-enabling interrupts */ 1031 ble- 12f 1032 1033 /* 1034 * hash_page couldn't handle it, set soft interrupt enable back 1035 * to what it was before the trap. Note that .raw_local_irq_restore 1036 * handles any interrupts pending at this point. 1037 */ 1038 ld r3,SOFTE(r1) 1039 TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f) 1040 bl .raw_local_irq_restore 1041 b 11f 1042 1043/* Here we have a page fault that hash_page can't handle. */ 1044handle_page_fault: 1045 ENABLE_INTS 104611: ld r4,_DAR(r1) 1047 ld r5,_DSISR(r1) 1048 addi r3,r1,STACK_FRAME_OVERHEAD 1049 bl .do_page_fault 1050 cmpdi r3,0 1051 beq+ 13f 1052 bl .save_nvgprs 1053 mr r5,r3 1054 addi r3,r1,STACK_FRAME_OVERHEAD 1055 lwz r4,_DAR(r1) 1056 bl .bad_page_fault 1057 b .ret_from_except 1058 105913: b .ret_from_except_lite 1060 1061/* We have a page fault that hash_page could handle but HV refused 1062 * the PTE insertion 1063 */ 106412: bl .save_nvgprs 1065 mr r5,r3 1066 addi r3,r1,STACK_FRAME_OVERHEAD 1067 ld r4,_DAR(r1) 1068 bl .low_hash_fault 1069 b .ret_from_except 1070 1071 /* here we have a segment miss */ 1072do_ste_alloc: 1073 bl .ste_allocate /* try to insert stab entry */ 1074 cmpdi r3,0 1075 bne- handle_page_fault 1076 b fast_exception_return 1077 1078/* 1079 * r13 points to the PACA, r9 contains the saved CR, 1080 * r11 and r12 contain the saved SRR0 and SRR1. 1081 * r9 - r13 are saved in paca->exslb. 1082 * We assume we aren't going to take any exceptions during this procedure. 1083 * We assume (DAR >> 60) == 0xc. 1084 */ 1085 .align 7 1086_GLOBAL(do_stab_bolted) 1087 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 1088 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ 1089 1090 /* Hash to the primary group */ 1091 ld r10,PACASTABVIRT(r13) 1092 mfspr r11,SPRN_DAR 1093 srdi r11,r11,28 1094 rldimi r10,r11,7,52 /* r10 = first ste of the group */ 1095 1096 /* Calculate VSID */ 1097 /* This is a kernel address, so protovsid = ESID */ 1098 ASM_VSID_SCRAMBLE(r11, r9, 256M) 1099 rldic r9,r11,12,16 /* r9 = vsid << 12 */ 1100 1101 /* Search the primary group for a free entry */ 11021: ld r11,0(r10) /* Test valid bit of the current ste */ 1103 andi. r11,r11,0x80 1104 beq 2f 1105 addi r10,r10,16 1106 andi. r11,r10,0x70 1107 bne 1b 1108 1109 /* Stick for only searching the primary group for now. */ 1110 /* At least for now, we use a very simple random castout scheme */ 1111 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ 1112 mftb r11 1113 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ 1114 ori r11,r11,0x10 1115 1116 /* r10 currently points to an ste one past the group of interest */ 1117 /* make it point to the randomly selected entry */ 1118 subi r10,r10,128 1119 or r10,r10,r11 /* r10 is the entry to invalidate */ 1120 1121 isync /* mark the entry invalid */ 1122 ld r11,0(r10) 1123 rldicl r11,r11,56,1 /* clear the valid bit */ 1124 rotldi r11,r11,8 1125 std r11,0(r10) 1126 sync 1127 1128 clrrdi r11,r11,28 /* Get the esid part of the ste */ 1129 slbie r11 1130 11312: std r9,8(r10) /* Store the vsid part of the ste */ 1132 eieio 1133 1134 mfspr r11,SPRN_DAR /* Get the new esid */ 1135 clrrdi r11,r11,28 /* Permits a full 32b of ESID */ 1136 ori r11,r11,0x90 /* Turn on valid and kp */ 1137 std r11,0(r10) /* Put new entry back into the stab */ 1138 1139 sync 1140 1141 /* All done -- return from exception. */ 1142 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 1143 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ 1144 1145 andi. r10,r12,MSR_RI 1146 beq- unrecov_slb 1147 1148 mtcrf 0x80,r9 /* restore CR */ 1149 1150 mfmsr r10 1151 clrrdi r10,r10,2 1152 mtmsrd r10,1 1153 1154 mtspr SPRN_SRR0,r11 1155 mtspr SPRN_SRR1,r12 1156 ld r9,PACA_EXSLB+EX_R9(r13) 1157 ld r10,PACA_EXSLB+EX_R10(r13) 1158 ld r11,PACA_EXSLB+EX_R11(r13) 1159 ld r12,PACA_EXSLB+EX_R12(r13) 1160 ld r13,PACA_EXSLB+EX_R13(r13) 1161 rfid 1162 b . /* prevent speculative execution */ 1163 1164/* 1165 * Space for CPU0's segment table. 1166 * 1167 * On iSeries, the hypervisor must fill in at least one entry before 1168 * we get control (with relocate on). The address is given to the hv 1169 * as a page number (see xLparMap below), so this must be at a 1170 * fixed address (the linker can't compute (u64)&initial_stab >> 1171 * PAGE_SHIFT). 1172 */ 1173 . = STAB0_OFFSET /* 0x6000 */ 1174 .globl initial_stab 1175initial_stab: 1176 .space 4096 1177 1178#ifdef CONFIG_PPC_PSERIES 1179/* 1180 * Data area reserved for FWNMI option. 1181 * This address (0x7000) is fixed by the RPA. 1182 */ 1183 .= 0x7000 1184 .globl fwnmi_data_area 1185fwnmi_data_area: 1186#endif /* CONFIG_PPC_PSERIES */ 1187 1188 /* iSeries does not use the FWNMI stuff, so it is safe to put 1189 * this here, even if we later allow kernels that will boot on 1190 * both pSeries and iSeries */ 1191#ifdef CONFIG_PPC_ISERIES 1192 . = LPARMAP_PHYS 1193 .globl xLparMap 1194xLparMap: 1195 .quad HvEsidsToMap /* xNumberEsids */ 1196 .quad HvRangesToMap /* xNumberRanges */ 1197 .quad STAB0_PAGE /* xSegmentTableOffs */ 1198 .zero 40 /* xRsvd */ 1199 /* xEsids (HvEsidsToMap entries of 2 quads) */ 1200 .quad PAGE_OFFSET_ESID /* xKernelEsid */ 1201 .quad PAGE_OFFSET_VSID /* xKernelVsid */ 1202 .quad VMALLOC_START_ESID /* xKernelEsid */ 1203 .quad VMALLOC_START_VSID /* xKernelVsid */ 1204 /* xRanges (HvRangesToMap entries of 3 quads) */ 1205 .quad HvPagesToMap /* xPages */ 1206 .quad 0 /* xOffset */ 1207 .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */ 1208 1209#endif /* CONFIG_PPC_ISERIES */ 1210 1211#ifdef CONFIG_PPC_PSERIES 1212 . = 0x8000 1213#endif /* CONFIG_PPC_PSERIES */ 1214 1215/* 1216 * On pSeries and most other platforms, secondary processors spin 1217 * in the following code. 1218 * At entry, r3 = this processor's number (physical cpu id) 1219 */ 1220_GLOBAL(generic_secondary_smp_init) 1221 mr r24,r3 1222 1223 /* turn on 64-bit mode */ 1224 bl .enable_64b_mode 1225 1226 /* get the TOC pointer (real address) */ 1227 bl .relative_toc 1228 1229 /* Set up a paca value for this processor. Since we have the 1230 * physical cpu id in r24, we need to search the pacas to find 1231 * which logical id maps to our physical one. 1232 */ 1233 LOAD_REG_ADDR(r13, paca) /* Get base vaddr of paca array */ 1234 li r5,0 /* logical cpu id */ 12351: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 1236 cmpw r6,r24 /* Compare to our id */ 1237 beq 2f 1238 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 1239 addi r5,r5,1 1240 cmpwi r5,NR_CPUS 1241 blt 1b 1242 1243 mr r3,r24 /* not found, copy phys to r3 */ 1244 b .kexec_wait /* next kernel might do better */ 1245 12462: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1247 /* From now on, r24 is expected to be logical cpuid */ 1248 mr r24,r5 12493: HMT_LOW 1250 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 1251 /* start. */ 1252 1253#ifndef CONFIG_SMP 1254 b 3b /* Never go on non-SMP */ 1255#else 1256 cmpwi 0,r23,0 1257 beq 3b /* Loop until told to go */ 1258 1259 sync /* order paca.run and cur_cpu_spec */ 1260 1261 /* See if we need to call a cpu state restore handler */ 1262 LOAD_REG_ADDR(r23, cur_cpu_spec) 1263 ld r23,0(r23) 1264 ld r23,CPU_SPEC_RESTORE(r23) 1265 cmpdi 0,r23,0 1266 beq 4f 1267 ld r23,0(r23) 1268 mtctr r23 1269 bctrl 1270 12714: /* Create a temp kernel stack for use before relocation is on. */ 1272 ld r1,PACAEMERGSP(r13) 1273 subi r1,r1,STACK_FRAME_OVERHEAD 1274 1275 b __secondary_start 1276#endif 1277 1278/* 1279 * Turn the MMU off. 1280 * Assumes we're mapped EA == RA if the MMU is on. 1281 */ 1282_STATIC(__mmu_off) 1283 mfmsr r3 1284 andi. r0,r3,MSR_IR|MSR_DR 1285 beqlr 1286 mflr r4 1287 andc r3,r3,r0 1288 mtspr SPRN_SRR0,r4 1289 mtspr SPRN_SRR1,r3 1290 sync 1291 rfid 1292 b . /* prevent speculative execution */ 1293 1294 1295/* 1296 * Here is our main kernel entry point. We support currently 2 kind of entries 1297 * depending on the value of r5. 1298 * 1299 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 1300 * in r3...r7 1301 * 1302 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 1303 * DT block, r4 is a physical pointer to the kernel itself 1304 * 1305 */ 1306_GLOBAL(__start_initialization_multiplatform) 1307 /* Make sure we are running in 64 bits mode */ 1308 bl .enable_64b_mode 1309 1310 /* Get TOC pointer (current runtime address) */ 1311 bl .relative_toc 1312 1313 /* find out where we are now */ 1314 bcl 20,31,$+4 13150: mflr r26 /* r26 = runtime addr here */ 1316 addis r26,r26,(_stext - 0b)@ha 1317 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 1318 1319 /* 1320 * Are we booted from a PROM Of-type client-interface ? 1321 */ 1322 cmpldi cr0,r5,0 1323 beq 1f 1324 b .__boot_from_prom /* yes -> prom */ 13251: 1326 /* Save parameters */ 1327 mr r31,r3 1328 mr r30,r4 1329 1330 /* Setup some critical 970 SPRs before switching MMU off */ 1331 mfspr r0,SPRN_PVR 1332 srwi r0,r0,16 1333 cmpwi r0,0x39 /* 970 */ 1334 beq 1f 1335 cmpwi r0,0x3c /* 970FX */ 1336 beq 1f 1337 cmpwi r0,0x44 /* 970MP */ 1338 beq 1f 1339 cmpwi r0,0x45 /* 970GX */ 1340 bne 2f 13411: bl .__cpu_preinit_ppc970 13422: 1343 1344 /* Switch off MMU if not already off */ 1345 bl .__mmu_off 1346 b .__after_prom_start 1347 1348_INIT_STATIC(__boot_from_prom) 1349 /* Save parameters */ 1350 mr r31,r3 1351 mr r30,r4 1352 mr r29,r5 1353 mr r28,r6 1354 mr r27,r7 1355 1356 /* 1357 * Align the stack to 16-byte boundary 1358 * Depending on the size and layout of the ELF sections in the initial 1359 * boot binary, the stack pointer may be unaligned on PowerMac 1360 */ 1361 rldicr r1,r1,0,59 1362 1363#ifdef CONFIG_RELOCATABLE 1364 /* Relocate code for where we are now */ 1365 mr r3,r26 1366 bl .relocate 1367#endif 1368 1369 /* Restore parameters */ 1370 mr r3,r31 1371 mr r4,r30 1372 mr r5,r29 1373 mr r6,r28 1374 mr r7,r27 1375 1376 /* Do all of the interaction with OF client interface */ 1377 mr r8,r26 1378 bl .prom_init 1379 /* We never return */ 1380 trap 1381 1382_STATIC(__after_prom_start) 1383#ifdef CONFIG_RELOCATABLE 1384 /* process relocations for the final address of the kernel */ 1385 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 1386 sldi r25,r25,32 1387 mr r3,r25 1388 bl .relocate 1389#endif 1390 1391/* 1392 * We need to run with _stext at physical address PHYSICAL_START. 1393 * This will leave some code in the first 256B of 1394 * real memory, which are reserved for software use. 1395 * 1396 * Note: This process overwrites the OF exception vectors. 1397 */ 1398 li r3,0 /* target addr */ 1399 mr. r4,r26 /* In some cases the loader may */ 1400 beq 9f /* have already put us at zero */ 1401 lis r5,(copy_to_here - _stext)@ha 1402 addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ 1403 li r6,0x100 /* Start offset, the first 0x100 */ 1404 /* bytes were copied earlier. */ 1405 1406 bl .copy_and_flush /* copy the first n bytes */ 1407 /* this includes the code being */ 1408 /* executed here. */ 1409 addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ 1410 addi r8,r8,(4f - _stext)@l /* that we just made */ 1411 mtctr r8 1412 bctr 1413 14144: /* Now copy the rest of the kernel up to _end */ 1415 addis r5,r26,(p_end - _stext)@ha 1416 ld r5,(p_end - _stext)@l(r5) /* get _end */ 1417 bl .copy_and_flush /* copy the rest */ 1418 14199: b .start_here_multiplatform 1420 1421p_end: .llong _end - _stext 1422 1423/* 1424 * Copy routine used to copy the kernel to start at physical address 0 1425 * and flush and invalidate the caches as needed. 1426 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 1427 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 1428 * 1429 * Note: this routine *only* clobbers r0, r6 and lr 1430 */ 1431_GLOBAL(copy_and_flush) 1432 addi r5,r5,-8 1433 addi r6,r6,-8 14344: li r0,8 /* Use the smallest common */ 1435 /* denominator cache line */ 1436 /* size. This results in */ 1437 /* extra cache line flushes */ 1438 /* but operation is correct. */ 1439 /* Can't get cache line size */ 1440 /* from NACA as it is being */ 1441 /* moved too. */ 1442 1443 mtctr r0 /* put # words/line in ctr */ 14443: addi r6,r6,8 /* copy a cache line */ 1445 ldx r0,r6,r4 1446 stdx r0,r6,r3 1447 bdnz 3b 1448 dcbst r6,r3 /* write it to memory */ 1449 sync 1450 icbi r6,r3 /* flush the icache line */ 1451 cmpld 0,r6,r5 1452 blt 4b 1453 sync 1454 addi r5,r5,8 1455 addi r6,r6,8 1456 blr 1457 1458.align 8 1459copy_to_here: 1460 1461#ifdef CONFIG_SMP 1462#ifdef CONFIG_PPC_PMAC 1463/* 1464 * On PowerMac, secondary processors starts from the reset vector, which 1465 * is temporarily turned into a call to one of the functions below. 1466 */ 1467 .section ".text"; 1468 .align 2 ; 1469 1470 .globl __secondary_start_pmac_0 1471__secondary_start_pmac_0: 1472 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 1473 li r24,0 1474 b 1f 1475 li r24,1 1476 b 1f 1477 li r24,2 1478 b 1f 1479 li r24,3 14801: 1481 1482_GLOBAL(pmac_secondary_start) 1483 /* turn on 64-bit mode */ 1484 bl .enable_64b_mode 1485 1486 /* get TOC pointer (real address) */ 1487 bl .relative_toc 1488 1489 /* Copy some CPU settings from CPU 0 */ 1490 bl .__restore_cpu_ppc970 1491 1492 /* pSeries do that early though I don't think we really need it */ 1493 mfmsr r3 1494 ori r3,r3,MSR_RI 1495 mtmsrd r3 /* RI on */ 1496 1497 /* Set up a paca value for this processor. */ 1498 LOAD_REG_ADDR(r4,paca) /* Get base vaddr of paca array */ 1499 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 1500 add r13,r13,r4 /* for this processor. */ 1501 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1502 1503 /* Create a temp kernel stack for use before relocation is on. */ 1504 ld r1,PACAEMERGSP(r13) 1505 subi r1,r1,STACK_FRAME_OVERHEAD 1506 1507 b __secondary_start 1508 1509#endif /* CONFIG_PPC_PMAC */ 1510 1511/* 1512 * This function is called after the master CPU has released the 1513 * secondary processors. The execution environment is relocation off. 1514 * The paca for this processor has the following fields initialized at 1515 * this point: 1516 * 1. Processor number 1517 * 2. Segment table pointer (virtual address) 1518 * On entry the following are set: 1519 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 1520 * r24 = cpu# (in Linux terms) 1521 * r13 = paca virtual address 1522 * SPRG3 = paca virtual address 1523 */ 1524 .globl __secondary_start 1525__secondary_start: 1526 /* Set thread priority to MEDIUM */ 1527 HMT_MEDIUM 1528 1529 /* Do early setup for that CPU (stab, slb, hash table pointer) */ 1530 bl .early_setup_secondary 1531 1532 /* Initialize the kernel stack. Just a repeat for iSeries. */ 1533 LOAD_REG_ADDR(r3, current_set) 1534 sldi r28,r24,3 /* get current_set[cpu#] */ 1535 ldx r1,r3,r28 1536 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1537 std r1,PACAKSAVE(r13) 1538 1539 /* Clear backchain so we get nice backtraces */ 1540 li r7,0 1541 mtlr r7 1542 1543 /* enable MMU and jump to start_secondary */ 1544 LOAD_REG_ADDR(r3, .start_secondary_prolog) 1545 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 1546#ifdef CONFIG_PPC_ISERIES 1547BEGIN_FW_FTR_SECTION 1548 ori r4,r4,MSR_EE 1549 li r8,1 1550 stb r8,PACAHARDIRQEN(r13) 1551END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1552#endif 1553BEGIN_FW_FTR_SECTION 1554 stb r7,PACAHARDIRQEN(r13) 1555END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1556 stb r7,PACASOFTIRQEN(r13) 1557 1558 mtspr SPRN_SRR0,r3 1559 mtspr SPRN_SRR1,r4 1560 rfid 1561 b . /* prevent speculative execution */ 1562 1563/* 1564 * Running with relocation on at this point. All we want to do is 1565 * zero the stack back-chain pointer and get the TOC virtual address 1566 * before going into C code. 1567 */ 1568_GLOBAL(start_secondary_prolog) 1569 ld r2,PACATOC(r13) 1570 li r3,0 1571 std r3,0(r1) /* Zero the stack frame pointer */ 1572 bl .start_secondary 1573 b . 1574#endif 1575 1576/* 1577 * This subroutine clobbers r11 and r12 1578 */ 1579_GLOBAL(enable_64b_mode) 1580 mfmsr r11 /* grab the current MSR */ 1581 li r12,(MSR_SF | MSR_ISF)@highest 1582 sldi r12,r12,48 1583 or r11,r11,r12 1584 mtmsrd r11 1585 isync 1586 blr 1587 1588/* 1589 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 1590 * by the toolchain). It computes the correct value for wherever we 1591 * are running at the moment, using position-independent code. 1592 */ 1593_GLOBAL(relative_toc) 1594 mflr r0 1595 bcl 20,31,$+4 15960: mflr r9 1597 ld r2,(p_toc - 0b)(r9) 1598 add r2,r2,r9 1599 mtlr r0 1600 blr 1601 1602p_toc: .llong __toc_start + 0x8000 - 0b 1603 1604/* 1605 * This is where the main kernel code starts. 1606 */ 1607_INIT_STATIC(start_here_multiplatform) 1608 /* set up the TOC (real address) */ 1609 bl .relative_toc 1610 1611 /* Clear out the BSS. It may have been done in prom_init, 1612 * already but that's irrelevant since prom_init will soon 1613 * be detached from the kernel completely. Besides, we need 1614 * to clear it now for kexec-style entry. 1615 */ 1616 LOAD_REG_ADDR(r11,__bss_stop) 1617 LOAD_REG_ADDR(r8,__bss_start) 1618 sub r11,r11,r8 /* bss size */ 1619 addi r11,r11,7 /* round up to an even double word */ 1620 srdi. r11,r11,3 /* shift right by 3 */ 1621 beq 4f 1622 addi r8,r8,-8 1623 li r0,0 1624 mtctr r11 /* zero this many doublewords */ 16253: stdu r0,8(r8) 1626 bdnz 3b 16274: 1628 1629 mfmsr r6 1630 ori r6,r6,MSR_RI 1631 mtmsrd r6 /* RI on */ 1632 1633#ifdef CONFIG_RELOCATABLE 1634 /* Save the physical address we're running at in kernstart_addr */ 1635 LOAD_REG_ADDR(r4, kernstart_addr) 1636 clrldi r0,r25,2 1637 std r0,0(r4) 1638#endif 1639 1640 /* The following gets the stack set up with the regs */ 1641 /* pointing to the real addr of the kernel stack. This is */ 1642 /* all done to support the C function call below which sets */ 1643 /* up the htab. This is done because we have relocated the */ 1644 /* kernel but are still running in real mode. */ 1645 1646 LOAD_REG_ADDR(r3,init_thread_union) 1647 1648 /* set up a stack pointer */ 1649 addi r1,r3,THREAD_SIZE 1650 li r0,0 1651 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1652 1653 /* Do very early kernel initializations, including initial hash table, 1654 * stab and slb setup before we turn on relocation. */ 1655 1656 /* Restore parameters passed from prom_init/kexec */ 1657 mr r3,r31 1658 bl .early_setup /* also sets r13 and SPRG3 */ 1659 1660 LOAD_REG_ADDR(r3, .start_here_common) 1661 ld r4,PACAKMSR(r13) 1662 mtspr SPRN_SRR0,r3 1663 mtspr SPRN_SRR1,r4 1664 rfid 1665 b . /* prevent speculative execution */ 1666 1667 /* This is where all platforms converge execution */ 1668_INIT_GLOBAL(start_here_common) 1669 /* relocation is on at this point */ 1670 std r1,PACAKSAVE(r13) 1671 1672 /* Load the TOC (virtual address) */ 1673 ld r2,PACATOC(r13) 1674 1675 bl .setup_system 1676 1677 /* Load up the kernel context */ 16785: 1679 li r5,0 1680 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ 1681#ifdef CONFIG_PPC_ISERIES 1682BEGIN_FW_FTR_SECTION 1683 mfmsr r5 1684 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/ 1685 mtmsrd r5 1686 li r5,1 1687END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1688#endif 1689 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */ 1690 1691 bl .start_kernel 1692 1693 /* Not reached */ 1694 BUG_OPCODE 1695 1696/* 1697 * We put a few things here that have to be page-aligned. 1698 * This stuff goes at the beginning of the bss, which is page-aligned. 1699 */ 1700 .section ".bss" 1701 1702 .align PAGE_SHIFT 1703 1704 .globl empty_zero_page 1705empty_zero_page: 1706 .space PAGE_SIZE 1707 1708 .globl swapper_pg_dir 1709swapper_pg_dir: 1710 .space PGD_TABLE_SIZE 1711