10ebc4cdaSBenjamin Herrenschmidt/* 20ebc4cdaSBenjamin Herrenschmidt * This file contains the 64-bit "server" PowerPC variant 30ebc4cdaSBenjamin Herrenschmidt * of the low level exception handling including exception 40ebc4cdaSBenjamin Herrenschmidt * vectors, exception return, part of the slb and stab 50ebc4cdaSBenjamin Herrenschmidt * handling and other fixed offset specific things. 60ebc4cdaSBenjamin Herrenschmidt * 70ebc4cdaSBenjamin Herrenschmidt * This file is meant to be #included from head_64.S due to 825985edcSLucas De Marchi * position dependent assembly. 90ebc4cdaSBenjamin Herrenschmidt * 100ebc4cdaSBenjamin Herrenschmidt * Most of this originates from head_64.S and thus has the same 110ebc4cdaSBenjamin Herrenschmidt * copyright history. 120ebc4cdaSBenjamin Herrenschmidt * 130ebc4cdaSBenjamin Herrenschmidt */ 140ebc4cdaSBenjamin Herrenschmidt 157230c564SBenjamin Herrenschmidt#include <asm/hw_irq.h> 168aa34ab8SBenjamin Herrenschmidt#include <asm/exception-64s.h> 1746f52210SStephen Rothwell#include <asm/ptrace.h> 187cba160aSShreyas B. Prabhu#include <asm/cpuidle.h> 19da2bc464SMichael Ellerman#include <asm/head-64.h> 208aa34ab8SBenjamin Herrenschmidt 210ebc4cdaSBenjamin Herrenschmidt/* 2257f26649SNicholas Piggin * There are a few constraints to be concerned with. 2357f26649SNicholas Piggin * - Real mode exceptions code/data must be located at their physical location. 2457f26649SNicholas Piggin * - Virtual mode exceptions must be mapped at their 0xc000... location. 2557f26649SNicholas Piggin * - Fixed location code must not call directly beyond the __end_interrupts 2657f26649SNicholas Piggin * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 2757f26649SNicholas Piggin * must be used. 2857f26649SNicholas Piggin * - LOAD_HANDLER targets must be within first 64K of physical 0 / 2957f26649SNicholas Piggin * virtual 0xc00... 3057f26649SNicholas Piggin * - Conditional branch targets must be within +/-32K of caller. 3157f26649SNicholas Piggin * 3257f26649SNicholas Piggin * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 3357f26649SNicholas Piggin * therefore don't have to run in physically located code or rfid to 3457f26649SNicholas Piggin * virtual mode kernel code. However on relocatable kernels they do have 3557f26649SNicholas Piggin * to branch to KERNELBASE offset because the rest of the kernel (outside 3657f26649SNicholas Piggin * the exception vectors) may be located elsewhere. 3757f26649SNicholas Piggin * 3857f26649SNicholas Piggin * Virtual exceptions correspond with physical, except their entry points 3957f26649SNicholas Piggin * are offset by 0xc000000000000000 and also tend to get an added 0x4000 4057f26649SNicholas Piggin * offset applied. Virtual exceptions are enabled with the Alternate 4157f26649SNicholas Piggin * Interrupt Location (AIL) bit set in the LPCR. However this does not 4257f26649SNicholas Piggin * guarantee they will be delivered virtually. Some conditions (see the ISA) 4357f26649SNicholas Piggin * cause exceptions to be delivered in real mode. 4457f26649SNicholas Piggin * 4557f26649SNicholas Piggin * It's impossible to receive interrupts below 0x300 via AIL. 4657f26649SNicholas Piggin * 4757f26649SNicholas Piggin * KVM: None of the virtual exceptions are from the guest. Anything that 4857f26649SNicholas Piggin * escalated to HV=1 from HV=0 is delivered via real mode handlers. 4957f26649SNicholas Piggin * 5057f26649SNicholas Piggin * 510ebc4cdaSBenjamin Herrenschmidt * We layout physical memory as follows: 520ebc4cdaSBenjamin Herrenschmidt * 0x0000 - 0x00ff : Secondary processor spin code 5357f26649SNicholas Piggin * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 5457f26649SNicholas Piggin * 0x1900 - 0x3fff : Real mode trampolines 5557f26649SNicholas Piggin * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 5657f26649SNicholas Piggin * 0x5900 - 0x6fff : Relon mode trampolines 570ebc4cdaSBenjamin Herrenschmidt * 0x7000 - 0x7fff : FWNMI data area 5857f26649SNicholas Piggin * 0x8000 - .... : Common interrupt handlers, remaining early 5957f26649SNicholas Piggin * setup code, rest of kernel. 600ebc4cdaSBenjamin Herrenschmidt */ 6157f26649SNicholas PigginOPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 6257f26649SNicholas PigginOPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 6357f26649SNicholas PigginOPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 6457f26649SNicholas PigginOPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 6557f26649SNicholas Piggin#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 6657f26649SNicholas Piggin/* 6757f26649SNicholas Piggin * Data area reserved for FWNMI option. 6857f26649SNicholas Piggin * This address (0x7000) is fixed by the RPA. 6957f26649SNicholas Piggin * pseries and powernv need to keep the whole page from 7057f26649SNicholas Piggin * 0x7000 to 0x8000 free for use by the firmware 7157f26649SNicholas Piggin */ 7257f26649SNicholas PigginZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 7357f26649SNicholas PigginOPEN_TEXT_SECTION(0x8000) 7457f26649SNicholas Piggin#else 7557f26649SNicholas PigginOPEN_TEXT_SECTION(0x7000) 7657f26649SNicholas Piggin#endif 7757f26649SNicholas Piggin 7857f26649SNicholas PigginUSE_FIXED_SECTION(real_vectors) 7957f26649SNicholas Piggin 8057f26649SNicholas Piggin#define LOAD_SYSCALL_HANDLER(reg) \ 8157f26649SNicholas Piggin ld reg,PACAKBASE(r13); \ 8257f26649SNicholas Piggin ori reg,reg,(ABS_ADDR(system_call_common))@l; 8357f26649SNicholas Piggin 84742415d6SMichael Neuling /* Syscall routine is used twice, in reloc-off and reloc-on paths */ 85742415d6SMichael Neuling#define SYSCALL_PSERIES_1 \ 86742415d6SMichael NeulingBEGIN_FTR_SECTION \ 87742415d6SMichael Neuling cmpdi r0,0x1ebe ; \ 88742415d6SMichael Neuling beq- 1f ; \ 89742415d6SMichael NeulingEND_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 90742415d6SMichael Neuling mr r9,r13 ; \ 91742415d6SMichael Neuling GET_PACA(r13) ; \ 92742415d6SMichael Neuling mfspr r11,SPRN_SRR0 ; \ 93742415d6SMichael Neuling0: 94742415d6SMichael Neuling 95742415d6SMichael Neuling#define SYSCALL_PSERIES_2_RFID \ 96742415d6SMichael Neuling mfspr r12,SPRN_SRR1 ; \ 9757f26649SNicholas Piggin LOAD_SYSCALL_HANDLER(r10) ; \ 98742415d6SMichael Neuling mtspr SPRN_SRR0,r10 ; \ 99742415d6SMichael Neuling ld r10,PACAKMSR(r13) ; \ 100742415d6SMichael Neuling mtspr SPRN_SRR1,r10 ; \ 101742415d6SMichael Neuling rfid ; \ 102742415d6SMichael Neuling b . ; /* prevent speculative execution */ 103742415d6SMichael Neuling 104742415d6SMichael Neuling#define SYSCALL_PSERIES_3 \ 105742415d6SMichael Neuling /* Fast LE/BE switch system call */ \ 106742415d6SMichael Neuling1: mfspr r12,SPRN_SRR1 ; \ 107742415d6SMichael Neuling xori r12,r12,MSR_LE ; \ 108742415d6SMichael Neuling mtspr SPRN_SRR1,r12 ; \ 109742415d6SMichael Neuling rfid ; /* return to userspace */ \ 110742415d6SMichael Neuling b . ; /* prevent speculative execution */ 111742415d6SMichael Neuling 1124700dfafSMichael Neuling#if defined(CONFIG_RELOCATABLE) 1134700dfafSMichael Neuling /* 11405b05f28SAnton Blanchard * We can't branch directly so we do it via the CTR which 11505b05f28SAnton Blanchard * is volatile across system calls. 1164700dfafSMichael Neuling */ 1174700dfafSMichael Neuling#define SYSCALL_PSERIES_2_DIRECT \ 11857f26649SNicholas Piggin LOAD_SYSCALL_HANDLER(r12) ; \ 1196a404806SMichael Neuling mtctr r12 ; \ 1204700dfafSMichael Neuling mfspr r12,SPRN_SRR1 ; \ 12118e3f56bSNicholas Piggin li r10,MSR_RI ; \ 12218e3f56bSNicholas Piggin mtmsrd r10,1 ; \ 1236a404806SMichael Neuling bctr ; 1244700dfafSMichael Neuling#else 1254700dfafSMichael Neuling /* We can branch directly */ 1264700dfafSMichael Neuling#define SYSCALL_PSERIES_2_DIRECT \ 1274700dfafSMichael Neuling mfspr r12,SPRN_SRR1 ; \ 1284700dfafSMichael Neuling li r10,MSR_RI ; \ 1294700dfafSMichael Neuling mtmsrd r10,1 ; /* Set RI (EE=0) */ \ 130d20be433SAnton Blanchard b system_call_common ; 1314700dfafSMichael Neuling#endif 1320ebc4cdaSBenjamin Herrenschmidt 1330ebc4cdaSBenjamin Herrenschmidt/* 1340ebc4cdaSBenjamin Herrenschmidt * This is the start of the interrupt handlers for pSeries 1350ebc4cdaSBenjamin Herrenschmidt * This code runs with relocation off. 1360ebc4cdaSBenjamin Herrenschmidt * Code from here to __end_interrupts gets copied down to real 1370ebc4cdaSBenjamin Herrenschmidt * address 0x100 when we are running a relocatable kernel. 1380ebc4cdaSBenjamin Herrenschmidt * Therefore any relative branches in this section must only 1390ebc4cdaSBenjamin Herrenschmidt * branch to labels in this section. 1400ebc4cdaSBenjamin Herrenschmidt */ 1410ebc4cdaSBenjamin Herrenschmidt .globl __start_interrupts 1420ebc4cdaSBenjamin Herrenschmidt__start_interrupts: 1430ebc4cdaSBenjamin Herrenschmidt 144da2bc464SMichael EllermanEXC_REAL_BEGIN(system_reset, 0x100, 0x200) 145948cf67cSBenjamin Herrenschmidt SET_SCRATCH0(r13) 146948cf67cSBenjamin Herrenschmidt#ifdef CONFIG_PPC_P7_NAP 147948cf67cSBenjamin HerrenschmidtBEGIN_FTR_SECTION 148948cf67cSBenjamin Herrenschmidt /* Running native on arch 2.06 or later, check if we are 14977b54e9fSShreyas B. Prabhu * waking up from nap/sleep/winkle. 150948cf67cSBenjamin Herrenschmidt */ 151948cf67cSBenjamin Herrenschmidt mfspr r13,SPRN_SRR1 152371fefd6SPaul Mackerras rlwinm. r13,r13,47-31,30,31 153371fefd6SPaul Mackerras beq 9f 154371fefd6SPaul Mackerras 1557cba160aSShreyas B. Prabhu cmpwi cr3,r13,2 156371fefd6SPaul Mackerras GET_PACA(r13) 1575fa6b6bdSShreyas B. Prabhu bl pnv_restore_hyp_resource 15877b54e9fSShreyas B. Prabhu 1597cba160aSShreyas B. Prabhu li r0,PNV_THREAD_RUNNING 1607cba160aSShreyas B. Prabhu stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ 161371fefd6SPaul Mackerras 1623a167beaSAneesh Kumar K.V#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 163f0888f70SPaul Mackerras li r0,KVM_HWTHREAD_IN_KERNEL 164f0888f70SPaul Mackerras stb r0,HSTATE_HWTHREAD_STATE(r13) 165f0888f70SPaul Mackerras /* Order setting hwthread_state vs. testing hwthread_req */ 166f0888f70SPaul Mackerras sync 167f0888f70SPaul Mackerras lbz r0,HSTATE_HWTHREAD_REQ(r13) 168f0888f70SPaul Mackerras cmpwi r0,0 169f0888f70SPaul Mackerras beq 1f 170371fefd6SPaul Mackerras b kvm_start_guest 171371fefd6SPaul Mackerras1: 172371fefd6SPaul Mackerras#endif 173371fefd6SPaul Mackerras 17456548fc0SPaul Mackerras /* Return SRR1 from power7_nap() */ 17556548fc0SPaul Mackerras mfspr r3,SPRN_SRR1 17617065671SShreyas B. Prabhu blt cr3,2f 1775fa6b6bdSShreyas B. Prabhu b pnv_wakeup_loss 1785fa6b6bdSShreyas B. Prabhu2: b pnv_wakeup_noloss 179aca79d2bSVaidyanathan Srinivasan 180371fefd6SPaul Mackerras9: 181969391c5SPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 182948cf67cSBenjamin Herrenschmidt#endif /* CONFIG_PPC_P7_NAP */ 183b01c8b54SPaul Mackerras EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, 184b01c8b54SPaul Mackerras NOTEST, 0x100) 185da2bc464SMichael EllermanEXC_REAL_END(system_reset, 0x100, 0x200) 186582baf44SNicholas PigginEXC_VIRT_NONE(0x4100, 0x4200) 187582baf44SNicholas PigginEXC_COMMON(system_reset_common, 0x100, system_reset_exception) 188582baf44SNicholas Piggin 189582baf44SNicholas Piggin#ifdef CONFIG_PPC_PSERIES 190582baf44SNicholas Piggin/* 191582baf44SNicholas Piggin * Vectors for the FWNMI option. Share common code. 192582baf44SNicholas Piggin */ 193582baf44SNicholas PigginTRAMP_REAL_BEGIN(system_reset_fwnmi) 194582baf44SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 195582baf44SNicholas Piggin EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, 196582baf44SNicholas Piggin NOTEST, 0x100) 197582baf44SNicholas Piggin#endif /* CONFIG_PPC_PSERIES */ 198582baf44SNicholas Piggin 1990ebc4cdaSBenjamin Herrenschmidt 200da2bc464SMichael EllermanEXC_REAL_BEGIN(machine_check, 0x200, 0x300) 201b01c8b54SPaul Mackerras /* This is moved out of line as it can be patched by FW, but 202b01c8b54SPaul Mackerras * some code path might still want to branch into the original 203b01c8b54SPaul Mackerras * vector 204b01c8b54SPaul Mackerras */ 2051707dd16SPaul Mackerras SET_SCRATCH0(r13) /* save r13 */ 206bc14c491SMahesh Salgaonkar /* 207bc14c491SMahesh Salgaonkar * Running native on arch 2.06 or later, we may wakeup from winkle 208bc14c491SMahesh Salgaonkar * inside machine check. If yes, then last bit of HSPGR0 would be set 209bc14c491SMahesh Salgaonkar * to 1. Hence clear it unconditionally. 2101c51089fSMahesh Salgaonkar */ 211bc14c491SMahesh Salgaonkar GET_PACA(r13) 212bc14c491SMahesh Salgaonkar clrrdi r13,r13,1 213bc14c491SMahesh Salgaonkar SET_PACA(r13) 2141707dd16SPaul Mackerras EXCEPTION_PROLOG_0(PACA_EXMC) 2151e9b4507SMahesh SalgaonkarBEGIN_FTR_SECTION 2162513767dSMahesh Salgaonkar b machine_check_powernv_early 2171e9b4507SMahesh SalgaonkarFTR_SECTION_ELSE 2181707dd16SPaul Mackerras b machine_check_pSeries_0 2191e9b4507SMahesh SalgaonkarALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 220da2bc464SMichael EllermanEXC_REAL_END(machine_check, 0x200, 0x300) 221afcf0095SNicholas PigginEXC_VIRT_NONE(0x4200, 0x4300) 222afcf0095SNicholas PigginTRAMP_REAL_BEGIN(machine_check_powernv_early) 223afcf0095SNicholas PigginBEGIN_FTR_SECTION 224afcf0095SNicholas Piggin EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) 225afcf0095SNicholas Piggin /* 226afcf0095SNicholas Piggin * Register contents: 227afcf0095SNicholas Piggin * R13 = PACA 228afcf0095SNicholas Piggin * R9 = CR 229afcf0095SNicholas Piggin * Original R9 to R13 is saved on PACA_EXMC 230afcf0095SNicholas Piggin * 231afcf0095SNicholas Piggin * Switch to mc_emergency stack and handle re-entrancy (we limit 232afcf0095SNicholas Piggin * the nested MCE upto level 4 to avoid stack overflow). 233afcf0095SNicholas Piggin * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 234afcf0095SNicholas Piggin * 235afcf0095SNicholas Piggin * We use paca->in_mce to check whether this is the first entry or 236afcf0095SNicholas Piggin * nested machine check. We increment paca->in_mce to track nested 237afcf0095SNicholas Piggin * machine checks. 238afcf0095SNicholas Piggin * 239afcf0095SNicholas Piggin * If this is the first entry then set stack pointer to 240afcf0095SNicholas Piggin * paca->mc_emergency_sp, otherwise r1 is already pointing to 241afcf0095SNicholas Piggin * stack frame on mc_emergency stack. 242afcf0095SNicholas Piggin * 243afcf0095SNicholas Piggin * NOTE: We are here with MSR_ME=0 (off), which means we risk a 244afcf0095SNicholas Piggin * checkstop if we get another machine check exception before we do 245afcf0095SNicholas Piggin * rfid with MSR_ME=1. 246afcf0095SNicholas Piggin */ 247afcf0095SNicholas Piggin mr r11,r1 /* Save r1 */ 248afcf0095SNicholas Piggin lhz r10,PACA_IN_MCE(r13) 249afcf0095SNicholas Piggin cmpwi r10,0 /* Are we in nested machine check */ 250afcf0095SNicholas Piggin bne 0f /* Yes, we are. */ 251afcf0095SNicholas Piggin /* First machine check entry */ 252afcf0095SNicholas Piggin ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 253afcf0095SNicholas Piggin0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 254afcf0095SNicholas Piggin addi r10,r10,1 /* increment paca->in_mce */ 255afcf0095SNicholas Piggin sth r10,PACA_IN_MCE(r13) 256afcf0095SNicholas Piggin /* Limit nested MCE to level 4 to avoid stack overflow */ 257afcf0095SNicholas Piggin cmpwi r10,4 258afcf0095SNicholas Piggin bgt 2f /* Check if we hit limit of 4 */ 259afcf0095SNicholas Piggin std r11,GPR1(r1) /* Save r1 on the stack. */ 260afcf0095SNicholas Piggin std r11,0(r1) /* make stack chain pointer */ 261afcf0095SNicholas Piggin mfspr r11,SPRN_SRR0 /* Save SRR0 */ 262afcf0095SNicholas Piggin std r11,_NIP(r1) 263afcf0095SNicholas Piggin mfspr r11,SPRN_SRR1 /* Save SRR1 */ 264afcf0095SNicholas Piggin std r11,_MSR(r1) 265afcf0095SNicholas Piggin mfspr r11,SPRN_DAR /* Save DAR */ 266afcf0095SNicholas Piggin std r11,_DAR(r1) 267afcf0095SNicholas Piggin mfspr r11,SPRN_DSISR /* Save DSISR */ 268afcf0095SNicholas Piggin std r11,_DSISR(r1) 269afcf0095SNicholas Piggin std r9,_CCR(r1) /* Save CR in stackframe */ 270afcf0095SNicholas Piggin /* Save r9 through r13 from EXMC save area to stack frame. */ 271afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 272afcf0095SNicholas Piggin mfmsr r11 /* get MSR value */ 273afcf0095SNicholas Piggin ori r11,r11,MSR_ME /* turn on ME bit */ 274afcf0095SNicholas Piggin ori r11,r11,MSR_RI /* turn on RI bit */ 275afcf0095SNicholas Piggin LOAD_HANDLER(r12, machine_check_handle_early) 276afcf0095SNicholas Piggin1: mtspr SPRN_SRR0,r12 277afcf0095SNicholas Piggin mtspr SPRN_SRR1,r11 278afcf0095SNicholas Piggin rfid 279afcf0095SNicholas Piggin b . /* prevent speculative execution */ 280afcf0095SNicholas Piggin2: 281afcf0095SNicholas Piggin /* Stack overflow. Stay on emergency stack and panic. 282afcf0095SNicholas Piggin * Keep the ME bit off while panic-ing, so that if we hit 283afcf0095SNicholas Piggin * another machine check we checkstop. 284afcf0095SNicholas Piggin */ 285afcf0095SNicholas Piggin addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 286afcf0095SNicholas Piggin ld r11,PACAKMSR(r13) 287afcf0095SNicholas Piggin LOAD_HANDLER(r12, unrecover_mce) 288afcf0095SNicholas Piggin li r10,MSR_ME 289afcf0095SNicholas Piggin andc r11,r11,r10 /* Turn off MSR_ME */ 290afcf0095SNicholas Piggin b 1b 291afcf0095SNicholas Piggin b . /* prevent speculative execution */ 292afcf0095SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 293afcf0095SNicholas Piggin 294afcf0095SNicholas PigginTRAMP_REAL_BEGIN(machine_check_pSeries) 295afcf0095SNicholas Piggin .globl machine_check_fwnmi 296afcf0095SNicholas Pigginmachine_check_fwnmi: 297afcf0095SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 298afcf0095SNicholas Piggin EXCEPTION_PROLOG_0(PACA_EXMC) 299afcf0095SNicholas Pigginmachine_check_pSeries_0: 300afcf0095SNicholas Piggin EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) 301afcf0095SNicholas Piggin /* 302afcf0095SNicholas Piggin * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the 303afcf0095SNicholas Piggin * difference that MSR_RI is not enabled, because PACA_EXMC is being 304afcf0095SNicholas Piggin * used, so nested machine check corrupts it. machine_check_common 305afcf0095SNicholas Piggin * enables MSR_RI. 306afcf0095SNicholas Piggin */ 307afcf0095SNicholas Piggin ld r10,PACAKMSR(r13) 308afcf0095SNicholas Piggin xori r10,r10,MSR_RI 309afcf0095SNicholas Piggin mfspr r11,SPRN_SRR0 310afcf0095SNicholas Piggin LOAD_HANDLER(r12, machine_check_common) 311afcf0095SNicholas Piggin mtspr SPRN_SRR0,r12 312afcf0095SNicholas Piggin mfspr r12,SPRN_SRR1 313afcf0095SNicholas Piggin mtspr SPRN_SRR1,r10 314afcf0095SNicholas Piggin rfid 315afcf0095SNicholas Piggin b . /* prevent speculative execution */ 316afcf0095SNicholas Piggin 317afcf0095SNicholas PigginTRAMP_KVM_SKIP(PACA_EXMC, 0x200) 318afcf0095SNicholas Piggin 319afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_common) 320afcf0095SNicholas Piggin /* 321afcf0095SNicholas Piggin * Machine check is different because we use a different 322afcf0095SNicholas Piggin * save area: PACA_EXMC instead of PACA_EXGEN. 323afcf0095SNicholas Piggin */ 324afcf0095SNicholas Piggin mfspr r10,SPRN_DAR 325afcf0095SNicholas Piggin std r10,PACA_EXMC+EX_DAR(r13) 326afcf0095SNicholas Piggin mfspr r10,SPRN_DSISR 327afcf0095SNicholas Piggin stw r10,PACA_EXMC+EX_DSISR(r13) 328afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 329afcf0095SNicholas Piggin FINISH_NAP 330afcf0095SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 331afcf0095SNicholas Piggin ld r3,PACA_EXMC+EX_DAR(r13) 332afcf0095SNicholas Piggin lwz r4,PACA_EXMC+EX_DSISR(r13) 333afcf0095SNicholas Piggin /* Enable MSR_RI when finished with PACA_EXMC */ 334afcf0095SNicholas Piggin li r10,MSR_RI 335afcf0095SNicholas Piggin mtmsrd r10,1 336afcf0095SNicholas Piggin std r3,_DAR(r1) 337afcf0095SNicholas Piggin std r4,_DSISR(r1) 338afcf0095SNicholas Piggin bl save_nvgprs 339afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 340afcf0095SNicholas Piggin bl machine_check_exception 341afcf0095SNicholas Piggin b ret_from_except 342afcf0095SNicholas Piggin 343afcf0095SNicholas Piggin#define MACHINE_CHECK_HANDLER_WINDUP \ 344afcf0095SNicholas Piggin /* Clear MSR_RI before setting SRR0 and SRR1. */\ 345afcf0095SNicholas Piggin li r0,MSR_RI; \ 346afcf0095SNicholas Piggin mfmsr r9; /* get MSR value */ \ 347afcf0095SNicholas Piggin andc r9,r9,r0; \ 348afcf0095SNicholas Piggin mtmsrd r9,1; /* Clear MSR_RI */ \ 349afcf0095SNicholas Piggin /* Move original SRR0 and SRR1 into the respective regs */ \ 350afcf0095SNicholas Piggin ld r9,_MSR(r1); \ 351afcf0095SNicholas Piggin mtspr SPRN_SRR1,r9; \ 352afcf0095SNicholas Piggin ld r3,_NIP(r1); \ 353afcf0095SNicholas Piggin mtspr SPRN_SRR0,r3; \ 354afcf0095SNicholas Piggin ld r9,_CTR(r1); \ 355afcf0095SNicholas Piggin mtctr r9; \ 356afcf0095SNicholas Piggin ld r9,_XER(r1); \ 357afcf0095SNicholas Piggin mtxer r9; \ 358afcf0095SNicholas Piggin ld r9,_LINK(r1); \ 359afcf0095SNicholas Piggin mtlr r9; \ 360afcf0095SNicholas Piggin REST_GPR(0, r1); \ 361afcf0095SNicholas Piggin REST_8GPRS(2, r1); \ 362afcf0095SNicholas Piggin REST_GPR(10, r1); \ 363afcf0095SNicholas Piggin ld r11,_CCR(r1); \ 364afcf0095SNicholas Piggin mtcr r11; \ 365afcf0095SNicholas Piggin /* Decrement paca->in_mce. */ \ 366afcf0095SNicholas Piggin lhz r12,PACA_IN_MCE(r13); \ 367afcf0095SNicholas Piggin subi r12,r12,1; \ 368afcf0095SNicholas Piggin sth r12,PACA_IN_MCE(r13); \ 369afcf0095SNicholas Piggin REST_GPR(11, r1); \ 370afcf0095SNicholas Piggin REST_2GPRS(12, r1); \ 371afcf0095SNicholas Piggin /* restore original r1. */ \ 372afcf0095SNicholas Piggin ld r1,GPR1(r1) 373afcf0095SNicholas Piggin 374afcf0095SNicholas Piggin /* 375afcf0095SNicholas Piggin * Handle machine check early in real mode. We come here with 376afcf0095SNicholas Piggin * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 377afcf0095SNicholas Piggin */ 378afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_handle_early) 379afcf0095SNicholas Piggin std r0,GPR0(r1) /* Save r0 */ 380afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_3(0x200) 381afcf0095SNicholas Piggin bl save_nvgprs 382afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 383afcf0095SNicholas Piggin bl machine_check_early 384afcf0095SNicholas Piggin std r3,RESULT(r1) /* Save result */ 385afcf0095SNicholas Piggin ld r12,_MSR(r1) 386afcf0095SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 387afcf0095SNicholas Piggin /* 388afcf0095SNicholas Piggin * Check if thread was in power saving mode. We come here when any 389afcf0095SNicholas Piggin * of the following is true: 390afcf0095SNicholas Piggin * a. thread wasn't in power saving mode 391afcf0095SNicholas Piggin * b. thread was in power saving mode with no state loss, 392afcf0095SNicholas Piggin * supervisor state loss or hypervisor state loss. 393afcf0095SNicholas Piggin * 394afcf0095SNicholas Piggin * Go back to nap/sleep/winkle mode again if (b) is true. 395afcf0095SNicholas Piggin */ 396afcf0095SNicholas Piggin rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ 397afcf0095SNicholas Piggin beq 4f /* No, it wasn;t */ 398afcf0095SNicholas Piggin /* Thread was in power saving mode. Go back to nap again. */ 399afcf0095SNicholas Piggin cmpwi r11,2 400afcf0095SNicholas Piggin blt 3f 401afcf0095SNicholas Piggin /* Supervisor/Hypervisor state loss */ 402afcf0095SNicholas Piggin li r0,1 403afcf0095SNicholas Piggin stb r0,PACA_NAPSTATELOST(r13) 404afcf0095SNicholas Piggin3: bl machine_check_queue_event 405afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 406afcf0095SNicholas Piggin GET_PACA(r13) 407afcf0095SNicholas Piggin ld r1,PACAR1(r13) 408afcf0095SNicholas Piggin /* 409afcf0095SNicholas Piggin * Check what idle state this CPU was in and go back to same mode 410afcf0095SNicholas Piggin * again. 411afcf0095SNicholas Piggin */ 412afcf0095SNicholas Piggin lbz r3,PACA_THREAD_IDLE_STATE(r13) 413afcf0095SNicholas Piggin cmpwi r3,PNV_THREAD_NAP 414afcf0095SNicholas Piggin bgt 10f 415afcf0095SNicholas Piggin IDLE_STATE_ENTER_SEQ(PPC_NAP) 416afcf0095SNicholas Piggin /* No return */ 417afcf0095SNicholas Piggin10: 418afcf0095SNicholas Piggin cmpwi r3,PNV_THREAD_SLEEP 419afcf0095SNicholas Piggin bgt 2f 420afcf0095SNicholas Piggin IDLE_STATE_ENTER_SEQ(PPC_SLEEP) 421afcf0095SNicholas Piggin /* No return */ 422afcf0095SNicholas Piggin 423afcf0095SNicholas Piggin2: 424afcf0095SNicholas Piggin /* 425afcf0095SNicholas Piggin * Go back to winkle. Please note that this thread was woken up in 426afcf0095SNicholas Piggin * machine check from winkle and have not restored the per-subcore 427afcf0095SNicholas Piggin * state. Hence before going back to winkle, set last bit of HSPGR0 428afcf0095SNicholas Piggin * to 1. This will make sure that if this thread gets woken up 429afcf0095SNicholas Piggin * again at reset vector 0x100 then it will get chance to restore 430afcf0095SNicholas Piggin * the subcore state. 431afcf0095SNicholas Piggin */ 432afcf0095SNicholas Piggin ori r13,r13,1 433afcf0095SNicholas Piggin SET_PACA(r13) 434afcf0095SNicholas Piggin IDLE_STATE_ENTER_SEQ(PPC_WINKLE) 435afcf0095SNicholas Piggin /* No return */ 436afcf0095SNicholas Piggin4: 437afcf0095SNicholas Piggin#endif 438afcf0095SNicholas Piggin /* 439afcf0095SNicholas Piggin * Check if we are coming from hypervisor userspace. If yes then we 440afcf0095SNicholas Piggin * continue in host kernel in V mode to deliver the MC event. 441afcf0095SNicholas Piggin */ 442afcf0095SNicholas Piggin rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 443afcf0095SNicholas Piggin beq 5f 444afcf0095SNicholas Piggin andi. r11,r12,MSR_PR /* See if coming from user. */ 445afcf0095SNicholas Piggin bne 9f /* continue in V mode if we are. */ 446afcf0095SNicholas Piggin 447afcf0095SNicholas Piggin5: 448afcf0095SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 449afcf0095SNicholas Piggin /* 450afcf0095SNicholas Piggin * We are coming from kernel context. Check if we are coming from 451afcf0095SNicholas Piggin * guest. if yes, then we can continue. We will fall through 452afcf0095SNicholas Piggin * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 453afcf0095SNicholas Piggin */ 454afcf0095SNicholas Piggin lbz r11,HSTATE_IN_GUEST(r13) 455afcf0095SNicholas Piggin cmpwi r11,0 /* Check if coming from guest */ 456afcf0095SNicholas Piggin bne 9f /* continue if we are. */ 457afcf0095SNicholas Piggin#endif 458afcf0095SNicholas Piggin /* 459afcf0095SNicholas Piggin * At this point we are not sure about what context we come from. 460afcf0095SNicholas Piggin * Queue up the MCE event and return from the interrupt. 461afcf0095SNicholas Piggin * But before that, check if this is an un-recoverable exception. 462afcf0095SNicholas Piggin * If yes, then stay on emergency stack and panic. 463afcf0095SNicholas Piggin */ 464afcf0095SNicholas Piggin andi. r11,r12,MSR_RI 465afcf0095SNicholas Piggin bne 2f 466afcf0095SNicholas Piggin1: mfspr r11,SPRN_SRR0 467afcf0095SNicholas Piggin LOAD_HANDLER(r10,unrecover_mce) 468afcf0095SNicholas Piggin mtspr SPRN_SRR0,r10 469afcf0095SNicholas Piggin ld r10,PACAKMSR(r13) 470afcf0095SNicholas Piggin /* 471afcf0095SNicholas Piggin * We are going down. But there are chances that we might get hit by 472afcf0095SNicholas Piggin * another MCE during panic path and we may run into unstable state 473afcf0095SNicholas Piggin * with no way out. Hence, turn ME bit off while going down, so that 474afcf0095SNicholas Piggin * when another MCE is hit during panic path, system will checkstop 475afcf0095SNicholas Piggin * and hypervisor will get restarted cleanly by SP. 476afcf0095SNicholas Piggin */ 477afcf0095SNicholas Piggin li r3,MSR_ME 478afcf0095SNicholas Piggin andc r10,r10,r3 /* Turn off MSR_ME */ 479afcf0095SNicholas Piggin mtspr SPRN_SRR1,r10 480afcf0095SNicholas Piggin rfid 481afcf0095SNicholas Piggin b . 482afcf0095SNicholas Piggin2: 483afcf0095SNicholas Piggin /* 484afcf0095SNicholas Piggin * Check if we have successfully handled/recovered from error, if not 485afcf0095SNicholas Piggin * then stay on emergency stack and panic. 486afcf0095SNicholas Piggin */ 487afcf0095SNicholas Piggin ld r3,RESULT(r1) /* Load result */ 488afcf0095SNicholas Piggin cmpdi r3,0 /* see if we handled MCE successfully */ 489afcf0095SNicholas Piggin 490afcf0095SNicholas Piggin beq 1b /* if !handled then panic */ 491afcf0095SNicholas Piggin /* 492afcf0095SNicholas Piggin * Return from MC interrupt. 493afcf0095SNicholas Piggin * Queue up the MCE event so that we can log it later, while 494afcf0095SNicholas Piggin * returning from kernel or opal call. 495afcf0095SNicholas Piggin */ 496afcf0095SNicholas Piggin bl machine_check_queue_event 497afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 498afcf0095SNicholas Piggin rfid 499afcf0095SNicholas Piggin9: 500afcf0095SNicholas Piggin /* Deliver the machine check to host kernel in V mode. */ 501afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 502afcf0095SNicholas Piggin b machine_check_pSeries 503afcf0095SNicholas Piggin 504afcf0095SNicholas PigginEXC_COMMON_BEGIN(unrecover_mce) 505afcf0095SNicholas Piggin /* Invoke machine_check_exception to print MCE event and panic. */ 506afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 507afcf0095SNicholas Piggin bl machine_check_exception 508afcf0095SNicholas Piggin /* 509afcf0095SNicholas Piggin * We will not reach here. Even if we did, there is no way out. Call 510afcf0095SNicholas Piggin * unrecoverable_exception and die. 511afcf0095SNicholas Piggin */ 512afcf0095SNicholas Piggin1: addi r3,r1,STACK_FRAME_OVERHEAD 513afcf0095SNicholas Piggin bl unrecoverable_exception 514afcf0095SNicholas Piggin b 1b 515afcf0095SNicholas Piggin 5160ebc4cdaSBenjamin Herrenschmidt 517da2bc464SMichael EllermanEXC_REAL(data_access, 0x300, 0x380) 51880795e6cSNicholas PigginEXC_VIRT(data_access, 0x4300, 0x4380, 0x300) 51980795e6cSNicholas PigginTRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 52080795e6cSNicholas Piggin 52180795e6cSNicholas PigginEXC_COMMON_BEGIN(data_access_common) 52280795e6cSNicholas Piggin /* 52380795e6cSNicholas Piggin * Here r13 points to the paca, r9 contains the saved CR, 52480795e6cSNicholas Piggin * SRR0 and SRR1 are saved in r11 and r12, 52580795e6cSNicholas Piggin * r9 - r13 are saved in paca->exgen. 52680795e6cSNicholas Piggin */ 52780795e6cSNicholas Piggin mfspr r10,SPRN_DAR 52880795e6cSNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 52980795e6cSNicholas Piggin mfspr r10,SPRN_DSISR 53080795e6cSNicholas Piggin stw r10,PACA_EXGEN+EX_DSISR(r13) 53180795e6cSNicholas Piggin EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 53280795e6cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 53380795e6cSNicholas Piggin ld r12,_MSR(r1) 53480795e6cSNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 53580795e6cSNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 53680795e6cSNicholas Piggin li r5,0x300 53780795e6cSNicholas Piggin std r3,_DAR(r1) 53880795e6cSNicholas Piggin std r4,_DSISR(r1) 53980795e6cSNicholas PigginBEGIN_MMU_FTR_SECTION 54080795e6cSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 54180795e6cSNicholas PigginMMU_FTR_SECTION_ELSE 54280795e6cSNicholas Piggin b handle_page_fault 54380795e6cSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 54480795e6cSNicholas Piggin 5450ebc4cdaSBenjamin Herrenschmidt 546da2bc464SMichael EllermanEXC_REAL_BEGIN(data_access_slb, 0x380, 0x400) 547673b189aSPaul Mackerras SET_SCRATCH0(r13) 5481707dd16SPaul Mackerras EXCEPTION_PROLOG_0(PACA_EXSLB) 549da2bc464SMichael Ellerman EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) 5500ebc4cdaSBenjamin Herrenschmidt std r3,PACA_EXSLB+EX_R3(r13) 5510ebc4cdaSBenjamin Herrenschmidt mfspr r3,SPRN_DAR 552b01c8b54SPaul Mackerras mfspr r12,SPRN_SRR1 553f0f558b1SPaul Mackerras crset 4*cr6+eq 5540ebc4cdaSBenjamin Herrenschmidt#ifndef CONFIG_RELOCATABLE 555b1576fecSAnton Blanchard b slb_miss_realmode 5560ebc4cdaSBenjamin Herrenschmidt#else 5570ebc4cdaSBenjamin Herrenschmidt /* 558ad0289e4SAnton Blanchard * We can't just use a direct branch to slb_miss_realmode 5590ebc4cdaSBenjamin Herrenschmidt * because the distance from here to there depends on where 5600ebc4cdaSBenjamin Herrenschmidt * the kernel ends up being put. 5610ebc4cdaSBenjamin Herrenschmidt */ 5620ebc4cdaSBenjamin Herrenschmidt mfctr r11 563ad0289e4SAnton Blanchard LOAD_HANDLER(r10, slb_miss_realmode) 5640ebc4cdaSBenjamin Herrenschmidt mtctr r10 5650ebc4cdaSBenjamin Herrenschmidt bctr 5660ebc4cdaSBenjamin Herrenschmidt#endif 567da2bc464SMichael EllermanEXC_REAL_END(data_access_slb, 0x380, 0x400) 5680ebc4cdaSBenjamin Herrenschmidt 5692b9af6e4SNicholas PigginEXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400) 5702b9af6e4SNicholas Piggin SET_SCRATCH0(r13) 5712b9af6e4SNicholas Piggin EXCEPTION_PROLOG_0(PACA_EXSLB) 5722b9af6e4SNicholas Piggin EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) 5732b9af6e4SNicholas Piggin std r3,PACA_EXSLB+EX_R3(r13) 5742b9af6e4SNicholas Piggin mfspr r3,SPRN_DAR 5752b9af6e4SNicholas Piggin mfspr r12,SPRN_SRR1 5762b9af6e4SNicholas Piggin crset 4*cr6+eq 5772b9af6e4SNicholas Piggin#ifndef CONFIG_RELOCATABLE 5782b9af6e4SNicholas Piggin b slb_miss_realmode 5792b9af6e4SNicholas Piggin#else 5802b9af6e4SNicholas Piggin /* 5812b9af6e4SNicholas Piggin * We can't just use a direct branch to slb_miss_realmode 5822b9af6e4SNicholas Piggin * because the distance from here to there depends on where 5832b9af6e4SNicholas Piggin * the kernel ends up being put. 5842b9af6e4SNicholas Piggin */ 5852b9af6e4SNicholas Piggin mfctr r11 5862b9af6e4SNicholas Piggin LOAD_HANDLER(r10, slb_miss_realmode) 5872b9af6e4SNicholas Piggin mtctr r10 5882b9af6e4SNicholas Piggin bctr 5892b9af6e4SNicholas Piggin#endif 5902b9af6e4SNicholas PigginEXC_VIRT_END(data_access_slb, 0x4380, 0x4400) 5912b9af6e4SNicholas PigginTRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 5922b9af6e4SNicholas Piggin 5932b9af6e4SNicholas Piggin 594da2bc464SMichael EllermanEXC_REAL(instruction_access, 0x400, 0x480) 59527ce77dfSNicholas PigginEXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400) 59627ce77dfSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x400) 59727ce77dfSNicholas Piggin 59827ce77dfSNicholas PigginEXC_COMMON_BEGIN(instruction_access_common) 59927ce77dfSNicholas Piggin EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 60027ce77dfSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 60127ce77dfSNicholas Piggin ld r12,_MSR(r1) 60227ce77dfSNicholas Piggin ld r3,_NIP(r1) 60327ce77dfSNicholas Piggin andis. r4,r12,0x5820 60427ce77dfSNicholas Piggin li r5,0x400 60527ce77dfSNicholas Piggin std r3,_DAR(r1) 60627ce77dfSNicholas Piggin std r4,_DSISR(r1) 60727ce77dfSNicholas PigginBEGIN_MMU_FTR_SECTION 60827ce77dfSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 60927ce77dfSNicholas PigginMMU_FTR_SECTION_ELSE 61027ce77dfSNicholas Piggin b handle_page_fault 61127ce77dfSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 61227ce77dfSNicholas Piggin 6130ebc4cdaSBenjamin Herrenschmidt 614da2bc464SMichael EllermanEXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500) 615673b189aSPaul Mackerras SET_SCRATCH0(r13) 6161707dd16SPaul Mackerras EXCEPTION_PROLOG_0(PACA_EXSLB) 617da2bc464SMichael Ellerman EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) 6180ebc4cdaSBenjamin Herrenschmidt std r3,PACA_EXSLB+EX_R3(r13) 6190ebc4cdaSBenjamin Herrenschmidt mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 620b01c8b54SPaul Mackerras mfspr r12,SPRN_SRR1 621f0f558b1SPaul Mackerras crclr 4*cr6+eq 6220ebc4cdaSBenjamin Herrenschmidt#ifndef CONFIG_RELOCATABLE 623b1576fecSAnton Blanchard b slb_miss_realmode 6240ebc4cdaSBenjamin Herrenschmidt#else 6250ebc4cdaSBenjamin Herrenschmidt mfctr r11 626ad0289e4SAnton Blanchard LOAD_HANDLER(r10, slb_miss_realmode) 6270ebc4cdaSBenjamin Herrenschmidt mtctr r10 6280ebc4cdaSBenjamin Herrenschmidt bctr 6290ebc4cdaSBenjamin Herrenschmidt#endif 630da2bc464SMichael EllermanEXC_REAL_END(instruction_access_slb, 0x480, 0x500) 6310ebc4cdaSBenjamin Herrenschmidt 6328d04631aSNicholas PigginEXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500) 6338d04631aSNicholas Piggin SET_SCRATCH0(r13) 6348d04631aSNicholas Piggin EXCEPTION_PROLOG_0(PACA_EXSLB) 6358d04631aSNicholas Piggin EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) 6368d04631aSNicholas Piggin std r3,PACA_EXSLB+EX_R3(r13) 6378d04631aSNicholas Piggin mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 6388d04631aSNicholas Piggin mfspr r12,SPRN_SRR1 6398d04631aSNicholas Piggin crclr 4*cr6+eq 6408d04631aSNicholas Piggin#ifndef CONFIG_RELOCATABLE 6418d04631aSNicholas Piggin b slb_miss_realmode 6428d04631aSNicholas Piggin#else 6438d04631aSNicholas Piggin mfctr r11 6448d04631aSNicholas Piggin LOAD_HANDLER(r10, slb_miss_realmode) 6458d04631aSNicholas Piggin mtctr r10 6468d04631aSNicholas Piggin bctr 6478d04631aSNicholas Piggin#endif 6488d04631aSNicholas PigginEXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500) 6498d04631aSNicholas PigginTRAMP_KVM(PACA_EXSLB, 0x480) 6508d04631aSNicholas Piggin 6518d04631aSNicholas Piggin 6528d04631aSNicholas Piggin/* This handler is used by both 0x380 and 0x480 slb miss interrupts */ 6538d04631aSNicholas PigginEXC_COMMON_BEGIN(slb_miss_realmode) 6548d04631aSNicholas Piggin /* 6558d04631aSNicholas Piggin * r13 points to the PACA, r9 contains the saved CR, 6568d04631aSNicholas Piggin * r12 contain the saved SRR1, SRR0 is still ready for return 6578d04631aSNicholas Piggin * r3 has the faulting address 6588d04631aSNicholas Piggin * r9 - r13 are saved in paca->exslb. 6598d04631aSNicholas Piggin * r3 is saved in paca->slb_r3 6608d04631aSNicholas Piggin * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss 6618d04631aSNicholas Piggin * We assume we aren't going to take any exceptions during this 6628d04631aSNicholas Piggin * procedure. 6638d04631aSNicholas Piggin */ 6648d04631aSNicholas Piggin mflr r10 6658d04631aSNicholas Piggin#ifdef CONFIG_RELOCATABLE 6668d04631aSNicholas Piggin mtctr r11 6678d04631aSNicholas Piggin#endif 6688d04631aSNicholas Piggin 6698d04631aSNicholas Piggin stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 6708d04631aSNicholas Piggin std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 6718d04631aSNicholas Piggin std r3,PACA_EXSLB+EX_DAR(r13) 6728d04631aSNicholas Piggin 6738d04631aSNicholas Piggin crset 4*cr0+eq 6748d04631aSNicholas Piggin#ifdef CONFIG_PPC_STD_MMU_64 6758d04631aSNicholas PigginBEGIN_MMU_FTR_SECTION 6768d04631aSNicholas Piggin bl slb_allocate_realmode 6778d04631aSNicholas PigginEND_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) 6788d04631aSNicholas Piggin#endif 6798d04631aSNicholas Piggin 6808d04631aSNicholas Piggin ld r10,PACA_EXSLB+EX_LR(r13) 6818d04631aSNicholas Piggin ld r3,PACA_EXSLB+EX_R3(r13) 6828d04631aSNicholas Piggin lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 6838d04631aSNicholas Piggin mtlr r10 6848d04631aSNicholas Piggin 6858d04631aSNicholas Piggin beq 8f /* if bad address, make full stack frame */ 6868d04631aSNicholas Piggin 6878d04631aSNicholas Piggin andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 6888d04631aSNicholas Piggin beq- 2f 6898d04631aSNicholas Piggin 6908d04631aSNicholas Piggin /* All done -- return from exception. */ 6918d04631aSNicholas Piggin 6928d04631aSNicholas Piggin.machine push 6938d04631aSNicholas Piggin.machine "power4" 6948d04631aSNicholas Piggin mtcrf 0x80,r9 6958d04631aSNicholas Piggin mtcrf 0x02,r9 /* I/D indication is in cr6 */ 6968d04631aSNicholas Piggin mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 6978d04631aSNicholas Piggin.machine pop 6988d04631aSNicholas Piggin 6998d04631aSNicholas Piggin RESTORE_PPR_PACA(PACA_EXSLB, r9) 7008d04631aSNicholas Piggin ld r9,PACA_EXSLB+EX_R9(r13) 7018d04631aSNicholas Piggin ld r10,PACA_EXSLB+EX_R10(r13) 7028d04631aSNicholas Piggin ld r11,PACA_EXSLB+EX_R11(r13) 7038d04631aSNicholas Piggin ld r12,PACA_EXSLB+EX_R12(r13) 7048d04631aSNicholas Piggin ld r13,PACA_EXSLB+EX_R13(r13) 7058d04631aSNicholas Piggin rfid 7068d04631aSNicholas Piggin b . /* prevent speculative execution */ 7078d04631aSNicholas Piggin 7088d04631aSNicholas Piggin2: mfspr r11,SPRN_SRR0 7098d04631aSNicholas Piggin LOAD_HANDLER(r10,unrecov_slb) 7108d04631aSNicholas Piggin mtspr SPRN_SRR0,r10 7118d04631aSNicholas Piggin ld r10,PACAKMSR(r13) 7128d04631aSNicholas Piggin mtspr SPRN_SRR1,r10 7138d04631aSNicholas Piggin rfid 7148d04631aSNicholas Piggin b . 7158d04631aSNicholas Piggin 7168d04631aSNicholas Piggin8: mfspr r11,SPRN_SRR0 7178d04631aSNicholas Piggin LOAD_HANDLER(r10,bad_addr_slb) 7188d04631aSNicholas Piggin mtspr SPRN_SRR0,r10 7198d04631aSNicholas Piggin ld r10,PACAKMSR(r13) 7208d04631aSNicholas Piggin mtspr SPRN_SRR1,r10 7218d04631aSNicholas Piggin rfid 7228d04631aSNicholas Piggin b . 7238d04631aSNicholas Piggin 7248d04631aSNicholas PigginEXC_COMMON_BEGIN(unrecov_slb) 7258d04631aSNicholas Piggin EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 7268d04631aSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 7278d04631aSNicholas Piggin bl save_nvgprs 7288d04631aSNicholas Piggin1: addi r3,r1,STACK_FRAME_OVERHEAD 7298d04631aSNicholas Piggin bl unrecoverable_exception 7308d04631aSNicholas Piggin b 1b 7318d04631aSNicholas Piggin 7328d04631aSNicholas PigginEXC_COMMON_BEGIN(bad_addr_slb) 7338d04631aSNicholas Piggin EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) 7348d04631aSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 7358d04631aSNicholas Piggin ld r3, PACA_EXSLB+EX_DAR(r13) 7368d04631aSNicholas Piggin std r3, _DAR(r1) 7378d04631aSNicholas Piggin beq cr6, 2f 7388d04631aSNicholas Piggin li r10, 0x480 /* fix trap number for I-SLB miss */ 7398d04631aSNicholas Piggin std r10, _TRAP(r1) 7408d04631aSNicholas Piggin2: bl save_nvgprs 7418d04631aSNicholas Piggin addi r3, r1, STACK_FRAME_OVERHEAD 7428d04631aSNicholas Piggin bl slb_miss_bad_addr 7438d04631aSNicholas Piggin b ret_from_except 7448d04631aSNicholas Piggin 745da2bc464SMichael EllermanEXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600) 746b3e6b5dfSBenjamin Herrenschmidt .globl hardware_interrupt_hv; 747b3e6b5dfSBenjamin Herrenschmidthardware_interrupt_hv: 748a5d4f3adSBenjamin Herrenschmidt BEGIN_FTR_SECTION 749da2bc464SMichael Ellerman _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 750b01c8b54SPaul Mackerras EXC_HV, SOFTEN_TEST_HV) 751da2bc464SMichael Ellermando_kvm_H0x500: 752b01c8b54SPaul Mackerras KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) 753de56a948SPaul Mackerras FTR_SECTION_ELSE 754da2bc464SMichael Ellerman _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, 75531a40e2bSPaul Mackerras EXC_STD, SOFTEN_TEST_PR) 756da2bc464SMichael Ellermando_kvm_0x500: 757de56a948SPaul Mackerras KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) 758969391c5SPaul Mackerras ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 759da2bc464SMichael EllermanEXC_REAL_END(hardware_interrupt, 0x500, 0x600) 760a5d4f3adSBenjamin Herrenschmidt 761c138e588SNicholas PigginEXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600) 762c138e588SNicholas Piggin .globl hardware_interrupt_relon_hv; 763c138e588SNicholas Pigginhardware_interrupt_relon_hv: 764c138e588SNicholas Piggin BEGIN_FTR_SECTION 765c138e588SNicholas Piggin _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) 766c138e588SNicholas Piggin FTR_SECTION_ELSE 767c138e588SNicholas Piggin _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) 768c138e588SNicholas Piggin ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 769c138e588SNicholas PigginEXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600) 770c138e588SNicholas Piggin 771c138e588SNicholas PigginEXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 772c138e588SNicholas Piggin 773c138e588SNicholas Piggin 774da2bc464SMichael EllermanEXC_REAL(alignment, 0x600, 0x700) 775f9aa6714SNicholas PigginEXC_VIRT(alignment, 0x4600, 0x4700, 0x600) 776da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x600) 777f9aa6714SNicholas PigginEXC_COMMON_BEGIN(alignment_common) 778f9aa6714SNicholas Piggin mfspr r10,SPRN_DAR 779f9aa6714SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 780f9aa6714SNicholas Piggin mfspr r10,SPRN_DSISR 781f9aa6714SNicholas Piggin stw r10,PACA_EXGEN+EX_DSISR(r13) 782f9aa6714SNicholas Piggin EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 783f9aa6714SNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 784f9aa6714SNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 785f9aa6714SNicholas Piggin std r3,_DAR(r1) 786f9aa6714SNicholas Piggin std r4,_DSISR(r1) 787f9aa6714SNicholas Piggin bl save_nvgprs 788f9aa6714SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 789f9aa6714SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 790f9aa6714SNicholas Piggin bl alignment_exception 791f9aa6714SNicholas Piggin b ret_from_except 792f9aa6714SNicholas Piggin 793b01c8b54SPaul Mackerras 794da2bc464SMichael EllermanEXC_REAL(program_check, 0x700, 0x800) 79511e87346SNicholas PigginEXC_VIRT(program_check, 0x4700, 0x4800, 0x700) 796da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x700) 79711e87346SNicholas PigginEXC_COMMON_BEGIN(program_check_common) 79811e87346SNicholas Piggin EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 79911e87346SNicholas Piggin bl save_nvgprs 80011e87346SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 80111e87346SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 80211e87346SNicholas Piggin bl program_check_exception 80311e87346SNicholas Piggin b ret_from_except 80411e87346SNicholas Piggin 805a485c709SPaul Mackerras 806da2bc464SMichael EllermanEXC_REAL(fp_unavailable, 0x800, 0x900) 807c78d9b97SNicholas PigginEXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800) 808da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x800) 809c78d9b97SNicholas PigginEXC_COMMON_BEGIN(fp_unavailable_common) 810c78d9b97SNicholas Piggin EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 811c78d9b97SNicholas Piggin bne 1f /* if from user, just load it up */ 812c78d9b97SNicholas Piggin bl save_nvgprs 813c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 814c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 815c78d9b97SNicholas Piggin bl kernel_fp_unavailable_exception 816c78d9b97SNicholas Piggin BUG_OPCODE 817c78d9b97SNicholas Piggin1: 818c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 819c78d9b97SNicholas PigginBEGIN_FTR_SECTION 820c78d9b97SNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 821c78d9b97SNicholas Piggin * transaction), go do TM stuff 822c78d9b97SNicholas Piggin */ 823c78d9b97SNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 824c78d9b97SNicholas Piggin bne- 2f 825c78d9b97SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_TM) 826c78d9b97SNicholas Piggin#endif 827c78d9b97SNicholas Piggin bl load_up_fpu 828c78d9b97SNicholas Piggin b fast_exception_return 829c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 830c78d9b97SNicholas Piggin2: /* User process was in a transaction */ 831c78d9b97SNicholas Piggin bl save_nvgprs 832c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 833c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 834c78d9b97SNicholas Piggin bl fp_unavailable_tm 835c78d9b97SNicholas Piggin b ret_from_except 836c78d9b97SNicholas Piggin#endif 837c78d9b97SNicholas Piggin 838b01c8b54SPaul Mackerras 839da2bc464SMichael EllermanEXC_REAL_MASKABLE(decrementer, 0x900, 0x980) 84039c0da57SNicholas PigginEXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) 84139c0da57SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x900) 84239c0da57SNicholas PigginEXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 84339c0da57SNicholas Piggin 8440ebc4cdaSBenjamin Herrenschmidt 845da2bc464SMichael EllermanEXC_REAL_HV(hdecrementer, 0x980, 0xa00) 846*facc6d74SNicholas PigginEXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980) 847*facc6d74SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0x980) 848*facc6d74SNicholas PigginEXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 849*facc6d74SNicholas Piggin 850da2bc464SMichael Ellerman 851da2bc464SMichael EllermanEXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00) 852da2bc464SMichael Ellerman 853da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xa00) 854da2bc464SMichael Ellerman 855da2bc464SMichael EllermanEXC_REAL(trap_0b, 0xb00, 0xc00) 856da2bc464SMichael Ellerman 857da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xb00) 858da2bc464SMichael Ellerman 859da2bc464SMichael EllermanEXC_REAL_BEGIN(system_call, 0xc00, 0xd00) 8608b91a255SSuresh E. Warrier /* 8618b91a255SSuresh E. Warrier * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems 8628b91a255SSuresh E. Warrier * that support it) before changing to HMT_MEDIUM. That allows the KVM 8638b91a255SSuresh E. Warrier * code to save that value into the guest state (it is the guest's PPR 8648b91a255SSuresh E. Warrier * value). Otherwise just change to HMT_MEDIUM as userspace has 8658b91a255SSuresh E. Warrier * already saved the PPR. 8668b91a255SSuresh E. Warrier */ 867b01c8b54SPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 868b01c8b54SPaul Mackerras SET_SCRATCH0(r13) 869b01c8b54SPaul Mackerras GET_PACA(r13) 870b01c8b54SPaul Mackerras std r9,PACA_EXGEN+EX_R9(r13) 8718b91a255SSuresh E. Warrier OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); 8728b91a255SSuresh E. Warrier HMT_MEDIUM; 873b01c8b54SPaul Mackerras std r10,PACA_EXGEN+EX_R10(r13) 8748b91a255SSuresh E. Warrier OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); 875b01c8b54SPaul Mackerras mfcr r9 876da2bc464SMichael Ellerman KVMTEST_PR(0xc00) 877b01c8b54SPaul Mackerras GET_SCRATCH0(r13) 8788b91a255SSuresh E. Warrier#else 8798b91a255SSuresh E. Warrier HMT_MEDIUM; 880b01c8b54SPaul Mackerras#endif 881742415d6SMichael Neuling SYSCALL_PSERIES_1 882742415d6SMichael Neuling SYSCALL_PSERIES_2_RFID 883742415d6SMichael Neuling SYSCALL_PSERIES_3 884da2bc464SMichael EllermanEXC_REAL_END(system_call, 0xc00, 0xd00) 885b01c8b54SPaul Mackerras 886da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xc00) 887da2bc464SMichael Ellerman 888da2bc464SMichael EllermanEXC_REAL(single_step, 0xd00, 0xe00) 889da2bc464SMichael Ellerman 890da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xd00) 891da2bc464SMichael Ellerman 892b3e6b5dfSBenjamin Herrenschmidt 893b3e6b5dfSBenjamin Herrenschmidt /* At 0xe??? we have a bunch of hypervisor exceptions, we branch 894b3e6b5dfSBenjamin Herrenschmidt * out of line to handle them 895b3e6b5dfSBenjamin Herrenschmidt */ 896da2bc464SMichael Ellerman__EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20) 8971707dd16SPaul Mackerras 898da2bc464SMichael Ellerman__EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40) 8991707dd16SPaul Mackerras 900da2bc464SMichael Ellerman__EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60) 9011707dd16SPaul Mackerras 902da2bc464SMichael Ellerman__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early) 9031707dd16SPaul Mackerras 904da2bc464SMichael Ellerman__EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0) 9050ebc4cdaSBenjamin Herrenschmidt 906da2bc464SMichael Ellerman__EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0) 9079baaef0aSBenjamin Herrenschmidt 908da2bc464SMichael EllermanEXC_REAL_NONE(0xec0, 0xf00) 9090ebc4cdaSBenjamin Herrenschmidt 910da2bc464SMichael Ellerman__EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20) 9110ebc4cdaSBenjamin Herrenschmidt 912da2bc464SMichael Ellerman__EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40) 9130ebc4cdaSBenjamin Herrenschmidt 914da2bc464SMichael Ellerman__EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60) 915d0c0c9a1SMichael Neuling 916da2bc464SMichael Ellerman__EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80) 917da2bc464SMichael Ellerman 918da2bc464SMichael Ellerman__EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0) 919da2bc464SMichael Ellerman 920da2bc464SMichael EllermanEXC_REAL_NONE(0xfa0, 0x1200) 921da2bc464SMichael Ellerman 9220ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 923da2bc464SMichael EllermanEXC_REAL_HV(cbe_system_error, 0x1200, 0x1300) 924b01c8b54SPaul Mackerras 925da2bc464SMichael EllermanTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 926b01c8b54SPaul Mackerras 927da2bc464SMichael Ellerman#else /* CONFIG_CBE_RAS */ 928da2bc464SMichael EllermanEXC_REAL_NONE(0x1200, 0x1300) 929da2bc464SMichael Ellerman#endif 930da2bc464SMichael Ellerman 931da2bc464SMichael EllermanEXC_REAL(instruction_breakpoint, 0x1300, 0x1400) 932da2bc464SMichael Ellerman 933da2bc464SMichael EllermanTRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 934da2bc464SMichael Ellerman 935da2bc464SMichael EllermanEXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600) 936b92a66a6SMichael Neuling mtspr SPRN_SPRG_HSCRATCH0,r13 9371707dd16SPaul Mackerras EXCEPTION_PROLOG_0(PACA_EXGEN) 938630573c1SPaul Mackerras EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) 939b92a66a6SMichael Neuling 940b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 941b92a66a6SMichael Neuling mfspr r10,SPRN_HSRR1 942b92a66a6SMichael Neuling mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 943b92a66a6SMichael Neuling andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 944b92a66a6SMichael Neuling addi r11,r11,-4 /* HSRR0 is next instruction */ 945b92a66a6SMichael Neuling bne+ denorm_assist 946b92a66a6SMichael Neuling#endif 947b92a66a6SMichael Neuling 948da2bc464SMichael Ellerman KVMTEST_PR(0x1500) 949b92a66a6SMichael Neuling EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) 950da2bc464SMichael EllermanEXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600) 951da2bc464SMichael Ellerman 952da2bc464SMichael EllermanTRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) 953b92a66a6SMichael Neuling 9540ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 955da2bc464SMichael EllermanEXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700) 956b01c8b54SPaul Mackerras 957da2bc464SMichael EllermanTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 958da2bc464SMichael Ellerman 959da2bc464SMichael Ellerman#else /* CONFIG_CBE_RAS */ 960da2bc464SMichael EllermanEXC_REAL_NONE(0x1600, 0x1700) 961da2bc464SMichael Ellerman#endif 962da2bc464SMichael Ellerman 963da2bc464SMichael EllermanEXC_REAL(altivec_assist, 0x1700, 0x1800) 964da2bc464SMichael Ellerman 965da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x1700) 966b01c8b54SPaul Mackerras 9670ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 968da2bc464SMichael EllermanEXC_REAL_HV(cbe_thermal, 0x1800, 0x1900) 969da2bc464SMichael Ellerman 970da2bc464SMichael EllermanTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 971da2bc464SMichael Ellerman 972da2bc464SMichael Ellerman#else /* CONFIG_CBE_RAS */ 973da2bc464SMichael EllermanEXC_REAL_NONE(0x1800, 0x1900) 974da2bc464SMichael Ellerman#endif 9750ebc4cdaSBenjamin Herrenschmidt 9760ebc4cdaSBenjamin Herrenschmidt 977b3e6b5dfSBenjamin Herrenschmidt/*** Out of line interrupts support ***/ 978b3e6b5dfSBenjamin Herrenschmidt 979b01c8b54SPaul Mackerras /* moved from 0x200 */ 980b01c8b54SPaul Mackerras 981b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 982da2bc464SMichael EllermanTRAMP_REAL_BEGIN(denorm_assist) 983b92a66a6SMichael NeulingBEGIN_FTR_SECTION 984b92a66a6SMichael Neuling/* 985b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 986b92a66a6SMichael Neuling * For POWER6 do that here for all FP regs. 987b92a66a6SMichael Neuling */ 988b92a66a6SMichael Neuling mfmsr r10 989b92a66a6SMichael Neuling ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 990b92a66a6SMichael Neuling xori r10,r10,(MSR_FE0|MSR_FE1) 991b92a66a6SMichael Neuling mtmsrd r10 992b92a66a6SMichael Neuling sync 993d7c67fb1SMichael Neuling 994d7c67fb1SMichael Neuling#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 995d7c67fb1SMichael Neuling#define FMR4(n) FMR2(n) ; FMR2(n+2) 996d7c67fb1SMichael Neuling#define FMR8(n) FMR4(n) ; FMR4(n+4) 997d7c67fb1SMichael Neuling#define FMR16(n) FMR8(n) ; FMR8(n+8) 998d7c67fb1SMichael Neuling#define FMR32(n) FMR16(n) ; FMR16(n+16) 999d7c67fb1SMichael Neuling FMR32(0) 1000d7c67fb1SMichael Neuling 1001b92a66a6SMichael NeulingFTR_SECTION_ELSE 1002b92a66a6SMichael Neuling/* 1003b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 1004b92a66a6SMichael Neuling * For POWER7 do that here for the first 32 VSX registers only. 1005b92a66a6SMichael Neuling */ 1006b92a66a6SMichael Neuling mfmsr r10 1007b92a66a6SMichael Neuling oris r10,r10,MSR_VSX@h 1008b92a66a6SMichael Neuling mtmsrd r10 1009b92a66a6SMichael Neuling sync 1010d7c67fb1SMichael Neuling 1011d7c67fb1SMichael Neuling#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) 1012d7c67fb1SMichael Neuling#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) 1013d7c67fb1SMichael Neuling#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) 1014d7c67fb1SMichael Neuling#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) 1015d7c67fb1SMichael Neuling#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) 1016d7c67fb1SMichael Neuling XVCPSGNDP32(0) 1017d7c67fb1SMichael Neuling 1018b92a66a6SMichael NeulingALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 1019fb0fce3eSMichael Neuling 1020fb0fce3eSMichael NeulingBEGIN_FTR_SECTION 1021fb0fce3eSMichael Neuling b denorm_done 1022fb0fce3eSMichael NeulingEND_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 1023fb0fce3eSMichael Neuling/* 1024fb0fce3eSMichael Neuling * To denormalise we need to move a copy of the register to itself. 1025fb0fce3eSMichael Neuling * For POWER8 we need to do that for all 64 VSX registers 1026fb0fce3eSMichael Neuling */ 1027fb0fce3eSMichael Neuling XVCPSGNDP32(32) 1028fb0fce3eSMichael Neulingdenorm_done: 1029b92a66a6SMichael Neuling mtspr SPRN_HSRR0,r11 1030b92a66a6SMichael Neuling mtcrf 0x80,r9 1031b92a66a6SMichael Neuling ld r9,PACA_EXGEN+EX_R9(r13) 103244e9309fSHaren Myneni RESTORE_PPR_PACA(PACA_EXGEN, r10) 1033630573c1SPaul MackerrasBEGIN_FTR_SECTION 1034630573c1SPaul Mackerras ld r10,PACA_EXGEN+EX_CFAR(r13) 1035630573c1SPaul Mackerras mtspr SPRN_CFAR,r10 1036630573c1SPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1037b92a66a6SMichael Neuling ld r10,PACA_EXGEN+EX_R10(r13) 1038b92a66a6SMichael Neuling ld r11,PACA_EXGEN+EX_R11(r13) 1039b92a66a6SMichael Neuling ld r12,PACA_EXGEN+EX_R12(r13) 1040b92a66a6SMichael Neuling ld r13,PACA_EXGEN+EX_R13(r13) 1041b92a66a6SMichael Neuling HRFID 1042b92a66a6SMichael Neuling b . 1043b92a66a6SMichael Neuling#endif 1044b92a66a6SMichael Neuling 1045b3e6b5dfSBenjamin Herrenschmidt /* moved from 0xe00 */ 1046da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL_HV(h_data_storage, 0xe00) 1047da2bc464SMichael EllermanTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 10480869b6fdSMahesh Salgaonkar 1049da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL_HV(h_instr_storage, 0xe20) 1050da2bc464SMichael EllermanTRAMP_KVM_HV(PACA_EXGEN, 0xe20) 10510ebc4cdaSBenjamin Herrenschmidt 1052da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL_HV(emulation_assist, 0xe40) 1053da2bc464SMichael EllermanTRAMP_KVM_HV(PACA_EXGEN, 0xe40) 1054da2bc464SMichael Ellerman 1055da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) 1056da2bc464SMichael EllermanTRAMP_KVM_HV(PACA_EXGEN, 0xe60) 1057da2bc464SMichael Ellerman 1058da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80) 1059da2bc464SMichael EllermanTRAMP_KVM_HV(PACA_EXGEN, 0xe80) 1060da2bc464SMichael Ellerman 1061da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0) 1062da2bc464SMichael EllermanTRAMP_KVM_HV(PACA_EXGEN, 0xea0) 10639baaef0aSBenjamin Herrenschmidt 10640ebc4cdaSBenjamin Herrenschmidt /* moved from 0xf00 */ 1065da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL(performance_monitor, 0xf00) 1066da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xf00) 1067da2bc464SMichael Ellerman 1068da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL(altivec_unavailable, 0xf20) 1069da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xf20) 1070da2bc464SMichael Ellerman 1071da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL(vsx_unavailable, 0xf40) 1072da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xf40) 1073da2bc464SMichael Ellerman 1074da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL(facility_unavailable, 0xf60) 1075da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xf60) 1076da2bc464SMichael Ellerman 1077da2bc464SMichael Ellerman__TRAMP_REAL_REAL_OOL_HV(h_facility_unavailable, 0xf80) 1078da2bc464SMichael EllermanTRAMP_KVM_HV(PACA_EXGEN, 0xf80) 10790ebc4cdaSBenjamin Herrenschmidt 10800ebc4cdaSBenjamin Herrenschmidt/* 1081fe9e1d54SIan Munsie * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 1082fe9e1d54SIan Munsie * - If it was a decrementer interrupt, we bump the dec to max and and return. 1083fe9e1d54SIan Munsie * - If it was a doorbell we return immediately since doorbells are edge 1084fe9e1d54SIan Munsie * triggered and won't automatically refire. 10850869b6fdSMahesh Salgaonkar * - If it was a HMI we return immediately since we handled it in realmode 10860869b6fdSMahesh Salgaonkar * and it won't refire. 1087fe9e1d54SIan Munsie * - else we hard disable and return. 1088fe9e1d54SIan Munsie * This is called with r10 containing the value to OR to the paca field. 10890ebc4cdaSBenjamin Herrenschmidt */ 10907230c564SBenjamin Herrenschmidt#define MASKED_INTERRUPT(_H) \ 10917230c564SBenjamin Herrenschmidtmasked_##_H##interrupt: \ 10927230c564SBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R11(r13); \ 10937230c564SBenjamin Herrenschmidt lbz r11,PACAIRQHAPPENED(r13); \ 10947230c564SBenjamin Herrenschmidt or r11,r11,r10; \ 10957230c564SBenjamin Herrenschmidt stb r11,PACAIRQHAPPENED(r13); \ 1096fe9e1d54SIan Munsie cmpwi r10,PACA_IRQ_DEC; \ 1097fe9e1d54SIan Munsie bne 1f; \ 10987230c564SBenjamin Herrenschmidt lis r10,0x7fff; \ 10997230c564SBenjamin Herrenschmidt ori r10,r10,0xffff; \ 11007230c564SBenjamin Herrenschmidt mtspr SPRN_DEC,r10; \ 11017230c564SBenjamin Herrenschmidt b 2f; \ 1102fe9e1d54SIan Munsie1: cmpwi r10,PACA_IRQ_DBELL; \ 1103fe9e1d54SIan Munsie beq 2f; \ 11040869b6fdSMahesh Salgaonkar cmpwi r10,PACA_IRQ_HMI; \ 11050869b6fdSMahesh Salgaonkar beq 2f; \ 1106fe9e1d54SIan Munsie mfspr r10,SPRN_##_H##SRR1; \ 11077230c564SBenjamin Herrenschmidt rldicl r10,r10,48,1; /* clear MSR_EE */ \ 11087230c564SBenjamin Herrenschmidt rotldi r10,r10,16; \ 11097230c564SBenjamin Herrenschmidt mtspr SPRN_##_H##SRR1,r10; \ 11107230c564SBenjamin Herrenschmidt2: mtcrf 0x80,r9; \ 11117230c564SBenjamin Herrenschmidt ld r9,PACA_EXGEN+EX_R9(r13); \ 11127230c564SBenjamin Herrenschmidt ld r10,PACA_EXGEN+EX_R10(r13); \ 11137230c564SBenjamin Herrenschmidt ld r11,PACA_EXGEN+EX_R11(r13); \ 11147230c564SBenjamin Herrenschmidt GET_SCRATCH0(r13); \ 11157230c564SBenjamin Herrenschmidt ##_H##rfid; \ 11160ebc4cdaSBenjamin Herrenschmidt b . 11170ebc4cdaSBenjamin Herrenschmidt 111857f26649SNicholas Piggin/* 111957f26649SNicholas Piggin * Real mode exceptions actually use this too, but alternate 112057f26649SNicholas Piggin * instruction code patches (which end up in the common .text area) 112157f26649SNicholas Piggin * cannot reach these if they are put there. 112257f26649SNicholas Piggin */ 112357f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 11247230c564SBenjamin Herrenschmidt MASKED_INTERRUPT() 11257230c564SBenjamin Herrenschmidt MASKED_INTERRUPT(H) 11267230c564SBenjamin Herrenschmidt 11277230c564SBenjamin Herrenschmidt/* 11287230c564SBenjamin Herrenschmidt * Called from arch_local_irq_enable when an interrupt needs 1129fe9e1d54SIan Munsie * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 1130fe9e1d54SIan Munsie * which kind of interrupt. MSR:EE is already off. We generate a 11317230c564SBenjamin Herrenschmidt * stackframe like if a real interrupt had happened. 11327230c564SBenjamin Herrenschmidt * 11337230c564SBenjamin Herrenschmidt * Note: While MSR:EE is off, we need to make sure that _MSR 11347230c564SBenjamin Herrenschmidt * in the generated frame has EE set to 1 or the exception 11357230c564SBenjamin Herrenschmidt * handler will not properly re-enable them. 11367230c564SBenjamin Herrenschmidt */ 113757f26649SNicholas PigginUSE_TEXT_SECTION() 11387230c564SBenjamin Herrenschmidt_GLOBAL(__replay_interrupt) 11397230c564SBenjamin Herrenschmidt /* We are going to jump to the exception common code which 11407230c564SBenjamin Herrenschmidt * will retrieve various register values from the PACA which 11417230c564SBenjamin Herrenschmidt * we don't give a damn about, so we don't bother storing them. 11427230c564SBenjamin Herrenschmidt */ 11437230c564SBenjamin Herrenschmidt mfmsr r12 11447230c564SBenjamin Herrenschmidt mflr r11 11457230c564SBenjamin Herrenschmidt mfcr r9 11467230c564SBenjamin Herrenschmidt ori r12,r12,MSR_EE 1147fe9e1d54SIan Munsie cmpwi r3,0x900 1148fe9e1d54SIan Munsie beq decrementer_common 1149fe9e1d54SIan Munsie cmpwi r3,0x500 1150fe9e1d54SIan Munsie beq hardware_interrupt_common 1151fe9e1d54SIan MunsieBEGIN_FTR_SECTION 1152fe9e1d54SIan Munsie cmpwi r3,0xe80 1153fe9e1d54SIan Munsie beq h_doorbell_common 11549baaef0aSBenjamin Herrenschmidt cmpwi r3,0xea0 11559baaef0aSBenjamin Herrenschmidt beq h_virt_irq_common 1156fd7bacbcSMahesh Salgaonkar cmpwi r3,0xe60 1157fd7bacbcSMahesh Salgaonkar beq hmi_exception_common 1158fe9e1d54SIan MunsieFTR_SECTION_ELSE 1159fe9e1d54SIan Munsie cmpwi r3,0xa00 1160fe9e1d54SIan Munsie beq doorbell_super_common 1161fe9e1d54SIan MunsieALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 1162fe9e1d54SIan Munsie blr 1163a5d4f3adSBenjamin Herrenschmidt 11644f6c11dbSPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1165da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 11664f6c11dbSPaul Mackerras /* 11674f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 11684f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 11694f6c11dbSPaul Mackerras */ 11704f6c11dbSPaul Mackerras mfspr r13, SPRN_SRR0 11714f6c11dbSPaul Mackerras addi r13, r13, 4 11724f6c11dbSPaul Mackerras mtspr SPRN_SRR0, r13 11734f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 11744f6c11dbSPaul Mackerras rfid 11754f6c11dbSPaul Mackerras b . 11764f6c11dbSPaul Mackerras 1177da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 11784f6c11dbSPaul Mackerras /* 11794f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 11804f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 11814f6c11dbSPaul Mackerras */ 11824f6c11dbSPaul Mackerras mfspr r13, SPRN_HSRR0 11834f6c11dbSPaul Mackerras addi r13, r13, 4 11844f6c11dbSPaul Mackerras mtspr SPRN_HSRR0, r13 11854f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 11864f6c11dbSPaul Mackerras hrfid 11874f6c11dbSPaul Mackerras b . 11884f6c11dbSPaul Mackerras#endif 11894f6c11dbSPaul Mackerras 11900ebc4cdaSBenjamin Herrenschmidt/* 1191057b6d7eSHari Bathini * Ensure that any handlers that get invoked from the exception prologs 1192057b6d7eSHari Bathini * above are below the first 64KB (0x10000) of the kernel image because 1193057b6d7eSHari Bathini * the prologs assemble the addresses of these handlers using the 1194057b6d7eSHari Bathini * LOAD_HANDLER macro, which uses an ori instruction. 11950ebc4cdaSBenjamin Herrenschmidt */ 11960ebc4cdaSBenjamin Herrenschmidt 11970ebc4cdaSBenjamin Herrenschmidt/*** Common interrupt handlers ***/ 11980ebc4cdaSBenjamin Herrenschmidt 11990ebc4cdaSBenjamin Herrenschmidt 12001dbdafecSIan Munsie#ifdef CONFIG_PPC_DOORBELL 1201da2bc464SMichael EllermanEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 12021dbdafecSIan Munsie#else 1203da2bc464SMichael EllermanEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 12041dbdafecSIan Munsie#endif 1205da2bc464SMichael EllermanEXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 1206da2bc464SMichael EllermanEXC_COMMON(single_step_common, 0xd00, single_step_exception) 1207da2bc464SMichael EllermanEXC_COMMON(trap_0e_common, 0xe00, unknown_exception) 1208da2bc464SMichael EllermanEXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 1209da2bc464SMichael EllermanEXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) 1210655bb3f4SIan Munsie#ifdef CONFIG_PPC_DOORBELL 1211da2bc464SMichael EllermanEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 1212655bb3f4SIan Munsie#else 1213da2bc464SMichael EllermanEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 1214655bb3f4SIan Munsie#endif 1215da2bc464SMichael EllermanEXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 1216da2bc464SMichael EllermanEXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1217da2bc464SMichael EllermanEXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 1218da2bc464SMichael EllermanEXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) 12190ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_ALTIVEC 1220da2bc464SMichael EllermanEXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 12210ebc4cdaSBenjamin Herrenschmidt#else 1222da2bc464SMichael EllermanEXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 12230ebc4cdaSBenjamin Herrenschmidt#endif 12240ebc4cdaSBenjamin Herrenschmidt 1225c1fb6816SMichael Neuling /* 1226c1fb6816SMichael Neuling * Relocation-on interrupts: A subset of the interrupts can be delivered 1227c1fb6816SMichael Neuling * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 1228c1fb6816SMichael Neuling * it. Addresses are the same as the original interrupt addresses, but 1229c1fb6816SMichael Neuling * offset by 0xc000000000004000. 1230c1fb6816SMichael Neuling * It's impossible to receive interrupts below 0x300 via this mechanism. 1231c1fb6816SMichael Neuling * KVM: None of these traps are from the guest ; anything that escalated 1232c1fb6816SMichael Neuling * to HV=1 from HV=0 is delivered via real mode handlers. 1233c1fb6816SMichael Neuling */ 1234c1fb6816SMichael Neuling 1235c1fb6816SMichael Neuling /* 1236c1fb6816SMichael Neuling * This uses the standard macro, since the original 0x300 vector 1237c1fb6816SMichael Neuling * only has extra guff for STAB-based processors -- which never 1238c1fb6816SMichael Neuling * come here. 1239c1fb6816SMichael Neuling */ 1240da2bc464SMichael Ellerman 1241da2bc464SMichael EllermanEXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00) 1242da2bc464SMichael EllermanEXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) 1243da2bc464SMichael Ellerman 1244da2bc464SMichael EllermanEXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00) 1245c1fb6816SMichael Neuling HMT_MEDIUM 1246c1fb6816SMichael Neuling SYSCALL_PSERIES_1 1247c1fb6816SMichael Neuling SYSCALL_PSERIES_2_DIRECT 1248c1fb6816SMichael Neuling SYSCALL_PSERIES_3 1249da2bc464SMichael EllermanEXC_VIRT_END(system_call, 0x4c00, 0x4d00) 1250c1fb6816SMichael Neuling 1251da2bc464SMichael EllermanEXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00) 1252c1fb6816SMichael Neuling 1253da2bc464SMichael EllermanEXC_VIRT_BEGIN(unused, 0x4e00, 0x4e20) 12541d567cb4SMichael Ellerman b . /* Can't happen, see v2.07 Book III-S section 6.5 */ 1255da2bc464SMichael EllermanEXC_VIRT_END(unused, 0x4e00, 0x4e20) 1256c1fb6816SMichael Neuling 1257da2bc464SMichael EllermanEXC_VIRT_BEGIN(unused, 0x4e20, 0x4e40) 12581d567cb4SMichael Ellerman b . /* Can't happen, see v2.07 Book III-S section 6.5 */ 1259da2bc464SMichael EllermanEXC_VIRT_END(unused, 0x4e20, 0x4e40) 1260c1fb6816SMichael Neuling 1261da2bc464SMichael Ellerman__EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60) 1262c1fb6816SMichael Neuling 1263da2bc464SMichael EllermanEXC_VIRT_BEGIN(unused, 0x4e60, 0x4e80) 12641d567cb4SMichael Ellerman b . /* Can't happen, see v2.07 Book III-S section 6.5 */ 1265da2bc464SMichael EllermanEXC_VIRT_END(unused, 0x4e60, 0x4e80) 1266c1fb6816SMichael Neuling 1267da2bc464SMichael Ellerman__EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0) 1268c1fb6816SMichael Neuling 1269da2bc464SMichael Ellerman__EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0) 12709baaef0aSBenjamin Herrenschmidt 1271da2bc464SMichael EllermanEXC_VIRT_NONE(0x4ec0, 0x4f00) 1272c1fb6816SMichael Neuling 1273da2bc464SMichael Ellerman__EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20) 1274c1fb6816SMichael Neuling 1275da2bc464SMichael Ellerman__EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40) 1276c1fb6816SMichael Neuling 1277da2bc464SMichael Ellerman__EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60) 1278d0c0c9a1SMichael Neuling 1279da2bc464SMichael Ellerman__EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80) 1280b14b6260SMichael Ellerman 1281da2bc464SMichael Ellerman__EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0) 1282da2bc464SMichael Ellerman 1283da2bc464SMichael EllermanEXC_VIRT_NONE(0x4fa0, 0x5200) 1284da2bc464SMichael Ellerman 1285da2bc464SMichael EllermanEXC_VIRT_NONE(0x5200, 0x5300) 1286da2bc464SMichael Ellerman 1287da2bc464SMichael EllermanEXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300) 1288da2bc464SMichael Ellerman 1289c1fb6816SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 1290da2bc464SMichael EllermanEXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600) 1291da2bc464SMichael Ellerman b exc_real_0x1500_denorm_exception_hv 1292da2bc464SMichael EllermanEXC_VIRT_END(denorm_exception, 0x5500, 0x5600) 1293da2bc464SMichael Ellerman#else 1294da2bc464SMichael EllermanEXC_VIRT_NONE(0x5500, 0x5600) 1295c1fb6816SMichael Neuling#endif 1296c1fb6816SMichael Neuling 1297da2bc464SMichael EllermanEXC_VIRT_NONE(0x5600, 0x5700) 1298da2bc464SMichael Ellerman 1299da2bc464SMichael EllermanEXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700) 1300da2bc464SMichael Ellerman 1301da2bc464SMichael EllermanEXC_VIRT_NONE(0x5800, 0x5900) 1302da2bc464SMichael Ellerman 130357f26649SNicholas PigginEXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 1304b1576fecSAnton Blanchard b __ppc64_runlatch_on 1305fe1952fcSBenjamin Herrenschmidt 1306da2bc464SMichael EllermanEXC_COMMON_BEGIN(h_data_storage_common) 1307b3e6b5dfSBenjamin Herrenschmidt mfspr r10,SPRN_HDAR 1308b3e6b5dfSBenjamin Herrenschmidt std r10,PACA_EXGEN+EX_DAR(r13) 1309b3e6b5dfSBenjamin Herrenschmidt mfspr r10,SPRN_HDSISR 1310b3e6b5dfSBenjamin Herrenschmidt stw r10,PACA_EXGEN+EX_DSISR(r13) 1311b3e6b5dfSBenjamin Herrenschmidt EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) 1312b1576fecSAnton Blanchard bl save_nvgprs 13139daf112bSMichael Ellerman RECONCILE_IRQ_STATE(r10, r11) 1314b3e6b5dfSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 1315b1576fecSAnton Blanchard bl unknown_exception 1316b1576fecSAnton Blanchard b ret_from_except 1317b3e6b5dfSBenjamin Herrenschmidt 13180ebc4cdaSBenjamin Herrenschmidt 1319da2bc464SMichael EllermanEXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 1320b3e6b5dfSBenjamin Herrenschmidt 1321da2bc464SMichael EllermanEXC_COMMON_BEGIN(altivec_unavailable_common) 13220ebc4cdaSBenjamin Herrenschmidt EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 13230ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_ALTIVEC 13240ebc4cdaSBenjamin HerrenschmidtBEGIN_FTR_SECTION 13250ebc4cdaSBenjamin Herrenschmidt beq 1f 1326bc2a9408SMichael Neuling#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1327bc2a9408SMichael Neuling BEGIN_FTR_SECTION_NESTED(69) 1328bc2a9408SMichael Neuling /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1329bc2a9408SMichael Neuling * transaction), go do TM stuff 1330bc2a9408SMichael Neuling */ 1331bc2a9408SMichael Neuling rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1332bc2a9408SMichael Neuling bne- 2f 1333bc2a9408SMichael Neuling END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1334bc2a9408SMichael Neuling#endif 1335b1576fecSAnton Blanchard bl load_up_altivec 13360ebc4cdaSBenjamin Herrenschmidt b fast_exception_return 1337bc2a9408SMichael Neuling#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1338bc2a9408SMichael Neuling2: /* User process was in a transaction */ 1339b1576fecSAnton Blanchard bl save_nvgprs 13409daf112bSMichael Ellerman RECONCILE_IRQ_STATE(r10, r11) 1341bc2a9408SMichael Neuling addi r3,r1,STACK_FRAME_OVERHEAD 1342b1576fecSAnton Blanchard bl altivec_unavailable_tm 1343b1576fecSAnton Blanchard b ret_from_except 1344bc2a9408SMichael Neuling#endif 13450ebc4cdaSBenjamin Herrenschmidt1: 13460ebc4cdaSBenjamin HerrenschmidtEND_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 13470ebc4cdaSBenjamin Herrenschmidt#endif 1348b1576fecSAnton Blanchard bl save_nvgprs 13499daf112bSMichael Ellerman RECONCILE_IRQ_STATE(r10, r11) 13500ebc4cdaSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 1351b1576fecSAnton Blanchard bl altivec_unavailable_exception 1352b1576fecSAnton Blanchard b ret_from_except 13530ebc4cdaSBenjamin Herrenschmidt 1354da2bc464SMichael EllermanEXC_COMMON_BEGIN(vsx_unavailable_common) 13550ebc4cdaSBenjamin Herrenschmidt EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) 13560ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_VSX 13570ebc4cdaSBenjamin HerrenschmidtBEGIN_FTR_SECTION 13587230c564SBenjamin Herrenschmidt beq 1f 1359bc2a9408SMichael Neuling#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1360bc2a9408SMichael Neuling BEGIN_FTR_SECTION_NESTED(69) 1361bc2a9408SMichael Neuling /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1362bc2a9408SMichael Neuling * transaction), go do TM stuff 1363bc2a9408SMichael Neuling */ 1364bc2a9408SMichael Neuling rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1365bc2a9408SMichael Neuling bne- 2f 1366bc2a9408SMichael Neuling END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1367bc2a9408SMichael Neuling#endif 1368b1576fecSAnton Blanchard b load_up_vsx 1369bc2a9408SMichael Neuling#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1370bc2a9408SMichael Neuling2: /* User process was in a transaction */ 1371b1576fecSAnton Blanchard bl save_nvgprs 13729daf112bSMichael Ellerman RECONCILE_IRQ_STATE(r10, r11) 1373bc2a9408SMichael Neuling addi r3,r1,STACK_FRAME_OVERHEAD 1374b1576fecSAnton Blanchard bl vsx_unavailable_tm 1375b1576fecSAnton Blanchard b ret_from_except 1376bc2a9408SMichael Neuling#endif 13770ebc4cdaSBenjamin Herrenschmidt1: 13780ebc4cdaSBenjamin HerrenschmidtEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 13790ebc4cdaSBenjamin Herrenschmidt#endif 1380b1576fecSAnton Blanchard bl save_nvgprs 13819daf112bSMichael Ellerman RECONCILE_IRQ_STATE(r10, r11) 13820ebc4cdaSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 1383b1576fecSAnton Blanchard bl vsx_unavailable_exception 1384b1576fecSAnton Blanchard b ret_from_except 13850ebc4cdaSBenjamin Herrenschmidt 138661383407SBenjamin Herrenschmidt /* Equivalents to the above handlers for relocation-on interrupt vectors */ 1387da2bc464SMichael Ellerman__TRAMP_REAL_VIRT_OOL_HV(emulation_assist, 0xe40) 1388da2bc464SMichael Ellerman__TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_doorbell, 0xe80) 1389da2bc464SMichael Ellerman__TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0xea0) 1390da2bc464SMichael Ellerman__TRAMP_REAL_VIRT_OOL(performance_monitor, 0xf00) 1391da2bc464SMichael Ellerman__TRAMP_REAL_VIRT_OOL(altivec_unavailable, 0xf20) 1392da2bc464SMichael Ellerman__TRAMP_REAL_VIRT_OOL(vsx_unavailable, 0xf40) 1393da2bc464SMichael Ellerman__TRAMP_REAL_VIRT_OOL(facility_unavailable, 0xf60) 1394da2bc464SMichael Ellerman__TRAMP_REAL_VIRT_OOL_HV(h_facility_unavailable, 0xf80) 139561383407SBenjamin Herrenschmidt 139657f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 13978ed8ab40SHari Bathini /* 13988ed8ab40SHari Bathini * The __end_interrupts marker must be past the out-of-line (OOL) 13998ed8ab40SHari Bathini * handlers, so that they are copied to real address 0x100 when running 14008ed8ab40SHari Bathini * a relocatable kernel. This ensures they can be reached from the short 14018ed8ab40SHari Bathini * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 14028ed8ab40SHari Bathini * directly, without using LOAD_HANDLER(). 14038ed8ab40SHari Bathini */ 14048ed8ab40SHari Bathini .align 7 14058ed8ab40SHari Bathini .globl __end_interrupts 14068ed8ab40SHari Bathini__end_interrupts: 140757f26649SNicholas PigginDEFINE_FIXED_SYMBOL(__end_interrupts) 140861383407SBenjamin Herrenschmidt 1409da2bc464SMichael EllermanEXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 1410da2bc464SMichael EllermanEXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 1411b88d4bceSBenjamin Herrenschmidt 1412b88d4bceSBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 1413da2bc464SMichael EllermanEXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1414da2bc464SMichael EllermanEXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 1415da2bc464SMichael EllermanEXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 1416b88d4bceSBenjamin Herrenschmidt#endif /* CONFIG_CBE_RAS */ 1417b88d4bceSBenjamin Herrenschmidt 1418da2bc464SMichael Ellerman 141957f26649SNicholas PigginTRAMP_REAL_BEGIN(hmi_exception_early) 1420da2bc464SMichael Ellerman EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) 142111d54904SGuenter Roeck mr r10,r1 /* Save r1 */ 142211d54904SGuenter Roeck ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 142311d54904SGuenter Roeck subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 142411d54904SGuenter Roeck std r9,_CCR(r1) /* save CR in stackframe */ 142511d54904SGuenter Roeck mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 142611d54904SGuenter Roeck std r11,_NIP(r1) /* save HSRR0 in stackframe */ 142711d54904SGuenter Roeck mfspr r12,SPRN_HSRR1 /* Save SRR1 */ 142811d54904SGuenter Roeck std r12,_MSR(r1) /* save SRR1 in stackframe */ 142911d54904SGuenter Roeck std r10,0(r1) /* make stack chain pointer */ 143011d54904SGuenter Roeck std r0,GPR0(r1) /* save r0 in stackframe */ 143111d54904SGuenter Roeck std r10,GPR1(r1) /* save r1 in stackframe */ 143211d54904SGuenter Roeck EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 143311d54904SGuenter Roeck EXCEPTION_PROLOG_COMMON_3(0xe60) 143411d54904SGuenter Roeck addi r3,r1,STACK_FRAME_OVERHEAD 143511d54904SGuenter Roeck bl hmi_exception_realmode 143611d54904SGuenter Roeck /* Windup the stack. */ 143711d54904SGuenter Roeck /* Move original HSRR0 and HSRR1 into the respective regs */ 143811d54904SGuenter Roeck ld r9,_MSR(r1) 143911d54904SGuenter Roeck mtspr SPRN_HSRR1,r9 144011d54904SGuenter Roeck ld r3,_NIP(r1) 144111d54904SGuenter Roeck mtspr SPRN_HSRR0,r3 144211d54904SGuenter Roeck ld r9,_CTR(r1) 144311d54904SGuenter Roeck mtctr r9 144411d54904SGuenter Roeck ld r9,_XER(r1) 144511d54904SGuenter Roeck mtxer r9 144611d54904SGuenter Roeck ld r9,_LINK(r1) 144711d54904SGuenter Roeck mtlr r9 144811d54904SGuenter Roeck REST_GPR(0, r1) 144911d54904SGuenter Roeck REST_8GPRS(2, r1) 145011d54904SGuenter Roeck REST_GPR(10, r1) 145111d54904SGuenter Roeck ld r11,_CCR(r1) 145211d54904SGuenter Roeck mtcr r11 145311d54904SGuenter Roeck REST_GPR(11, r1) 145411d54904SGuenter Roeck REST_2GPRS(12, r1) 145511d54904SGuenter Roeck /* restore original r1. */ 145611d54904SGuenter Roeck ld r1,GPR1(r1) 145711d54904SGuenter Roeck 145811d54904SGuenter Roeck /* 145911d54904SGuenter Roeck * Go to virtual mode and pull the HMI event information from 146011d54904SGuenter Roeck * firmware. 146111d54904SGuenter Roeck */ 146211d54904SGuenter Roeck .globl hmi_exception_after_realmode 146311d54904SGuenter Roeckhmi_exception_after_realmode: 146411d54904SGuenter Roeck SET_SCRATCH0(r13) 146511d54904SGuenter Roeck EXCEPTION_PROLOG_0(PACA_EXGEN) 1466da2bc464SMichael Ellerman b tramp_real_hmi_exception 146711d54904SGuenter Roeck 1468087aa036SChen Gang#ifdef CONFIG_PPC_970_NAP 1469da2bc464SMichael EllermanTRAMP_REAL_BEGIN(power4_fixup_nap) 1470087aa036SChen Gang andc r9,r9,r10 1471087aa036SChen Gang std r9,TI_LOCAL_FLAGS(r11) 1472087aa036SChen Gang ld r10,_LINK(r1) /* make idle task do the */ 1473087aa036SChen Gang std r10,_NIP(r1) /* equivalent of a blr */ 1474087aa036SChen Gang blr 1475087aa036SChen Gang#endif 1476087aa036SChen Gang 147757f26649SNicholas PigginCLOSE_FIXED_SECTION(real_vectors); 147857f26649SNicholas PigginCLOSE_FIXED_SECTION(real_trampolines); 147957f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_vectors); 148057f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_trampolines); 148157f26649SNicholas Piggin 148257f26649SNicholas PigginUSE_TEXT_SECTION() 148357f26649SNicholas Piggin 1484087aa036SChen Gang/* 14850ebc4cdaSBenjamin Herrenschmidt * Hash table stuff 14860ebc4cdaSBenjamin Herrenschmidt */ 14870ebc4cdaSBenjamin Herrenschmidt .align 7 14886a3bab90SAnton Blancharddo_hash_page: 1489caca285eSAneesh Kumar K.V#ifdef CONFIG_PPC_STD_MMU_64 14909c7cc234SK.Prasad andis. r0,r4,0xa410 /* weird error? */ 14910ebc4cdaSBenjamin Herrenschmidt bne- handle_page_fault /* if not, try to insert a HPTE */ 14929c7cc234SK.Prasad andis. r0,r4,DSISR_DABRMATCH@h 14939c7cc234SK.Prasad bne- handle_dabr_fault 14949778b696SStuart Yoder CURRENT_THREAD_INFO(r11, r1) 14959c1e1052SPaul Mackerras lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 14969c1e1052SPaul Mackerras andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 14979c1e1052SPaul Mackerras bne 77f /* then don't call hash_page now */ 14980ebc4cdaSBenjamin Herrenschmidt 14990ebc4cdaSBenjamin Herrenschmidt /* 15000ebc4cdaSBenjamin Herrenschmidt * r3 contains the faulting address 1501106713a1SAneesh Kumar K.V * r4 msr 15020ebc4cdaSBenjamin Herrenschmidt * r5 contains the trap number 1503aefa5688SAneesh Kumar K.V * r6 contains dsisr 15040ebc4cdaSBenjamin Herrenschmidt * 15057230c564SBenjamin Herrenschmidt * at return r3 = 0 for success, 1 for page fault, negative for error 15060ebc4cdaSBenjamin Herrenschmidt */ 1507106713a1SAneesh Kumar K.V mr r4,r12 1508aefa5688SAneesh Kumar K.V ld r6,_DSISR(r1) 1509106713a1SAneesh Kumar K.V bl __hash_page /* build HPTE if possible */ 1510106713a1SAneesh Kumar K.V cmpdi r3,0 /* see if __hash_page succeeded */ 15110ebc4cdaSBenjamin Herrenschmidt 15127230c564SBenjamin Herrenschmidt /* Success */ 15130ebc4cdaSBenjamin Herrenschmidt beq fast_exc_return_irq /* Return from exception on success */ 15140ebc4cdaSBenjamin Herrenschmidt 15157230c564SBenjamin Herrenschmidt /* Error */ 15167230c564SBenjamin Herrenschmidt blt- 13f 1517caca285eSAneesh Kumar K.V#endif /* CONFIG_PPC_STD_MMU_64 */ 15180ebc4cdaSBenjamin Herrenschmidt 1519a546498fSBenjamin Herrenschmidt/* Here we have a page fault that hash_page can't handle. */ 1520a546498fSBenjamin Herrenschmidthandle_page_fault: 1521a546498fSBenjamin Herrenschmidt11: ld r4,_DAR(r1) 1522a546498fSBenjamin Herrenschmidt ld r5,_DSISR(r1) 1523a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 1524b1576fecSAnton Blanchard bl do_page_fault 1525a546498fSBenjamin Herrenschmidt cmpdi r3,0 1526a546498fSBenjamin Herrenschmidt beq+ 12f 1527b1576fecSAnton Blanchard bl save_nvgprs 1528a546498fSBenjamin Herrenschmidt mr r5,r3 1529a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 1530a546498fSBenjamin Herrenschmidt lwz r4,_DAR(r1) 1531b1576fecSAnton Blanchard bl bad_page_fault 1532b1576fecSAnton Blanchard b ret_from_except 15330ebc4cdaSBenjamin Herrenschmidt 15349c7cc234SK.Prasad/* We have a data breakpoint exception - handle it */ 15359c7cc234SK.Prasadhandle_dabr_fault: 1536b1576fecSAnton Blanchard bl save_nvgprs 15379c7cc234SK.Prasad ld r4,_DAR(r1) 15389c7cc234SK.Prasad ld r5,_DSISR(r1) 15399c7cc234SK.Prasad addi r3,r1,STACK_FRAME_OVERHEAD 1540b1576fecSAnton Blanchard bl do_break 1541b1576fecSAnton Blanchard12: b ret_from_except_lite 15429c7cc234SK.Prasad 15430ebc4cdaSBenjamin Herrenschmidt 1544caca285eSAneesh Kumar K.V#ifdef CONFIG_PPC_STD_MMU_64 15450ebc4cdaSBenjamin Herrenschmidt/* We have a page fault that hash_page could handle but HV refused 15460ebc4cdaSBenjamin Herrenschmidt * the PTE insertion 15470ebc4cdaSBenjamin Herrenschmidt */ 1548b1576fecSAnton Blanchard13: bl save_nvgprs 15490ebc4cdaSBenjamin Herrenschmidt mr r5,r3 15500ebc4cdaSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 15510ebc4cdaSBenjamin Herrenschmidt ld r4,_DAR(r1) 1552b1576fecSAnton Blanchard bl low_hash_fault 1553b1576fecSAnton Blanchard b ret_from_except 1554caca285eSAneesh Kumar K.V#endif 15550ebc4cdaSBenjamin Herrenschmidt 15569c1e1052SPaul Mackerras/* 15579c1e1052SPaul Mackerras * We come here as a result of a DSI at a point where we don't want 15589c1e1052SPaul Mackerras * to call hash_page, such as when we are accessing memory (possibly 15599c1e1052SPaul Mackerras * user memory) inside a PMU interrupt that occurred while interrupts 15609c1e1052SPaul Mackerras * were soft-disabled. We want to invoke the exception handler for 15619c1e1052SPaul Mackerras * the access, or panic if there isn't a handler. 15629c1e1052SPaul Mackerras */ 1563b1576fecSAnton Blanchard77: bl save_nvgprs 15649c1e1052SPaul Mackerras mr r4,r3 15659c1e1052SPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 15669c1e1052SPaul Mackerras li r5,SIGSEGV 1567b1576fecSAnton Blanchard bl bad_page_fault 1568b1576fecSAnton Blanchard b ret_from_except 15694e2bf01bSMichael Ellerman 15704e2bf01bSMichael Ellerman/* 15714e2bf01bSMichael Ellerman * Here we have detected that the kernel stack pointer is bad. 15724e2bf01bSMichael Ellerman * R9 contains the saved CR, r13 points to the paca, 15734e2bf01bSMichael Ellerman * r10 contains the (bad) kernel stack pointer, 15744e2bf01bSMichael Ellerman * r11 and r12 contain the saved SRR0 and SRR1. 15754e2bf01bSMichael Ellerman * We switch to using an emergency stack, save the registers there, 15764e2bf01bSMichael Ellerman * and call kernel_bad_stack(), which panics. 15774e2bf01bSMichael Ellerman */ 15784e2bf01bSMichael Ellermanbad_stack: 15794e2bf01bSMichael Ellerman ld r1,PACAEMERGSP(r13) 15804e2bf01bSMichael Ellerman subi r1,r1,64+INT_FRAME_SIZE 15814e2bf01bSMichael Ellerman std r9,_CCR(r1) 15824e2bf01bSMichael Ellerman std r10,GPR1(r1) 15834e2bf01bSMichael Ellerman std r11,_NIP(r1) 15844e2bf01bSMichael Ellerman std r12,_MSR(r1) 15854e2bf01bSMichael Ellerman mfspr r11,SPRN_DAR 15864e2bf01bSMichael Ellerman mfspr r12,SPRN_DSISR 15874e2bf01bSMichael Ellerman std r11,_DAR(r1) 15884e2bf01bSMichael Ellerman std r12,_DSISR(r1) 15894e2bf01bSMichael Ellerman mflr r10 15904e2bf01bSMichael Ellerman mfctr r11 15914e2bf01bSMichael Ellerman mfxer r12 15924e2bf01bSMichael Ellerman std r10,_LINK(r1) 15934e2bf01bSMichael Ellerman std r11,_CTR(r1) 15944e2bf01bSMichael Ellerman std r12,_XER(r1) 15954e2bf01bSMichael Ellerman SAVE_GPR(0,r1) 15964e2bf01bSMichael Ellerman SAVE_GPR(2,r1) 15974e2bf01bSMichael Ellerman ld r10,EX_R3(r3) 15984e2bf01bSMichael Ellerman std r10,GPR3(r1) 15994e2bf01bSMichael Ellerman SAVE_GPR(4,r1) 16004e2bf01bSMichael Ellerman SAVE_4GPRS(5,r1) 16014e2bf01bSMichael Ellerman ld r9,EX_R9(r3) 16024e2bf01bSMichael Ellerman ld r10,EX_R10(r3) 16034e2bf01bSMichael Ellerman SAVE_2GPRS(9,r1) 16044e2bf01bSMichael Ellerman ld r9,EX_R11(r3) 16054e2bf01bSMichael Ellerman ld r10,EX_R12(r3) 16064e2bf01bSMichael Ellerman ld r11,EX_R13(r3) 16074e2bf01bSMichael Ellerman std r9,GPR11(r1) 16084e2bf01bSMichael Ellerman std r10,GPR12(r1) 16094e2bf01bSMichael Ellerman std r11,GPR13(r1) 16104e2bf01bSMichael EllermanBEGIN_FTR_SECTION 16114e2bf01bSMichael Ellerman ld r10,EX_CFAR(r3) 16124e2bf01bSMichael Ellerman std r10,ORIG_GPR3(r1) 16134e2bf01bSMichael EllermanEND_FTR_SECTION_IFSET(CPU_FTR_CFAR) 16144e2bf01bSMichael Ellerman SAVE_8GPRS(14,r1) 16154e2bf01bSMichael Ellerman SAVE_10GPRS(22,r1) 16164e2bf01bSMichael Ellerman lhz r12,PACA_TRAP_SAVE(r13) 16174e2bf01bSMichael Ellerman std r12,_TRAP(r1) 16184e2bf01bSMichael Ellerman addi r11,r1,INT_FRAME_SIZE 16194e2bf01bSMichael Ellerman std r11,0(r1) 16204e2bf01bSMichael Ellerman li r12,0 16214e2bf01bSMichael Ellerman std r12,0(r11) 16224e2bf01bSMichael Ellerman ld r2,PACATOC(r13) 16234e2bf01bSMichael Ellerman ld r11,exception_marker@toc(r2) 16244e2bf01bSMichael Ellerman std r12,RESULT(r1) 16254e2bf01bSMichael Ellerman std r11,STACK_FRAME_OVERHEAD-16(r1) 16264e2bf01bSMichael Ellerman1: addi r3,r1,STACK_FRAME_OVERHEAD 16274e2bf01bSMichael Ellerman bl kernel_bad_stack 16284e2bf01bSMichael Ellerman b 1b 1629