1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 20ebc4cdaSBenjamin Herrenschmidt/* 30ebc4cdaSBenjamin Herrenschmidt * This file contains the 64-bit "server" PowerPC variant 40ebc4cdaSBenjamin Herrenschmidt * of the low level exception handling including exception 50ebc4cdaSBenjamin Herrenschmidt * vectors, exception return, part of the slb and stab 60ebc4cdaSBenjamin Herrenschmidt * handling and other fixed offset specific things. 70ebc4cdaSBenjamin Herrenschmidt * 80ebc4cdaSBenjamin Herrenschmidt * This file is meant to be #included from head_64.S due to 925985edcSLucas De Marchi * position dependent assembly. 100ebc4cdaSBenjamin Herrenschmidt * 110ebc4cdaSBenjamin Herrenschmidt * Most of this originates from head_64.S and thus has the same 120ebc4cdaSBenjamin Herrenschmidt * copyright history. 130ebc4cdaSBenjamin Herrenschmidt * 140ebc4cdaSBenjamin Herrenschmidt */ 150ebc4cdaSBenjamin Herrenschmidt 167230c564SBenjamin Herrenschmidt#include <asm/hw_irq.h> 178aa34ab8SBenjamin Herrenschmidt#include <asm/exception-64s.h> 1846f52210SStephen Rothwell#include <asm/ptrace.h> 197cba160aSShreyas B. Prabhu#include <asm/cpuidle.h> 20da2bc464SMichael Ellerman#include <asm/head-64.h> 212c86cd18SChristophe Leroy#include <asm/feature-fixups.h> 228aa34ab8SBenjamin Herrenschmidt 230ebc4cdaSBenjamin Herrenschmidt/* 2457f26649SNicholas Piggin * There are a few constraints to be concerned with. 2557f26649SNicholas Piggin * - Real mode exceptions code/data must be located at their physical location. 2657f26649SNicholas Piggin * - Virtual mode exceptions must be mapped at their 0xc000... location. 2757f26649SNicholas Piggin * - Fixed location code must not call directly beyond the __end_interrupts 2857f26649SNicholas Piggin * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 2957f26649SNicholas Piggin * must be used. 3057f26649SNicholas Piggin * - LOAD_HANDLER targets must be within first 64K of physical 0 / 3157f26649SNicholas Piggin * virtual 0xc00... 3257f26649SNicholas Piggin * - Conditional branch targets must be within +/-32K of caller. 3357f26649SNicholas Piggin * 3457f26649SNicholas Piggin * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 3557f26649SNicholas Piggin * therefore don't have to run in physically located code or rfid to 3657f26649SNicholas Piggin * virtual mode kernel code. However on relocatable kernels they do have 3757f26649SNicholas Piggin * to branch to KERNELBASE offset because the rest of the kernel (outside 3857f26649SNicholas Piggin * the exception vectors) may be located elsewhere. 3957f26649SNicholas Piggin * 4057f26649SNicholas Piggin * Virtual exceptions correspond with physical, except their entry points 4157f26649SNicholas Piggin * are offset by 0xc000000000000000 and also tend to get an added 0x4000 4257f26649SNicholas Piggin * offset applied. Virtual exceptions are enabled with the Alternate 4357f26649SNicholas Piggin * Interrupt Location (AIL) bit set in the LPCR. However this does not 4457f26649SNicholas Piggin * guarantee they will be delivered virtually. Some conditions (see the ISA) 4557f26649SNicholas Piggin * cause exceptions to be delivered in real mode. 4657f26649SNicholas Piggin * 4757f26649SNicholas Piggin * It's impossible to receive interrupts below 0x300 via AIL. 4857f26649SNicholas Piggin * 4957f26649SNicholas Piggin * KVM: None of the virtual exceptions are from the guest. Anything that 5057f26649SNicholas Piggin * escalated to HV=1 from HV=0 is delivered via real mode handlers. 5157f26649SNicholas Piggin * 5257f26649SNicholas Piggin * 530ebc4cdaSBenjamin Herrenschmidt * We layout physical memory as follows: 540ebc4cdaSBenjamin Herrenschmidt * 0x0000 - 0x00ff : Secondary processor spin code 5557f26649SNicholas Piggin * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 5657f26649SNicholas Piggin * 0x1900 - 0x3fff : Real mode trampolines 5757f26649SNicholas Piggin * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 5857f26649SNicholas Piggin * 0x5900 - 0x6fff : Relon mode trampolines 590ebc4cdaSBenjamin Herrenschmidt * 0x7000 - 0x7fff : FWNMI data area 6057f26649SNicholas Piggin * 0x8000 - .... : Common interrupt handlers, remaining early 6157f26649SNicholas Piggin * setup code, rest of kernel. 62e0319829SNicholas Piggin * 63e0319829SNicholas Piggin * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 64e0319829SNicholas Piggin * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 65e0319829SNicholas Piggin * vectors there. 660ebc4cdaSBenjamin Herrenschmidt */ 6757f26649SNicholas PigginOPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 6857f26649SNicholas PigginOPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 6957f26649SNicholas PigginOPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 7057f26649SNicholas PigginOPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 71*ccd47702SNicholas Piggin 72*ccd47702SNicholas Piggin#ifdef CONFIG_PPC_POWERNV 73*ccd47702SNicholas Piggin .globl real_trampolines_start 74*ccd47702SNicholas Piggin .globl real_trampolines_end 75*ccd47702SNicholas Piggin .globl virt_trampolines_start 76*ccd47702SNicholas Piggin .globl virt_trampolines_end 77*ccd47702SNicholas Piggin#endif 78*ccd47702SNicholas Piggin 7957f26649SNicholas Piggin#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 8057f26649SNicholas Piggin/* 8157f26649SNicholas Piggin * Data area reserved for FWNMI option. 8257f26649SNicholas Piggin * This address (0x7000) is fixed by the RPA. 8357f26649SNicholas Piggin * pseries and powernv need to keep the whole page from 8457f26649SNicholas Piggin * 0x7000 to 0x8000 free for use by the firmware 8557f26649SNicholas Piggin */ 8657f26649SNicholas PigginZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 8757f26649SNicholas PigginOPEN_TEXT_SECTION(0x8000) 8857f26649SNicholas Piggin#else 8957f26649SNicholas PigginOPEN_TEXT_SECTION(0x7000) 9057f26649SNicholas Piggin#endif 9157f26649SNicholas Piggin 9257f26649SNicholas PigginUSE_FIXED_SECTION(real_vectors) 9357f26649SNicholas Piggin 940ebc4cdaSBenjamin Herrenschmidt/* 950ebc4cdaSBenjamin Herrenschmidt * This is the start of the interrupt handlers for pSeries 960ebc4cdaSBenjamin Herrenschmidt * This code runs with relocation off. 970ebc4cdaSBenjamin Herrenschmidt * Code from here to __end_interrupts gets copied down to real 980ebc4cdaSBenjamin Herrenschmidt * address 0x100 when we are running a relocatable kernel. 990ebc4cdaSBenjamin Herrenschmidt * Therefore any relative branches in this section must only 1000ebc4cdaSBenjamin Herrenschmidt * branch to labels in this section. 1010ebc4cdaSBenjamin Herrenschmidt */ 1020ebc4cdaSBenjamin Herrenschmidt .globl __start_interrupts 1030ebc4cdaSBenjamin Herrenschmidt__start_interrupts: 1040ebc4cdaSBenjamin Herrenschmidt 105e0319829SNicholas Piggin/* No virt vectors corresponding with 0x0..0x100 */ 1061a6822d1SNicholas PigginEXC_VIRT_NONE(0x4000, 0x100) 107e0319829SNicholas Piggin 108fb479e44SNicholas Piggin 109fb479e44SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 110fb479e44SNicholas Piggin /* 111fb479e44SNicholas Piggin * If running native on arch 2.06 or later, check if we are waking up 112ba6d334aSBenjamin Herrenschmidt * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 113ba6d334aSBenjamin Herrenschmidt * bits 46:47. A non-0 value indicates that we are coming from a power 114ba6d334aSBenjamin Herrenschmidt * saving state. The idle wakeup handler initially runs in real mode, 115ba6d334aSBenjamin Herrenschmidt * but we branch to the 0xc000... address so we can turn on relocation 116ba6d334aSBenjamin Herrenschmidt * with mtmsr. 117fb479e44SNicholas Piggin */ 118fb479e44SNicholas Piggin#define IDLETEST(n) \ 119fb479e44SNicholas Piggin BEGIN_FTR_SECTION ; \ 120fb479e44SNicholas Piggin mfspr r10,SPRN_SRR1 ; \ 121fb479e44SNicholas Piggin rlwinm. r10,r10,47-31,30,31 ; \ 122fb479e44SNicholas Piggin beq- 1f ; \ 123fb479e44SNicholas Piggin cmpwi cr3,r10,2 ; \ 124b51351e2SNicholas Piggin BRANCH_TO_C000(r10, system_reset_idle_common) ; \ 125fb479e44SNicholas Piggin1: \ 1266de6638bSNicholas Piggin KVMTEST_PR(n) ; \ 127fb479e44SNicholas Piggin END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 128fb479e44SNicholas Piggin#else 129fb479e44SNicholas Piggin#define IDLETEST NOTEST 130fb479e44SNicholas Piggin#endif 131fb479e44SNicholas Piggin 1321a6822d1SNicholas PigginEXC_REAL_BEGIN(system_reset, 0x100, 0x100) 133948cf67cSBenjamin Herrenschmidt SET_SCRATCH0(r13) 134c4f3b52cSNicholas Piggin /* 135c4f3b52cSNicholas Piggin * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 136c4f3b52cSNicholas Piggin * being used, so a nested NMI exception would corrupt it. 137c4f3b52cSNicholas Piggin */ 13894f3cc8eSMichael Ellerman EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD, 139fb479e44SNicholas Piggin IDLETEST, 0x100) 140371fefd6SPaul Mackerras 1411a6822d1SNicholas PigginEXC_REAL_END(system_reset, 0x100, 0x100) 1421a6822d1SNicholas PigginEXC_VIRT_NONE(0x4100, 0x100) 1436de6638bSNicholas PigginTRAMP_KVM(PACA_EXNMI, 0x100) 144fb479e44SNicholas Piggin 145fb479e44SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 146fb479e44SNicholas PigginEXC_COMMON_BEGIN(system_reset_idle_common) 1479d292501SNicholas Piggin mfspr r12,SPRN_SRR1 148bf0153c1SNicholas Piggin b pnv_powersave_wakeup 149371fefd6SPaul Mackerras#endif 150371fefd6SPaul Mackerras 15115b4dd79SNicholas Piggin/* 15215b4dd79SNicholas Piggin * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does 15315b4dd79SNicholas Piggin * the right thing. We do not want to reconcile because that goes 15415b4dd79SNicholas Piggin * through irq tracing which we don't want in NMI. 15515b4dd79SNicholas Piggin * 15615b4dd79SNicholas Piggin * Save PACAIRQHAPPENED because some code will do a hard disable 15715b4dd79SNicholas Piggin * (e.g., xmon). So we want to restore this back to where it was 15815b4dd79SNicholas Piggin * when we return. DAR is unused in the stack, so save it there. 15915b4dd79SNicholas Piggin */ 16015b4dd79SNicholas Piggin#define ADD_RECONCILE_NMI \ 16115b4dd79SNicholas Piggin li r10,IRQS_ALL_DISABLED; \ 16215b4dd79SNicholas Piggin stb r10,PACAIRQSOFTMASK(r13); \ 16315b4dd79SNicholas Piggin lbz r10,PACAIRQHAPPENED(r13); \ 16415b4dd79SNicholas Piggin std r10,_DAR(r1) 16515b4dd79SNicholas Piggin 166a3d96f70SNicholas PigginEXC_COMMON_BEGIN(system_reset_common) 167c4f3b52cSNicholas Piggin /* 168c4f3b52cSNicholas Piggin * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 169c4f3b52cSNicholas Piggin * to recover, but nested NMI will notice in_nmi and not recover 170c4f3b52cSNicholas Piggin * because of the use of the NMI stack. in_nmi reentrancy is tested in 171c4f3b52cSNicholas Piggin * system_reset_exception. 172c4f3b52cSNicholas Piggin */ 173c4f3b52cSNicholas Piggin lhz r10,PACA_IN_NMI(r13) 174c4f3b52cSNicholas Piggin addi r10,r10,1 175c4f3b52cSNicholas Piggin sth r10,PACA_IN_NMI(r13) 176c4f3b52cSNicholas Piggin li r10,MSR_RI 177c4f3b52cSNicholas Piggin mtmsrd r10,1 178aca79d2bSVaidyanathan Srinivasan 179b1ee8a3dSNicholas Piggin mr r10,r1 180b1ee8a3dSNicholas Piggin ld r1,PACA_NMI_EMERG_SP(r13) 181b1ee8a3dSNicholas Piggin subi r1,r1,INT_FRAME_SIZE 182b1ee8a3dSNicholas Piggin EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100, 183b1ee8a3dSNicholas Piggin system_reset, system_reset_exception, 18415b4dd79SNicholas Piggin ADD_NVGPRS;ADD_RECONCILE_NMI) 18515b4dd79SNicholas Piggin 18615b4dd79SNicholas Piggin /* This (and MCE) can be simplified with mtmsrd L=1 */ 18715b4dd79SNicholas Piggin /* Clear MSR_RI before setting SRR0 and SRR1. */ 18815b4dd79SNicholas Piggin li r0,MSR_RI 18915b4dd79SNicholas Piggin mfmsr r9 19015b4dd79SNicholas Piggin andc r9,r9,r0 19115b4dd79SNicholas Piggin mtmsrd r9,1 192c4f3b52cSNicholas Piggin 193c4f3b52cSNicholas Piggin /* 19415b4dd79SNicholas Piggin * MSR_RI is clear, now we can decrement paca->in_nmi. 195c4f3b52cSNicholas Piggin */ 196c4f3b52cSNicholas Piggin lhz r10,PACA_IN_NMI(r13) 197c4f3b52cSNicholas Piggin subi r10,r10,1 198c4f3b52cSNicholas Piggin sth r10,PACA_IN_NMI(r13) 199c4f3b52cSNicholas Piggin 20015b4dd79SNicholas Piggin /* 20115b4dd79SNicholas Piggin * Restore soft mask settings. 20215b4dd79SNicholas Piggin */ 20315b4dd79SNicholas Piggin ld r10,_DAR(r1) 20415b4dd79SNicholas Piggin stb r10,PACAIRQHAPPENED(r13) 20515b4dd79SNicholas Piggin ld r10,SOFTE(r1) 20615b4dd79SNicholas Piggin stb r10,PACAIRQSOFTMASK(r13) 20715b4dd79SNicholas Piggin 20815b4dd79SNicholas Piggin /* 20915b4dd79SNicholas Piggin * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP. 21015b4dd79SNicholas Piggin * Should share common bits... 21115b4dd79SNicholas Piggin */ 21215b4dd79SNicholas Piggin 21315b4dd79SNicholas Piggin /* Move original SRR0 and SRR1 into the respective regs */ 21415b4dd79SNicholas Piggin ld r9,_MSR(r1) 21515b4dd79SNicholas Piggin mtspr SPRN_SRR1,r9 21615b4dd79SNicholas Piggin ld r3,_NIP(r1) 21715b4dd79SNicholas Piggin mtspr SPRN_SRR0,r3 21815b4dd79SNicholas Piggin ld r9,_CTR(r1) 21915b4dd79SNicholas Piggin mtctr r9 22015b4dd79SNicholas Piggin ld r9,_XER(r1) 22115b4dd79SNicholas Piggin mtxer r9 22215b4dd79SNicholas Piggin ld r9,_LINK(r1) 22315b4dd79SNicholas Piggin mtlr r9 22415b4dd79SNicholas Piggin REST_GPR(0, r1) 22515b4dd79SNicholas Piggin REST_8GPRS(2, r1) 22615b4dd79SNicholas Piggin REST_GPR(10, r1) 22715b4dd79SNicholas Piggin ld r11,_CCR(r1) 22815b4dd79SNicholas Piggin mtcr r11 22915b4dd79SNicholas Piggin REST_GPR(11, r1) 23015b4dd79SNicholas Piggin REST_2GPRS(12, r1) 23115b4dd79SNicholas Piggin /* restore original r1. */ 23215b4dd79SNicholas Piggin ld r1,GPR1(r1) 23315b4dd79SNicholas Piggin RFI_TO_USER_OR_KERNEL 234582baf44SNicholas Piggin 235582baf44SNicholas Piggin#ifdef CONFIG_PPC_PSERIES 236582baf44SNicholas Piggin/* 237582baf44SNicholas Piggin * Vectors for the FWNMI option. Share common code. 238582baf44SNicholas Piggin */ 239582baf44SNicholas PigginTRAMP_REAL_BEGIN(system_reset_fwnmi) 240582baf44SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 241c4f3b52cSNicholas Piggin /* See comment at system_reset exception */ 24294f3cc8eSMichael Ellerman EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD, 24394f3cc8eSMichael Ellerman NOTEST, 0x100) 244582baf44SNicholas Piggin#endif /* CONFIG_PPC_PSERIES */ 245582baf44SNicholas Piggin 2460ebc4cdaSBenjamin Herrenschmidt 2471a6822d1SNicholas PigginEXC_REAL_BEGIN(machine_check, 0x200, 0x100) 248b01c8b54SPaul Mackerras /* This is moved out of line as it can be patched by FW, but 249b01c8b54SPaul Mackerras * some code path might still want to branch into the original 250b01c8b54SPaul Mackerras * vector 251b01c8b54SPaul Mackerras */ 2521707dd16SPaul Mackerras SET_SCRATCH0(r13) /* save r13 */ 2531707dd16SPaul Mackerras EXCEPTION_PROLOG_0(PACA_EXMC) 2541e9b4507SMahesh SalgaonkarBEGIN_FTR_SECTION 255db7d31acSMahesh Salgaonkar b machine_check_common_early 2561e9b4507SMahesh SalgaonkarFTR_SECTION_ELSE 2571707dd16SPaul Mackerras b machine_check_pSeries_0 2581e9b4507SMahesh SalgaonkarALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 2591a6822d1SNicholas PigginEXC_REAL_END(machine_check, 0x200, 0x100) 2601a6822d1SNicholas PigginEXC_VIRT_NONE(0x4200, 0x100) 261db7d31acSMahesh SalgaonkarTRAMP_REAL_BEGIN(machine_check_common_early) 262afcf0095SNicholas Piggin EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) 263afcf0095SNicholas Piggin /* 264afcf0095SNicholas Piggin * Register contents: 265afcf0095SNicholas Piggin * R13 = PACA 266afcf0095SNicholas Piggin * R9 = CR 267afcf0095SNicholas Piggin * Original R9 to R13 is saved on PACA_EXMC 268afcf0095SNicholas Piggin * 269afcf0095SNicholas Piggin * Switch to mc_emergency stack and handle re-entrancy (we limit 270afcf0095SNicholas Piggin * the nested MCE upto level 4 to avoid stack overflow). 271afcf0095SNicholas Piggin * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 272afcf0095SNicholas Piggin * 273afcf0095SNicholas Piggin * We use paca->in_mce to check whether this is the first entry or 274afcf0095SNicholas Piggin * nested machine check. We increment paca->in_mce to track nested 275afcf0095SNicholas Piggin * machine checks. 276afcf0095SNicholas Piggin * 277afcf0095SNicholas Piggin * If this is the first entry then set stack pointer to 278afcf0095SNicholas Piggin * paca->mc_emergency_sp, otherwise r1 is already pointing to 279afcf0095SNicholas Piggin * stack frame on mc_emergency stack. 280afcf0095SNicholas Piggin * 281afcf0095SNicholas Piggin * NOTE: We are here with MSR_ME=0 (off), which means we risk a 282afcf0095SNicholas Piggin * checkstop if we get another machine check exception before we do 283afcf0095SNicholas Piggin * rfid with MSR_ME=1. 2841945bc45SNicholas Piggin * 2851945bc45SNicholas Piggin * This interrupt can wake directly from idle. If that is the case, 2861945bc45SNicholas Piggin * the machine check is handled then the idle wakeup code is called 2872bf1071aSNicholas Piggin * to restore state. 288afcf0095SNicholas Piggin */ 289afcf0095SNicholas Piggin mr r11,r1 /* Save r1 */ 290afcf0095SNicholas Piggin lhz r10,PACA_IN_MCE(r13) 291afcf0095SNicholas Piggin cmpwi r10,0 /* Are we in nested machine check */ 292afcf0095SNicholas Piggin bne 0f /* Yes, we are. */ 293afcf0095SNicholas Piggin /* First machine check entry */ 294afcf0095SNicholas Piggin ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 295afcf0095SNicholas Piggin0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 296afcf0095SNicholas Piggin addi r10,r10,1 /* increment paca->in_mce */ 297afcf0095SNicholas Piggin sth r10,PACA_IN_MCE(r13) 298afcf0095SNicholas Piggin /* Limit nested MCE to level 4 to avoid stack overflow */ 299ba41e1e1SBalbir Singh cmpwi r10,MAX_MCE_DEPTH 300afcf0095SNicholas Piggin bgt 2f /* Check if we hit limit of 4 */ 301afcf0095SNicholas Piggin std r11,GPR1(r1) /* Save r1 on the stack. */ 302afcf0095SNicholas Piggin std r11,0(r1) /* make stack chain pointer */ 303afcf0095SNicholas Piggin mfspr r11,SPRN_SRR0 /* Save SRR0 */ 304afcf0095SNicholas Piggin std r11,_NIP(r1) 305afcf0095SNicholas Piggin mfspr r11,SPRN_SRR1 /* Save SRR1 */ 306afcf0095SNicholas Piggin std r11,_MSR(r1) 307afcf0095SNicholas Piggin mfspr r11,SPRN_DAR /* Save DAR */ 308afcf0095SNicholas Piggin std r11,_DAR(r1) 309afcf0095SNicholas Piggin mfspr r11,SPRN_DSISR /* Save DSISR */ 310afcf0095SNicholas Piggin std r11,_DSISR(r1) 311afcf0095SNicholas Piggin std r9,_CCR(r1) /* Save CR in stackframe */ 312afcf0095SNicholas Piggin /* Save r9 through r13 from EXMC save area to stack frame. */ 313afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 314afcf0095SNicholas Piggin mfmsr r11 /* get MSR value */ 315db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 316afcf0095SNicholas Piggin ori r11,r11,MSR_ME /* turn on ME bit */ 317db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 318afcf0095SNicholas Piggin ori r11,r11,MSR_RI /* turn on RI bit */ 319afcf0095SNicholas Piggin LOAD_HANDLER(r12, machine_check_handle_early) 320afcf0095SNicholas Piggin1: mtspr SPRN_SRR0,r12 321afcf0095SNicholas Piggin mtspr SPRN_SRR1,r11 322222f20f1SNicholas Piggin RFI_TO_KERNEL 323afcf0095SNicholas Piggin b . /* prevent speculative execution */ 324afcf0095SNicholas Piggin2: 325afcf0095SNicholas Piggin /* Stack overflow. Stay on emergency stack and panic. 326afcf0095SNicholas Piggin * Keep the ME bit off while panic-ing, so that if we hit 327afcf0095SNicholas Piggin * another machine check we checkstop. 328afcf0095SNicholas Piggin */ 329afcf0095SNicholas Piggin addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 330afcf0095SNicholas Piggin ld r11,PACAKMSR(r13) 331afcf0095SNicholas Piggin LOAD_HANDLER(r12, unrecover_mce) 332afcf0095SNicholas Piggin li r10,MSR_ME 333afcf0095SNicholas Piggin andc r11,r11,r10 /* Turn off MSR_ME */ 334afcf0095SNicholas Piggin b 1b 335afcf0095SNicholas Piggin b . /* prevent speculative execution */ 336afcf0095SNicholas Piggin 337afcf0095SNicholas PigginTRAMP_REAL_BEGIN(machine_check_pSeries) 338afcf0095SNicholas Piggin .globl machine_check_fwnmi 339afcf0095SNicholas Pigginmachine_check_fwnmi: 340afcf0095SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 341afcf0095SNicholas Piggin EXCEPTION_PROLOG_0(PACA_EXMC) 342a43c1590SMahesh SalgaonkarBEGIN_FTR_SECTION 343db7d31acSMahesh Salgaonkar b machine_check_common_early 344a43c1590SMahesh SalgaonkarEND_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 345afcf0095SNicholas Pigginmachine_check_pSeries_0: 346afcf0095SNicholas Piggin EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) 347afcf0095SNicholas Piggin /* 34883a980f7SNicholas Piggin * MSR_RI is not enabled, because PACA_EXMC is being used, so a 34983a980f7SNicholas Piggin * nested machine check corrupts it. machine_check_common enables 35083a980f7SNicholas Piggin * MSR_RI. 351afcf0095SNicholas Piggin */ 35294f3cc8eSMichael Ellerman EXCEPTION_PROLOG_2_NORI(machine_check_common, EXC_STD) 353afcf0095SNicholas Piggin 354afcf0095SNicholas PigginTRAMP_KVM_SKIP(PACA_EXMC, 0x200) 355afcf0095SNicholas Piggin 356afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_common) 357afcf0095SNicholas Piggin /* 358afcf0095SNicholas Piggin * Machine check is different because we use a different 359afcf0095SNicholas Piggin * save area: PACA_EXMC instead of PACA_EXGEN. 360afcf0095SNicholas Piggin */ 361afcf0095SNicholas Piggin mfspr r10,SPRN_DAR 362afcf0095SNicholas Piggin std r10,PACA_EXMC+EX_DAR(r13) 363afcf0095SNicholas Piggin mfspr r10,SPRN_DSISR 364afcf0095SNicholas Piggin stw r10,PACA_EXMC+EX_DSISR(r13) 365afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 366afcf0095SNicholas Piggin FINISH_NAP 367afcf0095SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 368afcf0095SNicholas Piggin ld r3,PACA_EXMC+EX_DAR(r13) 369afcf0095SNicholas Piggin lwz r4,PACA_EXMC+EX_DSISR(r13) 370afcf0095SNicholas Piggin /* Enable MSR_RI when finished with PACA_EXMC */ 371afcf0095SNicholas Piggin li r10,MSR_RI 372afcf0095SNicholas Piggin mtmsrd r10,1 373afcf0095SNicholas Piggin std r3,_DAR(r1) 374afcf0095SNicholas Piggin std r4,_DSISR(r1) 375afcf0095SNicholas Piggin bl save_nvgprs 376afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 377afcf0095SNicholas Piggin bl machine_check_exception 378afcf0095SNicholas Piggin b ret_from_except 379afcf0095SNicholas Piggin 380afcf0095SNicholas Piggin#define MACHINE_CHECK_HANDLER_WINDUP \ 381afcf0095SNicholas Piggin /* Clear MSR_RI before setting SRR0 and SRR1. */\ 382afcf0095SNicholas Piggin li r0,MSR_RI; \ 383afcf0095SNicholas Piggin mfmsr r9; /* get MSR value */ \ 384afcf0095SNicholas Piggin andc r9,r9,r0; \ 385afcf0095SNicholas Piggin mtmsrd r9,1; /* Clear MSR_RI */ \ 386afcf0095SNicholas Piggin /* Move original SRR0 and SRR1 into the respective regs */ \ 387afcf0095SNicholas Piggin ld r9,_MSR(r1); \ 388afcf0095SNicholas Piggin mtspr SPRN_SRR1,r9; \ 389afcf0095SNicholas Piggin ld r3,_NIP(r1); \ 390afcf0095SNicholas Piggin mtspr SPRN_SRR0,r3; \ 391afcf0095SNicholas Piggin ld r9,_CTR(r1); \ 392afcf0095SNicholas Piggin mtctr r9; \ 393afcf0095SNicholas Piggin ld r9,_XER(r1); \ 394afcf0095SNicholas Piggin mtxer r9; \ 395afcf0095SNicholas Piggin ld r9,_LINK(r1); \ 396afcf0095SNicholas Piggin mtlr r9; \ 397afcf0095SNicholas Piggin REST_GPR(0, r1); \ 398afcf0095SNicholas Piggin REST_8GPRS(2, r1); \ 399afcf0095SNicholas Piggin REST_GPR(10, r1); \ 400afcf0095SNicholas Piggin ld r11,_CCR(r1); \ 401afcf0095SNicholas Piggin mtcr r11; \ 402afcf0095SNicholas Piggin /* Decrement paca->in_mce. */ \ 403afcf0095SNicholas Piggin lhz r12,PACA_IN_MCE(r13); \ 404afcf0095SNicholas Piggin subi r12,r12,1; \ 405afcf0095SNicholas Piggin sth r12,PACA_IN_MCE(r13); \ 406afcf0095SNicholas Piggin REST_GPR(11, r1); \ 407afcf0095SNicholas Piggin REST_2GPRS(12, r1); \ 408afcf0095SNicholas Piggin /* restore original r1. */ \ 409afcf0095SNicholas Piggin ld r1,GPR1(r1) 410afcf0095SNicholas Piggin 4111945bc45SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 4121945bc45SNicholas Piggin/* 4131945bc45SNicholas Piggin * This is an idle wakeup. Low level machine check has already been 4141945bc45SNicholas Piggin * done. Queue the event then call the idle code to do the wake up. 4151945bc45SNicholas Piggin */ 4161945bc45SNicholas PigginEXC_COMMON_BEGIN(machine_check_idle_common) 4171945bc45SNicholas Piggin bl machine_check_queue_event 4181945bc45SNicholas Piggin 4191945bc45SNicholas Piggin /* 4201945bc45SNicholas Piggin * We have not used any non-volatile GPRs here, and as a rule 4211945bc45SNicholas Piggin * most exception code including machine check does not. 4221945bc45SNicholas Piggin * Therefore PACA_NAPSTATELOST does not need to be set. Idle 4231945bc45SNicholas Piggin * wakeup will restore volatile registers. 4241945bc45SNicholas Piggin * 4251945bc45SNicholas Piggin * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. 4261945bc45SNicholas Piggin * 4271945bc45SNicholas Piggin * Then decrement MCE nesting after finishing with the stack. 4281945bc45SNicholas Piggin */ 4291945bc45SNicholas Piggin ld r3,_MSR(r1) 4301945bc45SNicholas Piggin 4311945bc45SNicholas Piggin lhz r11,PACA_IN_MCE(r13) 4321945bc45SNicholas Piggin subi r11,r11,1 4331945bc45SNicholas Piggin sth r11,PACA_IN_MCE(r13) 4341945bc45SNicholas Piggin 4351945bc45SNicholas Piggin /* Turn off the RI bit because SRR1 is used by idle wakeup code. */ 4361945bc45SNicholas Piggin /* Recoverability could be improved by reducing the use of SRR1. */ 4371945bc45SNicholas Piggin li r11,0 4381945bc45SNicholas Piggin mtmsrd r11,1 4391945bc45SNicholas Piggin 4401945bc45SNicholas Piggin b pnv_powersave_wakeup_mce 4411945bc45SNicholas Piggin#endif 442afcf0095SNicholas Piggin /* 443afcf0095SNicholas Piggin * Handle machine check early in real mode. We come here with 444afcf0095SNicholas Piggin * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 445afcf0095SNicholas Piggin */ 446afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_handle_early) 447afcf0095SNicholas Piggin std r0,GPR0(r1) /* Save r0 */ 448afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_3(0x200) 449afcf0095SNicholas Piggin bl save_nvgprs 450afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 451afcf0095SNicholas Piggin bl machine_check_early 452afcf0095SNicholas Piggin std r3,RESULT(r1) /* Save result */ 453afcf0095SNicholas Piggin ld r12,_MSR(r1) 454db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 455db7d31acSMahesh Salgaonkar b 4f 456db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 4571945bc45SNicholas Piggin 458afcf0095SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 459afcf0095SNicholas Piggin /* 460afcf0095SNicholas Piggin * Check if thread was in power saving mode. We come here when any 461afcf0095SNicholas Piggin * of the following is true: 462afcf0095SNicholas Piggin * a. thread wasn't in power saving mode 463afcf0095SNicholas Piggin * b. thread was in power saving mode with no state loss, 464afcf0095SNicholas Piggin * supervisor state loss or hypervisor state loss. 465afcf0095SNicholas Piggin * 466afcf0095SNicholas Piggin * Go back to nap/sleep/winkle mode again if (b) is true. 467afcf0095SNicholas Piggin */ 4681945bc45SNicholas Piggin BEGIN_FTR_SECTION 4691945bc45SNicholas Piggin rlwinm. r11,r12,47-31,30,31 4706102c005SNicholas Piggin bne machine_check_idle_common 4711945bc45SNicholas Piggin END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 472afcf0095SNicholas Piggin#endif 4731945bc45SNicholas Piggin 474afcf0095SNicholas Piggin /* 475afcf0095SNicholas Piggin * Check if we are coming from hypervisor userspace. If yes then we 476afcf0095SNicholas Piggin * continue in host kernel in V mode to deliver the MC event. 477afcf0095SNicholas Piggin */ 478afcf0095SNicholas Piggin rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 479afcf0095SNicholas Piggin beq 5f 480db7d31acSMahesh Salgaonkar4: andi. r11,r12,MSR_PR /* See if coming from user. */ 481afcf0095SNicholas Piggin bne 9f /* continue in V mode if we are. */ 482afcf0095SNicholas Piggin 483afcf0095SNicholas Piggin5: 484afcf0095SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 485db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 486afcf0095SNicholas Piggin /* 487afcf0095SNicholas Piggin * We are coming from kernel context. Check if we are coming from 488afcf0095SNicholas Piggin * guest. if yes, then we can continue. We will fall through 489afcf0095SNicholas Piggin * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 490afcf0095SNicholas Piggin */ 491afcf0095SNicholas Piggin lbz r11,HSTATE_IN_GUEST(r13) 492afcf0095SNicholas Piggin cmpwi r11,0 /* Check if coming from guest */ 493afcf0095SNicholas Piggin bne 9f /* continue if we are. */ 494db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 495afcf0095SNicholas Piggin#endif 496afcf0095SNicholas Piggin /* 497afcf0095SNicholas Piggin * At this point we are not sure about what context we come from. 498afcf0095SNicholas Piggin * Queue up the MCE event and return from the interrupt. 499afcf0095SNicholas Piggin * But before that, check if this is an un-recoverable exception. 500afcf0095SNicholas Piggin * If yes, then stay on emergency stack and panic. 501afcf0095SNicholas Piggin */ 502afcf0095SNicholas Piggin andi. r11,r12,MSR_RI 503afcf0095SNicholas Piggin bne 2f 504afcf0095SNicholas Piggin1: mfspr r11,SPRN_SRR0 505afcf0095SNicholas Piggin LOAD_HANDLER(r10,unrecover_mce) 506afcf0095SNicholas Piggin mtspr SPRN_SRR0,r10 507afcf0095SNicholas Piggin ld r10,PACAKMSR(r13) 508afcf0095SNicholas Piggin /* 509afcf0095SNicholas Piggin * We are going down. But there are chances that we might get hit by 510afcf0095SNicholas Piggin * another MCE during panic path and we may run into unstable state 511afcf0095SNicholas Piggin * with no way out. Hence, turn ME bit off while going down, so that 512afcf0095SNicholas Piggin * when another MCE is hit during panic path, system will checkstop 513afcf0095SNicholas Piggin * and hypervisor will get restarted cleanly by SP. 514afcf0095SNicholas Piggin */ 515afcf0095SNicholas Piggin li r3,MSR_ME 516afcf0095SNicholas Piggin andc r10,r10,r3 /* Turn off MSR_ME */ 517afcf0095SNicholas Piggin mtspr SPRN_SRR1,r10 518222f20f1SNicholas Piggin RFI_TO_KERNEL 519afcf0095SNicholas Piggin b . 520afcf0095SNicholas Piggin2: 521afcf0095SNicholas Piggin /* 522afcf0095SNicholas Piggin * Check if we have successfully handled/recovered from error, if not 523afcf0095SNicholas Piggin * then stay on emergency stack and panic. 524afcf0095SNicholas Piggin */ 525afcf0095SNicholas Piggin ld r3,RESULT(r1) /* Load result */ 526afcf0095SNicholas Piggin cmpdi r3,0 /* see if we handled MCE successfully */ 527afcf0095SNicholas Piggin 528afcf0095SNicholas Piggin beq 1b /* if !handled then panic */ 529db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 530afcf0095SNicholas Piggin /* 531afcf0095SNicholas Piggin * Return from MC interrupt. 532afcf0095SNicholas Piggin * Queue up the MCE event so that we can log it later, while 533afcf0095SNicholas Piggin * returning from kernel or opal call. 534afcf0095SNicholas Piggin */ 535afcf0095SNicholas Piggin bl machine_check_queue_event 536afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 537222f20f1SNicholas Piggin RFI_TO_USER_OR_KERNEL 538db7d31acSMahesh SalgaonkarFTR_SECTION_ELSE 539db7d31acSMahesh Salgaonkar /* 540db7d31acSMahesh Salgaonkar * pSeries: Return from MC interrupt. Before that stay on emergency 541db7d31acSMahesh Salgaonkar * stack and call machine_check_exception to log the MCE event. 542db7d31acSMahesh Salgaonkar */ 543db7d31acSMahesh Salgaonkar LOAD_HANDLER(r10,mce_return) 544db7d31acSMahesh Salgaonkar mtspr SPRN_SRR0,r10 545db7d31acSMahesh Salgaonkar ld r10,PACAKMSR(r13) 546db7d31acSMahesh Salgaonkar mtspr SPRN_SRR1,r10 547db7d31acSMahesh Salgaonkar RFI_TO_KERNEL 548db7d31acSMahesh Salgaonkar b . 549db7d31acSMahesh SalgaonkarALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 550afcf0095SNicholas Piggin9: 551afcf0095SNicholas Piggin /* Deliver the machine check to host kernel in V mode. */ 552afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 553db7d31acSMahesh Salgaonkar SET_SCRATCH0(r13) /* save r13 */ 554db7d31acSMahesh Salgaonkar EXCEPTION_PROLOG_0(PACA_EXMC) 555db7d31acSMahesh Salgaonkar b machine_check_pSeries_0 556afcf0095SNicholas Piggin 557afcf0095SNicholas PigginEXC_COMMON_BEGIN(unrecover_mce) 558afcf0095SNicholas Piggin /* Invoke machine_check_exception to print MCE event and panic. */ 559afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 560afcf0095SNicholas Piggin bl machine_check_exception 561afcf0095SNicholas Piggin /* 562afcf0095SNicholas Piggin * We will not reach here. Even if we did, there is no way out. Call 563afcf0095SNicholas Piggin * unrecoverable_exception and die. 564afcf0095SNicholas Piggin */ 565afcf0095SNicholas Piggin1: addi r3,r1,STACK_FRAME_OVERHEAD 566afcf0095SNicholas Piggin bl unrecoverable_exception 567afcf0095SNicholas Piggin b 1b 568afcf0095SNicholas Piggin 569a43c1590SMahesh SalgaonkarEXC_COMMON_BEGIN(mce_return) 570a43c1590SMahesh Salgaonkar /* Invoke machine_check_exception to print MCE event and return. */ 571a43c1590SMahesh Salgaonkar addi r3,r1,STACK_FRAME_OVERHEAD 572a43c1590SMahesh Salgaonkar bl machine_check_exception 573db7d31acSMahesh Salgaonkar MACHINE_CHECK_HANDLER_WINDUP 574a43c1590SMahesh Salgaonkar RFI_TO_KERNEL 575a43c1590SMahesh Salgaonkar b . 5760ebc4cdaSBenjamin Herrenschmidt 5771a6822d1SNicholas PigginEXC_REAL(data_access, 0x300, 0x80) 5781a6822d1SNicholas PigginEXC_VIRT(data_access, 0x4300, 0x80, 0x300) 57980795e6cSNicholas PigginTRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 58080795e6cSNicholas Piggin 58180795e6cSNicholas PigginEXC_COMMON_BEGIN(data_access_common) 58280795e6cSNicholas Piggin /* 58380795e6cSNicholas Piggin * Here r13 points to the paca, r9 contains the saved CR, 58480795e6cSNicholas Piggin * SRR0 and SRR1 are saved in r11 and r12, 58580795e6cSNicholas Piggin * r9 - r13 are saved in paca->exgen. 58680795e6cSNicholas Piggin */ 58780795e6cSNicholas Piggin mfspr r10,SPRN_DAR 58880795e6cSNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 58980795e6cSNicholas Piggin mfspr r10,SPRN_DSISR 59080795e6cSNicholas Piggin stw r10,PACA_EXGEN+EX_DSISR(r13) 59180795e6cSNicholas Piggin EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 59280795e6cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 59380795e6cSNicholas Piggin ld r12,_MSR(r1) 59480795e6cSNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 59580795e6cSNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 59680795e6cSNicholas Piggin li r5,0x300 59780795e6cSNicholas Piggin std r3,_DAR(r1) 59880795e6cSNicholas Piggin std r4,_DSISR(r1) 59980795e6cSNicholas PigginBEGIN_MMU_FTR_SECTION 60080795e6cSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 60180795e6cSNicholas PigginMMU_FTR_SECTION_ELSE 60280795e6cSNicholas Piggin b handle_page_fault 60380795e6cSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 60480795e6cSNicholas Piggin 6050ebc4cdaSBenjamin Herrenschmidt 6061a6822d1SNicholas PigginEXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 60748e7b769SNicholas PigginEXCEPTION_PROLOG(PACA_EXSLB, data_access_slb_common, EXC_STD, KVMTEST_PR, 0x380); 6081a6822d1SNicholas PigginEXC_REAL_END(data_access_slb, 0x380, 0x80) 6090ebc4cdaSBenjamin Herrenschmidt 6101a6822d1SNicholas PigginEXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 61148e7b769SNicholas PigginEXCEPTION_RELON_PROLOG(PACA_EXSLB, data_access_slb_common, EXC_STD, NOTEST, 0x380); 6121a6822d1SNicholas PigginEXC_VIRT_END(data_access_slb, 0x4380, 0x80) 61348e7b769SNicholas Piggin 6142b9af6e4SNicholas PigginTRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 6152b9af6e4SNicholas Piggin 61648e7b769SNicholas PigginEXC_COMMON_BEGIN(data_access_slb_common) 61748e7b769SNicholas Piggin mfspr r10,SPRN_DAR 61848e7b769SNicholas Piggin std r10,PACA_EXSLB+EX_DAR(r13) 61948e7b769SNicholas Piggin EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) 62048e7b769SNicholas Piggin ld r4,PACA_EXSLB+EX_DAR(r13) 62148e7b769SNicholas Piggin std r4,_DAR(r1) 62248e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 62348e7b769SNicholas Piggin bl do_slb_fault 62448e7b769SNicholas Piggin cmpdi r3,0 62548e7b769SNicholas Piggin bne- 1f 62648e7b769SNicholas Piggin b fast_exception_return 62748e7b769SNicholas Piggin1: /* Error case */ 62848e7b769SNicholas Piggin std r3,RESULT(r1) 62948e7b769SNicholas Piggin bl save_nvgprs 63048e7b769SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 63148e7b769SNicholas Piggin ld r4,_DAR(r1) 63248e7b769SNicholas Piggin ld r5,RESULT(r1) 63348e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 63448e7b769SNicholas Piggin bl do_bad_slb_fault 63548e7b769SNicholas Piggin b ret_from_except 63648e7b769SNicholas Piggin 6372b9af6e4SNicholas Piggin 6381a6822d1SNicholas PigginEXC_REAL(instruction_access, 0x400, 0x80) 6391a6822d1SNicholas PigginEXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) 64027ce77dfSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x400) 64127ce77dfSNicholas Piggin 64227ce77dfSNicholas PigginEXC_COMMON_BEGIN(instruction_access_common) 64327ce77dfSNicholas Piggin EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 64427ce77dfSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 64527ce77dfSNicholas Piggin ld r12,_MSR(r1) 64627ce77dfSNicholas Piggin ld r3,_NIP(r1) 647475b581fSMichael Ellerman andis. r4,r12,DSISR_SRR1_MATCH_64S@h 64827ce77dfSNicholas Piggin li r5,0x400 64927ce77dfSNicholas Piggin std r3,_DAR(r1) 65027ce77dfSNicholas Piggin std r4,_DSISR(r1) 65127ce77dfSNicholas PigginBEGIN_MMU_FTR_SECTION 65227ce77dfSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 65327ce77dfSNicholas PigginMMU_FTR_SECTION_ELSE 65427ce77dfSNicholas Piggin b handle_page_fault 65527ce77dfSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 65627ce77dfSNicholas Piggin 6570ebc4cdaSBenjamin Herrenschmidt 6581a6822d1SNicholas PigginEXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) 65948e7b769SNicholas PigginEXCEPTION_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, KVMTEST_PR, 0x480); 6601a6822d1SNicholas PigginEXC_REAL_END(instruction_access_slb, 0x480, 0x80) 6610ebc4cdaSBenjamin Herrenschmidt 6621a6822d1SNicholas PigginEXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) 66348e7b769SNicholas PigginEXCEPTION_RELON_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, NOTEST, 0x480); 6641a6822d1SNicholas PigginEXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) 66548e7b769SNicholas Piggin 6668d04631aSNicholas PigginTRAMP_KVM(PACA_EXSLB, 0x480) 6678d04631aSNicholas Piggin 66848e7b769SNicholas PigginEXC_COMMON_BEGIN(instruction_access_slb_common) 66948e7b769SNicholas Piggin EXCEPTION_PROLOG_COMMON(0x480, PACA_EXSLB) 67048e7b769SNicholas Piggin ld r4,_NIP(r1) 67154be0b9cSMichael Ellerman addi r3,r1,STACK_FRAME_OVERHEAD 67248e7b769SNicholas Piggin bl do_slb_fault 67348e7b769SNicholas Piggin cmpdi r3,0 67448e7b769SNicholas Piggin bne- 1f 67548e7b769SNicholas Piggin b fast_exception_return 67648e7b769SNicholas Piggin1: /* Error case */ 67748e7b769SNicholas Piggin std r3,RESULT(r1) 67848e7b769SNicholas Piggin bl save_nvgprs 67948e7b769SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 68048e7b769SNicholas Piggin ld r4,_NIP(r1) 68148e7b769SNicholas Piggin ld r5,RESULT(r1) 68248e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 68348e7b769SNicholas Piggin bl do_bad_slb_fault 68454be0b9cSMichael Ellerman b ret_from_except 6855e46e29eSNicholas Piggin 68648e7b769SNicholas Piggin 6871a6822d1SNicholas PigginEXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 688b3e6b5dfSBenjamin Herrenschmidt .globl hardware_interrupt_hv; 689b3e6b5dfSBenjamin Herrenschmidthardware_interrupt_hv: 690a5d4f3adSBenjamin Herrenschmidt BEGIN_FTR_SECTION 6910b924de4SMichael Ellerman MASKABLE_EXCEPTION_HV(0x500, hardware_interrupt_common, IRQS_DISABLED) 692de56a948SPaul Mackerras FTR_SECTION_ELSE 6930b924de4SMichael Ellerman MASKABLE_EXCEPTION(0x500, hardware_interrupt_common, IRQS_DISABLED) 694969391c5SPaul Mackerras ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 6951a6822d1SNicholas PigginEXC_REAL_END(hardware_interrupt, 0x500, 0x100) 696a5d4f3adSBenjamin Herrenschmidt 6971a6822d1SNicholas PigginEXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 698c138e588SNicholas Piggin .globl hardware_interrupt_relon_hv; 699c138e588SNicholas Pigginhardware_interrupt_relon_hv: 700c138e588SNicholas Piggin BEGIN_FTR_SECTION 7010b924de4SMichael Ellerman MASKABLE_RELON_EXCEPTION_HV(0x500, hardware_interrupt_common, 702f14e953bSMadhavan Srinivasan IRQS_DISABLED) 703c138e588SNicholas Piggin FTR_SECTION_ELSE 7040a55c241SMichael Ellerman __MASKABLE_RELON_EXCEPTION(0x500, hardware_interrupt_common, 7050b924de4SMichael Ellerman EXC_STD, SOFTEN_TEST_PR, IRQS_DISABLED) 706c138e588SNicholas Piggin ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 7071a6822d1SNicholas PigginEXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 708c138e588SNicholas Piggin 7097ede5317SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x500) 7107ede5317SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0x500) 711c138e588SNicholas PigginEXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 712c138e588SNicholas Piggin 713c138e588SNicholas Piggin 7141a6822d1SNicholas PigginEXC_REAL(alignment, 0x600, 0x100) 7151a6822d1SNicholas PigginEXC_VIRT(alignment, 0x4600, 0x100, 0x600) 716da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x600) 717f9aa6714SNicholas PigginEXC_COMMON_BEGIN(alignment_common) 718f9aa6714SNicholas Piggin mfspr r10,SPRN_DAR 719f9aa6714SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 720f9aa6714SNicholas Piggin mfspr r10,SPRN_DSISR 721f9aa6714SNicholas Piggin stw r10,PACA_EXGEN+EX_DSISR(r13) 722f9aa6714SNicholas Piggin EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 723f9aa6714SNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 724f9aa6714SNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 725f9aa6714SNicholas Piggin std r3,_DAR(r1) 726f9aa6714SNicholas Piggin std r4,_DSISR(r1) 727f9aa6714SNicholas Piggin bl save_nvgprs 728f9aa6714SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 729f9aa6714SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 730f9aa6714SNicholas Piggin bl alignment_exception 731f9aa6714SNicholas Piggin b ret_from_except 732f9aa6714SNicholas Piggin 733b01c8b54SPaul Mackerras 7341a6822d1SNicholas PigginEXC_REAL(program_check, 0x700, 0x100) 7351a6822d1SNicholas PigginEXC_VIRT(program_check, 0x4700, 0x100, 0x700) 736da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x700) 73711e87346SNicholas PigginEXC_COMMON_BEGIN(program_check_common) 738265e60a1SCyril Bur /* 739265e60a1SCyril Bur * It's possible to receive a TM Bad Thing type program check with 740265e60a1SCyril Bur * userspace register values (in particular r1), but with SRR1 reporting 741265e60a1SCyril Bur * that we came from the kernel. Normally that would confuse the bad 742265e60a1SCyril Bur * stack logic, and we would report a bad kernel stack pointer. Instead 743265e60a1SCyril Bur * we switch to the emergency stack if we're taking a TM Bad Thing from 744265e60a1SCyril Bur * the kernel. 745265e60a1SCyril Bur */ 746265e60a1SCyril Bur li r10,MSR_PR /* Build a mask of MSR_PR .. */ 747265e60a1SCyril Bur oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ 748265e60a1SCyril Bur and r10,r10,r12 /* Mask SRR1 with that. */ 749265e60a1SCyril Bur srdi r10,r10,8 /* Shift it so we can compare */ 750265e60a1SCyril Bur cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ 751265e60a1SCyril Bur bne 1f /* If != go to normal path. */ 752265e60a1SCyril Bur 753265e60a1SCyril Bur /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ 754265e60a1SCyril Bur andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ 755265e60a1SCyril Bur /* 3 in EXCEPTION_PROLOG_COMMON */ 756265e60a1SCyril Bur mr r10,r1 /* Save r1 */ 757265e60a1SCyril Bur ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 758265e60a1SCyril Bur subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 759265e60a1SCyril Bur b 3f /* Jump into the macro !! */ 760265e60a1SCyril Bur1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 76111e87346SNicholas Piggin bl save_nvgprs 76211e87346SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 76311e87346SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 76411e87346SNicholas Piggin bl program_check_exception 76511e87346SNicholas Piggin b ret_from_except 76611e87346SNicholas Piggin 767a485c709SPaul Mackerras 7681a6822d1SNicholas PigginEXC_REAL(fp_unavailable, 0x800, 0x100) 7691a6822d1SNicholas PigginEXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) 770da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x800) 771c78d9b97SNicholas PigginEXC_COMMON_BEGIN(fp_unavailable_common) 772c78d9b97SNicholas Piggin EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 773c78d9b97SNicholas Piggin bne 1f /* if from user, just load it up */ 774c78d9b97SNicholas Piggin bl save_nvgprs 775c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 776c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 777c78d9b97SNicholas Piggin bl kernel_fp_unavailable_exception 778c78d9b97SNicholas Piggin BUG_OPCODE 779c78d9b97SNicholas Piggin1: 780c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 781c78d9b97SNicholas PigginBEGIN_FTR_SECTION 782c78d9b97SNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 783c78d9b97SNicholas Piggin * transaction), go do TM stuff 784c78d9b97SNicholas Piggin */ 785c78d9b97SNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 786c78d9b97SNicholas Piggin bne- 2f 787c78d9b97SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_TM) 788c78d9b97SNicholas Piggin#endif 789c78d9b97SNicholas Piggin bl load_up_fpu 790c78d9b97SNicholas Piggin b fast_exception_return 791c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 792c78d9b97SNicholas Piggin2: /* User process was in a transaction */ 793c78d9b97SNicholas Piggin bl save_nvgprs 794c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 795c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 796c78d9b97SNicholas Piggin bl fp_unavailable_tm 797c78d9b97SNicholas Piggin b ret_from_except 798c78d9b97SNicholas Piggin#endif 799c78d9b97SNicholas Piggin 800b01c8b54SPaul Mackerras 801a048a07dSNicholas PigginEXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) 802f14e953bSMadhavan SrinivasanEXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) 80339c0da57SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x900) 80439c0da57SNicholas PigginEXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 80539c0da57SNicholas Piggin 8060ebc4cdaSBenjamin Herrenschmidt 8071a6822d1SNicholas PigginEXC_REAL_HV(hdecrementer, 0x980, 0x80) 8081a6822d1SNicholas PigginEXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) 809facc6d74SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0x980) 810facc6d74SNicholas PigginEXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 811facc6d74SNicholas Piggin 812da2bc464SMichael Ellerman 813f14e953bSMadhavan SrinivasanEXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) 814f14e953bSMadhavan SrinivasanEXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) 815da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xa00) 816ca243163SNicholas Piggin#ifdef CONFIG_PPC_DOORBELL 817ca243163SNicholas PigginEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 818ca243163SNicholas Piggin#else 819ca243163SNicholas PigginEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 820ca243163SNicholas Piggin#endif 821ca243163SNicholas Piggin 822da2bc464SMichael Ellerman 8231a6822d1SNicholas PigginEXC_REAL(trap_0b, 0xb00, 0x100) 8241a6822d1SNicholas PigginEXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) 825da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xb00) 826341215dcSNicholas PigginEXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 827341215dcSNicholas Piggin 828acd7d8ceSNicholas Piggin/* 829acd7d8ceSNicholas Piggin * system call / hypercall (0xc00, 0x4c00) 830acd7d8ceSNicholas Piggin * 831acd7d8ceSNicholas Piggin * The system call exception is invoked with "sc 0" and does not alter HV bit. 832acd7d8ceSNicholas Piggin * There is support for kernel code to invoke system calls but there are no 833acd7d8ceSNicholas Piggin * in-tree users. 834acd7d8ceSNicholas Piggin * 835acd7d8ceSNicholas Piggin * The hypercall is invoked with "sc 1" and sets HV=1. 836acd7d8ceSNicholas Piggin * 837acd7d8ceSNicholas Piggin * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 838acd7d8ceSNicholas Piggin * 0x4c00 virtual mode. 839acd7d8ceSNicholas Piggin * 840acd7d8ceSNicholas Piggin * Call convention: 841acd7d8ceSNicholas Piggin * 842acd7d8ceSNicholas Piggin * syscall register convention is in Documentation/powerpc/syscall64-abi.txt 843acd7d8ceSNicholas Piggin * 844acd7d8ceSNicholas Piggin * For hypercalls, the register convention is as follows: 845acd7d8ceSNicholas Piggin * r0 volatile 846acd7d8ceSNicholas Piggin * r1-2 nonvolatile 847acd7d8ceSNicholas Piggin * r3 volatile parameter and return value for status 848acd7d8ceSNicholas Piggin * r4-r10 volatile input and output value 849acd7d8ceSNicholas Piggin * r11 volatile hypercall number and output value 85076fc0cfcSNicholas Piggin * r12 volatile input and output value 851acd7d8ceSNicholas Piggin * r13-r31 nonvolatile 852acd7d8ceSNicholas Piggin * LR nonvolatile 853acd7d8ceSNicholas Piggin * CTR volatile 854acd7d8ceSNicholas Piggin * XER volatile 855acd7d8ceSNicholas Piggin * CR0-1 CR5-7 volatile 856acd7d8ceSNicholas Piggin * CR2-4 nonvolatile 857acd7d8ceSNicholas Piggin * Other registers nonvolatile 858acd7d8ceSNicholas Piggin * 859acd7d8ceSNicholas Piggin * The intersection of volatile registers that don't contain possible 86076fc0cfcSNicholas Piggin * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 86176fc0cfcSNicholas Piggin * without saving, though xer is not a good idea to use, as hardware may 86276fc0cfcSNicholas Piggin * interpret some bits so it may be costly to change them. 863acd7d8ceSNicholas Piggin */ 864bc355125SPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 865bc355125SPaul Mackerras /* 866acd7d8ceSNicholas Piggin * There is a little bit of juggling to get syscall and hcall 86776fc0cfcSNicholas Piggin * working well. Save r13 in ctr to avoid using SPRG scratch 86876fc0cfcSNicholas Piggin * register. 869acd7d8ceSNicholas Piggin * 870acd7d8ceSNicholas Piggin * Userspace syscalls have already saved the PPR, hcalls must save 871acd7d8ceSNicholas Piggin * it before setting HMT_MEDIUM. 872bc355125SPaul Mackerras */ 873bc355125SPaul Mackerras#define SYSCALL_KVMTEST \ 87476fc0cfcSNicholas Piggin mtctr r13; \ 875bc355125SPaul Mackerras GET_PACA(r13); \ 87676fc0cfcSNicholas Piggin std r10,PACA_EXGEN+EX_R10(r13); \ 877a048a07dSNicholas Piggin INTERRUPT_TO_KERNEL; \ 878acd7d8ceSNicholas Piggin KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \ 879bc355125SPaul Mackerras HMT_MEDIUM; \ 88076fc0cfcSNicholas Piggin mfctr r9; 881bc355125SPaul Mackerras 882bc355125SPaul Mackerras#else 883bc355125SPaul Mackerras#define SYSCALL_KVMTEST \ 884acd7d8ceSNicholas Piggin HMT_MEDIUM; \ 885acd7d8ceSNicholas Piggin mr r9,r13; \ 886a048a07dSNicholas Piggin GET_PACA(r13); \ 887a048a07dSNicholas Piggin INTERRUPT_TO_KERNEL; 888bc355125SPaul Mackerras#endif 889bc355125SPaul Mackerras 890d807ad37SNicholas Piggin#define LOAD_SYSCALL_HANDLER(reg) \ 891fb479e44SNicholas Piggin __LOAD_HANDLER(reg, system_call_common) 892d807ad37SNicholas Piggin 893acd7d8ceSNicholas Piggin/* 894acd7d8ceSNicholas Piggin * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9, 895acd7d8ceSNicholas Piggin * and HMT_MEDIUM. 896acd7d8ceSNicholas Piggin */ 897acd7d8ceSNicholas Piggin#define SYSCALL_REAL \ 898acd7d8ceSNicholas Piggin mfspr r11,SPRN_SRR0 ; \ 899d807ad37SNicholas Piggin mfspr r12,SPRN_SRR1 ; \ 900d807ad37SNicholas Piggin LOAD_SYSCALL_HANDLER(r10) ; \ 901d807ad37SNicholas Piggin mtspr SPRN_SRR0,r10 ; \ 902d807ad37SNicholas Piggin ld r10,PACAKMSR(r13) ; \ 903d807ad37SNicholas Piggin mtspr SPRN_SRR1,r10 ; \ 904222f20f1SNicholas Piggin RFI_TO_KERNEL ; \ 905d807ad37SNicholas Piggin b . ; /* prevent speculative execution */ 906d807ad37SNicholas Piggin 907727f1361SMichael Ellerman#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 9085c2511bfSMichael Ellerman#define SYSCALL_FASTENDIAN_TEST \ 9095c2511bfSMichael EllermanBEGIN_FTR_SECTION \ 9105c2511bfSMichael Ellerman cmpdi r0,0x1ebe ; \ 9115c2511bfSMichael Ellerman beq- 1f ; \ 9125c2511bfSMichael EllermanEND_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 9135c2511bfSMichael Ellerman 914acd7d8ceSNicholas Piggin#define SYSCALL_FASTENDIAN \ 915d807ad37SNicholas Piggin /* Fast LE/BE switch system call */ \ 916d807ad37SNicholas Piggin1: mfspr r12,SPRN_SRR1 ; \ 917d807ad37SNicholas Piggin xori r12,r12,MSR_LE ; \ 918d807ad37SNicholas Piggin mtspr SPRN_SRR1,r12 ; \ 919acd7d8ceSNicholas Piggin mr r13,r9 ; \ 920222f20f1SNicholas Piggin RFI_TO_USER ; /* return to userspace */ \ 921d807ad37SNicholas Piggin b . ; /* prevent speculative execution */ 922727f1361SMichael Ellerman#else 923727f1361SMichael Ellerman#define SYSCALL_FASTENDIAN_TEST 924727f1361SMichael Ellerman#define SYSCALL_FASTENDIAN 925727f1361SMichael Ellerman#endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */ 926d807ad37SNicholas Piggin 927d807ad37SNicholas Piggin#if defined(CONFIG_RELOCATABLE) 928d807ad37SNicholas Piggin /* 929d807ad37SNicholas Piggin * We can't branch directly so we do it via the CTR which 930d807ad37SNicholas Piggin * is volatile across system calls. 931d807ad37SNicholas Piggin */ 932acd7d8ceSNicholas Piggin#define SYSCALL_VIRT \ 933acd7d8ceSNicholas Piggin LOAD_SYSCALL_HANDLER(r10) ; \ 934acd7d8ceSNicholas Piggin mtctr r10 ; \ 935acd7d8ceSNicholas Piggin mfspr r11,SPRN_SRR0 ; \ 936d807ad37SNicholas Piggin mfspr r12,SPRN_SRR1 ; \ 937d807ad37SNicholas Piggin li r10,MSR_RI ; \ 938d807ad37SNicholas Piggin mtmsrd r10,1 ; \ 939d807ad37SNicholas Piggin bctr ; 940d807ad37SNicholas Piggin#else 941d807ad37SNicholas Piggin /* We can branch directly */ 942acd7d8ceSNicholas Piggin#define SYSCALL_VIRT \ 943acd7d8ceSNicholas Piggin mfspr r11,SPRN_SRR0 ; \ 944d807ad37SNicholas Piggin mfspr r12,SPRN_SRR1 ; \ 945d807ad37SNicholas Piggin li r10,MSR_RI ; \ 946d807ad37SNicholas Piggin mtmsrd r10,1 ; /* Set RI (EE=0) */ \ 947d807ad37SNicholas Piggin b system_call_common ; 948d807ad37SNicholas Piggin#endif 949d807ad37SNicholas Piggin 9501a6822d1SNicholas PigginEXC_REAL_BEGIN(system_call, 0xc00, 0x100) 951acd7d8ceSNicholas Piggin SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 952acd7d8ceSNicholas Piggin SYSCALL_FASTENDIAN_TEST 953acd7d8ceSNicholas Piggin SYSCALL_REAL 954acd7d8ceSNicholas Piggin SYSCALL_FASTENDIAN 9551a6822d1SNicholas PigginEXC_REAL_END(system_call, 0xc00, 0x100) 956b01c8b54SPaul Mackerras 9571a6822d1SNicholas PigginEXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 958acd7d8ceSNicholas Piggin SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ 959acd7d8ceSNicholas Piggin SYSCALL_FASTENDIAN_TEST 960acd7d8ceSNicholas Piggin SYSCALL_VIRT 961acd7d8ceSNicholas Piggin SYSCALL_FASTENDIAN 9621a6822d1SNicholas PigginEXC_VIRT_END(system_call, 0x4c00, 0x100) 963d807ad37SNicholas Piggin 964acd7d8ceSNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 965acd7d8ceSNicholas Piggin /* 966acd7d8ceSNicholas Piggin * This is a hcall, so register convention is as above, with these 967acd7d8ceSNicholas Piggin * differences: 968acd7d8ceSNicholas Piggin * r13 = PACA 96976fc0cfcSNicholas Piggin * ctr = orig r13 97076fc0cfcSNicholas Piggin * orig r10 saved in PACA 971acd7d8ceSNicholas Piggin */ 972acd7d8ceSNicholas PigginTRAMP_KVM_BEGIN(do_kvm_0xc00) 973acd7d8ceSNicholas Piggin /* 974acd7d8ceSNicholas Piggin * Save the PPR (on systems that support it) before changing to 975acd7d8ceSNicholas Piggin * HMT_MEDIUM. That allows the KVM code to save that value into the 976acd7d8ceSNicholas Piggin * guest state (it is the guest's PPR value). 977acd7d8ceSNicholas Piggin */ 97876fc0cfcSNicholas Piggin OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) 979acd7d8ceSNicholas Piggin HMT_MEDIUM 98076fc0cfcSNicholas Piggin OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) 981acd7d8ceSNicholas Piggin mfctr r10 98276fc0cfcSNicholas Piggin SET_SCRATCH0(r10) 983acd7d8ceSNicholas Piggin std r9,PACA_EXGEN+EX_R9(r13) 984acd7d8ceSNicholas Piggin mfcr r9 985acd7d8ceSNicholas Piggin KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) 986acd7d8ceSNicholas Piggin#endif 987da2bc464SMichael Ellerman 988d807ad37SNicholas Piggin 9891a6822d1SNicholas PigginEXC_REAL(single_step, 0xd00, 0x100) 9901a6822d1SNicholas PigginEXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) 991da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xd00) 992bc6675c6SNicholas PigginEXC_COMMON(single_step_common, 0xd00, single_step_exception) 993da2bc464SMichael Ellerman 9941a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) 995da0e7e62SMichael EllermanEXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) 996f5c32c1dSNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 997f5c32c1dSNicholas PigginEXC_COMMON_BEGIN(h_data_storage_common) 998f5c32c1dSNicholas Piggin mfspr r10,SPRN_HDAR 999f5c32c1dSNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 1000f5c32c1dSNicholas Piggin mfspr r10,SPRN_HDSISR 1001f5c32c1dSNicholas Piggin stw r10,PACA_EXGEN+EX_DSISR(r13) 1002f5c32c1dSNicholas Piggin EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) 1003f5c32c1dSNicholas Piggin bl save_nvgprs 1004f5c32c1dSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1005f5c32c1dSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1006d7b45615SSuraj Jitindar SinghBEGIN_MMU_FTR_SECTION 1007d7b45615SSuraj Jitindar Singh ld r4,PACA_EXGEN+EX_DAR(r13) 1008d7b45615SSuraj Jitindar Singh lwz r5,PACA_EXGEN+EX_DSISR(r13) 1009d7b45615SSuraj Jitindar Singh std r4,_DAR(r1) 1010d7b45615SSuraj Jitindar Singh std r5,_DSISR(r1) 1011d7b45615SSuraj Jitindar Singh li r5,SIGSEGV 1012d7b45615SSuraj Jitindar Singh bl bad_page_fault 1013d7b45615SSuraj Jitindar SinghMMU_FTR_SECTION_ELSE 1014f5c32c1dSNicholas Piggin bl unknown_exception 1015d7b45615SSuraj Jitindar SinghALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) 1016f5c32c1dSNicholas Piggin b ret_from_except 1017f5c32c1dSNicholas Piggin 10181707dd16SPaul Mackerras 10191a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) 1020da0e7e62SMichael EllermanEXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) 102182517cabSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe20) 102282517cabSNicholas PigginEXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 102382517cabSNicholas Piggin 10241707dd16SPaul Mackerras 10251a6822d1SNicholas PigginEXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) 10261a6822d1SNicholas PigginEXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) 1027031b4026SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe40) 1028031b4026SNicholas PigginEXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 1029031b4026SNicholas Piggin 10301707dd16SPaul Mackerras 1031e0319829SNicholas Piggin/* 1032e0319829SNicholas Piggin * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 1033e0319829SNicholas Piggin * first, and then eventaully from there to the trampoline to get into virtual 1034e0319829SNicholas Piggin * mode. 1035e0319829SNicholas Piggin */ 10361a6822d1SNicholas Piggin__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) 1037f14e953bSMadhavan Srinivasan__TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED) 10381a6822d1SNicholas PigginEXC_VIRT_NONE(0x4e60, 0x20) 103962f9b03bSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe60) 104062f9b03bSNicholas PigginTRAMP_REAL_BEGIN(hmi_exception_early) 104162f9b03bSNicholas Piggin EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) 104262f9b03bSNicholas Piggin mr r10,r1 /* Save r1 */ 1043a4087a4dSNicholas Piggin ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 104462f9b03bSNicholas Piggin subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 104562f9b03bSNicholas Piggin mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 1046a4087a4dSNicholas Piggin mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ 1047a4087a4dSNicholas Piggin EXCEPTION_PROLOG_COMMON_1() 104862f9b03bSNicholas Piggin EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 104962f9b03bSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(0xe60) 105062f9b03bSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1051505a314fSBenjamin Herrenschmidt BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */ 10525080332cSMichael Neuling cmpdi cr0,r3,0 10535080332cSMichael Neuling 105462f9b03bSNicholas Piggin /* Windup the stack. */ 105562f9b03bSNicholas Piggin /* Move original HSRR0 and HSRR1 into the respective regs */ 105662f9b03bSNicholas Piggin ld r9,_MSR(r1) 105762f9b03bSNicholas Piggin mtspr SPRN_HSRR1,r9 105862f9b03bSNicholas Piggin ld r3,_NIP(r1) 105962f9b03bSNicholas Piggin mtspr SPRN_HSRR0,r3 106062f9b03bSNicholas Piggin ld r9,_CTR(r1) 106162f9b03bSNicholas Piggin mtctr r9 106262f9b03bSNicholas Piggin ld r9,_XER(r1) 106362f9b03bSNicholas Piggin mtxer r9 106462f9b03bSNicholas Piggin ld r9,_LINK(r1) 106562f9b03bSNicholas Piggin mtlr r9 106662f9b03bSNicholas Piggin REST_GPR(0, r1) 106762f9b03bSNicholas Piggin REST_8GPRS(2, r1) 106862f9b03bSNicholas Piggin REST_GPR(10, r1) 106962f9b03bSNicholas Piggin ld r11,_CCR(r1) 10705080332cSMichael Neuling REST_2GPRS(12, r1) 10715080332cSMichael Neuling bne 1f 107262f9b03bSNicholas Piggin mtcr r11 107362f9b03bSNicholas Piggin REST_GPR(11, r1) 10745080332cSMichael Neuling ld r1,GPR1(r1) 1075222f20f1SNicholas Piggin HRFI_TO_USER_OR_KERNEL 10765080332cSMichael Neuling 10775080332cSMichael Neuling1: mtcr r11 10785080332cSMichael Neuling REST_GPR(11, r1) 107962f9b03bSNicholas Piggin ld r1,GPR1(r1) 108062f9b03bSNicholas Piggin 108162f9b03bSNicholas Piggin /* 108262f9b03bSNicholas Piggin * Go to virtual mode and pull the HMI event information from 108362f9b03bSNicholas Piggin * firmware. 108462f9b03bSNicholas Piggin */ 108562f9b03bSNicholas Piggin .globl hmi_exception_after_realmode 108662f9b03bSNicholas Pigginhmi_exception_after_realmode: 108762f9b03bSNicholas Piggin SET_SCRATCH0(r13) 108862f9b03bSNicholas Piggin EXCEPTION_PROLOG_0(PACA_EXGEN) 108962f9b03bSNicholas Piggin b tramp_real_hmi_exception 109062f9b03bSNicholas Piggin 10915080332cSMichael NeulingEXC_COMMON_BEGIN(hmi_exception_common) 10925080332cSMichael NeulingEXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception, 10935080332cSMichael Neuling ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON) 10941707dd16SPaul Mackerras 1095f14e953bSMadhavan SrinivasanEXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) 1096f14e953bSMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) 10979bcb81bfSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe80) 10989bcb81bfSNicholas Piggin#ifdef CONFIG_PPC_DOORBELL 10999bcb81bfSNicholas PigginEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 11009bcb81bfSNicholas Piggin#else 11019bcb81bfSNicholas PigginEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 11029bcb81bfSNicholas Piggin#endif 11039bcb81bfSNicholas Piggin 11040ebc4cdaSBenjamin Herrenschmidt 1105f14e953bSMadhavan SrinivasanEXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) 1106f14e953bSMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) 110774408776SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xea0) 110874408776SNicholas PigginEXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 110974408776SNicholas Piggin 11109baaef0aSBenjamin Herrenschmidt 11111a6822d1SNicholas PigginEXC_REAL_NONE(0xec0, 0x20) 11121a6822d1SNicholas PigginEXC_VIRT_NONE(0x4ec0, 0x20) 11131a6822d1SNicholas PigginEXC_REAL_NONE(0xee0, 0x20) 11141a6822d1SNicholas PigginEXC_VIRT_NONE(0x4ee0, 0x20) 1115bda7fea2SNicholas Piggin 11160ebc4cdaSBenjamin Herrenschmidt 1117f442d004SMadhavan SrinivasanEXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) 1118f442d004SMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) 1119b1c7f150SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf00) 1120b1c7f150SNicholas PigginEXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1121b1c7f150SNicholas Piggin 11220ebc4cdaSBenjamin Herrenschmidt 11231a6822d1SNicholas PigginEXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) 11241a6822d1SNicholas PigginEXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) 1125d1a0ca9cSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf20) 1126d1a0ca9cSNicholas PigginEXC_COMMON_BEGIN(altivec_unavailable_common) 1127d1a0ca9cSNicholas Piggin EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1128d1a0ca9cSNicholas Piggin#ifdef CONFIG_ALTIVEC 1129d1a0ca9cSNicholas PigginBEGIN_FTR_SECTION 1130d1a0ca9cSNicholas Piggin beq 1f 1131d1a0ca9cSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1132d1a0ca9cSNicholas Piggin BEGIN_FTR_SECTION_NESTED(69) 1133d1a0ca9cSNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1134d1a0ca9cSNicholas Piggin * transaction), go do TM stuff 1135d1a0ca9cSNicholas Piggin */ 1136d1a0ca9cSNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1137d1a0ca9cSNicholas Piggin bne- 2f 1138d1a0ca9cSNicholas Piggin END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1139d1a0ca9cSNicholas Piggin#endif 1140d1a0ca9cSNicholas Piggin bl load_up_altivec 1141d1a0ca9cSNicholas Piggin b fast_exception_return 1142d1a0ca9cSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1143d1a0ca9cSNicholas Piggin2: /* User process was in a transaction */ 1144d1a0ca9cSNicholas Piggin bl save_nvgprs 1145d1a0ca9cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1146d1a0ca9cSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1147d1a0ca9cSNicholas Piggin bl altivec_unavailable_tm 1148d1a0ca9cSNicholas Piggin b ret_from_except 1149d1a0ca9cSNicholas Piggin#endif 1150d1a0ca9cSNicholas Piggin1: 1151d1a0ca9cSNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1152d1a0ca9cSNicholas Piggin#endif 1153d1a0ca9cSNicholas Piggin bl save_nvgprs 1154d1a0ca9cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1155d1a0ca9cSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1156d1a0ca9cSNicholas Piggin bl altivec_unavailable_exception 1157d1a0ca9cSNicholas Piggin b ret_from_except 1158d1a0ca9cSNicholas Piggin 11590ebc4cdaSBenjamin Herrenschmidt 11601a6822d1SNicholas PigginEXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) 11611a6822d1SNicholas PigginEXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) 1162792cbdddSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf40) 1163792cbdddSNicholas PigginEXC_COMMON_BEGIN(vsx_unavailable_common) 1164792cbdddSNicholas Piggin EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) 1165792cbdddSNicholas Piggin#ifdef CONFIG_VSX 1166792cbdddSNicholas PigginBEGIN_FTR_SECTION 1167792cbdddSNicholas Piggin beq 1f 1168792cbdddSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1169792cbdddSNicholas Piggin BEGIN_FTR_SECTION_NESTED(69) 1170792cbdddSNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1171792cbdddSNicholas Piggin * transaction), go do TM stuff 1172792cbdddSNicholas Piggin */ 1173792cbdddSNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1174792cbdddSNicholas Piggin bne- 2f 1175792cbdddSNicholas Piggin END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1176792cbdddSNicholas Piggin#endif 1177792cbdddSNicholas Piggin b load_up_vsx 1178792cbdddSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1179792cbdddSNicholas Piggin2: /* User process was in a transaction */ 1180792cbdddSNicholas Piggin bl save_nvgprs 1181792cbdddSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1182792cbdddSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1183792cbdddSNicholas Piggin bl vsx_unavailable_tm 1184792cbdddSNicholas Piggin b ret_from_except 1185792cbdddSNicholas Piggin#endif 1186792cbdddSNicholas Piggin1: 1187792cbdddSNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 1188792cbdddSNicholas Piggin#endif 1189792cbdddSNicholas Piggin bl save_nvgprs 1190792cbdddSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1191792cbdddSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1192792cbdddSNicholas Piggin bl vsx_unavailable_exception 1193792cbdddSNicholas Piggin b ret_from_except 1194792cbdddSNicholas Piggin 1195d0c0c9a1SMichael Neuling 11961a6822d1SNicholas PigginEXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) 11971a6822d1SNicholas PigginEXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) 11981134713cSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf60) 11991134713cSNicholas PigginEXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 12001134713cSNicholas Piggin 1201da2bc464SMichael Ellerman 12021a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) 12031a6822d1SNicholas PigginEXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) 120414b0072cSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xf80) 120514b0072cSNicholas PigginEXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 120614b0072cSNicholas Piggin 1207da2bc464SMichael Ellerman 12081a6822d1SNicholas PigginEXC_REAL_NONE(0xfa0, 0x20) 12091a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fa0, 0x20) 12101a6822d1SNicholas PigginEXC_REAL_NONE(0xfc0, 0x20) 12111a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fc0, 0x20) 12121a6822d1SNicholas PigginEXC_REAL_NONE(0xfe0, 0x20) 12131a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fe0, 0x20) 12141a6822d1SNicholas Piggin 12151a6822d1SNicholas PigginEXC_REAL_NONE(0x1000, 0x100) 12161a6822d1SNicholas PigginEXC_VIRT_NONE(0x5000, 0x100) 12171a6822d1SNicholas PigginEXC_REAL_NONE(0x1100, 0x100) 12181a6822d1SNicholas PigginEXC_VIRT_NONE(0x5100, 0x100) 1219da2bc464SMichael Ellerman 12200ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 12211a6822d1SNicholas PigginEXC_REAL_HV(cbe_system_error, 0x1200, 0x100) 12221a6822d1SNicholas PigginEXC_VIRT_NONE(0x5200, 0x100) 1223da2bc464SMichael EllermanTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1224ff1b3206SNicholas PigginEXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1225da2bc464SMichael Ellerman#else /* CONFIG_CBE_RAS */ 12261a6822d1SNicholas PigginEXC_REAL_NONE(0x1200, 0x100) 12271a6822d1SNicholas PigginEXC_VIRT_NONE(0x5200, 0x100) 1228da2bc464SMichael Ellerman#endif 1229da2bc464SMichael Ellerman 1230ff1b3206SNicholas Piggin 12311a6822d1SNicholas PigginEXC_REAL(instruction_breakpoint, 0x1300, 0x100) 12321a6822d1SNicholas PigginEXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) 1233da2bc464SMichael EllermanTRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 12344e96dbbfSNicholas PigginEXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 12354e96dbbfSNicholas Piggin 12361a6822d1SNicholas PigginEXC_REAL_NONE(0x1400, 0x100) 12371a6822d1SNicholas PigginEXC_VIRT_NONE(0x5400, 0x100) 1238da2bc464SMichael Ellerman 12391a6822d1SNicholas PigginEXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) 1240b92a66a6SMichael Neuling mtspr SPRN_SPRG_HSCRATCH0,r13 12411707dd16SPaul Mackerras EXCEPTION_PROLOG_0(PACA_EXGEN) 1242630573c1SPaul Mackerras EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) 1243b92a66a6SMichael Neuling 1244b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 1245b92a66a6SMichael Neuling mfspr r10,SPRN_HSRR1 1246b92a66a6SMichael Neuling andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1247b92a66a6SMichael Neuling bne+ denorm_assist 1248b92a66a6SMichael Neuling#endif 1249b92a66a6SMichael Neuling 12504bb3c7a0SPaul Mackerras KVMTEST_HV(0x1500) 1251cb58a4a4SMichael Ellerman EXCEPTION_PROLOG_2(denorm_common, EXC_HV) 12521a6822d1SNicholas PigginEXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) 1253da2bc464SMichael Ellerman 1254d7e89849SNicholas Piggin#ifdef CONFIG_PPC_DENORMALISATION 12551a6822d1SNicholas PigginEXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 1256d7e89849SNicholas Piggin b exc_real_0x1500_denorm_exception_hv 12571a6822d1SNicholas PigginEXC_VIRT_END(denorm_exception, 0x5500, 0x100) 1258d7e89849SNicholas Piggin#else 12591a6822d1SNicholas PigginEXC_VIRT_NONE(0x5500, 0x100) 1260d7e89849SNicholas Piggin#endif 1261d7e89849SNicholas Piggin 12624bb3c7a0SPaul MackerrasTRAMP_KVM_HV(PACA_EXGEN, 0x1500) 1263b92a66a6SMichael Neuling 1264b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 1265da2bc464SMichael EllermanTRAMP_REAL_BEGIN(denorm_assist) 1266b92a66a6SMichael NeulingBEGIN_FTR_SECTION 1267b92a66a6SMichael Neuling/* 1268b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 1269b92a66a6SMichael Neuling * For POWER6 do that here for all FP regs. 1270b92a66a6SMichael Neuling */ 1271b92a66a6SMichael Neuling mfmsr r10 1272b92a66a6SMichael Neuling ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 1273b92a66a6SMichael Neuling xori r10,r10,(MSR_FE0|MSR_FE1) 1274b92a66a6SMichael Neuling mtmsrd r10 1275b92a66a6SMichael Neuling sync 1276d7c67fb1SMichael Neuling 1277d7c67fb1SMichael Neuling#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 1278d7c67fb1SMichael Neuling#define FMR4(n) FMR2(n) ; FMR2(n+2) 1279d7c67fb1SMichael Neuling#define FMR8(n) FMR4(n) ; FMR4(n+4) 1280d7c67fb1SMichael Neuling#define FMR16(n) FMR8(n) ; FMR8(n+8) 1281d7c67fb1SMichael Neuling#define FMR32(n) FMR16(n) ; FMR16(n+16) 1282d7c67fb1SMichael Neuling FMR32(0) 1283d7c67fb1SMichael Neuling 1284b92a66a6SMichael NeulingFTR_SECTION_ELSE 1285b92a66a6SMichael Neuling/* 1286b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 1287b92a66a6SMichael Neuling * For POWER7 do that here for the first 32 VSX registers only. 1288b92a66a6SMichael Neuling */ 1289b92a66a6SMichael Neuling mfmsr r10 1290b92a66a6SMichael Neuling oris r10,r10,MSR_VSX@h 1291b92a66a6SMichael Neuling mtmsrd r10 1292b92a66a6SMichael Neuling sync 1293d7c67fb1SMichael Neuling 1294d7c67fb1SMichael Neuling#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) 1295d7c67fb1SMichael Neuling#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) 1296d7c67fb1SMichael Neuling#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) 1297d7c67fb1SMichael Neuling#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) 1298d7c67fb1SMichael Neuling#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) 1299d7c67fb1SMichael Neuling XVCPSGNDP32(0) 1300d7c67fb1SMichael Neuling 1301b92a66a6SMichael NeulingALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 1302fb0fce3eSMichael Neuling 1303fb0fce3eSMichael NeulingBEGIN_FTR_SECTION 1304fb0fce3eSMichael Neuling b denorm_done 1305fb0fce3eSMichael NeulingEND_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 1306fb0fce3eSMichael Neuling/* 1307fb0fce3eSMichael Neuling * To denormalise we need to move a copy of the register to itself. 1308fb0fce3eSMichael Neuling * For POWER8 we need to do that for all 64 VSX registers 1309fb0fce3eSMichael Neuling */ 1310fb0fce3eSMichael Neuling XVCPSGNDP32(32) 1311fb0fce3eSMichael Neulingdenorm_done: 1312f14040bcSMichael Neuling mfspr r11,SPRN_HSRR0 1313f14040bcSMichael Neuling subi r11,r11,4 1314b92a66a6SMichael Neuling mtspr SPRN_HSRR0,r11 1315b92a66a6SMichael Neuling mtcrf 0x80,r9 1316b92a66a6SMichael Neuling ld r9,PACA_EXGEN+EX_R9(r13) 131744e9309fSHaren Myneni RESTORE_PPR_PACA(PACA_EXGEN, r10) 1318630573c1SPaul MackerrasBEGIN_FTR_SECTION 1319630573c1SPaul Mackerras ld r10,PACA_EXGEN+EX_CFAR(r13) 1320630573c1SPaul Mackerras mtspr SPRN_CFAR,r10 1321630573c1SPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1322b92a66a6SMichael Neuling ld r10,PACA_EXGEN+EX_R10(r13) 1323b92a66a6SMichael Neuling ld r11,PACA_EXGEN+EX_R11(r13) 1324b92a66a6SMichael Neuling ld r12,PACA_EXGEN+EX_R12(r13) 1325b92a66a6SMichael Neuling ld r13,PACA_EXGEN+EX_R13(r13) 1326222f20f1SNicholas Piggin HRFI_TO_UNKNOWN 1327b92a66a6SMichael Neuling b . 1328b92a66a6SMichael Neuling#endif 1329b92a66a6SMichael Neuling 1330872e2ae4SBenjamin HerrenschmidtEXC_COMMON(denorm_common, 0x1500, unknown_exception) 1331d7e89849SNicholas Piggin 1332d7e89849SNicholas Piggin 1333d7e89849SNicholas Piggin#ifdef CONFIG_CBE_RAS 13341a6822d1SNicholas PigginEXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) 13351a6822d1SNicholas PigginEXC_VIRT_NONE(0x5600, 0x100) 1336d7e89849SNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 133769a79344SNicholas PigginEXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 1338d7e89849SNicholas Piggin#else /* CONFIG_CBE_RAS */ 13391a6822d1SNicholas PigginEXC_REAL_NONE(0x1600, 0x100) 13401a6822d1SNicholas PigginEXC_VIRT_NONE(0x5600, 0x100) 1341d7e89849SNicholas Piggin#endif 1342d7e89849SNicholas Piggin 134369a79344SNicholas Piggin 13441a6822d1SNicholas PigginEXC_REAL(altivec_assist, 0x1700, 0x100) 13451a6822d1SNicholas PigginEXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) 1346d7e89849SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x1700) 1347b51c079eSNicholas Piggin#ifdef CONFIG_ALTIVEC 1348b51c079eSNicholas PigginEXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 1349b51c079eSNicholas Piggin#else 1350b51c079eSNicholas PigginEXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 1351b51c079eSNicholas Piggin#endif 1352b51c079eSNicholas Piggin 1353d7e89849SNicholas Piggin 1354d7e89849SNicholas Piggin#ifdef CONFIG_CBE_RAS 13551a6822d1SNicholas PigginEXC_REAL_HV(cbe_thermal, 0x1800, 0x100) 13561a6822d1SNicholas PigginEXC_VIRT_NONE(0x5800, 0x100) 1357d7e89849SNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 13583965f8abSNicholas PigginEXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 1359d7e89849SNicholas Piggin#else /* CONFIG_CBE_RAS */ 13601a6822d1SNicholas PigginEXC_REAL_NONE(0x1800, 0x100) 13611a6822d1SNicholas PigginEXC_VIRT_NONE(0x5800, 0x100) 1362d7e89849SNicholas Piggin#endif 1363d7e89849SNicholas Piggin 136475eb767eSNicholas Piggin#ifdef CONFIG_PPC_WATCHDOG 13652104180aSNicholas Piggin 13662104180aSNicholas Piggin#define MASKED_DEC_HANDLER_LABEL 3f 13672104180aSNicholas Piggin 13682104180aSNicholas Piggin#define MASKED_DEC_HANDLER(_H) \ 13692104180aSNicholas Piggin3: /* soft-nmi */ \ 13702104180aSNicholas Piggin std r12,PACA_EXGEN+EX_R12(r13); \ 13712104180aSNicholas Piggin GET_SCRATCH0(r10); \ 13722104180aSNicholas Piggin std r10,PACA_EXGEN+EX_R13(r13); \ 1373cb58a4a4SMichael Ellerman EXCEPTION_PROLOG_2(soft_nmi_common, _H) 13742104180aSNicholas Piggin 1375cc491f1dSNicholas Piggin/* 1376cc491f1dSNicholas Piggin * Branch to soft_nmi_interrupt using the emergency stack. The emergency 1377cc491f1dSNicholas Piggin * stack is one that is usable by maskable interrupts so long as MSR_EE 1378cc491f1dSNicholas Piggin * remains off. It is used for recovery when something has corrupted the 1379cc491f1dSNicholas Piggin * normal kernel stack, for example. The "soft NMI" must not use the process 1380cc491f1dSNicholas Piggin * stack because we want irq disabled sections to avoid touching the stack 1381cc491f1dSNicholas Piggin * at all (other than PMU interrupts), so use the emergency stack for this, 1382cc491f1dSNicholas Piggin * and run it entirely with interrupts hard disabled. 1383cc491f1dSNicholas Piggin */ 13842104180aSNicholas PigginEXC_COMMON_BEGIN(soft_nmi_common) 13852104180aSNicholas Piggin mr r10,r1 13862104180aSNicholas Piggin ld r1,PACAEMERGSP(r13) 13872104180aSNicholas Piggin subi r1,r1,INT_FRAME_SIZE 13882104180aSNicholas Piggin EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900, 13892104180aSNicholas Piggin system_reset, soft_nmi_interrupt, 13902104180aSNicholas Piggin ADD_NVGPRS;ADD_RECONCILE) 13912104180aSNicholas Piggin b ret_from_except 13922104180aSNicholas Piggin 139375eb767eSNicholas Piggin#else /* CONFIG_PPC_WATCHDOG */ 13942104180aSNicholas Piggin#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ 13952104180aSNicholas Piggin#define MASKED_DEC_HANDLER(_H) 139675eb767eSNicholas Piggin#endif /* CONFIG_PPC_WATCHDOG */ 1397d7e89849SNicholas Piggin 13980ebc4cdaSBenjamin Herrenschmidt/* 1399fe9e1d54SIan Munsie * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 1400fe9e1d54SIan Munsie * - If it was a decrementer interrupt, we bump the dec to max and and return. 1401fe9e1d54SIan Munsie * - If it was a doorbell we return immediately since doorbells are edge 1402fe9e1d54SIan Munsie * triggered and won't automatically refire. 14030869b6fdSMahesh Salgaonkar * - If it was a HMI we return immediately since we handled it in realmode 14040869b6fdSMahesh Salgaonkar * and it won't refire. 14056cc3f91bSNicholas Piggin * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. 1406fe9e1d54SIan Munsie * This is called with r10 containing the value to OR to the paca field. 14070ebc4cdaSBenjamin Herrenschmidt */ 14087230c564SBenjamin Herrenschmidt#define MASKED_INTERRUPT(_H) \ 14097230c564SBenjamin Herrenschmidtmasked_##_H##interrupt: \ 14107230c564SBenjamin Herrenschmidt std r11,PACA_EXGEN+EX_R11(r13); \ 14117230c564SBenjamin Herrenschmidt lbz r11,PACAIRQHAPPENED(r13); \ 14127230c564SBenjamin Herrenschmidt or r11,r11,r10; \ 14137230c564SBenjamin Herrenschmidt stb r11,PACAIRQHAPPENED(r13); \ 1414fe9e1d54SIan Munsie cmpwi r10,PACA_IRQ_DEC; \ 1415fe9e1d54SIan Munsie bne 1f; \ 14167230c564SBenjamin Herrenschmidt lis r10,0x7fff; \ 14177230c564SBenjamin Herrenschmidt ori r10,r10,0xffff; \ 14187230c564SBenjamin Herrenschmidt mtspr SPRN_DEC,r10; \ 14192104180aSNicholas Piggin b MASKED_DEC_HANDLER_LABEL; \ 14206cc3f91bSNicholas Piggin1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK; \ 14216cc3f91bSNicholas Piggin beq 2f; \ 1422fe9e1d54SIan Munsie mfspr r10,SPRN_##_H##SRR1; \ 14236e9a2f6eSNicholas Piggin xori r10,r10,MSR_EE; /* clear MSR_EE */ \ 14247230c564SBenjamin Herrenschmidt mtspr SPRN_##_H##SRR1,r10; \ 14259b81c021SNicholas Piggin ori r11,r11,PACA_IRQ_HARD_DIS; \ 14269b81c021SNicholas Piggin stb r11,PACAIRQHAPPENED(r13); \ 14279b81c021SNicholas Piggin2: /* done */ \ 14289b81c021SNicholas Piggin mtcrf 0x80,r9; \ 14297b08729cSMichael Ellerman std r1,PACAR1(r13); \ 14307230c564SBenjamin Herrenschmidt ld r9,PACA_EXGEN+EX_R9(r13); \ 14317230c564SBenjamin Herrenschmidt ld r10,PACA_EXGEN+EX_R10(r13); \ 14327230c564SBenjamin Herrenschmidt ld r11,PACA_EXGEN+EX_R11(r13); \ 1433c05f0be8SNicholas Piggin /* returns to kernel where r13 must be set up, so don't restore it */ \ 1434222f20f1SNicholas Piggin ##_H##RFI_TO_KERNEL; \ 14352104180aSNicholas Piggin b .; \ 14362104180aSNicholas Piggin MASKED_DEC_HANDLER(_H) 14370ebc4cdaSBenjamin Herrenschmidt 1438a048a07dSNicholas PigginTRAMP_REAL_BEGIN(stf_barrier_fallback) 1439a048a07dSNicholas Piggin std r9,PACA_EXRFI+EX_R9(r13) 1440a048a07dSNicholas Piggin std r10,PACA_EXRFI+EX_R10(r13) 1441a048a07dSNicholas Piggin sync 1442a048a07dSNicholas Piggin ld r9,PACA_EXRFI+EX_R9(r13) 1443a048a07dSNicholas Piggin ld r10,PACA_EXRFI+EX_R10(r13) 1444a048a07dSNicholas Piggin ori 31,31,0 1445a048a07dSNicholas Piggin .rept 14 1446a048a07dSNicholas Piggin b 1f 1447a048a07dSNicholas Piggin1: 1448a048a07dSNicholas Piggin .endr 1449a048a07dSNicholas Piggin blr 1450a048a07dSNicholas Piggin 1451aa8a5e00SMichael EllermanTRAMP_REAL_BEGIN(rfi_flush_fallback) 1452aa8a5e00SMichael Ellerman SET_SCRATCH0(r13); 1453aa8a5e00SMichael Ellerman GET_PACA(r13); 145478ee9946SMichael Ellerman std r1,PACA_EXRFI+EX_R12(r13) 145578ee9946SMichael Ellerman ld r1,PACAKSAVE(r13) 1456aa8a5e00SMichael Ellerman std r9,PACA_EXRFI+EX_R9(r13) 1457aa8a5e00SMichael Ellerman std r10,PACA_EXRFI+EX_R10(r13) 1458aa8a5e00SMichael Ellerman std r11,PACA_EXRFI+EX_R11(r13) 1459aa8a5e00SMichael Ellerman mfctr r9 1460aa8a5e00SMichael Ellerman ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 1461bdcb1aefSNicholas Piggin ld r11,PACA_L1D_FLUSH_SIZE(r13) 1462bdcb1aefSNicholas Piggin srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 1463aa8a5e00SMichael Ellerman mtctr r11 146415a3204dSNicholas Piggin DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 1465aa8a5e00SMichael Ellerman 1466aa8a5e00SMichael Ellerman /* order ld/st prior to dcbt stop all streams with flushing */ 1467aa8a5e00SMichael Ellerman sync 1468bdcb1aefSNicholas Piggin 1469bdcb1aefSNicholas Piggin /* 1470bdcb1aefSNicholas Piggin * The load adresses are at staggered offsets within cachelines, 1471bdcb1aefSNicholas Piggin * which suits some pipelines better (on others it should not 1472bdcb1aefSNicholas Piggin * hurt). 1473bdcb1aefSNicholas Piggin */ 1474bdcb1aefSNicholas Piggin1: 1475bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*0(r10) 1476bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*1(r10) 1477bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*2(r10) 1478bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*3(r10) 1479bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*4(r10) 1480bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*5(r10) 1481bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*6(r10) 1482bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*7(r10) 1483bdcb1aefSNicholas Piggin addi r10,r10,0x80*8 1484aa8a5e00SMichael Ellerman bdnz 1b 1485aa8a5e00SMichael Ellerman 1486aa8a5e00SMichael Ellerman mtctr r9 1487aa8a5e00SMichael Ellerman ld r9,PACA_EXRFI+EX_R9(r13) 1488aa8a5e00SMichael Ellerman ld r10,PACA_EXRFI+EX_R10(r13) 1489aa8a5e00SMichael Ellerman ld r11,PACA_EXRFI+EX_R11(r13) 149078ee9946SMichael Ellerman ld r1,PACA_EXRFI+EX_R12(r13) 1491aa8a5e00SMichael Ellerman GET_SCRATCH0(r13); 1492aa8a5e00SMichael Ellerman rfid 1493aa8a5e00SMichael Ellerman 1494aa8a5e00SMichael EllermanTRAMP_REAL_BEGIN(hrfi_flush_fallback) 1495aa8a5e00SMichael Ellerman SET_SCRATCH0(r13); 1496aa8a5e00SMichael Ellerman GET_PACA(r13); 149778ee9946SMichael Ellerman std r1,PACA_EXRFI+EX_R12(r13) 149878ee9946SMichael Ellerman ld r1,PACAKSAVE(r13) 1499aa8a5e00SMichael Ellerman std r9,PACA_EXRFI+EX_R9(r13) 1500aa8a5e00SMichael Ellerman std r10,PACA_EXRFI+EX_R10(r13) 1501aa8a5e00SMichael Ellerman std r11,PACA_EXRFI+EX_R11(r13) 1502aa8a5e00SMichael Ellerman mfctr r9 1503aa8a5e00SMichael Ellerman ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 1504bdcb1aefSNicholas Piggin ld r11,PACA_L1D_FLUSH_SIZE(r13) 1505bdcb1aefSNicholas Piggin srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 1506aa8a5e00SMichael Ellerman mtctr r11 150715a3204dSNicholas Piggin DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 1508aa8a5e00SMichael Ellerman 1509aa8a5e00SMichael Ellerman /* order ld/st prior to dcbt stop all streams with flushing */ 1510aa8a5e00SMichael Ellerman sync 1511bdcb1aefSNicholas Piggin 1512bdcb1aefSNicholas Piggin /* 1513bdcb1aefSNicholas Piggin * The load adresses are at staggered offsets within cachelines, 1514bdcb1aefSNicholas Piggin * which suits some pipelines better (on others it should not 1515bdcb1aefSNicholas Piggin * hurt). 1516bdcb1aefSNicholas Piggin */ 1517bdcb1aefSNicholas Piggin1: 1518bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*0(r10) 1519bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*1(r10) 1520bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*2(r10) 1521bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*3(r10) 1522bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*4(r10) 1523bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*5(r10) 1524bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*6(r10) 1525bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*7(r10) 1526bdcb1aefSNicholas Piggin addi r10,r10,0x80*8 1527aa8a5e00SMichael Ellerman bdnz 1b 1528aa8a5e00SMichael Ellerman 1529aa8a5e00SMichael Ellerman mtctr r9 1530aa8a5e00SMichael Ellerman ld r9,PACA_EXRFI+EX_R9(r13) 1531aa8a5e00SMichael Ellerman ld r10,PACA_EXRFI+EX_R10(r13) 1532aa8a5e00SMichael Ellerman ld r11,PACA_EXRFI+EX_R11(r13) 153378ee9946SMichael Ellerman ld r1,PACA_EXRFI+EX_R12(r13) 1534aa8a5e00SMichael Ellerman GET_SCRATCH0(r13); 1535aa8a5e00SMichael Ellerman hrfid 1536aa8a5e00SMichael Ellerman 153757f26649SNicholas Piggin/* 153857f26649SNicholas Piggin * Real mode exceptions actually use this too, but alternate 153957f26649SNicholas Piggin * instruction code patches (which end up in the common .text area) 154057f26649SNicholas Piggin * cannot reach these if they are put there. 154157f26649SNicholas Piggin */ 154257f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 15437230c564SBenjamin Herrenschmidt MASKED_INTERRUPT() 15447230c564SBenjamin Herrenschmidt MASKED_INTERRUPT(H) 15457230c564SBenjamin Herrenschmidt 15464f6c11dbSPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1547da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 15484f6c11dbSPaul Mackerras /* 15494f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 15504f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 15514f6c11dbSPaul Mackerras */ 15524f6c11dbSPaul Mackerras mfspr r13, SPRN_SRR0 15534f6c11dbSPaul Mackerras addi r13, r13, 4 15544f6c11dbSPaul Mackerras mtspr SPRN_SRR0, r13 15554f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 1556222f20f1SNicholas Piggin RFI_TO_KERNEL 15574f6c11dbSPaul Mackerras b . 15584f6c11dbSPaul Mackerras 1559da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 15604f6c11dbSPaul Mackerras /* 15614f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 15624f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 15634f6c11dbSPaul Mackerras */ 15644f6c11dbSPaul Mackerras mfspr r13, SPRN_HSRR0 15654f6c11dbSPaul Mackerras addi r13, r13, 4 15664f6c11dbSPaul Mackerras mtspr SPRN_HSRR0, r13 15674f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 1568222f20f1SNicholas Piggin HRFI_TO_KERNEL 15694f6c11dbSPaul Mackerras b . 15704f6c11dbSPaul Mackerras#endif 15714f6c11dbSPaul Mackerras 15720ebc4cdaSBenjamin Herrenschmidt/* 1573057b6d7eSHari Bathini * Ensure that any handlers that get invoked from the exception prologs 1574057b6d7eSHari Bathini * above are below the first 64KB (0x10000) of the kernel image because 1575057b6d7eSHari Bathini * the prologs assemble the addresses of these handlers using the 1576057b6d7eSHari Bathini * LOAD_HANDLER macro, which uses an ori instruction. 15770ebc4cdaSBenjamin Herrenschmidt */ 15780ebc4cdaSBenjamin Herrenschmidt 15790ebc4cdaSBenjamin Herrenschmidt/*** Common interrupt handlers ***/ 15800ebc4cdaSBenjamin Herrenschmidt 15810ebc4cdaSBenjamin Herrenschmidt 1582c1fb6816SMichael Neuling /* 1583c1fb6816SMichael Neuling * Relocation-on interrupts: A subset of the interrupts can be delivered 1584c1fb6816SMichael Neuling * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 1585c1fb6816SMichael Neuling * it. Addresses are the same as the original interrupt addresses, but 1586c1fb6816SMichael Neuling * offset by 0xc000000000004000. 1587c1fb6816SMichael Neuling * It's impossible to receive interrupts below 0x300 via this mechanism. 1588c1fb6816SMichael Neuling * KVM: None of these traps are from the guest ; anything that escalated 1589c1fb6816SMichael Neuling * to HV=1 from HV=0 is delivered via real mode handlers. 1590c1fb6816SMichael Neuling */ 1591c1fb6816SMichael Neuling 1592c1fb6816SMichael Neuling /* 1593c1fb6816SMichael Neuling * This uses the standard macro, since the original 0x300 vector 1594c1fb6816SMichael Neuling * only has extra guff for STAB-based processors -- which never 1595c1fb6816SMichael Neuling * come here. 1596c1fb6816SMichael Neuling */ 1597da2bc464SMichael Ellerman 159857f26649SNicholas PigginEXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 1599b1576fecSAnton Blanchard b __ppc64_runlatch_on 1600fe1952fcSBenjamin Herrenschmidt 160157f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 16028ed8ab40SHari Bathini /* 16038ed8ab40SHari Bathini * The __end_interrupts marker must be past the out-of-line (OOL) 16048ed8ab40SHari Bathini * handlers, so that they are copied to real address 0x100 when running 16058ed8ab40SHari Bathini * a relocatable kernel. This ensures they can be reached from the short 16068ed8ab40SHari Bathini * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 16078ed8ab40SHari Bathini * directly, without using LOAD_HANDLER(). 16088ed8ab40SHari Bathini */ 16098ed8ab40SHari Bathini .align 7 16108ed8ab40SHari Bathini .globl __end_interrupts 16118ed8ab40SHari Bathini__end_interrupts: 161257f26649SNicholas PigginDEFINE_FIXED_SYMBOL(__end_interrupts) 161361383407SBenjamin Herrenschmidt 1614087aa036SChen Gang#ifdef CONFIG_PPC_970_NAP 16157c8cb4b5SNicholas PigginEXC_COMMON_BEGIN(power4_fixup_nap) 1616087aa036SChen Gang andc r9,r9,r10 1617087aa036SChen Gang std r9,TI_LOCAL_FLAGS(r11) 1618087aa036SChen Gang ld r10,_LINK(r1) /* make idle task do the */ 1619087aa036SChen Gang std r10,_NIP(r1) /* equivalent of a blr */ 1620087aa036SChen Gang blr 1621087aa036SChen Gang#endif 1622087aa036SChen Gang 162357f26649SNicholas PigginCLOSE_FIXED_SECTION(real_vectors); 162457f26649SNicholas PigginCLOSE_FIXED_SECTION(real_trampolines); 162557f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_vectors); 162657f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_trampolines); 162757f26649SNicholas Piggin 162857f26649SNicholas PigginUSE_TEXT_SECTION() 162957f26649SNicholas Piggin 1630087aa036SChen Gang/* 16310ebc4cdaSBenjamin Herrenschmidt * Hash table stuff 16320ebc4cdaSBenjamin Herrenschmidt */ 1633f4329f2eSNicholas Piggin .balign IFETCH_ALIGN_BYTES 16346a3bab90SAnton Blancharddo_hash_page: 16354e003747SMichael Ellerman#ifdef CONFIG_PPC_BOOK3S_64 1636e6c2a479SRam Pai lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h 1637398a719dSBenjamin Herrenschmidt ori r0,r0,DSISR_BAD_FAULT_64S@l 1638398a719dSBenjamin Herrenschmidt and. r0,r4,r0 /* weird error? */ 16390ebc4cdaSBenjamin Herrenschmidt bne- handle_page_fault /* if not, try to insert a HPTE */ 1640c911d2e1SChristophe Leroy ld r11, PACA_THREAD_INFO(r13) 16419c1e1052SPaul Mackerras lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 16429c1e1052SPaul Mackerras andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 16439c1e1052SPaul Mackerras bne 77f /* then don't call hash_page now */ 16440ebc4cdaSBenjamin Herrenschmidt 16450ebc4cdaSBenjamin Herrenschmidt /* 16460ebc4cdaSBenjamin Herrenschmidt * r3 contains the faulting address 1647106713a1SAneesh Kumar K.V * r4 msr 16480ebc4cdaSBenjamin Herrenschmidt * r5 contains the trap number 1649aefa5688SAneesh Kumar K.V * r6 contains dsisr 16500ebc4cdaSBenjamin Herrenschmidt * 16517230c564SBenjamin Herrenschmidt * at return r3 = 0 for success, 1 for page fault, negative for error 16520ebc4cdaSBenjamin Herrenschmidt */ 1653106713a1SAneesh Kumar K.V mr r4,r12 1654aefa5688SAneesh Kumar K.V ld r6,_DSISR(r1) 1655106713a1SAneesh Kumar K.V bl __hash_page /* build HPTE if possible */ 1656106713a1SAneesh Kumar K.V cmpdi r3,0 /* see if __hash_page succeeded */ 16570ebc4cdaSBenjamin Herrenschmidt 16587230c564SBenjamin Herrenschmidt /* Success */ 16590ebc4cdaSBenjamin Herrenschmidt beq fast_exc_return_irq /* Return from exception on success */ 16600ebc4cdaSBenjamin Herrenschmidt 16617230c564SBenjamin Herrenschmidt /* Error */ 16627230c564SBenjamin Herrenschmidt blt- 13f 1663d89ba535SNaveen N. Rao 1664d89ba535SNaveen N. Rao /* Reload DSISR into r4 for the DABR check below */ 1665d89ba535SNaveen N. Rao ld r4,_DSISR(r1) 16664e003747SMichael Ellerman#endif /* CONFIG_PPC_BOOK3S_64 */ 16670ebc4cdaSBenjamin Herrenschmidt 1668a546498fSBenjamin Herrenschmidt/* Here we have a page fault that hash_page can't handle. */ 1669a546498fSBenjamin Herrenschmidthandle_page_fault: 1670d89ba535SNaveen N. Rao11: andis. r0,r4,DSISR_DABRMATCH@h 1671d89ba535SNaveen N. Rao bne- handle_dabr_fault 1672d89ba535SNaveen N. Rao ld r4,_DAR(r1) 1673a546498fSBenjamin Herrenschmidt ld r5,_DSISR(r1) 1674a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 1675b1576fecSAnton Blanchard bl do_page_fault 1676a546498fSBenjamin Herrenschmidt cmpdi r3,0 1677a546498fSBenjamin Herrenschmidt beq+ 12f 1678b1576fecSAnton Blanchard bl save_nvgprs 1679a546498fSBenjamin Herrenschmidt mr r5,r3 1680a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 1681a546498fSBenjamin Herrenschmidt lwz r4,_DAR(r1) 1682b1576fecSAnton Blanchard bl bad_page_fault 1683b1576fecSAnton Blanchard b ret_from_except 16840ebc4cdaSBenjamin Herrenschmidt 16859c7cc234SK.Prasad/* We have a data breakpoint exception - handle it */ 16869c7cc234SK.Prasadhandle_dabr_fault: 1687b1576fecSAnton Blanchard bl save_nvgprs 16889c7cc234SK.Prasad ld r4,_DAR(r1) 16899c7cc234SK.Prasad ld r5,_DSISR(r1) 16909c7cc234SK.Prasad addi r3,r1,STACK_FRAME_OVERHEAD 1691b1576fecSAnton Blanchard bl do_break 1692b1576fecSAnton Blanchard12: b ret_from_except_lite 16939c7cc234SK.Prasad 16940ebc4cdaSBenjamin Herrenschmidt 16954e003747SMichael Ellerman#ifdef CONFIG_PPC_BOOK3S_64 16960ebc4cdaSBenjamin Herrenschmidt/* We have a page fault that hash_page could handle but HV refused 16970ebc4cdaSBenjamin Herrenschmidt * the PTE insertion 16980ebc4cdaSBenjamin Herrenschmidt */ 1699b1576fecSAnton Blanchard13: bl save_nvgprs 17000ebc4cdaSBenjamin Herrenschmidt mr r5,r3 17010ebc4cdaSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 17020ebc4cdaSBenjamin Herrenschmidt ld r4,_DAR(r1) 1703b1576fecSAnton Blanchard bl low_hash_fault 1704b1576fecSAnton Blanchard b ret_from_except 1705caca285eSAneesh Kumar K.V#endif 17060ebc4cdaSBenjamin Herrenschmidt 17079c1e1052SPaul Mackerras/* 17089c1e1052SPaul Mackerras * We come here as a result of a DSI at a point where we don't want 17099c1e1052SPaul Mackerras * to call hash_page, such as when we are accessing memory (possibly 17109c1e1052SPaul Mackerras * user memory) inside a PMU interrupt that occurred while interrupts 17119c1e1052SPaul Mackerras * were soft-disabled. We want to invoke the exception handler for 17129c1e1052SPaul Mackerras * the access, or panic if there isn't a handler. 17139c1e1052SPaul Mackerras */ 1714b1576fecSAnton Blanchard77: bl save_nvgprs 17159c1e1052SPaul Mackerras mr r4,r3 17169c1e1052SPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 17179c1e1052SPaul Mackerras li r5,SIGSEGV 1718b1576fecSAnton Blanchard bl bad_page_fault 1719b1576fecSAnton Blanchard b ret_from_except 17204e2bf01bSMichael Ellerman 17214e2bf01bSMichael Ellerman/* 17224e2bf01bSMichael Ellerman * Here we have detected that the kernel stack pointer is bad. 17234e2bf01bSMichael Ellerman * R9 contains the saved CR, r13 points to the paca, 17244e2bf01bSMichael Ellerman * r10 contains the (bad) kernel stack pointer, 17254e2bf01bSMichael Ellerman * r11 and r12 contain the saved SRR0 and SRR1. 17264e2bf01bSMichael Ellerman * We switch to using an emergency stack, save the registers there, 17274e2bf01bSMichael Ellerman * and call kernel_bad_stack(), which panics. 17284e2bf01bSMichael Ellerman */ 17294e2bf01bSMichael Ellermanbad_stack: 17304e2bf01bSMichael Ellerman ld r1,PACAEMERGSP(r13) 17314e2bf01bSMichael Ellerman subi r1,r1,64+INT_FRAME_SIZE 17324e2bf01bSMichael Ellerman std r9,_CCR(r1) 17334e2bf01bSMichael Ellerman std r10,GPR1(r1) 17344e2bf01bSMichael Ellerman std r11,_NIP(r1) 17354e2bf01bSMichael Ellerman std r12,_MSR(r1) 17364e2bf01bSMichael Ellerman mfspr r11,SPRN_DAR 17374e2bf01bSMichael Ellerman mfspr r12,SPRN_DSISR 17384e2bf01bSMichael Ellerman std r11,_DAR(r1) 17394e2bf01bSMichael Ellerman std r12,_DSISR(r1) 17404e2bf01bSMichael Ellerman mflr r10 17414e2bf01bSMichael Ellerman mfctr r11 17424e2bf01bSMichael Ellerman mfxer r12 17434e2bf01bSMichael Ellerman std r10,_LINK(r1) 17444e2bf01bSMichael Ellerman std r11,_CTR(r1) 17454e2bf01bSMichael Ellerman std r12,_XER(r1) 17464e2bf01bSMichael Ellerman SAVE_GPR(0,r1) 17474e2bf01bSMichael Ellerman SAVE_GPR(2,r1) 17484e2bf01bSMichael Ellerman ld r10,EX_R3(r3) 17494e2bf01bSMichael Ellerman std r10,GPR3(r1) 17504e2bf01bSMichael Ellerman SAVE_GPR(4,r1) 17514e2bf01bSMichael Ellerman SAVE_4GPRS(5,r1) 17524e2bf01bSMichael Ellerman ld r9,EX_R9(r3) 17534e2bf01bSMichael Ellerman ld r10,EX_R10(r3) 17544e2bf01bSMichael Ellerman SAVE_2GPRS(9,r1) 17554e2bf01bSMichael Ellerman ld r9,EX_R11(r3) 17564e2bf01bSMichael Ellerman ld r10,EX_R12(r3) 17574e2bf01bSMichael Ellerman ld r11,EX_R13(r3) 17584e2bf01bSMichael Ellerman std r9,GPR11(r1) 17594e2bf01bSMichael Ellerman std r10,GPR12(r1) 17604e2bf01bSMichael Ellerman std r11,GPR13(r1) 17614e2bf01bSMichael EllermanBEGIN_FTR_SECTION 17624e2bf01bSMichael Ellerman ld r10,EX_CFAR(r3) 17634e2bf01bSMichael Ellerman std r10,ORIG_GPR3(r1) 17644e2bf01bSMichael EllermanEND_FTR_SECTION_IFSET(CPU_FTR_CFAR) 17654e2bf01bSMichael Ellerman SAVE_8GPRS(14,r1) 17664e2bf01bSMichael Ellerman SAVE_10GPRS(22,r1) 17674e2bf01bSMichael Ellerman lhz r12,PACA_TRAP_SAVE(r13) 17684e2bf01bSMichael Ellerman std r12,_TRAP(r1) 17694e2bf01bSMichael Ellerman addi r11,r1,INT_FRAME_SIZE 17704e2bf01bSMichael Ellerman std r11,0(r1) 17714e2bf01bSMichael Ellerman li r12,0 17724e2bf01bSMichael Ellerman std r12,0(r11) 17734e2bf01bSMichael Ellerman ld r2,PACATOC(r13) 17744e2bf01bSMichael Ellerman ld r11,exception_marker@toc(r2) 17754e2bf01bSMichael Ellerman std r12,RESULT(r1) 17764e2bf01bSMichael Ellerman std r11,STACK_FRAME_OVERHEAD-16(r1) 17774e2bf01bSMichael Ellerman1: addi r3,r1,STACK_FRAME_OVERHEAD 17784e2bf01bSMichael Ellerman bl kernel_bad_stack 17794e2bf01bSMichael Ellerman b 1b 178015770a13SNaveen N. Rao_ASM_NOKPROBE_SYMBOL(bad_stack); 17810f0c6ca1SNicholas Piggin 17820f0c6ca1SNicholas Piggin/* 1783a9af97aaSNicholas Piggin * When doorbell is triggered from system reset wakeup, the message is 1784a9af97aaSNicholas Piggin * not cleared, so it would fire again when EE is enabled. 1785a9af97aaSNicholas Piggin * 1786a9af97aaSNicholas Piggin * When coming from local_irq_enable, there may be the same problem if 1787a9af97aaSNicholas Piggin * we were hard disabled. 1788a9af97aaSNicholas Piggin * 1789a9af97aaSNicholas Piggin * Execute msgclr to clear pending exceptions before handling it. 1790a9af97aaSNicholas Piggin */ 1791a9af97aaSNicholas Pigginh_doorbell_common_msgclr: 1792a9af97aaSNicholas Piggin LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1793a9af97aaSNicholas Piggin PPC_MSGCLR(3) 1794a9af97aaSNicholas Piggin b h_doorbell_common 1795a9af97aaSNicholas Piggin 1796a9af97aaSNicholas Piggindoorbell_super_common_msgclr: 1797a9af97aaSNicholas Piggin LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 1798a9af97aaSNicholas Piggin PPC_MSGCLRP(3) 1799a9af97aaSNicholas Piggin b doorbell_super_common 1800a9af97aaSNicholas Piggin 1801a9af97aaSNicholas Piggin/* 18020f0c6ca1SNicholas Piggin * Called from arch_local_irq_enable when an interrupt needs 18030f0c6ca1SNicholas Piggin * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 18040f0c6ca1SNicholas Piggin * which kind of interrupt. MSR:EE is already off. We generate a 18050f0c6ca1SNicholas Piggin * stackframe like if a real interrupt had happened. 18060f0c6ca1SNicholas Piggin * 18070f0c6ca1SNicholas Piggin * Note: While MSR:EE is off, we need to make sure that _MSR 18080f0c6ca1SNicholas Piggin * in the generated frame has EE set to 1 or the exception 18090f0c6ca1SNicholas Piggin * handler will not properly re-enable them. 1810b48bbb82SNicholas Piggin * 1811b48bbb82SNicholas Piggin * Note that we don't specify LR as the NIP (return address) for 1812b48bbb82SNicholas Piggin * the interrupt because that would unbalance the return branch 1813b48bbb82SNicholas Piggin * predictor. 18140f0c6ca1SNicholas Piggin */ 18150f0c6ca1SNicholas Piggin_GLOBAL(__replay_interrupt) 18160f0c6ca1SNicholas Piggin /* We are going to jump to the exception common code which 18170f0c6ca1SNicholas Piggin * will retrieve various register values from the PACA which 18180f0c6ca1SNicholas Piggin * we don't give a damn about, so we don't bother storing them. 18190f0c6ca1SNicholas Piggin */ 18200f0c6ca1SNicholas Piggin mfmsr r12 18213e23a12bSMichael Ellerman LOAD_REG_ADDR(r11, replay_interrupt_return) 18220f0c6ca1SNicholas Piggin mfcr r9 18230f0c6ca1SNicholas Piggin ori r12,r12,MSR_EE 18240f0c6ca1SNicholas Piggin cmpwi r3,0x900 18250f0c6ca1SNicholas Piggin beq decrementer_common 18260f0c6ca1SNicholas Piggin cmpwi r3,0x500 1827e6c1203dSNicholas PigginBEGIN_FTR_SECTION 1828e6c1203dSNicholas Piggin beq h_virt_irq_common 1829e6c1203dSNicholas PigginFTR_SECTION_ELSE 18300f0c6ca1SNicholas Piggin beq hardware_interrupt_common 1831e6c1203dSNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) 1832f442d004SMadhavan Srinivasan cmpwi r3,0xf00 1833f442d004SMadhavan Srinivasan beq performance_monitor_common 18340f0c6ca1SNicholas PigginBEGIN_FTR_SECTION 1835d6f73fc6SNicholas Piggin cmpwi r3,0xa00 1836a9af97aaSNicholas Piggin beq h_doorbell_common_msgclr 18370f0c6ca1SNicholas Piggin cmpwi r3,0xe60 18380f0c6ca1SNicholas Piggin beq hmi_exception_common 18390f0c6ca1SNicholas PigginFTR_SECTION_ELSE 18400f0c6ca1SNicholas Piggin cmpwi r3,0xa00 1841a9af97aaSNicholas Piggin beq doorbell_super_common_msgclr 18420f0c6ca1SNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 18433e23a12bSMichael Ellermanreplay_interrupt_return: 18440f0c6ca1SNicholas Piggin blr 1845b48bbb82SNicholas Piggin 184615770a13SNaveen N. Rao_ASM_NOKPROBE_SYMBOL(__replay_interrupt) 1847