1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 20ebc4cdaSBenjamin Herrenschmidt/* 30ebc4cdaSBenjamin Herrenschmidt * This file contains the 64-bit "server" PowerPC variant 40ebc4cdaSBenjamin Herrenschmidt * of the low level exception handling including exception 50ebc4cdaSBenjamin Herrenschmidt * vectors, exception return, part of the slb and stab 60ebc4cdaSBenjamin Herrenschmidt * handling and other fixed offset specific things. 70ebc4cdaSBenjamin Herrenschmidt * 80ebc4cdaSBenjamin Herrenschmidt * This file is meant to be #included from head_64.S due to 925985edcSLucas De Marchi * position dependent assembly. 100ebc4cdaSBenjamin Herrenschmidt * 110ebc4cdaSBenjamin Herrenschmidt * Most of this originates from head_64.S and thus has the same 120ebc4cdaSBenjamin Herrenschmidt * copyright history. 130ebc4cdaSBenjamin Herrenschmidt * 140ebc4cdaSBenjamin Herrenschmidt */ 150ebc4cdaSBenjamin Herrenschmidt 167230c564SBenjamin Herrenschmidt#include <asm/hw_irq.h> 178aa34ab8SBenjamin Herrenschmidt#include <asm/exception-64s.h> 1846f52210SStephen Rothwell#include <asm/ptrace.h> 197cba160aSShreyas B. Prabhu#include <asm/cpuidle.h> 20da2bc464SMichael Ellerman#include <asm/head-64.h> 212c86cd18SChristophe Leroy#include <asm/feature-fixups.h> 22890274c2SMichael Ellerman#include <asm/kup.h> 238aa34ab8SBenjamin Herrenschmidt 2415820091SNicholas Piggin/* PACA save area offsets (exgen, exmc, etc) */ 2515820091SNicholas Piggin#define EX_R9 0 2615820091SNicholas Piggin#define EX_R10 8 2715820091SNicholas Piggin#define EX_R11 16 2815820091SNicholas Piggin#define EX_R12 24 2915820091SNicholas Piggin#define EX_R13 32 3015820091SNicholas Piggin#define EX_DAR 40 3115820091SNicholas Piggin#define EX_DSISR 48 3215820091SNicholas Piggin#define EX_CCR 52 3315820091SNicholas Piggin#define EX_CFAR 56 3415820091SNicholas Piggin#define EX_PPR 64 3515820091SNicholas Piggin#if defined(CONFIG_RELOCATABLE) 3615820091SNicholas Piggin#define EX_CTR 72 3715820091SNicholas Piggin.if EX_SIZE != 10 3815820091SNicholas Piggin .error "EX_SIZE is wrong" 3915820091SNicholas Piggin.endif 4015820091SNicholas Piggin#else 4115820091SNicholas Piggin.if EX_SIZE != 9 4215820091SNicholas Piggin .error "EX_SIZE is wrong" 4315820091SNicholas Piggin.endif 4415820091SNicholas Piggin#endif 4515820091SNicholas Piggin 460ebc4cdaSBenjamin Herrenschmidt/* 4712a04809SNicholas Piggin * We're short on space and time in the exception prolog, so we can't 4812a04809SNicholas Piggin * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 4912a04809SNicholas Piggin * Instead we get the base of the kernel from paca->kernelbase and or in the low 5012a04809SNicholas Piggin * part of label. This requires that the label be within 64KB of kernelbase, and 5112a04809SNicholas Piggin * that kernelbase be 64K aligned. 5212a04809SNicholas Piggin */ 5312a04809SNicholas Piggin#define LOAD_HANDLER(reg, label) \ 5412a04809SNicholas Piggin ld reg,PACAKBASE(r13); /* get high part of &label */ \ 5512a04809SNicholas Piggin ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) 5612a04809SNicholas Piggin 5712a04809SNicholas Piggin#define __LOAD_HANDLER(reg, label) \ 5812a04809SNicholas Piggin ld reg,PACAKBASE(r13); \ 5912a04809SNicholas Piggin ori reg,reg,(ABS_ADDR(label))@l 6012a04809SNicholas Piggin 6112a04809SNicholas Piggin/* 6212a04809SNicholas Piggin * Branches from unrelocated code (e.g., interrupts) to labels outside 6312a04809SNicholas Piggin * head-y require >64K offsets. 6412a04809SNicholas Piggin */ 6512a04809SNicholas Piggin#define __LOAD_FAR_HANDLER(reg, label) \ 6612a04809SNicholas Piggin ld reg,PACAKBASE(r13); \ 6712a04809SNicholas Piggin ori reg,reg,(ABS_ADDR(label))@l; \ 6812a04809SNicholas Piggin addis reg,reg,(ABS_ADDR(label))@h 6912a04809SNicholas Piggin 7012a04809SNicholas Piggin/* Exception register prefixes */ 7112a04809SNicholas Piggin#define EXC_HV 1 7212a04809SNicholas Piggin#define EXC_STD 0 7312a04809SNicholas Piggin 7412a04809SNicholas Piggin#if defined(CONFIG_RELOCATABLE) 7512a04809SNicholas Piggin/* 7612a04809SNicholas Piggin * If we support interrupts with relocation on AND we're a relocatable kernel, 7712a04809SNicholas Piggin * we need to use CTR to get to the 2nd level handler. So, save/restore it 7812a04809SNicholas Piggin * when required. 7912a04809SNicholas Piggin */ 8012a04809SNicholas Piggin#define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 8112a04809SNicholas Piggin#define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 8212a04809SNicholas Piggin#define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 8312a04809SNicholas Piggin#else 8412a04809SNicholas Piggin/* ...else CTR is unused and in register. */ 8512a04809SNicholas Piggin#define SAVE_CTR(reg, area) 8612a04809SNicholas Piggin#define GET_CTR(reg, area) mfctr reg 8712a04809SNicholas Piggin#define RESTORE_CTR(reg, area) 8812a04809SNicholas Piggin#endif 8912a04809SNicholas Piggin 9012a04809SNicholas Piggin/* 9112a04809SNicholas Piggin * PPR save/restore macros used in exceptions-64s.S 9212a04809SNicholas Piggin * Used for P7 or later processors 9312a04809SNicholas Piggin */ 9412a04809SNicholas Piggin#define SAVE_PPR(area, ra) \ 9512a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(940) \ 9612a04809SNicholas Piggin ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \ 9712a04809SNicholas Piggin std ra,_PPR(r1); \ 9812a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 9912a04809SNicholas Piggin 10012a04809SNicholas Piggin#define RESTORE_PPR_PACA(area, ra) \ 10112a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(941) \ 10212a04809SNicholas Piggin ld ra,area+EX_PPR(r13); \ 10312a04809SNicholas Piggin mtspr SPRN_PPR,ra; \ 10412a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 10512a04809SNicholas Piggin 10612a04809SNicholas Piggin/* 10712a04809SNicholas Piggin * Get an SPR into a register if the CPU has the given feature 10812a04809SNicholas Piggin */ 10912a04809SNicholas Piggin#define OPT_GET_SPR(ra, spr, ftr) \ 11012a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(943) \ 11112a04809SNicholas Piggin mfspr ra,spr; \ 11212a04809SNicholas PigginEND_FTR_SECTION_NESTED(ftr,ftr,943) 11312a04809SNicholas Piggin 11412a04809SNicholas Piggin/* 11512a04809SNicholas Piggin * Set an SPR from a register if the CPU has the given feature 11612a04809SNicholas Piggin */ 11712a04809SNicholas Piggin#define OPT_SET_SPR(ra, spr, ftr) \ 11812a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(943) \ 11912a04809SNicholas Piggin mtspr spr,ra; \ 12012a04809SNicholas PigginEND_FTR_SECTION_NESTED(ftr,ftr,943) 12112a04809SNicholas Piggin 12212a04809SNicholas Piggin/* 12312a04809SNicholas Piggin * Save a register to the PACA if the CPU has the given feature 12412a04809SNicholas Piggin */ 12512a04809SNicholas Piggin#define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 12612a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(943) \ 12712a04809SNicholas Piggin std ra,offset(r13); \ 12812a04809SNicholas PigginEND_FTR_SECTION_NESTED(ftr,ftr,943) 12912a04809SNicholas Piggin 13012a04809SNicholas Piggin.macro EXCEPTION_PROLOG_0 area 13112a04809SNicholas Piggin GET_PACA(r13) 13212a04809SNicholas Piggin std r9,\area\()+EX_R9(r13) /* save r9 */ 13312a04809SNicholas Piggin OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR) 13412a04809SNicholas Piggin HMT_MEDIUM 13512a04809SNicholas Piggin std r10,\area\()+EX_R10(r13) /* save r10 - r12 */ 13612a04809SNicholas Piggin OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 13712a04809SNicholas Piggin.endm 13812a04809SNicholas Piggin 13912a04809SNicholas Piggin.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask 14012a04809SNicholas Piggin OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR) 14112a04809SNicholas Piggin OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR) 14212a04809SNicholas Piggin INTERRUPT_TO_KERNEL 14312a04809SNicholas Piggin SAVE_CTR(r10, \area\()) 14412a04809SNicholas Piggin mfcr r9 14512a04809SNicholas Piggin .if \kvm 14612a04809SNicholas Piggin KVMTEST \hsrr \vec 14712a04809SNicholas Piggin .endif 14812a04809SNicholas Piggin .if \bitmask 14912a04809SNicholas Piggin lbz r10,PACAIRQSOFTMASK(r13) 15012a04809SNicholas Piggin andi. r10,r10,\bitmask 15112a04809SNicholas Piggin /* Associate vector numbers with bits in paca->irq_happened */ 15212a04809SNicholas Piggin .if \vec == 0x500 || \vec == 0xea0 15312a04809SNicholas Piggin li r10,PACA_IRQ_EE 15412a04809SNicholas Piggin .elseif \vec == 0x900 15512a04809SNicholas Piggin li r10,PACA_IRQ_DEC 15612a04809SNicholas Piggin .elseif \vec == 0xa00 || \vec == 0xe80 15712a04809SNicholas Piggin li r10,PACA_IRQ_DBELL 15812a04809SNicholas Piggin .elseif \vec == 0xe60 15912a04809SNicholas Piggin li r10,PACA_IRQ_HMI 16012a04809SNicholas Piggin .elseif \vec == 0xf00 16112a04809SNicholas Piggin li r10,PACA_IRQ_PMI 16212a04809SNicholas Piggin .else 16312a04809SNicholas Piggin .abort "Bad maskable vector" 16412a04809SNicholas Piggin .endif 16512a04809SNicholas Piggin 16612a04809SNicholas Piggin .if \hsrr 16712a04809SNicholas Piggin bne masked_Hinterrupt 16812a04809SNicholas Piggin .else 16912a04809SNicholas Piggin bne masked_interrupt 17012a04809SNicholas Piggin .endif 17112a04809SNicholas Piggin .endif 17212a04809SNicholas Piggin 17312a04809SNicholas Piggin std r11,\area\()+EX_R11(r13) 17412a04809SNicholas Piggin std r12,\area\()+EX_R12(r13) 17512a04809SNicholas Piggin GET_SCRATCH0(r10) 17612a04809SNicholas Piggin std r10,\area\()+EX_R13(r13) 17712a04809SNicholas Piggin.endm 17812a04809SNicholas Piggin 17912a04809SNicholas Piggin.macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri 18012a04809SNicholas Piggin ld r10,PACAKMSR(r13) /* get MSR value for kernel */ 18112a04809SNicholas Piggin .if ! \set_ri 18212a04809SNicholas Piggin xori r10,r10,MSR_RI /* Clear MSR_RI */ 18312a04809SNicholas Piggin .endif 18412a04809SNicholas Piggin .if \hsrr 18512a04809SNicholas Piggin mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 18612a04809SNicholas Piggin .else 18712a04809SNicholas Piggin mfspr r11,SPRN_SRR0 /* save SRR0 */ 18812a04809SNicholas Piggin .endif 18912a04809SNicholas Piggin LOAD_HANDLER(r12, \label\()) 19012a04809SNicholas Piggin .if \hsrr 19112a04809SNicholas Piggin mtspr SPRN_HSRR0,r12 19212a04809SNicholas Piggin mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 19312a04809SNicholas Piggin mtspr SPRN_HSRR1,r10 19412a04809SNicholas Piggin HRFI_TO_KERNEL 19512a04809SNicholas Piggin .else 19612a04809SNicholas Piggin mtspr SPRN_SRR0,r12 19712a04809SNicholas Piggin mfspr r12,SPRN_SRR1 /* and SRR1 */ 19812a04809SNicholas Piggin mtspr SPRN_SRR1,r10 19912a04809SNicholas Piggin RFI_TO_KERNEL 20012a04809SNicholas Piggin .endif 20112a04809SNicholas Piggin b . /* prevent speculative execution */ 20212a04809SNicholas Piggin.endm 20312a04809SNicholas Piggin 20412a04809SNicholas Piggin.macro EXCEPTION_PROLOG_2_VIRT label, hsrr 20512a04809SNicholas Piggin#ifdef CONFIG_RELOCATABLE 20612a04809SNicholas Piggin .if \hsrr 20712a04809SNicholas Piggin mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 20812a04809SNicholas Piggin .else 20912a04809SNicholas Piggin mfspr r11,SPRN_SRR0 /* save SRR0 */ 21012a04809SNicholas Piggin .endif 21112a04809SNicholas Piggin LOAD_HANDLER(r12, \label\()) 21212a04809SNicholas Piggin mtctr r12 21312a04809SNicholas Piggin .if \hsrr 21412a04809SNicholas Piggin mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 21512a04809SNicholas Piggin .else 21612a04809SNicholas Piggin mfspr r12,SPRN_SRR1 /* and HSRR1 */ 21712a04809SNicholas Piggin .endif 21812a04809SNicholas Piggin li r10,MSR_RI 21912a04809SNicholas Piggin mtmsrd r10,1 /* Set RI (EE=0) */ 22012a04809SNicholas Piggin bctr 22112a04809SNicholas Piggin#else 22212a04809SNicholas Piggin .if \hsrr 22312a04809SNicholas Piggin mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 22412a04809SNicholas Piggin mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 22512a04809SNicholas Piggin .else 22612a04809SNicholas Piggin mfspr r11,SPRN_SRR0 /* save SRR0 */ 22712a04809SNicholas Piggin mfspr r12,SPRN_SRR1 /* and SRR1 */ 22812a04809SNicholas Piggin .endif 22912a04809SNicholas Piggin li r10,MSR_RI 23012a04809SNicholas Piggin mtmsrd r10,1 /* Set RI (EE=0) */ 23112a04809SNicholas Piggin b \label 23212a04809SNicholas Piggin#endif 23312a04809SNicholas Piggin.endm 23412a04809SNicholas Piggin 23512a04809SNicholas Piggin/* 23612a04809SNicholas Piggin * Branch to label using its 0xC000 address. This results in instruction 23712a04809SNicholas Piggin * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 23812a04809SNicholas Piggin * on using mtmsr rather than rfid. 23912a04809SNicholas Piggin * 24012a04809SNicholas Piggin * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 24112a04809SNicholas Piggin * load KBASE for a slight optimisation. 24212a04809SNicholas Piggin */ 24312a04809SNicholas Piggin#define BRANCH_TO_C000(reg, label) \ 24412a04809SNicholas Piggin __LOAD_HANDLER(reg, label); \ 24512a04809SNicholas Piggin mtctr reg; \ 24612a04809SNicholas Piggin bctr 24712a04809SNicholas Piggin 24812a04809SNicholas Piggin#ifdef CONFIG_RELOCATABLE 24912a04809SNicholas Piggin#define BRANCH_LINK_TO_FAR(label) \ 25012a04809SNicholas Piggin __LOAD_FAR_HANDLER(r12, label); \ 25112a04809SNicholas Piggin mtctr r12; \ 25212a04809SNicholas Piggin bctrl 25312a04809SNicholas Piggin 25412a04809SNicholas Piggin#else 25512a04809SNicholas Piggin#define BRANCH_LINK_TO_FAR(label) \ 25612a04809SNicholas Piggin bl label 25712a04809SNicholas Piggin#endif 25812a04809SNicholas Piggin 25912a04809SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 26012a04809SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 26112a04809SNicholas Piggin/* 26212a04809SNicholas Piggin * If hv is possible, interrupts come into to the hv version 26312a04809SNicholas Piggin * of the kvmppc_interrupt code, which then jumps to the PR handler, 26412a04809SNicholas Piggin * kvmppc_interrupt_pr, if the guest is a PR guest. 26512a04809SNicholas Piggin */ 26612a04809SNicholas Piggin#define kvmppc_interrupt kvmppc_interrupt_hv 26712a04809SNicholas Piggin#else 26812a04809SNicholas Piggin#define kvmppc_interrupt kvmppc_interrupt_pr 26912a04809SNicholas Piggin#endif 27012a04809SNicholas Piggin 27112a04809SNicholas Piggin.macro KVMTEST hsrr, n 27212a04809SNicholas Piggin lbz r10,HSTATE_IN_GUEST(r13) 27312a04809SNicholas Piggin cmpwi r10,0 27412a04809SNicholas Piggin .if \hsrr 27512a04809SNicholas Piggin bne do_kvm_H\n 27612a04809SNicholas Piggin .else 27712a04809SNicholas Piggin bne do_kvm_\n 27812a04809SNicholas Piggin .endif 27912a04809SNicholas Piggin.endm 28012a04809SNicholas Piggin 28112a04809SNicholas Piggin.macro KVM_HANDLER area, hsrr, n, skip 28212a04809SNicholas Piggin .if \skip 28312a04809SNicholas Piggin cmpwi r10,KVM_GUEST_MODE_SKIP 28412a04809SNicholas Piggin beq 89f 28512a04809SNicholas Piggin .else 28612a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(947) 28712a04809SNicholas Piggin ld r10,\area+EX_CFAR(r13) 28812a04809SNicholas Piggin std r10,HSTATE_CFAR(r13) 28912a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947) 29012a04809SNicholas Piggin .endif 29112a04809SNicholas Piggin 29212a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(948) 29312a04809SNicholas Piggin ld r10,\area+EX_PPR(r13) 29412a04809SNicholas Piggin std r10,HSTATE_PPR(r13) 29512a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948) 29612a04809SNicholas Piggin ld r10,\area+EX_R10(r13) 29712a04809SNicholas Piggin std r12,HSTATE_SCRATCH0(r13) 29812a04809SNicholas Piggin sldi r12,r9,32 29912a04809SNicholas Piggin /* HSRR variants have the 0x2 bit added to their trap number */ 30012a04809SNicholas Piggin .if \hsrr 30112a04809SNicholas Piggin ori r12,r12,(\n + 0x2) 30212a04809SNicholas Piggin .else 30312a04809SNicholas Piggin ori r12,r12,(\n) 30412a04809SNicholas Piggin .endif 30564e41351SNicholas Piggin 30664e41351SNicholas Piggin#ifdef CONFIG_RELOCATABLE 30764e41351SNicholas Piggin /* 30864e41351SNicholas Piggin * KVM requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives 30964e41351SNicholas Piggin * outside the head section. CONFIG_RELOCATABLE KVM expects CTR 31064e41351SNicholas Piggin * to be saved in HSTATE_SCRATCH1. 31164e41351SNicholas Piggin */ 31264e41351SNicholas Piggin mfctr r9 31364e41351SNicholas Piggin std r9,HSTATE_SCRATCH1(r13) 31464e41351SNicholas Piggin __LOAD_FAR_HANDLER(r9, kvmppc_interrupt) 31564e41351SNicholas Piggin mtctr r9 31664e41351SNicholas Piggin ld r9,\area+EX_R9(r13) 31764e41351SNicholas Piggin bctr 31864e41351SNicholas Piggin#else 31964e41351SNicholas Piggin ld r9,\area+EX_R9(r13) 32064e41351SNicholas Piggin b kvmppc_interrupt 32164e41351SNicholas Piggin#endif 32264e41351SNicholas Piggin 32312a04809SNicholas Piggin 32412a04809SNicholas Piggin .if \skip 32512a04809SNicholas Piggin89: mtocrf 0x80,r9 32612a04809SNicholas Piggin ld r9,\area+EX_R9(r13) 32712a04809SNicholas Piggin ld r10,\area+EX_R10(r13) 32812a04809SNicholas Piggin .if \hsrr 32912a04809SNicholas Piggin b kvmppc_skip_Hinterrupt 33012a04809SNicholas Piggin .else 33112a04809SNicholas Piggin b kvmppc_skip_interrupt 33212a04809SNicholas Piggin .endif 33312a04809SNicholas Piggin .endif 33412a04809SNicholas Piggin.endm 33512a04809SNicholas Piggin 33612a04809SNicholas Piggin#else 33712a04809SNicholas Piggin.macro KVMTEST hsrr, n 33812a04809SNicholas Piggin.endm 33912a04809SNicholas Piggin.macro KVM_HANDLER area, hsrr, n, skip 34012a04809SNicholas Piggin.endm 34112a04809SNicholas Piggin#endif 34212a04809SNicholas Piggin 34312a04809SNicholas Piggin#define EXCEPTION_PROLOG_COMMON_1() \ 34412a04809SNicholas Piggin std r9,_CCR(r1); /* save CR in stackframe */ \ 34512a04809SNicholas Piggin std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 34612a04809SNicholas Piggin std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 34712a04809SNicholas Piggin std r10,0(r1); /* make stack chain pointer */ \ 34812a04809SNicholas Piggin std r0,GPR0(r1); /* save r0 in stackframe */ \ 34912a04809SNicholas Piggin std r10,GPR1(r1); /* save r1 in stackframe */ \ 35012a04809SNicholas Piggin 35112a04809SNicholas Piggin/* Save original regs values from save area to stack frame. */ 35212a04809SNicholas Piggin#define EXCEPTION_PROLOG_COMMON_2(area) \ 35312a04809SNicholas Piggin ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 35412a04809SNicholas Piggin ld r10,area+EX_R10(r13); \ 35512a04809SNicholas Piggin std r9,GPR9(r1); \ 35612a04809SNicholas Piggin std r10,GPR10(r1); \ 35712a04809SNicholas Piggin ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 35812a04809SNicholas Piggin ld r10,area+EX_R12(r13); \ 35912a04809SNicholas Piggin ld r11,area+EX_R13(r13); \ 36012a04809SNicholas Piggin std r9,GPR11(r1); \ 36112a04809SNicholas Piggin std r10,GPR12(r1); \ 36212a04809SNicholas Piggin std r11,GPR13(r1); \ 36312a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(66); \ 36412a04809SNicholas Piggin ld r10,area+EX_CFAR(r13); \ 36512a04809SNicholas Piggin std r10,ORIG_GPR3(r1); \ 36612a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 36712a04809SNicholas Piggin GET_CTR(r10, area); \ 36812a04809SNicholas Piggin std r10,_CTR(r1); 36912a04809SNicholas Piggin 370d064151fSNicholas Piggin#define EXCEPTION_PROLOG_COMMON_3(trap) \ 37112a04809SNicholas Piggin std r2,GPR2(r1); /* save r2 in stackframe */ \ 37212a04809SNicholas Piggin SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 37312a04809SNicholas Piggin SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 37412a04809SNicholas Piggin mflr r9; /* Get LR, later save to stack */ \ 37512a04809SNicholas Piggin ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 37612a04809SNicholas Piggin std r9,_LINK(r1); \ 37712a04809SNicholas Piggin lbz r10,PACAIRQSOFTMASK(r13); \ 37812a04809SNicholas Piggin mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 37912a04809SNicholas Piggin std r10,SOFTE(r1); \ 38012a04809SNicholas Piggin std r11,_XER(r1); \ 381d064151fSNicholas Piggin li r9,(trap)+1; \ 38212a04809SNicholas Piggin std r9,_TRAP(r1); /* set trap number */ \ 38312a04809SNicholas Piggin li r10,0; \ 38412a04809SNicholas Piggin ld r11,exception_marker@toc(r2); \ 38512a04809SNicholas Piggin std r10,RESULT(r1); /* clear regs->result */ \ 38612a04809SNicholas Piggin std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 38712a04809SNicholas Piggin 388d064151fSNicholas Piggin/* 389d064151fSNicholas Piggin * On entry r13 points to the paca, r9-r13 are saved in the paca, 390d064151fSNicholas Piggin * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 391d064151fSNicholas Piggin * SRR1, and relocation is on. 392d064151fSNicholas Piggin */ 393d064151fSNicholas Piggin#define EXCEPTION_COMMON(area, trap) \ 394d064151fSNicholas Piggin andi. r10,r12,MSR_PR; /* See if coming from user */ \ 395d064151fSNicholas Piggin mr r10,r1; /* Save r1 */ \ 396d064151fSNicholas Piggin subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 397d064151fSNicholas Piggin beq- 1f; \ 398d064151fSNicholas Piggin ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 399d064151fSNicholas Piggin1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 400d064151fSNicholas Piggin blt+ cr1,3f; /* abort if it is */ \ 401d064151fSNicholas Piggin li r1,(trap); /* will be reloaded later */ \ 402d064151fSNicholas Piggin sth r1,PACA_TRAP_SAVE(r13); \ 403d064151fSNicholas Piggin std r3,area+EX_R3(r13); \ 404d064151fSNicholas Piggin addi r3,r13,area; /* r3 -> where regs are saved*/ \ 405d064151fSNicholas Piggin RESTORE_CTR(r1, area); \ 406d064151fSNicholas Piggin b bad_stack; \ 407d064151fSNicholas Piggin3: EXCEPTION_PROLOG_COMMON_1(); \ 408d064151fSNicholas Piggin kuap_save_amr_and_lock r9, r10, cr1, cr0; \ 409d064151fSNicholas Piggin beq 4f; /* if from kernel mode */ \ 410d064151fSNicholas Piggin ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 411d064151fSNicholas Piggin SAVE_PPR(area, r9); \ 412d064151fSNicholas Piggin4: EXCEPTION_PROLOG_COMMON_2(area); \ 413d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(trap); \ 414d064151fSNicholas Piggin ACCOUNT_STOLEN_TIME 415d064151fSNicholas Piggin 416d064151fSNicholas Piggin 417d064151fSNicholas Piggin/* 418d064151fSNicholas Piggin * Exception where stack is already set in r1, r1 is saved in r10. 419d064151fSNicholas Piggin * PPR save and CPU accounting is not done (for some reason). 420d064151fSNicholas Piggin */ 421d064151fSNicholas Piggin#define EXCEPTION_COMMON_STACK(area, trap) \ 422d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_1(); \ 423d064151fSNicholas Piggin kuap_save_amr_and_lock r9, r10, cr1; \ 424d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_2(area); \ 425d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(trap) 426d064151fSNicholas Piggin 427d064151fSNicholas Piggin 42812a04809SNicholas Piggin#define RUNLATCH_ON \ 42912a04809SNicholas PigginBEGIN_FTR_SECTION \ 43012a04809SNicholas Piggin ld r3, PACA_THREAD_INFO(r13); \ 43112a04809SNicholas Piggin ld r4,TI_LOCAL_FLAGS(r3); \ 43212a04809SNicholas Piggin andi. r0,r4,_TLF_RUNLATCH; \ 43312a04809SNicholas Piggin beql ppc64_runlatch_on_trampoline; \ 43412a04809SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_CTRL) 43512a04809SNicholas Piggin 43612a04809SNicholas Piggin/* 43712a04809SNicholas Piggin * When the idle code in power4_idle puts the CPU into NAP mode, 43812a04809SNicholas Piggin * it has to do so in a loop, and relies on the external interrupt 43912a04809SNicholas Piggin * and decrementer interrupt entry code to get it out of the loop. 44012a04809SNicholas Piggin * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 44112a04809SNicholas Piggin * to signal that it is in the loop and needs help to get out. 44212a04809SNicholas Piggin */ 44312a04809SNicholas Piggin#ifdef CONFIG_PPC_970_NAP 44412a04809SNicholas Piggin#define FINISH_NAP \ 44512a04809SNicholas PigginBEGIN_FTR_SECTION \ 44612a04809SNicholas Piggin ld r11, PACA_THREAD_INFO(r13); \ 44712a04809SNicholas Piggin ld r9,TI_LOCAL_FLAGS(r11); \ 44812a04809SNicholas Piggin andi. r10,r9,_TLF_NAPPING; \ 44912a04809SNicholas Piggin bnel power4_fixup_nap; \ 45012a04809SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 45112a04809SNicholas Piggin#else 45212a04809SNicholas Piggin#define FINISH_NAP 45312a04809SNicholas Piggin#endif 45412a04809SNicholas Piggin 455a0502434SNicholas Piggin/* 456a0502434SNicholas Piggin * Following are the BOOK3S exception handler helper macros. 457a0502434SNicholas Piggin * Handlers come in a number of types, and each type has a number of varieties. 458a0502434SNicholas Piggin * 459a0502434SNicholas Piggin * EXC_REAL_* - real, unrelocated exception vectors 460a0502434SNicholas Piggin * EXC_VIRT_* - virt (AIL), unrelocated exception vectors 461a0502434SNicholas Piggin * TRAMP_REAL_* - real, unrelocated helpers (virt can call these) 462a0502434SNicholas Piggin * TRAMP_VIRT_* - virt, unreloc helpers (in practice, real can use) 463a0502434SNicholas Piggin * TRAMP_KVM - KVM handlers that get put into real, unrelocated 464a0502434SNicholas Piggin * EXC_COMMON - virt, relocated common handlers 465a0502434SNicholas Piggin * 466a0502434SNicholas Piggin * The EXC handlers are given a name, and branch to name_common, or the 467a0502434SNicholas Piggin * appropriate KVM or masking function. Vector handler verieties are as 468a0502434SNicholas Piggin * follows: 469a0502434SNicholas Piggin * 470a0502434SNicholas Piggin * EXC_{REAL|VIRT}_BEGIN/END - used to open-code the exception 471a0502434SNicholas Piggin * 472a0502434SNicholas Piggin * EXC_{REAL|VIRT} - standard exception 473a0502434SNicholas Piggin * 474a0502434SNicholas Piggin * EXC_{REAL|VIRT}_suffix 475a0502434SNicholas Piggin * where _suffix is: 476a0502434SNicholas Piggin * - _MASKABLE - maskable exception 477a0502434SNicholas Piggin * - _OOL - out of line with trampoline to common handler 478a0502434SNicholas Piggin * - _HV - HV exception 479a0502434SNicholas Piggin * 480a0502434SNicholas Piggin * There can be combinations, e.g., EXC_VIRT_OOL_MASKABLE_HV 481a0502434SNicholas Piggin * 482a0502434SNicholas Piggin * The one unusual case is __EXC_REAL_OOL_HV_DIRECT, which is 483a0502434SNicholas Piggin * an OOL vector that branches to a specified handler rather than the usual 484a0502434SNicholas Piggin * trampoline that goes to common. It, and other underscore macros, should 485a0502434SNicholas Piggin * be used with care. 486a0502434SNicholas Piggin * 487a0502434SNicholas Piggin * KVM handlers come in the following verieties: 488a0502434SNicholas Piggin * TRAMP_KVM 489a0502434SNicholas Piggin * TRAMP_KVM_SKIP 490a0502434SNicholas Piggin * TRAMP_KVM_HV 491a0502434SNicholas Piggin * TRAMP_KVM_HV_SKIP 492a0502434SNicholas Piggin * 493a0502434SNicholas Piggin * COMMON handlers come in the following verieties: 494a0502434SNicholas Piggin * EXC_COMMON_BEGIN/END - used to open-code the handler 495a0502434SNicholas Piggin * EXC_COMMON 496a0502434SNicholas Piggin * EXC_COMMON_ASYNC 497a0502434SNicholas Piggin * 498a0502434SNicholas Piggin * TRAMP_REAL and TRAMP_VIRT can be used with BEGIN/END. KVM 499a0502434SNicholas Piggin * and OOL handlers are implemented as types of TRAMP and TRAMP_VIRT handlers. 500a0502434SNicholas Piggin */ 501a0502434SNicholas Piggin 502a0502434SNicholas Piggin#define __EXC_REAL(name, start, size, area) \ 503a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 504a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 505a0502434SNicholas Piggin EXCEPTION_PROLOG_0 area ; \ 506a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0 ; \ 507a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ 508a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 509a0502434SNicholas Piggin 510a0502434SNicholas Piggin#define EXC_REAL(name, start, size) \ 511a0502434SNicholas Piggin __EXC_REAL(name, start, size, PACA_EXGEN) 512a0502434SNicholas Piggin 513a0502434SNicholas Piggin#define __EXC_VIRT(name, start, size, realvec, area) \ 514a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 515a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 516a0502434SNicholas Piggin EXCEPTION_PROLOG_0 area ; \ 517a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0; \ 518a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ 519a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 520a0502434SNicholas Piggin 521a0502434SNicholas Piggin#define EXC_VIRT(name, start, size, realvec) \ 522a0502434SNicholas Piggin __EXC_VIRT(name, start, size, realvec, PACA_EXGEN) 523a0502434SNicholas Piggin 524a0502434SNicholas Piggin#define EXC_REAL_MASKABLE(name, start, size, bitmask) \ 525a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 526a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 527a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 528a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, bitmask ; \ 529a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ 530a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 531a0502434SNicholas Piggin 532a0502434SNicholas Piggin#define EXC_VIRT_MASKABLE(name, start, size, realvec, bitmask) \ 533a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 534a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 535a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 536a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \ 537a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ 538a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 539a0502434SNicholas Piggin 540a0502434SNicholas Piggin#define EXC_REAL_HV(name, start, size) \ 541a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 542a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 543a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN; \ 544a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0 ; \ 545a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 ; \ 546a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 547a0502434SNicholas Piggin 548a0502434SNicholas Piggin#define EXC_VIRT_HV(name, start, size, realvec) \ 549a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 550a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 551a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN; \ 552a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \ 553a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV ; \ 554a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 555a0502434SNicholas Piggin 556a0502434SNicholas Piggin#define __EXC_REAL_OOL(name, start, size) \ 557a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 558a0502434SNicholas Piggin SET_SCRATCH0(r13); \ 559a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 560a0502434SNicholas Piggin b tramp_real_##name ; \ 561a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 562a0502434SNicholas Piggin 563a0502434SNicholas Piggin#define __TRAMP_REAL_OOL(name, vec) \ 564a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 565a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0 ; \ 566a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 567a0502434SNicholas Piggin 568a0502434SNicholas Piggin#define EXC_REAL_OOL(name, start, size) \ 569a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size); \ 570a0502434SNicholas Piggin __TRAMP_REAL_OOL(name, start) 571a0502434SNicholas Piggin 572a0502434SNicholas Piggin#define __EXC_REAL_OOL_MASKABLE(name, start, size) \ 573a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size) 574a0502434SNicholas Piggin 575a0502434SNicholas Piggin#define __TRAMP_REAL_OOL_MASKABLE(name, vec, bitmask) \ 576a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 577a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ; \ 578a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 579a0502434SNicholas Piggin 580a0502434SNicholas Piggin#define EXC_REAL_OOL_MASKABLE(name, start, size, bitmask) \ 581a0502434SNicholas Piggin __EXC_REAL_OOL_MASKABLE(name, start, size); \ 582a0502434SNicholas Piggin __TRAMP_REAL_OOL_MASKABLE(name, start, bitmask) 583a0502434SNicholas Piggin 584a0502434SNicholas Piggin#define __EXC_REAL_OOL_HV_DIRECT(name, start, size, handler) \ 585a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 586a0502434SNicholas Piggin SET_SCRATCH0(r13); \ 587a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 588a0502434SNicholas Piggin b handler; \ 589a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 590a0502434SNicholas Piggin 591a0502434SNicholas Piggin#define __EXC_REAL_OOL_HV(name, start, size) \ 592a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size) 593a0502434SNicholas Piggin 594a0502434SNicholas Piggin#define __TRAMP_REAL_OOL_HV(name, vec) \ 595a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 596a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \ 597a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 598a0502434SNicholas Piggin 599a0502434SNicholas Piggin#define EXC_REAL_OOL_HV(name, start, size) \ 600a0502434SNicholas Piggin __EXC_REAL_OOL_HV(name, start, size); \ 601a0502434SNicholas Piggin __TRAMP_REAL_OOL_HV(name, start) 602a0502434SNicholas Piggin 603a0502434SNicholas Piggin#define __EXC_REAL_OOL_MASKABLE_HV(name, start, size) \ 604a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size) 605a0502434SNicholas Piggin 606a0502434SNicholas Piggin#define __TRAMP_REAL_OOL_MASKABLE_HV(name, vec, bitmask) \ 607a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 608a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \ 609a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 610a0502434SNicholas Piggin 611a0502434SNicholas Piggin#define EXC_REAL_OOL_MASKABLE_HV(name, start, size, bitmask) \ 612a0502434SNicholas Piggin __EXC_REAL_OOL_MASKABLE_HV(name, start, size); \ 613a0502434SNicholas Piggin __TRAMP_REAL_OOL_MASKABLE_HV(name, start, bitmask) 614a0502434SNicholas Piggin 615a0502434SNicholas Piggin#define __EXC_VIRT_OOL(name, start, size) \ 616a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 617a0502434SNicholas Piggin SET_SCRATCH0(r13); \ 618a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 619a0502434SNicholas Piggin b tramp_virt_##name; \ 620a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 621a0502434SNicholas Piggin 622a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL(name, realvec) \ 623a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 624a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0 ; \ 625a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD 626a0502434SNicholas Piggin 627a0502434SNicholas Piggin#define EXC_VIRT_OOL(name, start, size, realvec) \ 628a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size); \ 629a0502434SNicholas Piggin __TRAMP_VIRT_OOL(name, realvec) 630a0502434SNicholas Piggin 631a0502434SNicholas Piggin#define __EXC_VIRT_OOL_MASKABLE(name, start, size) \ 632a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size) 633a0502434SNicholas Piggin 634a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) \ 635a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 636a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \ 637a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 638a0502434SNicholas Piggin 639a0502434SNicholas Piggin#define EXC_VIRT_OOL_MASKABLE(name, start, size, realvec, bitmask) \ 640a0502434SNicholas Piggin __EXC_VIRT_OOL_MASKABLE(name, start, size); \ 641a0502434SNicholas Piggin __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) 642a0502434SNicholas Piggin 643a0502434SNicholas Piggin#define __EXC_VIRT_OOL_HV(name, start, size) \ 644a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size) 645a0502434SNicholas Piggin 646a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL_HV(name, realvec) \ 647a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 648a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \ 649a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV 650a0502434SNicholas Piggin 651a0502434SNicholas Piggin#define EXC_VIRT_OOL_HV(name, start, size, realvec) \ 652a0502434SNicholas Piggin __EXC_VIRT_OOL_HV(name, start, size); \ 653a0502434SNicholas Piggin __TRAMP_VIRT_OOL_HV(name, realvec) 654a0502434SNicholas Piggin 655a0502434SNicholas Piggin#define __EXC_VIRT_OOL_MASKABLE_HV(name, start, size) \ 656a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size) 657a0502434SNicholas Piggin 658a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) \ 659a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 660a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, bitmask ; \ 661a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV 662a0502434SNicholas Piggin 663a0502434SNicholas Piggin#define EXC_VIRT_OOL_MASKABLE_HV(name, start, size, realvec, bitmask) \ 664a0502434SNicholas Piggin __EXC_VIRT_OOL_MASKABLE_HV(name, start, size); \ 665a0502434SNicholas Piggin __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) 666a0502434SNicholas Piggin 667a0502434SNicholas Piggin#define TRAMP_KVM(area, n) \ 668a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_##n); \ 669a0502434SNicholas Piggin KVM_HANDLER area, EXC_STD, n, 0 670a0502434SNicholas Piggin 671a0502434SNicholas Piggin#define TRAMP_KVM_SKIP(area, n) \ 672a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_##n); \ 673a0502434SNicholas Piggin KVM_HANDLER area, EXC_STD, n, 1 674a0502434SNicholas Piggin 675a0502434SNicholas Piggin#define TRAMP_KVM_HV(area, n) \ 676a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_H##n); \ 677a0502434SNicholas Piggin KVM_HANDLER area, EXC_HV, n, 0 678a0502434SNicholas Piggin 679a0502434SNicholas Piggin#define TRAMP_KVM_HV_SKIP(area, n) \ 680a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_H##n); \ 681a0502434SNicholas Piggin KVM_HANDLER area, EXC_HV, n, 1 682a0502434SNicholas Piggin 683a0502434SNicholas Piggin#define EXC_COMMON(name, realvec, hdlr) \ 684a0502434SNicholas Piggin EXC_COMMON_BEGIN(name); \ 685a0502434SNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, realvec); \ 686a0502434SNicholas Piggin bl save_nvgprs; \ 687a0502434SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11); \ 688a0502434SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD; \ 689a0502434SNicholas Piggin bl hdlr; \ 690a0502434SNicholas Piggin b ret_from_except 691a0502434SNicholas Piggin 692a0502434SNicholas Piggin/* 693a0502434SNicholas Piggin * Like EXC_COMMON, but for exceptions that can occur in the idle task and 694a0502434SNicholas Piggin * therefore need the special idle handling (finish nap and runlatch) 695a0502434SNicholas Piggin */ 696a0502434SNicholas Piggin#define EXC_COMMON_ASYNC(name, realvec, hdlr) \ 697a0502434SNicholas Piggin EXC_COMMON_BEGIN(name); \ 698a0502434SNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, realvec); \ 699a0502434SNicholas Piggin FINISH_NAP; \ 700a0502434SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11); \ 701a0502434SNicholas Piggin RUNLATCH_ON; \ 702a0502434SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD; \ 703a0502434SNicholas Piggin bl hdlr; \ 704a0502434SNicholas Piggin b ret_from_except_lite 705a0502434SNicholas Piggin 70612a04809SNicholas Piggin 70712a04809SNicholas Piggin/* 70857f26649SNicholas Piggin * There are a few constraints to be concerned with. 70957f26649SNicholas Piggin * - Real mode exceptions code/data must be located at their physical location. 71057f26649SNicholas Piggin * - Virtual mode exceptions must be mapped at their 0xc000... location. 71157f26649SNicholas Piggin * - Fixed location code must not call directly beyond the __end_interrupts 71257f26649SNicholas Piggin * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 71357f26649SNicholas Piggin * must be used. 71457f26649SNicholas Piggin * - LOAD_HANDLER targets must be within first 64K of physical 0 / 71557f26649SNicholas Piggin * virtual 0xc00... 71657f26649SNicholas Piggin * - Conditional branch targets must be within +/-32K of caller. 71757f26649SNicholas Piggin * 71857f26649SNicholas Piggin * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 71957f26649SNicholas Piggin * therefore don't have to run in physically located code or rfid to 72057f26649SNicholas Piggin * virtual mode kernel code. However on relocatable kernels they do have 72157f26649SNicholas Piggin * to branch to KERNELBASE offset because the rest of the kernel (outside 72257f26649SNicholas Piggin * the exception vectors) may be located elsewhere. 72357f26649SNicholas Piggin * 72457f26649SNicholas Piggin * Virtual exceptions correspond with physical, except their entry points 72557f26649SNicholas Piggin * are offset by 0xc000000000000000 and also tend to get an added 0x4000 72657f26649SNicholas Piggin * offset applied. Virtual exceptions are enabled with the Alternate 72757f26649SNicholas Piggin * Interrupt Location (AIL) bit set in the LPCR. However this does not 72857f26649SNicholas Piggin * guarantee they will be delivered virtually. Some conditions (see the ISA) 72957f26649SNicholas Piggin * cause exceptions to be delivered in real mode. 73057f26649SNicholas Piggin * 73157f26649SNicholas Piggin * It's impossible to receive interrupts below 0x300 via AIL. 73257f26649SNicholas Piggin * 73357f26649SNicholas Piggin * KVM: None of the virtual exceptions are from the guest. Anything that 73457f26649SNicholas Piggin * escalated to HV=1 from HV=0 is delivered via real mode handlers. 73557f26649SNicholas Piggin * 73657f26649SNicholas Piggin * 7370ebc4cdaSBenjamin Herrenschmidt * We layout physical memory as follows: 7380ebc4cdaSBenjamin Herrenschmidt * 0x0000 - 0x00ff : Secondary processor spin code 73957f26649SNicholas Piggin * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 74057f26649SNicholas Piggin * 0x1900 - 0x3fff : Real mode trampolines 74157f26649SNicholas Piggin * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 74257f26649SNicholas Piggin * 0x5900 - 0x6fff : Relon mode trampolines 7430ebc4cdaSBenjamin Herrenschmidt * 0x7000 - 0x7fff : FWNMI data area 74457f26649SNicholas Piggin * 0x8000 - .... : Common interrupt handlers, remaining early 74557f26649SNicholas Piggin * setup code, rest of kernel. 746e0319829SNicholas Piggin * 747e0319829SNicholas Piggin * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 748e0319829SNicholas Piggin * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 749e0319829SNicholas Piggin * vectors there. 7500ebc4cdaSBenjamin Herrenschmidt */ 75157f26649SNicholas PigginOPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 75257f26649SNicholas PigginOPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 75357f26649SNicholas PigginOPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 75457f26649SNicholas PigginOPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 755ccd47702SNicholas Piggin 756ccd47702SNicholas Piggin#ifdef CONFIG_PPC_POWERNV 757bd3524feSNicholas Piggin .globl start_real_trampolines 758bd3524feSNicholas Piggin .globl end_real_trampolines 759bd3524feSNicholas Piggin .globl start_virt_trampolines 760bd3524feSNicholas Piggin .globl end_virt_trampolines 761ccd47702SNicholas Piggin#endif 762ccd47702SNicholas Piggin 76357f26649SNicholas Piggin#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 76457f26649SNicholas Piggin/* 76557f26649SNicholas Piggin * Data area reserved for FWNMI option. 76657f26649SNicholas Piggin * This address (0x7000) is fixed by the RPA. 76757f26649SNicholas Piggin * pseries and powernv need to keep the whole page from 76857f26649SNicholas Piggin * 0x7000 to 0x8000 free for use by the firmware 76957f26649SNicholas Piggin */ 77057f26649SNicholas PigginZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 77157f26649SNicholas PigginOPEN_TEXT_SECTION(0x8000) 77257f26649SNicholas Piggin#else 77357f26649SNicholas PigginOPEN_TEXT_SECTION(0x7000) 77457f26649SNicholas Piggin#endif 77557f26649SNicholas Piggin 77657f26649SNicholas PigginUSE_FIXED_SECTION(real_vectors) 77757f26649SNicholas Piggin 7780ebc4cdaSBenjamin Herrenschmidt/* 7790ebc4cdaSBenjamin Herrenschmidt * This is the start of the interrupt handlers for pSeries 7800ebc4cdaSBenjamin Herrenschmidt * This code runs with relocation off. 7810ebc4cdaSBenjamin Herrenschmidt * Code from here to __end_interrupts gets copied down to real 7820ebc4cdaSBenjamin Herrenschmidt * address 0x100 when we are running a relocatable kernel. 7830ebc4cdaSBenjamin Herrenschmidt * Therefore any relative branches in this section must only 7840ebc4cdaSBenjamin Herrenschmidt * branch to labels in this section. 7850ebc4cdaSBenjamin Herrenschmidt */ 7860ebc4cdaSBenjamin Herrenschmidt .globl __start_interrupts 7870ebc4cdaSBenjamin Herrenschmidt__start_interrupts: 7880ebc4cdaSBenjamin Herrenschmidt 789e0319829SNicholas Piggin/* No virt vectors corresponding with 0x0..0x100 */ 7901a6822d1SNicholas PigginEXC_VIRT_NONE(0x4000, 0x100) 791e0319829SNicholas Piggin 792fb479e44SNicholas Piggin 793a7c1ca19SNicholas PigginEXC_REAL_BEGIN(system_reset, 0x100, 0x100) 794a7c1ca19SNicholas Piggin SET_SCRATCH0(r13) 7955dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXNMI 796a7c1ca19SNicholas Piggin 797a7c1ca19SNicholas Piggin /* This is EXCEPTION_PROLOG_1 with the idle feature section added */ 798a7c1ca19SNicholas Piggin OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_PPR, r9, CPU_FTR_HAS_PPR) 799a7c1ca19SNicholas Piggin OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_CFAR, r10, CPU_FTR_CFAR) 800a7c1ca19SNicholas Piggin INTERRUPT_TO_KERNEL 801a7c1ca19SNicholas Piggin SAVE_CTR(r10, PACA_EXNMI) 802a7c1ca19SNicholas Piggin mfcr r9 803a7c1ca19SNicholas Piggin 804fb479e44SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 805fb479e44SNicholas Piggin /* 806fb479e44SNicholas Piggin * If running native on arch 2.06 or later, check if we are waking up 807ba6d334aSBenjamin Herrenschmidt * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 808ba6d334aSBenjamin Herrenschmidt * bits 46:47. A non-0 value indicates that we are coming from a power 809ba6d334aSBenjamin Herrenschmidt * saving state. The idle wakeup handler initially runs in real mode, 810ba6d334aSBenjamin Herrenschmidt * but we branch to the 0xc000... address so we can turn on relocation 811ba6d334aSBenjamin Herrenschmidt * with mtmsr. 812fb479e44SNicholas Piggin */ 813a7c1ca19SNicholas PigginBEGIN_FTR_SECTION 814a7c1ca19SNicholas Piggin mfspr r10,SPRN_SRR1 815a7c1ca19SNicholas Piggin rlwinm. r10,r10,47-31,30,31 816a7c1ca19SNicholas Piggin beq- 1f 817a7c1ca19SNicholas Piggin cmpwi cr1,r10,2 818a7c1ca19SNicholas Piggin mfspr r3,SPRN_SRR1 819a7c1ca19SNicholas Piggin bltlr cr1 /* no state loss, return to idle caller */ 820a7c1ca19SNicholas Piggin BRANCH_TO_C000(r10, system_reset_idle_common) 821a7c1ca19SNicholas Piggin1: 822a7c1ca19SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 823fb479e44SNicholas Piggin#endif 824fb479e44SNicholas Piggin 825a7c1ca19SNicholas Piggin KVMTEST EXC_STD 0x100 826a7c1ca19SNicholas Piggin std r11,PACA_EXNMI+EX_R11(r13) 827a7c1ca19SNicholas Piggin std r12,PACA_EXNMI+EX_R12(r13) 828a7c1ca19SNicholas Piggin GET_SCRATCH0(r10) 829a7c1ca19SNicholas Piggin std r10,PACA_EXNMI+EX_R13(r13) 830a7c1ca19SNicholas Piggin 831a7c1ca19SNicholas Piggin EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 832c4f3b52cSNicholas Piggin /* 833c4f3b52cSNicholas Piggin * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 834c4f3b52cSNicholas Piggin * being used, so a nested NMI exception would corrupt it. 835c4f3b52cSNicholas Piggin */ 836371fefd6SPaul Mackerras 8371a6822d1SNicholas PigginEXC_REAL_END(system_reset, 0x100, 0x100) 8381a6822d1SNicholas PigginEXC_VIRT_NONE(0x4100, 0x100) 8396de6638bSNicholas PigginTRAMP_KVM(PACA_EXNMI, 0x100) 840fb479e44SNicholas Piggin 841fb479e44SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 842fb479e44SNicholas PigginEXC_COMMON_BEGIN(system_reset_idle_common) 84310d91611SNicholas Piggin /* 84410d91611SNicholas Piggin * This must be a direct branch (without linker branch stub) because 84510d91611SNicholas Piggin * we can not use TOC at this point as r2 may not be restored yet. 84610d91611SNicholas Piggin */ 84710d91611SNicholas Piggin b idle_return_gpr_loss 848371fefd6SPaul Mackerras#endif 849371fefd6SPaul Mackerras 850a3d96f70SNicholas PigginEXC_COMMON_BEGIN(system_reset_common) 851c4f3b52cSNicholas Piggin /* 852c4f3b52cSNicholas Piggin * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 853c4f3b52cSNicholas Piggin * to recover, but nested NMI will notice in_nmi and not recover 854c4f3b52cSNicholas Piggin * because of the use of the NMI stack. in_nmi reentrancy is tested in 855c4f3b52cSNicholas Piggin * system_reset_exception. 856c4f3b52cSNicholas Piggin */ 857c4f3b52cSNicholas Piggin lhz r10,PACA_IN_NMI(r13) 858c4f3b52cSNicholas Piggin addi r10,r10,1 859c4f3b52cSNicholas Piggin sth r10,PACA_IN_NMI(r13) 860c4f3b52cSNicholas Piggin li r10,MSR_RI 861c4f3b52cSNicholas Piggin mtmsrd r10,1 862aca79d2bSVaidyanathan Srinivasan 863b1ee8a3dSNicholas Piggin mr r10,r1 864b1ee8a3dSNicholas Piggin ld r1,PACA_NMI_EMERG_SP(r13) 865b1ee8a3dSNicholas Piggin subi r1,r1,INT_FRAME_SIZE 86647169fbaSNicholas Piggin EXCEPTION_COMMON_STACK(PACA_EXNMI, 0x100) 86747169fbaSNicholas Piggin bl save_nvgprs 86847169fbaSNicholas Piggin /* 86947169fbaSNicholas Piggin * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does 87047169fbaSNicholas Piggin * the right thing. We do not want to reconcile because that goes 87147169fbaSNicholas Piggin * through irq tracing which we don't want in NMI. 87247169fbaSNicholas Piggin * 87347169fbaSNicholas Piggin * Save PACAIRQHAPPENED because some code will do a hard disable 87447169fbaSNicholas Piggin * (e.g., xmon). So we want to restore this back to where it was 87547169fbaSNicholas Piggin * when we return. DAR is unused in the stack, so save it there. 87647169fbaSNicholas Piggin */ 87747169fbaSNicholas Piggin li r10,IRQS_ALL_DISABLED 87847169fbaSNicholas Piggin stb r10,PACAIRQSOFTMASK(r13) 87947169fbaSNicholas Piggin lbz r10,PACAIRQHAPPENED(r13) 88047169fbaSNicholas Piggin std r10,_DAR(r1) 88147169fbaSNicholas Piggin 882c06075f3SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 883c06075f3SNicholas Piggin bl system_reset_exception 88415b4dd79SNicholas Piggin 88515b4dd79SNicholas Piggin /* This (and MCE) can be simplified with mtmsrd L=1 */ 88615b4dd79SNicholas Piggin /* Clear MSR_RI before setting SRR0 and SRR1. */ 88715b4dd79SNicholas Piggin li r0,MSR_RI 88815b4dd79SNicholas Piggin mfmsr r9 88915b4dd79SNicholas Piggin andc r9,r9,r0 89015b4dd79SNicholas Piggin mtmsrd r9,1 891c4f3b52cSNicholas Piggin 892c4f3b52cSNicholas Piggin /* 89315b4dd79SNicholas Piggin * MSR_RI is clear, now we can decrement paca->in_nmi. 894c4f3b52cSNicholas Piggin */ 895c4f3b52cSNicholas Piggin lhz r10,PACA_IN_NMI(r13) 896c4f3b52cSNicholas Piggin subi r10,r10,1 897c4f3b52cSNicholas Piggin sth r10,PACA_IN_NMI(r13) 898c4f3b52cSNicholas Piggin 89915b4dd79SNicholas Piggin /* 90015b4dd79SNicholas Piggin * Restore soft mask settings. 90115b4dd79SNicholas Piggin */ 90215b4dd79SNicholas Piggin ld r10,_DAR(r1) 90315b4dd79SNicholas Piggin stb r10,PACAIRQHAPPENED(r13) 90415b4dd79SNicholas Piggin ld r10,SOFTE(r1) 90515b4dd79SNicholas Piggin stb r10,PACAIRQSOFTMASK(r13) 90615b4dd79SNicholas Piggin 90715b4dd79SNicholas Piggin /* 90815b4dd79SNicholas Piggin * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP. 90915b4dd79SNicholas Piggin * Should share common bits... 91015b4dd79SNicholas Piggin */ 91115b4dd79SNicholas Piggin 91215b4dd79SNicholas Piggin /* Move original SRR0 and SRR1 into the respective regs */ 91315b4dd79SNicholas Piggin ld r9,_MSR(r1) 91415b4dd79SNicholas Piggin mtspr SPRN_SRR1,r9 91515b4dd79SNicholas Piggin ld r3,_NIP(r1) 91615b4dd79SNicholas Piggin mtspr SPRN_SRR0,r3 91715b4dd79SNicholas Piggin ld r9,_CTR(r1) 91815b4dd79SNicholas Piggin mtctr r9 91915b4dd79SNicholas Piggin ld r9,_XER(r1) 92015b4dd79SNicholas Piggin mtxer r9 92115b4dd79SNicholas Piggin ld r9,_LINK(r1) 92215b4dd79SNicholas Piggin mtlr r9 92315b4dd79SNicholas Piggin REST_GPR(0, r1) 92415b4dd79SNicholas Piggin REST_8GPRS(2, r1) 92515b4dd79SNicholas Piggin REST_GPR(10, r1) 92615b4dd79SNicholas Piggin ld r11,_CCR(r1) 92715b4dd79SNicholas Piggin mtcr r11 92815b4dd79SNicholas Piggin REST_GPR(11, r1) 92915b4dd79SNicholas Piggin REST_2GPRS(12, r1) 93015b4dd79SNicholas Piggin /* restore original r1. */ 93115b4dd79SNicholas Piggin ld r1,GPR1(r1) 93215b4dd79SNicholas Piggin RFI_TO_USER_OR_KERNEL 933582baf44SNicholas Piggin 934582baf44SNicholas Piggin#ifdef CONFIG_PPC_PSERIES 935582baf44SNicholas Piggin/* 936582baf44SNicholas Piggin * Vectors for the FWNMI option. Share common code. 937582baf44SNicholas Piggin */ 938582baf44SNicholas PigginTRAMP_REAL_BEGIN(system_reset_fwnmi) 939582baf44SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 940fc557537SNicholas Piggin /* See comment at system_reset exception, don't turn on RI */ 941fc557537SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXNMI 942fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0 943fc557537SNicholas Piggin EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 944fc557537SNicholas Piggin 945582baf44SNicholas Piggin#endif /* CONFIG_PPC_PSERIES */ 946582baf44SNicholas Piggin 9470ebc4cdaSBenjamin Herrenschmidt 9481a6822d1SNicholas PigginEXC_REAL_BEGIN(machine_check, 0x200, 0x100) 949b01c8b54SPaul Mackerras /* This is moved out of line as it can be patched by FW, but 950b01c8b54SPaul Mackerras * some code path might still want to branch into the original 951b01c8b54SPaul Mackerras * vector 952b01c8b54SPaul Mackerras */ 9531707dd16SPaul Mackerras SET_SCRATCH0(r13) /* save r13 */ 9545dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXMC 9551e9b4507SMahesh SalgaonkarBEGIN_FTR_SECTION 956db7d31acSMahesh Salgaonkar b machine_check_common_early 9571e9b4507SMahesh SalgaonkarFTR_SECTION_ELSE 9581707dd16SPaul Mackerras b machine_check_pSeries_0 9591e9b4507SMahesh SalgaonkarALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 9601a6822d1SNicholas PigginEXC_REAL_END(machine_check, 0x200, 0x100) 9611a6822d1SNicholas PigginEXC_VIRT_NONE(0x4200, 0x100) 962db7d31acSMahesh SalgaonkarTRAMP_REAL_BEGIN(machine_check_common_early) 963fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0 964afcf0095SNicholas Piggin /* 965afcf0095SNicholas Piggin * Register contents: 966afcf0095SNicholas Piggin * R13 = PACA 967afcf0095SNicholas Piggin * R9 = CR 968afcf0095SNicholas Piggin * Original R9 to R13 is saved on PACA_EXMC 969afcf0095SNicholas Piggin * 970afcf0095SNicholas Piggin * Switch to mc_emergency stack and handle re-entrancy (we limit 971afcf0095SNicholas Piggin * the nested MCE upto level 4 to avoid stack overflow). 972afcf0095SNicholas Piggin * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 973afcf0095SNicholas Piggin * 974afcf0095SNicholas Piggin * We use paca->in_mce to check whether this is the first entry or 975afcf0095SNicholas Piggin * nested machine check. We increment paca->in_mce to track nested 976afcf0095SNicholas Piggin * machine checks. 977afcf0095SNicholas Piggin * 978afcf0095SNicholas Piggin * If this is the first entry then set stack pointer to 979afcf0095SNicholas Piggin * paca->mc_emergency_sp, otherwise r1 is already pointing to 980afcf0095SNicholas Piggin * stack frame on mc_emergency stack. 981afcf0095SNicholas Piggin * 982afcf0095SNicholas Piggin * NOTE: We are here with MSR_ME=0 (off), which means we risk a 983afcf0095SNicholas Piggin * checkstop if we get another machine check exception before we do 984afcf0095SNicholas Piggin * rfid with MSR_ME=1. 9851945bc45SNicholas Piggin * 9861945bc45SNicholas Piggin * This interrupt can wake directly from idle. If that is the case, 9871945bc45SNicholas Piggin * the machine check is handled then the idle wakeup code is called 9882bf1071aSNicholas Piggin * to restore state. 989afcf0095SNicholas Piggin */ 990afcf0095SNicholas Piggin mr r11,r1 /* Save r1 */ 991afcf0095SNicholas Piggin lhz r10,PACA_IN_MCE(r13) 992afcf0095SNicholas Piggin cmpwi r10,0 /* Are we in nested machine check */ 993afcf0095SNicholas Piggin bne 0f /* Yes, we are. */ 994afcf0095SNicholas Piggin /* First machine check entry */ 995afcf0095SNicholas Piggin ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 996afcf0095SNicholas Piggin0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 997afcf0095SNicholas Piggin addi r10,r10,1 /* increment paca->in_mce */ 998afcf0095SNicholas Piggin sth r10,PACA_IN_MCE(r13) 999afcf0095SNicholas Piggin /* Limit nested MCE to level 4 to avoid stack overflow */ 1000ba41e1e1SBalbir Singh cmpwi r10,MAX_MCE_DEPTH 1001afcf0095SNicholas Piggin bgt 2f /* Check if we hit limit of 4 */ 1002afcf0095SNicholas Piggin std r11,GPR1(r1) /* Save r1 on the stack. */ 1003afcf0095SNicholas Piggin std r11,0(r1) /* make stack chain pointer */ 1004afcf0095SNicholas Piggin mfspr r11,SPRN_SRR0 /* Save SRR0 */ 1005afcf0095SNicholas Piggin std r11,_NIP(r1) 1006afcf0095SNicholas Piggin mfspr r11,SPRN_SRR1 /* Save SRR1 */ 1007afcf0095SNicholas Piggin std r11,_MSR(r1) 1008afcf0095SNicholas Piggin mfspr r11,SPRN_DAR /* Save DAR */ 1009afcf0095SNicholas Piggin std r11,_DAR(r1) 1010afcf0095SNicholas Piggin mfspr r11,SPRN_DSISR /* Save DSISR */ 1011afcf0095SNicholas Piggin std r11,_DSISR(r1) 1012afcf0095SNicholas Piggin std r9,_CCR(r1) /* Save CR in stackframe */ 1013e13e7cd4SNicholas Piggin /* We don't touch AMR here, we never go to virtual mode */ 1014afcf0095SNicholas Piggin /* Save r9 through r13 from EXMC save area to stack frame. */ 1015afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 1016afcf0095SNicholas Piggin mfmsr r11 /* get MSR value */ 1017db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1018afcf0095SNicholas Piggin ori r11,r11,MSR_ME /* turn on ME bit */ 1019db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1020afcf0095SNicholas Piggin ori r11,r11,MSR_RI /* turn on RI bit */ 1021afcf0095SNicholas Piggin LOAD_HANDLER(r12, machine_check_handle_early) 1022afcf0095SNicholas Piggin1: mtspr SPRN_SRR0,r12 1023afcf0095SNicholas Piggin mtspr SPRN_SRR1,r11 1024222f20f1SNicholas Piggin RFI_TO_KERNEL 1025afcf0095SNicholas Piggin b . /* prevent speculative execution */ 1026afcf0095SNicholas Piggin2: 1027afcf0095SNicholas Piggin /* Stack overflow. Stay on emergency stack and panic. 1028afcf0095SNicholas Piggin * Keep the ME bit off while panic-ing, so that if we hit 1029afcf0095SNicholas Piggin * another machine check we checkstop. 1030afcf0095SNicholas Piggin */ 1031afcf0095SNicholas Piggin addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 1032afcf0095SNicholas Piggin ld r11,PACAKMSR(r13) 1033afcf0095SNicholas Piggin LOAD_HANDLER(r12, unrecover_mce) 1034afcf0095SNicholas Piggin li r10,MSR_ME 1035afcf0095SNicholas Piggin andc r11,r11,r10 /* Turn off MSR_ME */ 1036afcf0095SNicholas Piggin b 1b 1037afcf0095SNicholas Piggin b . /* prevent speculative execution */ 1038afcf0095SNicholas Piggin 1039afcf0095SNicholas PigginTRAMP_REAL_BEGIN(machine_check_pSeries) 1040afcf0095SNicholas Piggin .globl machine_check_fwnmi 1041afcf0095SNicholas Pigginmachine_check_fwnmi: 1042afcf0095SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 10435dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXMC 1044a43c1590SMahesh SalgaonkarBEGIN_FTR_SECTION 1045db7d31acSMahesh Salgaonkar b machine_check_common_early 1046a43c1590SMahesh SalgaonkarEND_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 1047afcf0095SNicholas Pigginmachine_check_pSeries_0: 1048fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0 1049afcf0095SNicholas Piggin /* 105083a980f7SNicholas Piggin * MSR_RI is not enabled, because PACA_EXMC is being used, so a 105183a980f7SNicholas Piggin * nested machine check corrupts it. machine_check_common enables 105283a980f7SNicholas Piggin * MSR_RI. 1053afcf0095SNicholas Piggin */ 10542d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0 1055afcf0095SNicholas Piggin 1056afcf0095SNicholas PigginTRAMP_KVM_SKIP(PACA_EXMC, 0x200) 1057afcf0095SNicholas Piggin 1058afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_common) 1059afcf0095SNicholas Piggin /* 1060afcf0095SNicholas Piggin * Machine check is different because we use a different 1061afcf0095SNicholas Piggin * save area: PACA_EXMC instead of PACA_EXGEN. 1062afcf0095SNicholas Piggin */ 1063afcf0095SNicholas Piggin mfspr r10,SPRN_DAR 1064afcf0095SNicholas Piggin std r10,PACA_EXMC+EX_DAR(r13) 1065afcf0095SNicholas Piggin mfspr r10,SPRN_DSISR 1066afcf0095SNicholas Piggin stw r10,PACA_EXMC+EX_DSISR(r13) 1067d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXMC, 0x200) 1068afcf0095SNicholas Piggin FINISH_NAP 1069afcf0095SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1070afcf0095SNicholas Piggin ld r3,PACA_EXMC+EX_DAR(r13) 1071afcf0095SNicholas Piggin lwz r4,PACA_EXMC+EX_DSISR(r13) 1072afcf0095SNicholas Piggin /* Enable MSR_RI when finished with PACA_EXMC */ 1073afcf0095SNicholas Piggin li r10,MSR_RI 1074afcf0095SNicholas Piggin mtmsrd r10,1 1075afcf0095SNicholas Piggin std r3,_DAR(r1) 1076afcf0095SNicholas Piggin std r4,_DSISR(r1) 1077afcf0095SNicholas Piggin bl save_nvgprs 1078afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1079afcf0095SNicholas Piggin bl machine_check_exception 1080afcf0095SNicholas Piggin b ret_from_except 1081afcf0095SNicholas Piggin 1082afcf0095SNicholas Piggin#define MACHINE_CHECK_HANDLER_WINDUP \ 1083afcf0095SNicholas Piggin /* Clear MSR_RI before setting SRR0 and SRR1. */\ 1084afcf0095SNicholas Piggin li r0,MSR_RI; \ 1085afcf0095SNicholas Piggin mfmsr r9; /* get MSR value */ \ 1086afcf0095SNicholas Piggin andc r9,r9,r0; \ 1087afcf0095SNicholas Piggin mtmsrd r9,1; /* Clear MSR_RI */ \ 1088afcf0095SNicholas Piggin /* Move original SRR0 and SRR1 into the respective regs */ \ 1089afcf0095SNicholas Piggin ld r9,_MSR(r1); \ 1090afcf0095SNicholas Piggin mtspr SPRN_SRR1,r9; \ 1091afcf0095SNicholas Piggin ld r3,_NIP(r1); \ 1092afcf0095SNicholas Piggin mtspr SPRN_SRR0,r3; \ 1093afcf0095SNicholas Piggin ld r9,_CTR(r1); \ 1094afcf0095SNicholas Piggin mtctr r9; \ 1095afcf0095SNicholas Piggin ld r9,_XER(r1); \ 1096afcf0095SNicholas Piggin mtxer r9; \ 1097afcf0095SNicholas Piggin ld r9,_LINK(r1); \ 1098afcf0095SNicholas Piggin mtlr r9; \ 1099afcf0095SNicholas Piggin REST_GPR(0, r1); \ 1100afcf0095SNicholas Piggin REST_8GPRS(2, r1); \ 1101afcf0095SNicholas Piggin REST_GPR(10, r1); \ 1102afcf0095SNicholas Piggin ld r11,_CCR(r1); \ 1103afcf0095SNicholas Piggin mtcr r11; \ 1104afcf0095SNicholas Piggin /* Decrement paca->in_mce. */ \ 1105afcf0095SNicholas Piggin lhz r12,PACA_IN_MCE(r13); \ 1106afcf0095SNicholas Piggin subi r12,r12,1; \ 1107afcf0095SNicholas Piggin sth r12,PACA_IN_MCE(r13); \ 1108afcf0095SNicholas Piggin REST_GPR(11, r1); \ 1109afcf0095SNicholas Piggin REST_2GPRS(12, r1); \ 1110afcf0095SNicholas Piggin /* restore original r1. */ \ 1111afcf0095SNicholas Piggin ld r1,GPR1(r1) 1112afcf0095SNicholas Piggin 11131945bc45SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 11141945bc45SNicholas Piggin/* 11151945bc45SNicholas Piggin * This is an idle wakeup. Low level machine check has already been 11161945bc45SNicholas Piggin * done. Queue the event then call the idle code to do the wake up. 11171945bc45SNicholas Piggin */ 11181945bc45SNicholas PigginEXC_COMMON_BEGIN(machine_check_idle_common) 11191945bc45SNicholas Piggin bl machine_check_queue_event 11201945bc45SNicholas Piggin 11211945bc45SNicholas Piggin /* 11221945bc45SNicholas Piggin * We have not used any non-volatile GPRs here, and as a rule 11231945bc45SNicholas Piggin * most exception code including machine check does not. 11241945bc45SNicholas Piggin * Therefore PACA_NAPSTATELOST does not need to be set. Idle 11251945bc45SNicholas Piggin * wakeup will restore volatile registers. 11261945bc45SNicholas Piggin * 11271945bc45SNicholas Piggin * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. 11281945bc45SNicholas Piggin * 11291945bc45SNicholas Piggin * Then decrement MCE nesting after finishing with the stack. 11301945bc45SNicholas Piggin */ 11311945bc45SNicholas Piggin ld r3,_MSR(r1) 113210d91611SNicholas Piggin ld r4,_LINK(r1) 11331945bc45SNicholas Piggin 11341945bc45SNicholas Piggin lhz r11,PACA_IN_MCE(r13) 11351945bc45SNicholas Piggin subi r11,r11,1 11361945bc45SNicholas Piggin sth r11,PACA_IN_MCE(r13) 11371945bc45SNicholas Piggin 113810d91611SNicholas Piggin mtlr r4 113910d91611SNicholas Piggin rlwinm r10,r3,47-31,30,31 114010d91611SNicholas Piggin cmpwi cr1,r10,2 114110d91611SNicholas Piggin bltlr cr1 /* no state loss, return to idle caller */ 114210d91611SNicholas Piggin b idle_return_gpr_loss 11431945bc45SNicholas Piggin#endif 1144afcf0095SNicholas Piggin /* 1145afcf0095SNicholas Piggin * Handle machine check early in real mode. We come here with 1146afcf0095SNicholas Piggin * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 1147afcf0095SNicholas Piggin */ 1148afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_handle_early) 1149afcf0095SNicholas Piggin std r0,GPR0(r1) /* Save r0 */ 1150afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_3(0x200) 1151afcf0095SNicholas Piggin bl save_nvgprs 1152afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1153afcf0095SNicholas Piggin bl machine_check_early 1154afcf0095SNicholas Piggin std r3,RESULT(r1) /* Save result */ 1155afcf0095SNicholas Piggin ld r12,_MSR(r1) 1156db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1157db7d31acSMahesh Salgaonkar b 4f 1158db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 11591945bc45SNicholas Piggin 1160afcf0095SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 1161afcf0095SNicholas Piggin /* 1162afcf0095SNicholas Piggin * Check if thread was in power saving mode. We come here when any 1163afcf0095SNicholas Piggin * of the following is true: 1164afcf0095SNicholas Piggin * a. thread wasn't in power saving mode 1165afcf0095SNicholas Piggin * b. thread was in power saving mode with no state loss, 1166afcf0095SNicholas Piggin * supervisor state loss or hypervisor state loss. 1167afcf0095SNicholas Piggin * 1168afcf0095SNicholas Piggin * Go back to nap/sleep/winkle mode again if (b) is true. 1169afcf0095SNicholas Piggin */ 11701945bc45SNicholas PigginBEGIN_FTR_SECTION 11711945bc45SNicholas Piggin rlwinm. r11,r12,47-31,30,31 11726102c005SNicholas Piggin bne machine_check_idle_common 11731945bc45SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 1174afcf0095SNicholas Piggin#endif 11751945bc45SNicholas Piggin 1176afcf0095SNicholas Piggin /* 1177afcf0095SNicholas Piggin * Check if we are coming from hypervisor userspace. If yes then we 1178afcf0095SNicholas Piggin * continue in host kernel in V mode to deliver the MC event. 1179afcf0095SNicholas Piggin */ 1180afcf0095SNicholas Piggin rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 1181afcf0095SNicholas Piggin beq 5f 1182db7d31acSMahesh Salgaonkar4: andi. r11,r12,MSR_PR /* See if coming from user. */ 1183afcf0095SNicholas Piggin bne 9f /* continue in V mode if we are. */ 1184afcf0095SNicholas Piggin 1185afcf0095SNicholas Piggin5: 1186afcf0095SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1187db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1188afcf0095SNicholas Piggin /* 1189afcf0095SNicholas Piggin * We are coming from kernel context. Check if we are coming from 1190afcf0095SNicholas Piggin * guest. if yes, then we can continue. We will fall through 1191afcf0095SNicholas Piggin * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 1192afcf0095SNicholas Piggin */ 1193afcf0095SNicholas Piggin lbz r11,HSTATE_IN_GUEST(r13) 1194afcf0095SNicholas Piggin cmpwi r11,0 /* Check if coming from guest */ 1195afcf0095SNicholas Piggin bne 9f /* continue if we are. */ 1196db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1197afcf0095SNicholas Piggin#endif 1198afcf0095SNicholas Piggin /* 1199afcf0095SNicholas Piggin * At this point we are not sure about what context we come from. 1200afcf0095SNicholas Piggin * Queue up the MCE event and return from the interrupt. 1201afcf0095SNicholas Piggin * But before that, check if this is an un-recoverable exception. 1202afcf0095SNicholas Piggin * If yes, then stay on emergency stack and panic. 1203afcf0095SNicholas Piggin */ 1204afcf0095SNicholas Piggin andi. r11,r12,MSR_RI 1205afcf0095SNicholas Piggin bne 2f 1206afcf0095SNicholas Piggin1: mfspr r11,SPRN_SRR0 1207afcf0095SNicholas Piggin LOAD_HANDLER(r10,unrecover_mce) 1208afcf0095SNicholas Piggin mtspr SPRN_SRR0,r10 1209afcf0095SNicholas Piggin ld r10,PACAKMSR(r13) 1210afcf0095SNicholas Piggin /* 1211afcf0095SNicholas Piggin * We are going down. But there are chances that we might get hit by 1212afcf0095SNicholas Piggin * another MCE during panic path and we may run into unstable state 1213afcf0095SNicholas Piggin * with no way out. Hence, turn ME bit off while going down, so that 1214afcf0095SNicholas Piggin * when another MCE is hit during panic path, system will checkstop 1215afcf0095SNicholas Piggin * and hypervisor will get restarted cleanly by SP. 1216afcf0095SNicholas Piggin */ 1217afcf0095SNicholas Piggin li r3,MSR_ME 1218afcf0095SNicholas Piggin andc r10,r10,r3 /* Turn off MSR_ME */ 1219afcf0095SNicholas Piggin mtspr SPRN_SRR1,r10 1220222f20f1SNicholas Piggin RFI_TO_KERNEL 1221afcf0095SNicholas Piggin b . 1222afcf0095SNicholas Piggin2: 1223afcf0095SNicholas Piggin /* 1224afcf0095SNicholas Piggin * Check if we have successfully handled/recovered from error, if not 1225afcf0095SNicholas Piggin * then stay on emergency stack and panic. 1226afcf0095SNicholas Piggin */ 1227afcf0095SNicholas Piggin ld r3,RESULT(r1) /* Load result */ 1228afcf0095SNicholas Piggin cmpdi r3,0 /* see if we handled MCE successfully */ 1229afcf0095SNicholas Piggin 1230afcf0095SNicholas Piggin beq 1b /* if !handled then panic */ 1231db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1232afcf0095SNicholas Piggin /* 1233afcf0095SNicholas Piggin * Return from MC interrupt. 1234afcf0095SNicholas Piggin * Queue up the MCE event so that we can log it later, while 1235afcf0095SNicholas Piggin * returning from kernel or opal call. 1236afcf0095SNicholas Piggin */ 1237afcf0095SNicholas Piggin bl machine_check_queue_event 1238afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 1239222f20f1SNicholas Piggin RFI_TO_USER_OR_KERNEL 1240db7d31acSMahesh SalgaonkarFTR_SECTION_ELSE 1241db7d31acSMahesh Salgaonkar /* 1242db7d31acSMahesh Salgaonkar * pSeries: Return from MC interrupt. Before that stay on emergency 1243db7d31acSMahesh Salgaonkar * stack and call machine_check_exception to log the MCE event. 1244db7d31acSMahesh Salgaonkar */ 1245db7d31acSMahesh Salgaonkar LOAD_HANDLER(r10,mce_return) 1246db7d31acSMahesh Salgaonkar mtspr SPRN_SRR0,r10 1247db7d31acSMahesh Salgaonkar ld r10,PACAKMSR(r13) 1248db7d31acSMahesh Salgaonkar mtspr SPRN_SRR1,r10 1249db7d31acSMahesh Salgaonkar RFI_TO_KERNEL 1250db7d31acSMahesh Salgaonkar b . 1251db7d31acSMahesh SalgaonkarALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 1252afcf0095SNicholas Piggin9: 1253afcf0095SNicholas Piggin /* Deliver the machine check to host kernel in V mode. */ 1254afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 1255db7d31acSMahesh Salgaonkar SET_SCRATCH0(r13) /* save r13 */ 12565dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXMC 1257db7d31acSMahesh Salgaonkar b machine_check_pSeries_0 1258afcf0095SNicholas Piggin 1259afcf0095SNicholas PigginEXC_COMMON_BEGIN(unrecover_mce) 1260afcf0095SNicholas Piggin /* Invoke machine_check_exception to print MCE event and panic. */ 1261afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1262afcf0095SNicholas Piggin bl machine_check_exception 1263afcf0095SNicholas Piggin /* 1264afcf0095SNicholas Piggin * We will not reach here. Even if we did, there is no way out. Call 1265afcf0095SNicholas Piggin * unrecoverable_exception and die. 1266afcf0095SNicholas Piggin */ 1267afcf0095SNicholas Piggin1: addi r3,r1,STACK_FRAME_OVERHEAD 1268afcf0095SNicholas Piggin bl unrecoverable_exception 1269afcf0095SNicholas Piggin b 1b 1270afcf0095SNicholas Piggin 1271a43c1590SMahesh SalgaonkarEXC_COMMON_BEGIN(mce_return) 1272a43c1590SMahesh Salgaonkar /* Invoke machine_check_exception to print MCE event and return. */ 1273a43c1590SMahesh Salgaonkar addi r3,r1,STACK_FRAME_OVERHEAD 1274a43c1590SMahesh Salgaonkar bl machine_check_exception 1275db7d31acSMahesh Salgaonkar MACHINE_CHECK_HANDLER_WINDUP 1276a43c1590SMahesh Salgaonkar RFI_TO_KERNEL 1277a43c1590SMahesh Salgaonkar b . 12780ebc4cdaSBenjamin Herrenschmidt 1279e779fc93SNicholas PigginEXC_REAL_BEGIN(data_access, 0x300, 0x80) 1280e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 12815dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1282e779fc93SNicholas Piggin b tramp_real_data_access 1283e779fc93SNicholas PigginEXC_REAL_END(data_access, 0x300, 0x80) 1284e779fc93SNicholas Piggin 1285e779fc93SNicholas PigginTRAMP_REAL_BEGIN(tramp_real_data_access) 1286fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0 128738555434SNicholas Piggin /* 128838555434SNicholas Piggin * DAR/DSISR must be read before setting MSR[RI], because 128938555434SNicholas Piggin * a d-side MCE will clobber those registers so is not 129038555434SNicholas Piggin * recoverable if they are live. 129138555434SNicholas Piggin */ 129238555434SNicholas Piggin mfspr r10,SPRN_DAR 129338555434SNicholas Piggin mfspr r11,SPRN_DSISR 129438555434SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 129538555434SNicholas Piggin stw r11,PACA_EXGEN+EX_DSISR(r13) 12962d046308SNicholas PigginEXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1 1297e779fc93SNicholas Piggin 1298e779fc93SNicholas PigginEXC_VIRT_BEGIN(data_access, 0x4300, 0x80) 1299e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 13005dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1301fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0 130238555434SNicholas Piggin mfspr r10,SPRN_DAR 130338555434SNicholas Piggin mfspr r11,SPRN_DSISR 130438555434SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 130538555434SNicholas Piggin stw r11,PACA_EXGEN+EX_DSISR(r13) 13062d046308SNicholas PigginEXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD 1307e779fc93SNicholas PigginEXC_VIRT_END(data_access, 0x4300, 0x80) 1308e779fc93SNicholas Piggin 130980795e6cSNicholas PigginTRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 131080795e6cSNicholas Piggin 131180795e6cSNicholas PigginEXC_COMMON_BEGIN(data_access_common) 131280795e6cSNicholas Piggin /* 131380795e6cSNicholas Piggin * Here r13 points to the paca, r9 contains the saved CR, 131480795e6cSNicholas Piggin * SRR0 and SRR1 are saved in r11 and r12, 131580795e6cSNicholas Piggin * r9 - r13 are saved in paca->exgen. 131638555434SNicholas Piggin * EX_DAR and EX_DSISR have saved DAR/DSISR 131780795e6cSNicholas Piggin */ 1318d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x300) 131980795e6cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 132080795e6cSNicholas Piggin ld r12,_MSR(r1) 132180795e6cSNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 132280795e6cSNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 132380795e6cSNicholas Piggin li r5,0x300 132480795e6cSNicholas Piggin std r3,_DAR(r1) 132580795e6cSNicholas Piggin std r4,_DSISR(r1) 132680795e6cSNicholas PigginBEGIN_MMU_FTR_SECTION 132780795e6cSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 132880795e6cSNicholas PigginMMU_FTR_SECTION_ELSE 132980795e6cSNicholas Piggin b handle_page_fault 133080795e6cSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 133180795e6cSNicholas Piggin 13320ebc4cdaSBenjamin Herrenschmidt 13331a6822d1SNicholas PigginEXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 1334e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 13355dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXSLB 1336e779fc93SNicholas Piggin b tramp_real_data_access_slb 13371a6822d1SNicholas PigginEXC_REAL_END(data_access_slb, 0x380, 0x80) 13380ebc4cdaSBenjamin Herrenschmidt 1339e779fc93SNicholas PigginTRAMP_REAL_BEGIN(tramp_real_data_access_slb) 1340fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0 134138555434SNicholas Piggin mfspr r10,SPRN_DAR 134238555434SNicholas Piggin std r10,PACA_EXSLB+EX_DAR(r13) 13432d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1 1344e779fc93SNicholas Piggin 13451a6822d1SNicholas PigginEXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 1346e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 13475dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXSLB 1348fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0 134938555434SNicholas Piggin mfspr r10,SPRN_DAR 135038555434SNicholas Piggin std r10,PACA_EXSLB+EX_DAR(r13) 13512d046308SNicholas Piggin EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD 13521a6822d1SNicholas PigginEXC_VIRT_END(data_access_slb, 0x4380, 0x80) 135348e7b769SNicholas Piggin 13542b9af6e4SNicholas PigginTRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 13552b9af6e4SNicholas Piggin 135648e7b769SNicholas PigginEXC_COMMON_BEGIN(data_access_slb_common) 1357d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXSLB, 0x380) 135848e7b769SNicholas Piggin ld r4,PACA_EXSLB+EX_DAR(r13) 135948e7b769SNicholas Piggin std r4,_DAR(r1) 136048e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 13617100e870SNicholas PigginBEGIN_MMU_FTR_SECTION 13627100e870SNicholas Piggin /* HPT case, do SLB fault */ 136348e7b769SNicholas Piggin bl do_slb_fault 136448e7b769SNicholas Piggin cmpdi r3,0 136548e7b769SNicholas Piggin bne- 1f 136648e7b769SNicholas Piggin b fast_exception_return 136748e7b769SNicholas Piggin1: /* Error case */ 13687100e870SNicholas PigginMMU_FTR_SECTION_ELSE 13697100e870SNicholas Piggin /* Radix case, access is outside page table range */ 13707100e870SNicholas Piggin li r3,-EFAULT 13717100e870SNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 137248e7b769SNicholas Piggin std r3,RESULT(r1) 137348e7b769SNicholas Piggin bl save_nvgprs 137448e7b769SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 137548e7b769SNicholas Piggin ld r4,_DAR(r1) 137648e7b769SNicholas Piggin ld r5,RESULT(r1) 137748e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 137848e7b769SNicholas Piggin bl do_bad_slb_fault 137948e7b769SNicholas Piggin b ret_from_except 138048e7b769SNicholas Piggin 13812b9af6e4SNicholas Piggin 13821a6822d1SNicholas PigginEXC_REAL(instruction_access, 0x400, 0x80) 13831a6822d1SNicholas PigginEXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) 138427ce77dfSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x400) 138527ce77dfSNicholas Piggin 138627ce77dfSNicholas PigginEXC_COMMON_BEGIN(instruction_access_common) 1387d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x400) 138827ce77dfSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 138927ce77dfSNicholas Piggin ld r12,_MSR(r1) 139027ce77dfSNicholas Piggin ld r3,_NIP(r1) 1391475b581fSMichael Ellerman andis. r4,r12,DSISR_SRR1_MATCH_64S@h 139227ce77dfSNicholas Piggin li r5,0x400 139327ce77dfSNicholas Piggin std r3,_DAR(r1) 139427ce77dfSNicholas Piggin std r4,_DSISR(r1) 139527ce77dfSNicholas PigginBEGIN_MMU_FTR_SECTION 139627ce77dfSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 139727ce77dfSNicholas PigginMMU_FTR_SECTION_ELSE 139827ce77dfSNicholas Piggin b handle_page_fault 139927ce77dfSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 140027ce77dfSNicholas Piggin 14010ebc4cdaSBenjamin Herrenschmidt 1402fc557537SNicholas Piggin__EXC_REAL(instruction_access_slb, 0x480, 0x80, PACA_EXSLB) 1403fc557537SNicholas Piggin__EXC_VIRT(instruction_access_slb, 0x4480, 0x80, 0x480, PACA_EXSLB) 14048d04631aSNicholas PigginTRAMP_KVM(PACA_EXSLB, 0x480) 14058d04631aSNicholas Piggin 140648e7b769SNicholas PigginEXC_COMMON_BEGIN(instruction_access_slb_common) 1407d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXSLB, 0x480) 140848e7b769SNicholas Piggin ld r4,_NIP(r1) 140954be0b9cSMichael Ellerman addi r3,r1,STACK_FRAME_OVERHEAD 14107100e870SNicholas PigginBEGIN_MMU_FTR_SECTION 14117100e870SNicholas Piggin /* HPT case, do SLB fault */ 141248e7b769SNicholas Piggin bl do_slb_fault 141348e7b769SNicholas Piggin cmpdi r3,0 141448e7b769SNicholas Piggin bne- 1f 141548e7b769SNicholas Piggin b fast_exception_return 141648e7b769SNicholas Piggin1: /* Error case */ 14177100e870SNicholas PigginMMU_FTR_SECTION_ELSE 14187100e870SNicholas Piggin /* Radix case, access is outside page table range */ 14197100e870SNicholas Piggin li r3,-EFAULT 14207100e870SNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 142148e7b769SNicholas Piggin std r3,RESULT(r1) 142248e7b769SNicholas Piggin bl save_nvgprs 142348e7b769SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 142448e7b769SNicholas Piggin ld r4,_NIP(r1) 142548e7b769SNicholas Piggin ld r5,RESULT(r1) 142648e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 142748e7b769SNicholas Piggin bl do_bad_slb_fault 142854be0b9cSMichael Ellerman b ret_from_except 14295e46e29eSNicholas Piggin 143048e7b769SNicholas Piggin 14311a6822d1SNicholas PigginEXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 1432fc557537SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 1433fc557537SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 143480bd9177SNicholas PigginBEGIN_FTR_SECTION 1435fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED 1436fc557537SNicholas Piggin EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1 1437de56a948SPaul MackerrasFTR_SECTION_ELSE 1438fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED 1439fc557537SNicholas Piggin EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1 1440969391c5SPaul MackerrasALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 14411a6822d1SNicholas PigginEXC_REAL_END(hardware_interrupt, 0x500, 0x100) 1442a5d4f3adSBenjamin Herrenschmidt 14431a6822d1SNicholas PigginEXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 1444fc557537SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 1445fc557537SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 144680bd9177SNicholas PigginBEGIN_FTR_SECTION 1447fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED 1448fc557537SNicholas Piggin EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV 1449c138e588SNicholas PigginFTR_SECTION_ELSE 1450fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED 1451fc557537SNicholas Piggin EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD 1452c138e588SNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 14531a6822d1SNicholas PigginEXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 1454c138e588SNicholas Piggin 14557ede5317SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x500) 14567ede5317SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0x500) 1457c138e588SNicholas PigginEXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 1458c138e588SNicholas Piggin 1459c138e588SNicholas Piggin 1460e779fc93SNicholas PigginEXC_REAL_BEGIN(alignment, 0x600, 0x100) 1461e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 14625dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1463fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0 146438555434SNicholas Piggin mfspr r10,SPRN_DAR 146538555434SNicholas Piggin mfspr r11,SPRN_DSISR 146638555434SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 146738555434SNicholas Piggin stw r11,PACA_EXGEN+EX_DSISR(r13) 14682d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1 1469e779fc93SNicholas PigginEXC_REAL_END(alignment, 0x600, 0x100) 1470e779fc93SNicholas Piggin 1471e779fc93SNicholas PigginEXC_VIRT_BEGIN(alignment, 0x4600, 0x100) 1472e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 14735dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1474fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0 147538555434SNicholas Piggin mfspr r10,SPRN_DAR 147638555434SNicholas Piggin mfspr r11,SPRN_DSISR 147738555434SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 147838555434SNicholas Piggin stw r11,PACA_EXGEN+EX_DSISR(r13) 14792d046308SNicholas Piggin EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD 1480e779fc93SNicholas PigginEXC_VIRT_END(alignment, 0x4600, 0x100) 1481e779fc93SNicholas Piggin 1482da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x600) 1483f9aa6714SNicholas PigginEXC_COMMON_BEGIN(alignment_common) 1484d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x600) 1485f9aa6714SNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 1486f9aa6714SNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 1487f9aa6714SNicholas Piggin std r3,_DAR(r1) 1488f9aa6714SNicholas Piggin std r4,_DSISR(r1) 1489f9aa6714SNicholas Piggin bl save_nvgprs 1490f9aa6714SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1491f9aa6714SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1492f9aa6714SNicholas Piggin bl alignment_exception 1493f9aa6714SNicholas Piggin b ret_from_except 1494f9aa6714SNicholas Piggin 1495b01c8b54SPaul Mackerras 14961a6822d1SNicholas PigginEXC_REAL(program_check, 0x700, 0x100) 14971a6822d1SNicholas PigginEXC_VIRT(program_check, 0x4700, 0x100, 0x700) 1498da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x700) 149911e87346SNicholas PigginEXC_COMMON_BEGIN(program_check_common) 1500265e60a1SCyril Bur /* 1501265e60a1SCyril Bur * It's possible to receive a TM Bad Thing type program check with 1502265e60a1SCyril Bur * userspace register values (in particular r1), but with SRR1 reporting 1503265e60a1SCyril Bur * that we came from the kernel. Normally that would confuse the bad 1504265e60a1SCyril Bur * stack logic, and we would report a bad kernel stack pointer. Instead 1505265e60a1SCyril Bur * we switch to the emergency stack if we're taking a TM Bad Thing from 1506265e60a1SCyril Bur * the kernel. 1507265e60a1SCyril Bur */ 1508265e60a1SCyril Bur li r10,MSR_PR /* Build a mask of MSR_PR .. */ 1509265e60a1SCyril Bur oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ 1510265e60a1SCyril Bur and r10,r10,r12 /* Mask SRR1 with that. */ 1511265e60a1SCyril Bur srdi r10,r10,8 /* Shift it so we can compare */ 1512265e60a1SCyril Bur cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ 1513265e60a1SCyril Bur bne 1f /* If != go to normal path. */ 1514265e60a1SCyril Bur 1515265e60a1SCyril Bur /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ 1516265e60a1SCyril Bur andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ 1517265e60a1SCyril Bur /* 3 in EXCEPTION_PROLOG_COMMON */ 1518265e60a1SCyril Bur mr r10,r1 /* Save r1 */ 1519265e60a1SCyril Bur ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 1520265e60a1SCyril Bur subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1521265e60a1SCyril Bur b 3f /* Jump into the macro !! */ 1522d064151fSNicholas Piggin1: EXCEPTION_COMMON(PACA_EXGEN, 0x700) 152311e87346SNicholas Piggin bl save_nvgprs 152411e87346SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 152511e87346SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 152611e87346SNicholas Piggin bl program_check_exception 152711e87346SNicholas Piggin b ret_from_except 152811e87346SNicholas Piggin 1529a485c709SPaul Mackerras 15301a6822d1SNicholas PigginEXC_REAL(fp_unavailable, 0x800, 0x100) 15311a6822d1SNicholas PigginEXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) 1532da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x800) 1533c78d9b97SNicholas PigginEXC_COMMON_BEGIN(fp_unavailable_common) 1534d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x800) 1535c78d9b97SNicholas Piggin bne 1f /* if from user, just load it up */ 1536c78d9b97SNicholas Piggin bl save_nvgprs 1537c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1538c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1539c78d9b97SNicholas Piggin bl kernel_fp_unavailable_exception 1540c78d9b97SNicholas Piggin BUG_OPCODE 1541c78d9b97SNicholas Piggin1: 1542c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1543c78d9b97SNicholas PigginBEGIN_FTR_SECTION 1544c78d9b97SNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1545c78d9b97SNicholas Piggin * transaction), go do TM stuff 1546c78d9b97SNicholas Piggin */ 1547c78d9b97SNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1548c78d9b97SNicholas Piggin bne- 2f 1549c78d9b97SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_TM) 1550c78d9b97SNicholas Piggin#endif 1551c78d9b97SNicholas Piggin bl load_up_fpu 1552c78d9b97SNicholas Piggin b fast_exception_return 1553c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1554c78d9b97SNicholas Piggin2: /* User process was in a transaction */ 1555c78d9b97SNicholas Piggin bl save_nvgprs 1556c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1557c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1558c78d9b97SNicholas Piggin bl fp_unavailable_tm 1559c78d9b97SNicholas Piggin b ret_from_except 1560c78d9b97SNicholas Piggin#endif 1561c78d9b97SNicholas Piggin 1562b01c8b54SPaul Mackerras 1563a048a07dSNicholas PigginEXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) 1564f14e953bSMadhavan SrinivasanEXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) 156539c0da57SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x900) 156639c0da57SNicholas PigginEXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 156739c0da57SNicholas Piggin 15680ebc4cdaSBenjamin Herrenschmidt 15691a6822d1SNicholas PigginEXC_REAL_HV(hdecrementer, 0x980, 0x80) 15701a6822d1SNicholas PigginEXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) 1571facc6d74SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0x980) 1572facc6d74SNicholas PigginEXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 1573facc6d74SNicholas Piggin 1574da2bc464SMichael Ellerman 1575f14e953bSMadhavan SrinivasanEXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) 1576f14e953bSMadhavan SrinivasanEXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) 1577da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xa00) 1578ca243163SNicholas Piggin#ifdef CONFIG_PPC_DOORBELL 1579ca243163SNicholas PigginEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 1580ca243163SNicholas Piggin#else 1581ca243163SNicholas PigginEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 1582ca243163SNicholas Piggin#endif 1583ca243163SNicholas Piggin 1584da2bc464SMichael Ellerman 15851a6822d1SNicholas PigginEXC_REAL(trap_0b, 0xb00, 0x100) 15861a6822d1SNicholas PigginEXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) 1587da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xb00) 1588341215dcSNicholas PigginEXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 1589341215dcSNicholas Piggin 1590acd7d8ceSNicholas Piggin/* 1591acd7d8ceSNicholas Piggin * system call / hypercall (0xc00, 0x4c00) 1592acd7d8ceSNicholas Piggin * 1593acd7d8ceSNicholas Piggin * The system call exception is invoked with "sc 0" and does not alter HV bit. 1594acd7d8ceSNicholas Piggin * There is support for kernel code to invoke system calls but there are no 1595acd7d8ceSNicholas Piggin * in-tree users. 1596acd7d8ceSNicholas Piggin * 1597acd7d8ceSNicholas Piggin * The hypercall is invoked with "sc 1" and sets HV=1. 1598acd7d8ceSNicholas Piggin * 1599acd7d8ceSNicholas Piggin * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 1600acd7d8ceSNicholas Piggin * 0x4c00 virtual mode. 1601acd7d8ceSNicholas Piggin * 1602acd7d8ceSNicholas Piggin * Call convention: 1603acd7d8ceSNicholas Piggin * 1604acd7d8ceSNicholas Piggin * syscall register convention is in Documentation/powerpc/syscall64-abi.txt 1605acd7d8ceSNicholas Piggin * 1606acd7d8ceSNicholas Piggin * For hypercalls, the register convention is as follows: 1607acd7d8ceSNicholas Piggin * r0 volatile 1608acd7d8ceSNicholas Piggin * r1-2 nonvolatile 1609acd7d8ceSNicholas Piggin * r3 volatile parameter and return value for status 1610acd7d8ceSNicholas Piggin * r4-r10 volatile input and output value 1611acd7d8ceSNicholas Piggin * r11 volatile hypercall number and output value 161276fc0cfcSNicholas Piggin * r12 volatile input and output value 1613acd7d8ceSNicholas Piggin * r13-r31 nonvolatile 1614acd7d8ceSNicholas Piggin * LR nonvolatile 1615acd7d8ceSNicholas Piggin * CTR volatile 1616acd7d8ceSNicholas Piggin * XER volatile 1617acd7d8ceSNicholas Piggin * CR0-1 CR5-7 volatile 1618acd7d8ceSNicholas Piggin * CR2-4 nonvolatile 1619acd7d8ceSNicholas Piggin * Other registers nonvolatile 1620acd7d8ceSNicholas Piggin * 1621acd7d8ceSNicholas Piggin * The intersection of volatile registers that don't contain possible 162276fc0cfcSNicholas Piggin * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 162376fc0cfcSNicholas Piggin * without saving, though xer is not a good idea to use, as hardware may 162476fc0cfcSNicholas Piggin * interpret some bits so it may be costly to change them. 1625acd7d8ceSNicholas Piggin */ 16261b4d4a79SNicholas Piggin.macro SYSTEM_CALL virt 1627bc355125SPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1628bc355125SPaul Mackerras /* 1629acd7d8ceSNicholas Piggin * There is a little bit of juggling to get syscall and hcall 163076fc0cfcSNicholas Piggin * working well. Save r13 in ctr to avoid using SPRG scratch 163176fc0cfcSNicholas Piggin * register. 1632acd7d8ceSNicholas Piggin * 1633acd7d8ceSNicholas Piggin * Userspace syscalls have already saved the PPR, hcalls must save 1634acd7d8ceSNicholas Piggin * it before setting HMT_MEDIUM. 1635bc355125SPaul Mackerras */ 16361b4d4a79SNicholas Piggin mtctr r13 16371b4d4a79SNicholas Piggin GET_PACA(r13) 16381b4d4a79SNicholas Piggin std r10,PACA_EXGEN+EX_R10(r13) 16391b4d4a79SNicholas Piggin INTERRUPT_TO_KERNEL 16401b4d4a79SNicholas Piggin KVMTEST EXC_STD 0xc00 /* uses r10, branch to do_kvm_0xc00_system_call */ 16411b4d4a79SNicholas Piggin mfctr r9 1642bc355125SPaul Mackerras#else 16431b4d4a79SNicholas Piggin mr r9,r13 16441b4d4a79SNicholas Piggin GET_PACA(r13) 16451b4d4a79SNicholas Piggin INTERRUPT_TO_KERNEL 1646bc355125SPaul Mackerras#endif 1647bc355125SPaul Mackerras 1648727f1361SMichael Ellerman#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 16491b4d4a79SNicholas PigginBEGIN_FTR_SECTION 16501b4d4a79SNicholas Piggin cmpdi r0,0x1ebe 16511b4d4a79SNicholas Piggin beq- 1f 16521b4d4a79SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) 16531b4d4a79SNicholas Piggin#endif 16545c2511bfSMichael Ellerman 1655*b0b2a93dSNicholas Piggin /* We reach here with PACA in r13, r13 in r9. */ 16561b4d4a79SNicholas Piggin mfspr r11,SPRN_SRR0 16571b4d4a79SNicholas Piggin mfspr r12,SPRN_SRR1 1658*b0b2a93dSNicholas Piggin 1659*b0b2a93dSNicholas Piggin HMT_MEDIUM 1660*b0b2a93dSNicholas Piggin 1661*b0b2a93dSNicholas Piggin .if ! \virt 16621b4d4a79SNicholas Piggin __LOAD_HANDLER(r10, system_call_common) 16631b4d4a79SNicholas Piggin mtspr SPRN_SRR0,r10 16641b4d4a79SNicholas Piggin ld r10,PACAKMSR(r13) 16651b4d4a79SNicholas Piggin mtspr SPRN_SRR1,r10 16661b4d4a79SNicholas Piggin RFI_TO_KERNEL 16671b4d4a79SNicholas Piggin b . /* prevent speculative execution */ 16681b4d4a79SNicholas Piggin .else 16691b4d4a79SNicholas Piggin li r10,MSR_RI 16701b4d4a79SNicholas Piggin mtmsrd r10,1 /* Set RI (EE=0) */ 1671*b0b2a93dSNicholas Piggin#ifdef CONFIG_RELOCATABLE 1672*b0b2a93dSNicholas Piggin __LOAD_HANDLER(r10, system_call_common) 1673*b0b2a93dSNicholas Piggin mtctr r10 1674*b0b2a93dSNicholas Piggin bctr 1675*b0b2a93dSNicholas Piggin#else 16761b4d4a79SNicholas Piggin b system_call_common 1677d807ad37SNicholas Piggin#endif 16781b4d4a79SNicholas Piggin .endif 16791b4d4a79SNicholas Piggin 16801b4d4a79SNicholas Piggin#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 16811b4d4a79SNicholas Piggin /* Fast LE/BE switch system call */ 16821b4d4a79SNicholas Piggin1: mfspr r12,SPRN_SRR1 16831b4d4a79SNicholas Piggin xori r12,r12,MSR_LE 16841b4d4a79SNicholas Piggin mtspr SPRN_SRR1,r12 16851b4d4a79SNicholas Piggin mr r13,r9 16861b4d4a79SNicholas Piggin RFI_TO_USER /* return to userspace */ 16871b4d4a79SNicholas Piggin b . /* prevent speculative execution */ 16881b4d4a79SNicholas Piggin#endif 16891b4d4a79SNicholas Piggin.endm 1690d807ad37SNicholas Piggin 16911a6822d1SNicholas PigginEXC_REAL_BEGIN(system_call, 0xc00, 0x100) 16921b4d4a79SNicholas Piggin SYSTEM_CALL 0 16931a6822d1SNicholas PigginEXC_REAL_END(system_call, 0xc00, 0x100) 1694b01c8b54SPaul Mackerras 16951a6822d1SNicholas PigginEXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 16961b4d4a79SNicholas Piggin SYSTEM_CALL 1 16971a6822d1SNicholas PigginEXC_VIRT_END(system_call, 0x4c00, 0x100) 1698d807ad37SNicholas Piggin 1699acd7d8ceSNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1700acd7d8ceSNicholas Piggin /* 1701acd7d8ceSNicholas Piggin * This is a hcall, so register convention is as above, with these 1702acd7d8ceSNicholas Piggin * differences: 1703acd7d8ceSNicholas Piggin * r13 = PACA 170476fc0cfcSNicholas Piggin * ctr = orig r13 170576fc0cfcSNicholas Piggin * orig r10 saved in PACA 1706acd7d8ceSNicholas Piggin */ 1707acd7d8ceSNicholas PigginTRAMP_KVM_BEGIN(do_kvm_0xc00) 1708acd7d8ceSNicholas Piggin /* 1709acd7d8ceSNicholas Piggin * Save the PPR (on systems that support it) before changing to 1710acd7d8ceSNicholas Piggin * HMT_MEDIUM. That allows the KVM code to save that value into the 1711acd7d8ceSNicholas Piggin * guest state (it is the guest's PPR value). 1712acd7d8ceSNicholas Piggin */ 171376fc0cfcSNicholas Piggin OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) 1714acd7d8ceSNicholas Piggin HMT_MEDIUM 171576fc0cfcSNicholas Piggin OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) 1716acd7d8ceSNicholas Piggin mfctr r10 171776fc0cfcSNicholas Piggin SET_SCRATCH0(r10) 1718acd7d8ceSNicholas Piggin std r9,PACA_EXGEN+EX_R9(r13) 1719acd7d8ceSNicholas Piggin mfcr r9 172017bdc064SNicholas Piggin KVM_HANDLER PACA_EXGEN, EXC_STD, 0xc00, 0 1721acd7d8ceSNicholas Piggin#endif 1722da2bc464SMichael Ellerman 1723d807ad37SNicholas Piggin 17241a6822d1SNicholas PigginEXC_REAL(single_step, 0xd00, 0x100) 17251a6822d1SNicholas PigginEXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) 1726da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xd00) 1727bc6675c6SNicholas PigginEXC_COMMON(single_step_common, 0xd00, single_step_exception) 1728da2bc464SMichael Ellerman 17291a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) 1730da0e7e62SMichael EllermanEXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) 1731f5c32c1dSNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 1732f5c32c1dSNicholas PigginEXC_COMMON_BEGIN(h_data_storage_common) 1733f5c32c1dSNicholas Piggin mfspr r10,SPRN_HDAR 1734f5c32c1dSNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 1735f5c32c1dSNicholas Piggin mfspr r10,SPRN_HDSISR 1736f5c32c1dSNicholas Piggin stw r10,PACA_EXGEN+EX_DSISR(r13) 1737d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xe00) 1738f5c32c1dSNicholas Piggin bl save_nvgprs 1739f5c32c1dSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1740f5c32c1dSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1741d7b45615SSuraj Jitindar SinghBEGIN_MMU_FTR_SECTION 1742d7b45615SSuraj Jitindar Singh ld r4,PACA_EXGEN+EX_DAR(r13) 1743d7b45615SSuraj Jitindar Singh lwz r5,PACA_EXGEN+EX_DSISR(r13) 1744d7b45615SSuraj Jitindar Singh std r4,_DAR(r1) 1745d7b45615SSuraj Jitindar Singh std r5,_DSISR(r1) 1746d7b45615SSuraj Jitindar Singh li r5,SIGSEGV 1747d7b45615SSuraj Jitindar Singh bl bad_page_fault 1748d7b45615SSuraj Jitindar SinghMMU_FTR_SECTION_ELSE 1749f5c32c1dSNicholas Piggin bl unknown_exception 1750d7b45615SSuraj Jitindar SinghALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) 1751f5c32c1dSNicholas Piggin b ret_from_except 1752f5c32c1dSNicholas Piggin 17531707dd16SPaul Mackerras 17541a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) 1755da0e7e62SMichael EllermanEXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) 175682517cabSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe20) 175782517cabSNicholas PigginEXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 175882517cabSNicholas Piggin 17591707dd16SPaul Mackerras 17601a6822d1SNicholas PigginEXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) 17611a6822d1SNicholas PigginEXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) 1762031b4026SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe40) 1763031b4026SNicholas PigginEXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 1764031b4026SNicholas Piggin 17651707dd16SPaul Mackerras 1766e0319829SNicholas Piggin/* 1767e0319829SNicholas Piggin * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 1768e0319829SNicholas Piggin * first, and then eventaully from there to the trampoline to get into virtual 1769e0319829SNicholas Piggin * mode. 1770e0319829SNicholas Piggin */ 17711a6822d1SNicholas Piggin__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) 1772f14e953bSMadhavan Srinivasan__TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED) 17731a6822d1SNicholas PigginEXC_VIRT_NONE(0x4e60, 0x20) 177462f9b03bSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe60) 177562f9b03bSNicholas PigginTRAMP_REAL_BEGIN(hmi_exception_early) 1776fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0 177762f9b03bSNicholas Piggin mr r10,r1 /* Save r1 */ 1778a4087a4dSNicholas Piggin ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 177962f9b03bSNicholas Piggin subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 178062f9b03bSNicholas Piggin mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 1781a4087a4dSNicholas Piggin mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ 1782a4087a4dSNicholas Piggin EXCEPTION_PROLOG_COMMON_1() 1783890274c2SMichael Ellerman /* We don't touch AMR here, we never go to virtual mode */ 178462f9b03bSNicholas Piggin EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 178562f9b03bSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(0xe60) 178662f9b03bSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1787505a314fSBenjamin Herrenschmidt BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */ 17885080332cSMichael Neuling cmpdi cr0,r3,0 17895080332cSMichael Neuling 179062f9b03bSNicholas Piggin /* Windup the stack. */ 179162f9b03bSNicholas Piggin /* Move original HSRR0 and HSRR1 into the respective regs */ 179262f9b03bSNicholas Piggin ld r9,_MSR(r1) 179362f9b03bSNicholas Piggin mtspr SPRN_HSRR1,r9 179462f9b03bSNicholas Piggin ld r3,_NIP(r1) 179562f9b03bSNicholas Piggin mtspr SPRN_HSRR0,r3 179662f9b03bSNicholas Piggin ld r9,_CTR(r1) 179762f9b03bSNicholas Piggin mtctr r9 179862f9b03bSNicholas Piggin ld r9,_XER(r1) 179962f9b03bSNicholas Piggin mtxer r9 180062f9b03bSNicholas Piggin ld r9,_LINK(r1) 180162f9b03bSNicholas Piggin mtlr r9 180262f9b03bSNicholas Piggin REST_GPR(0, r1) 180362f9b03bSNicholas Piggin REST_8GPRS(2, r1) 180462f9b03bSNicholas Piggin REST_GPR(10, r1) 180562f9b03bSNicholas Piggin ld r11,_CCR(r1) 18065080332cSMichael Neuling REST_2GPRS(12, r1) 18075080332cSMichael Neuling bne 1f 180862f9b03bSNicholas Piggin mtcr r11 180962f9b03bSNicholas Piggin REST_GPR(11, r1) 18105080332cSMichael Neuling ld r1,GPR1(r1) 1811222f20f1SNicholas Piggin HRFI_TO_USER_OR_KERNEL 18125080332cSMichael Neuling 18135080332cSMichael Neuling1: mtcr r11 18145080332cSMichael Neuling REST_GPR(11, r1) 181562f9b03bSNicholas Piggin ld r1,GPR1(r1) 181662f9b03bSNicholas Piggin 181762f9b03bSNicholas Piggin /* 181862f9b03bSNicholas Piggin * Go to virtual mode and pull the HMI event information from 181962f9b03bSNicholas Piggin * firmware. 182062f9b03bSNicholas Piggin */ 182162f9b03bSNicholas Piggin .globl hmi_exception_after_realmode 182262f9b03bSNicholas Pigginhmi_exception_after_realmode: 182362f9b03bSNicholas Piggin SET_SCRATCH0(r13) 18245dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 182562f9b03bSNicholas Piggin b tramp_real_hmi_exception 182662f9b03bSNicholas Piggin 18275080332cSMichael NeulingEXC_COMMON_BEGIN(hmi_exception_common) 182847169fbaSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xe60) 182947169fbaSNicholas Piggin FINISH_NAP 183047169fbaSNicholas Piggin bl save_nvgprs 183147169fbaSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 183247169fbaSNicholas Piggin RUNLATCH_ON 1833c06075f3SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1834c06075f3SNicholas Piggin bl handle_hmi_exception 1835c06075f3SNicholas Piggin b ret_from_except 18361707dd16SPaul Mackerras 1837f14e953bSMadhavan SrinivasanEXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) 1838f14e953bSMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) 18399bcb81bfSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe80) 18409bcb81bfSNicholas Piggin#ifdef CONFIG_PPC_DOORBELL 18419bcb81bfSNicholas PigginEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 18429bcb81bfSNicholas Piggin#else 18439bcb81bfSNicholas PigginEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 18449bcb81bfSNicholas Piggin#endif 18459bcb81bfSNicholas Piggin 18460ebc4cdaSBenjamin Herrenschmidt 1847f14e953bSMadhavan SrinivasanEXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) 1848f14e953bSMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) 184974408776SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xea0) 185074408776SNicholas PigginEXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 185174408776SNicholas Piggin 18529baaef0aSBenjamin Herrenschmidt 18531a6822d1SNicholas PigginEXC_REAL_NONE(0xec0, 0x20) 18541a6822d1SNicholas PigginEXC_VIRT_NONE(0x4ec0, 0x20) 18551a6822d1SNicholas PigginEXC_REAL_NONE(0xee0, 0x20) 18561a6822d1SNicholas PigginEXC_VIRT_NONE(0x4ee0, 0x20) 1857bda7fea2SNicholas Piggin 18580ebc4cdaSBenjamin Herrenschmidt 1859f442d004SMadhavan SrinivasanEXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) 1860f442d004SMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) 1861b1c7f150SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf00) 1862b1c7f150SNicholas PigginEXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1863b1c7f150SNicholas Piggin 18640ebc4cdaSBenjamin Herrenschmidt 18651a6822d1SNicholas PigginEXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) 18661a6822d1SNicholas PigginEXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) 1867d1a0ca9cSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf20) 1868d1a0ca9cSNicholas PigginEXC_COMMON_BEGIN(altivec_unavailable_common) 1869d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xf20) 1870d1a0ca9cSNicholas Piggin#ifdef CONFIG_ALTIVEC 1871d1a0ca9cSNicholas PigginBEGIN_FTR_SECTION 1872d1a0ca9cSNicholas Piggin beq 1f 1873d1a0ca9cSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1874d1a0ca9cSNicholas Piggin BEGIN_FTR_SECTION_NESTED(69) 1875d1a0ca9cSNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1876d1a0ca9cSNicholas Piggin * transaction), go do TM stuff 1877d1a0ca9cSNicholas Piggin */ 1878d1a0ca9cSNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1879d1a0ca9cSNicholas Piggin bne- 2f 1880d1a0ca9cSNicholas Piggin END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1881d1a0ca9cSNicholas Piggin#endif 1882d1a0ca9cSNicholas Piggin bl load_up_altivec 1883d1a0ca9cSNicholas Piggin b fast_exception_return 1884d1a0ca9cSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1885d1a0ca9cSNicholas Piggin2: /* User process was in a transaction */ 1886d1a0ca9cSNicholas Piggin bl save_nvgprs 1887d1a0ca9cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1888d1a0ca9cSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1889d1a0ca9cSNicholas Piggin bl altivec_unavailable_tm 1890d1a0ca9cSNicholas Piggin b ret_from_except 1891d1a0ca9cSNicholas Piggin#endif 1892d1a0ca9cSNicholas Piggin1: 1893d1a0ca9cSNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1894d1a0ca9cSNicholas Piggin#endif 1895d1a0ca9cSNicholas Piggin bl save_nvgprs 1896d1a0ca9cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1897d1a0ca9cSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1898d1a0ca9cSNicholas Piggin bl altivec_unavailable_exception 1899d1a0ca9cSNicholas Piggin b ret_from_except 1900d1a0ca9cSNicholas Piggin 19010ebc4cdaSBenjamin Herrenschmidt 19021a6822d1SNicholas PigginEXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) 19031a6822d1SNicholas PigginEXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) 1904792cbdddSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf40) 1905792cbdddSNicholas PigginEXC_COMMON_BEGIN(vsx_unavailable_common) 1906d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xf40) 1907792cbdddSNicholas Piggin#ifdef CONFIG_VSX 1908792cbdddSNicholas PigginBEGIN_FTR_SECTION 1909792cbdddSNicholas Piggin beq 1f 1910792cbdddSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1911792cbdddSNicholas Piggin BEGIN_FTR_SECTION_NESTED(69) 1912792cbdddSNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1913792cbdddSNicholas Piggin * transaction), go do TM stuff 1914792cbdddSNicholas Piggin */ 1915792cbdddSNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1916792cbdddSNicholas Piggin bne- 2f 1917792cbdddSNicholas Piggin END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1918792cbdddSNicholas Piggin#endif 1919792cbdddSNicholas Piggin b load_up_vsx 1920792cbdddSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1921792cbdddSNicholas Piggin2: /* User process was in a transaction */ 1922792cbdddSNicholas Piggin bl save_nvgprs 1923792cbdddSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1924792cbdddSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1925792cbdddSNicholas Piggin bl vsx_unavailable_tm 1926792cbdddSNicholas Piggin b ret_from_except 1927792cbdddSNicholas Piggin#endif 1928792cbdddSNicholas Piggin1: 1929792cbdddSNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 1930792cbdddSNicholas Piggin#endif 1931792cbdddSNicholas Piggin bl save_nvgprs 1932792cbdddSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1933792cbdddSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1934792cbdddSNicholas Piggin bl vsx_unavailable_exception 1935792cbdddSNicholas Piggin b ret_from_except 1936792cbdddSNicholas Piggin 1937d0c0c9a1SMichael Neuling 19381a6822d1SNicholas PigginEXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) 19391a6822d1SNicholas PigginEXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) 19401134713cSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf60) 19411134713cSNicholas PigginEXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 19421134713cSNicholas Piggin 1943da2bc464SMichael Ellerman 19441a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) 19451a6822d1SNicholas PigginEXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) 194614b0072cSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xf80) 194714b0072cSNicholas PigginEXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 194814b0072cSNicholas Piggin 1949da2bc464SMichael Ellerman 19501a6822d1SNicholas PigginEXC_REAL_NONE(0xfa0, 0x20) 19511a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fa0, 0x20) 19521a6822d1SNicholas PigginEXC_REAL_NONE(0xfc0, 0x20) 19531a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fc0, 0x20) 19541a6822d1SNicholas PigginEXC_REAL_NONE(0xfe0, 0x20) 19551a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fe0, 0x20) 19561a6822d1SNicholas Piggin 19571a6822d1SNicholas PigginEXC_REAL_NONE(0x1000, 0x100) 19581a6822d1SNicholas PigginEXC_VIRT_NONE(0x5000, 0x100) 19591a6822d1SNicholas PigginEXC_REAL_NONE(0x1100, 0x100) 19601a6822d1SNicholas PigginEXC_VIRT_NONE(0x5100, 0x100) 1961da2bc464SMichael Ellerman 19620ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 19631a6822d1SNicholas PigginEXC_REAL_HV(cbe_system_error, 0x1200, 0x100) 19641a6822d1SNicholas PigginEXC_VIRT_NONE(0x5200, 0x100) 1965da2bc464SMichael EllermanTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1966ff1b3206SNicholas PigginEXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1967da2bc464SMichael Ellerman#else /* CONFIG_CBE_RAS */ 19681a6822d1SNicholas PigginEXC_REAL_NONE(0x1200, 0x100) 19691a6822d1SNicholas PigginEXC_VIRT_NONE(0x5200, 0x100) 1970da2bc464SMichael Ellerman#endif 1971da2bc464SMichael Ellerman 1972ff1b3206SNicholas Piggin 19731a6822d1SNicholas PigginEXC_REAL(instruction_breakpoint, 0x1300, 0x100) 19741a6822d1SNicholas PigginEXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) 1975da2bc464SMichael EllermanTRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 19764e96dbbfSNicholas PigginEXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 19774e96dbbfSNicholas Piggin 19781a6822d1SNicholas PigginEXC_REAL_NONE(0x1400, 0x100) 19791a6822d1SNicholas PigginEXC_VIRT_NONE(0x5400, 0x100) 1980da2bc464SMichael Ellerman 19811a6822d1SNicholas PigginEXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) 1982b92a66a6SMichael Neuling mtspr SPRN_SPRG_HSCRATCH0,r13 19835dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1984fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0 1985b92a66a6SMichael Neuling 1986b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 1987b92a66a6SMichael Neuling mfspr r10,SPRN_HSRR1 1988b92a66a6SMichael Neuling andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1989b92a66a6SMichael Neuling bne+ denorm_assist 1990b92a66a6SMichael Neuling#endif 1991b92a66a6SMichael Neuling 1992a7c1ca19SNicholas Piggin KVMTEST EXC_HV 0x1500 19932d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1 19941a6822d1SNicholas PigginEXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) 1995da2bc464SMichael Ellerman 1996d7e89849SNicholas Piggin#ifdef CONFIG_PPC_DENORMALISATION 19971a6822d1SNicholas PigginEXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 1998d7e89849SNicholas Piggin b exc_real_0x1500_denorm_exception_hv 19991a6822d1SNicholas PigginEXC_VIRT_END(denorm_exception, 0x5500, 0x100) 2000d7e89849SNicholas Piggin#else 20011a6822d1SNicholas PigginEXC_VIRT_NONE(0x5500, 0x100) 2002d7e89849SNicholas Piggin#endif 2003d7e89849SNicholas Piggin 20044bb3c7a0SPaul MackerrasTRAMP_KVM_HV(PACA_EXGEN, 0x1500) 2005b92a66a6SMichael Neuling 2006b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 2007da2bc464SMichael EllermanTRAMP_REAL_BEGIN(denorm_assist) 2008b92a66a6SMichael NeulingBEGIN_FTR_SECTION 2009b92a66a6SMichael Neuling/* 2010b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 2011b92a66a6SMichael Neuling * For POWER6 do that here for all FP regs. 2012b92a66a6SMichael Neuling */ 2013b92a66a6SMichael Neuling mfmsr r10 2014b92a66a6SMichael Neuling ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 2015b92a66a6SMichael Neuling xori r10,r10,(MSR_FE0|MSR_FE1) 2016b92a66a6SMichael Neuling mtmsrd r10 2017b92a66a6SMichael Neuling sync 2018d7c67fb1SMichael Neuling 2019f3c8b6c6SNicholas Piggin .Lreg=0 2020f3c8b6c6SNicholas Piggin .rept 32 2021f3c8b6c6SNicholas Piggin fmr .Lreg,.Lreg 2022f3c8b6c6SNicholas Piggin .Lreg=.Lreg+1 2023f3c8b6c6SNicholas Piggin .endr 2024d7c67fb1SMichael Neuling 2025b92a66a6SMichael NeulingFTR_SECTION_ELSE 2026b92a66a6SMichael Neuling/* 2027b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 2028b92a66a6SMichael Neuling * For POWER7 do that here for the first 32 VSX registers only. 2029b92a66a6SMichael Neuling */ 2030b92a66a6SMichael Neuling mfmsr r10 2031b92a66a6SMichael Neuling oris r10,r10,MSR_VSX@h 2032b92a66a6SMichael Neuling mtmsrd r10 2033b92a66a6SMichael Neuling sync 2034d7c67fb1SMichael Neuling 2035f3c8b6c6SNicholas Piggin .Lreg=0 2036f3c8b6c6SNicholas Piggin .rept 32 2037f3c8b6c6SNicholas Piggin XVCPSGNDP(.Lreg,.Lreg,.Lreg) 2038f3c8b6c6SNicholas Piggin .Lreg=.Lreg+1 2039f3c8b6c6SNicholas Piggin .endr 2040d7c67fb1SMichael Neuling 2041b92a66a6SMichael NeulingALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 2042fb0fce3eSMichael Neuling 2043fb0fce3eSMichael NeulingBEGIN_FTR_SECTION 2044fb0fce3eSMichael Neuling b denorm_done 2045fb0fce3eSMichael NeulingEND_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 2046fb0fce3eSMichael Neuling/* 2047fb0fce3eSMichael Neuling * To denormalise we need to move a copy of the register to itself. 2048fb0fce3eSMichael Neuling * For POWER8 we need to do that for all 64 VSX registers 2049fb0fce3eSMichael Neuling */ 2050f3c8b6c6SNicholas Piggin .Lreg=32 2051f3c8b6c6SNicholas Piggin .rept 32 2052f3c8b6c6SNicholas Piggin XVCPSGNDP(.Lreg,.Lreg,.Lreg) 2053f3c8b6c6SNicholas Piggin .Lreg=.Lreg+1 2054f3c8b6c6SNicholas Piggin .endr 2055f3c8b6c6SNicholas Piggin 2056fb0fce3eSMichael Neulingdenorm_done: 2057f14040bcSMichael Neuling mfspr r11,SPRN_HSRR0 2058f14040bcSMichael Neuling subi r11,r11,4 2059b92a66a6SMichael Neuling mtspr SPRN_HSRR0,r11 2060b92a66a6SMichael Neuling mtcrf 0x80,r9 2061b92a66a6SMichael Neuling ld r9,PACA_EXGEN+EX_R9(r13) 206244e9309fSHaren Myneni RESTORE_PPR_PACA(PACA_EXGEN, r10) 2063630573c1SPaul MackerrasBEGIN_FTR_SECTION 2064630573c1SPaul Mackerras ld r10,PACA_EXGEN+EX_CFAR(r13) 2065630573c1SPaul Mackerras mtspr SPRN_CFAR,r10 2066630573c1SPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CFAR) 2067b92a66a6SMichael Neuling ld r10,PACA_EXGEN+EX_R10(r13) 2068b92a66a6SMichael Neuling ld r11,PACA_EXGEN+EX_R11(r13) 2069b92a66a6SMichael Neuling ld r12,PACA_EXGEN+EX_R12(r13) 2070b92a66a6SMichael Neuling ld r13,PACA_EXGEN+EX_R13(r13) 2071222f20f1SNicholas Piggin HRFI_TO_UNKNOWN 2072b92a66a6SMichael Neuling b . 2073b92a66a6SMichael Neuling#endif 2074b92a66a6SMichael Neuling 2075872e2ae4SBenjamin HerrenschmidtEXC_COMMON(denorm_common, 0x1500, unknown_exception) 2076d7e89849SNicholas Piggin 2077d7e89849SNicholas Piggin 2078d7e89849SNicholas Piggin#ifdef CONFIG_CBE_RAS 20791a6822d1SNicholas PigginEXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) 20801a6822d1SNicholas PigginEXC_VIRT_NONE(0x5600, 0x100) 2081d7e89849SNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 208269a79344SNicholas PigginEXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 2083d7e89849SNicholas Piggin#else /* CONFIG_CBE_RAS */ 20841a6822d1SNicholas PigginEXC_REAL_NONE(0x1600, 0x100) 20851a6822d1SNicholas PigginEXC_VIRT_NONE(0x5600, 0x100) 2086d7e89849SNicholas Piggin#endif 2087d7e89849SNicholas Piggin 208869a79344SNicholas Piggin 20891a6822d1SNicholas PigginEXC_REAL(altivec_assist, 0x1700, 0x100) 20901a6822d1SNicholas PigginEXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) 2091d7e89849SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x1700) 2092b51c079eSNicholas Piggin#ifdef CONFIG_ALTIVEC 2093b51c079eSNicholas PigginEXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 2094b51c079eSNicholas Piggin#else 2095b51c079eSNicholas PigginEXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 2096b51c079eSNicholas Piggin#endif 2097b51c079eSNicholas Piggin 2098d7e89849SNicholas Piggin 2099d7e89849SNicholas Piggin#ifdef CONFIG_CBE_RAS 21001a6822d1SNicholas PigginEXC_REAL_HV(cbe_thermal, 0x1800, 0x100) 21011a6822d1SNicholas PigginEXC_VIRT_NONE(0x5800, 0x100) 2102d7e89849SNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 21033965f8abSNicholas PigginEXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 2104d7e89849SNicholas Piggin#else /* CONFIG_CBE_RAS */ 21051a6822d1SNicholas PigginEXC_REAL_NONE(0x1800, 0x100) 21061a6822d1SNicholas PigginEXC_VIRT_NONE(0x5800, 0x100) 2107d7e89849SNicholas Piggin#endif 2108d7e89849SNicholas Piggin 210975eb767eSNicholas Piggin#ifdef CONFIG_PPC_WATCHDOG 21102104180aSNicholas Piggin 21112104180aSNicholas Piggin#define MASKED_DEC_HANDLER_LABEL 3f 21122104180aSNicholas Piggin 21132104180aSNicholas Piggin#define MASKED_DEC_HANDLER(_H) \ 21142104180aSNicholas Piggin3: /* soft-nmi */ \ 21152104180aSNicholas Piggin std r12,PACA_EXGEN+EX_R12(r13); \ 21162104180aSNicholas Piggin GET_SCRATCH0(r10); \ 21172104180aSNicholas Piggin std r10,PACA_EXGEN+EX_R13(r13); \ 21182d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1 21192104180aSNicholas Piggin 2120cc491f1dSNicholas Piggin/* 2121cc491f1dSNicholas Piggin * Branch to soft_nmi_interrupt using the emergency stack. The emergency 2122cc491f1dSNicholas Piggin * stack is one that is usable by maskable interrupts so long as MSR_EE 2123cc491f1dSNicholas Piggin * remains off. It is used for recovery when something has corrupted the 2124cc491f1dSNicholas Piggin * normal kernel stack, for example. The "soft NMI" must not use the process 2125cc491f1dSNicholas Piggin * stack because we want irq disabled sections to avoid touching the stack 2126cc491f1dSNicholas Piggin * at all (other than PMU interrupts), so use the emergency stack for this, 2127cc491f1dSNicholas Piggin * and run it entirely with interrupts hard disabled. 2128cc491f1dSNicholas Piggin */ 21292104180aSNicholas PigginEXC_COMMON_BEGIN(soft_nmi_common) 21302104180aSNicholas Piggin mr r10,r1 21312104180aSNicholas Piggin ld r1,PACAEMERGSP(r13) 21322104180aSNicholas Piggin subi r1,r1,INT_FRAME_SIZE 213347169fbaSNicholas Piggin EXCEPTION_COMMON_STACK(PACA_EXGEN, 0x900) 213447169fbaSNicholas Piggin bl save_nvgprs 213547169fbaSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 2136c06075f3SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 2137c06075f3SNicholas Piggin bl soft_nmi_interrupt 21382104180aSNicholas Piggin b ret_from_except 21392104180aSNicholas Piggin 214075eb767eSNicholas Piggin#else /* CONFIG_PPC_WATCHDOG */ 21412104180aSNicholas Piggin#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ 21422104180aSNicholas Piggin#define MASKED_DEC_HANDLER(_H) 214375eb767eSNicholas Piggin#endif /* CONFIG_PPC_WATCHDOG */ 2144d7e89849SNicholas Piggin 21450ebc4cdaSBenjamin Herrenschmidt/* 2146fe9e1d54SIan Munsie * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 2147fe9e1d54SIan Munsie * - If it was a decrementer interrupt, we bump the dec to max and and return. 2148fe9e1d54SIan Munsie * - If it was a doorbell we return immediately since doorbells are edge 2149fe9e1d54SIan Munsie * triggered and won't automatically refire. 21500869b6fdSMahesh Salgaonkar * - If it was a HMI we return immediately since we handled it in realmode 21510869b6fdSMahesh Salgaonkar * and it won't refire. 21526cc3f91bSNicholas Piggin * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. 2153fe9e1d54SIan Munsie * This is called with r10 containing the value to OR to the paca field. 21540ebc4cdaSBenjamin Herrenschmidt */ 21554508a74aSNicholas Piggin.macro MASKED_INTERRUPT hsrr 21564508a74aSNicholas Piggin .if \hsrr 21574508a74aSNicholas Pigginmasked_Hinterrupt: 21584508a74aSNicholas Piggin .else 21594508a74aSNicholas Pigginmasked_interrupt: 21604508a74aSNicholas Piggin .endif 21614508a74aSNicholas Piggin std r11,PACA_EXGEN+EX_R11(r13) 21624508a74aSNicholas Piggin lbz r11,PACAIRQHAPPENED(r13) 21634508a74aSNicholas Piggin or r11,r11,r10 21644508a74aSNicholas Piggin stb r11,PACAIRQHAPPENED(r13) 21654508a74aSNicholas Piggin cmpwi r10,PACA_IRQ_DEC 21664508a74aSNicholas Piggin bne 1f 21674508a74aSNicholas Piggin lis r10,0x7fff 21684508a74aSNicholas Piggin ori r10,r10,0xffff 21694508a74aSNicholas Piggin mtspr SPRN_DEC,r10 21704508a74aSNicholas Piggin b MASKED_DEC_HANDLER_LABEL 21714508a74aSNicholas Piggin1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK 21724508a74aSNicholas Piggin beq 2f 21734508a74aSNicholas Piggin .if \hsrr 21744508a74aSNicholas Piggin mfspr r10,SPRN_HSRR1 21754508a74aSNicholas Piggin xori r10,r10,MSR_EE /* clear MSR_EE */ 21764508a74aSNicholas Piggin mtspr SPRN_HSRR1,r10 21774508a74aSNicholas Piggin .else 21784508a74aSNicholas Piggin mfspr r10,SPRN_SRR1 21794508a74aSNicholas Piggin xori r10,r10,MSR_EE /* clear MSR_EE */ 21804508a74aSNicholas Piggin mtspr SPRN_SRR1,r10 21814508a74aSNicholas Piggin .endif 21824508a74aSNicholas Piggin ori r11,r11,PACA_IRQ_HARD_DIS 21834508a74aSNicholas Piggin stb r11,PACAIRQHAPPENED(r13) 21844508a74aSNicholas Piggin2: /* done */ 21854508a74aSNicholas Piggin mtcrf 0x80,r9 21864508a74aSNicholas Piggin std r1,PACAR1(r13) 21874508a74aSNicholas Piggin ld r9,PACA_EXGEN+EX_R9(r13) 21884508a74aSNicholas Piggin ld r10,PACA_EXGEN+EX_R10(r13) 21894508a74aSNicholas Piggin ld r11,PACA_EXGEN+EX_R11(r13) 21904508a74aSNicholas Piggin /* returns to kernel where r13 must be set up, so don't restore it */ 21914508a74aSNicholas Piggin .if \hsrr 21924508a74aSNicholas Piggin HRFI_TO_KERNEL 21934508a74aSNicholas Piggin .else 21944508a74aSNicholas Piggin RFI_TO_KERNEL 21954508a74aSNicholas Piggin .endif 21964508a74aSNicholas Piggin b . 21974508a74aSNicholas Piggin MASKED_DEC_HANDLER(\hsrr\()) 21984508a74aSNicholas Piggin.endm 21990ebc4cdaSBenjamin Herrenschmidt 2200a048a07dSNicholas PigginTRAMP_REAL_BEGIN(stf_barrier_fallback) 2201a048a07dSNicholas Piggin std r9,PACA_EXRFI+EX_R9(r13) 2202a048a07dSNicholas Piggin std r10,PACA_EXRFI+EX_R10(r13) 2203a048a07dSNicholas Piggin sync 2204a048a07dSNicholas Piggin ld r9,PACA_EXRFI+EX_R9(r13) 2205a048a07dSNicholas Piggin ld r10,PACA_EXRFI+EX_R10(r13) 2206a048a07dSNicholas Piggin ori 31,31,0 2207a048a07dSNicholas Piggin .rept 14 2208a048a07dSNicholas Piggin b 1f 2209a048a07dSNicholas Piggin1: 2210a048a07dSNicholas Piggin .endr 2211a048a07dSNicholas Piggin blr 2212a048a07dSNicholas Piggin 2213aa8a5e00SMichael EllermanTRAMP_REAL_BEGIN(rfi_flush_fallback) 2214aa8a5e00SMichael Ellerman SET_SCRATCH0(r13); 2215aa8a5e00SMichael Ellerman GET_PACA(r13); 221678ee9946SMichael Ellerman std r1,PACA_EXRFI+EX_R12(r13) 221778ee9946SMichael Ellerman ld r1,PACAKSAVE(r13) 2218aa8a5e00SMichael Ellerman std r9,PACA_EXRFI+EX_R9(r13) 2219aa8a5e00SMichael Ellerman std r10,PACA_EXRFI+EX_R10(r13) 2220aa8a5e00SMichael Ellerman std r11,PACA_EXRFI+EX_R11(r13) 2221aa8a5e00SMichael Ellerman mfctr r9 2222aa8a5e00SMichael Ellerman ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2223bdcb1aefSNicholas Piggin ld r11,PACA_L1D_FLUSH_SIZE(r13) 2224bdcb1aefSNicholas Piggin srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2225aa8a5e00SMichael Ellerman mtctr r11 222615a3204dSNicholas Piggin DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2227aa8a5e00SMichael Ellerman 2228aa8a5e00SMichael Ellerman /* order ld/st prior to dcbt stop all streams with flushing */ 2229aa8a5e00SMichael Ellerman sync 2230bdcb1aefSNicholas Piggin 2231bdcb1aefSNicholas Piggin /* 2232bdcb1aefSNicholas Piggin * The load adresses are at staggered offsets within cachelines, 2233bdcb1aefSNicholas Piggin * which suits some pipelines better (on others it should not 2234bdcb1aefSNicholas Piggin * hurt). 2235bdcb1aefSNicholas Piggin */ 2236bdcb1aefSNicholas Piggin1: 2237bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*0(r10) 2238bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*1(r10) 2239bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*2(r10) 2240bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*3(r10) 2241bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*4(r10) 2242bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*5(r10) 2243bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*6(r10) 2244bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*7(r10) 2245bdcb1aefSNicholas Piggin addi r10,r10,0x80*8 2246aa8a5e00SMichael Ellerman bdnz 1b 2247aa8a5e00SMichael Ellerman 2248aa8a5e00SMichael Ellerman mtctr r9 2249aa8a5e00SMichael Ellerman ld r9,PACA_EXRFI+EX_R9(r13) 2250aa8a5e00SMichael Ellerman ld r10,PACA_EXRFI+EX_R10(r13) 2251aa8a5e00SMichael Ellerman ld r11,PACA_EXRFI+EX_R11(r13) 225278ee9946SMichael Ellerman ld r1,PACA_EXRFI+EX_R12(r13) 2253aa8a5e00SMichael Ellerman GET_SCRATCH0(r13); 2254aa8a5e00SMichael Ellerman rfid 2255aa8a5e00SMichael Ellerman 2256aa8a5e00SMichael EllermanTRAMP_REAL_BEGIN(hrfi_flush_fallback) 2257aa8a5e00SMichael Ellerman SET_SCRATCH0(r13); 2258aa8a5e00SMichael Ellerman GET_PACA(r13); 225978ee9946SMichael Ellerman std r1,PACA_EXRFI+EX_R12(r13) 226078ee9946SMichael Ellerman ld r1,PACAKSAVE(r13) 2261aa8a5e00SMichael Ellerman std r9,PACA_EXRFI+EX_R9(r13) 2262aa8a5e00SMichael Ellerman std r10,PACA_EXRFI+EX_R10(r13) 2263aa8a5e00SMichael Ellerman std r11,PACA_EXRFI+EX_R11(r13) 2264aa8a5e00SMichael Ellerman mfctr r9 2265aa8a5e00SMichael Ellerman ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2266bdcb1aefSNicholas Piggin ld r11,PACA_L1D_FLUSH_SIZE(r13) 2267bdcb1aefSNicholas Piggin srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2268aa8a5e00SMichael Ellerman mtctr r11 226915a3204dSNicholas Piggin DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2270aa8a5e00SMichael Ellerman 2271aa8a5e00SMichael Ellerman /* order ld/st prior to dcbt stop all streams with flushing */ 2272aa8a5e00SMichael Ellerman sync 2273bdcb1aefSNicholas Piggin 2274bdcb1aefSNicholas Piggin /* 2275bdcb1aefSNicholas Piggin * The load adresses are at staggered offsets within cachelines, 2276bdcb1aefSNicholas Piggin * which suits some pipelines better (on others it should not 2277bdcb1aefSNicholas Piggin * hurt). 2278bdcb1aefSNicholas Piggin */ 2279bdcb1aefSNicholas Piggin1: 2280bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*0(r10) 2281bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*1(r10) 2282bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*2(r10) 2283bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*3(r10) 2284bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*4(r10) 2285bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*5(r10) 2286bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*6(r10) 2287bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*7(r10) 2288bdcb1aefSNicholas Piggin addi r10,r10,0x80*8 2289aa8a5e00SMichael Ellerman bdnz 1b 2290aa8a5e00SMichael Ellerman 2291aa8a5e00SMichael Ellerman mtctr r9 2292aa8a5e00SMichael Ellerman ld r9,PACA_EXRFI+EX_R9(r13) 2293aa8a5e00SMichael Ellerman ld r10,PACA_EXRFI+EX_R10(r13) 2294aa8a5e00SMichael Ellerman ld r11,PACA_EXRFI+EX_R11(r13) 229578ee9946SMichael Ellerman ld r1,PACA_EXRFI+EX_R12(r13) 2296aa8a5e00SMichael Ellerman GET_SCRATCH0(r13); 2297aa8a5e00SMichael Ellerman hrfid 2298aa8a5e00SMichael Ellerman 229957f26649SNicholas Piggin/* 230057f26649SNicholas Piggin * Real mode exceptions actually use this too, but alternate 230157f26649SNicholas Piggin * instruction code patches (which end up in the common .text area) 230257f26649SNicholas Piggin * cannot reach these if they are put there. 230357f26649SNicholas Piggin */ 230457f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 23054508a74aSNicholas Piggin MASKED_INTERRUPT EXC_STD 23064508a74aSNicholas Piggin MASKED_INTERRUPT EXC_HV 23077230c564SBenjamin Herrenschmidt 23084f6c11dbSPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 2309da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 23104f6c11dbSPaul Mackerras /* 23114f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 23124f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 23134f6c11dbSPaul Mackerras */ 23144f6c11dbSPaul Mackerras mfspr r13, SPRN_SRR0 23154f6c11dbSPaul Mackerras addi r13, r13, 4 23164f6c11dbSPaul Mackerras mtspr SPRN_SRR0, r13 23174f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 2318222f20f1SNicholas Piggin RFI_TO_KERNEL 23194f6c11dbSPaul Mackerras b . 23204f6c11dbSPaul Mackerras 2321da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 23224f6c11dbSPaul Mackerras /* 23234f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 23244f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 23254f6c11dbSPaul Mackerras */ 23264f6c11dbSPaul Mackerras mfspr r13, SPRN_HSRR0 23274f6c11dbSPaul Mackerras addi r13, r13, 4 23284f6c11dbSPaul Mackerras mtspr SPRN_HSRR0, r13 23294f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 2330222f20f1SNicholas Piggin HRFI_TO_KERNEL 23314f6c11dbSPaul Mackerras b . 23324f6c11dbSPaul Mackerras#endif 23334f6c11dbSPaul Mackerras 23340ebc4cdaSBenjamin Herrenschmidt/* 2335057b6d7eSHari Bathini * Ensure that any handlers that get invoked from the exception prologs 2336057b6d7eSHari Bathini * above are below the first 64KB (0x10000) of the kernel image because 2337057b6d7eSHari Bathini * the prologs assemble the addresses of these handlers using the 2338057b6d7eSHari Bathini * LOAD_HANDLER macro, which uses an ori instruction. 23390ebc4cdaSBenjamin Herrenschmidt */ 23400ebc4cdaSBenjamin Herrenschmidt 23410ebc4cdaSBenjamin Herrenschmidt/*** Common interrupt handlers ***/ 23420ebc4cdaSBenjamin Herrenschmidt 23430ebc4cdaSBenjamin Herrenschmidt 2344c1fb6816SMichael Neuling /* 2345c1fb6816SMichael Neuling * Relocation-on interrupts: A subset of the interrupts can be delivered 2346c1fb6816SMichael Neuling * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 2347c1fb6816SMichael Neuling * it. Addresses are the same as the original interrupt addresses, but 2348c1fb6816SMichael Neuling * offset by 0xc000000000004000. 2349c1fb6816SMichael Neuling * It's impossible to receive interrupts below 0x300 via this mechanism. 2350c1fb6816SMichael Neuling * KVM: None of these traps are from the guest ; anything that escalated 2351c1fb6816SMichael Neuling * to HV=1 from HV=0 is delivered via real mode handlers. 2352c1fb6816SMichael Neuling */ 2353c1fb6816SMichael Neuling 2354c1fb6816SMichael Neuling /* 2355c1fb6816SMichael Neuling * This uses the standard macro, since the original 0x300 vector 2356c1fb6816SMichael Neuling * only has extra guff for STAB-based processors -- which never 2357c1fb6816SMichael Neuling * come here. 2358c1fb6816SMichael Neuling */ 2359da2bc464SMichael Ellerman 236057f26649SNicholas PigginEXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 2361b1576fecSAnton Blanchard b __ppc64_runlatch_on 2362fe1952fcSBenjamin Herrenschmidt 236357f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 23648ed8ab40SHari Bathini /* 23658ed8ab40SHari Bathini * The __end_interrupts marker must be past the out-of-line (OOL) 23668ed8ab40SHari Bathini * handlers, so that they are copied to real address 0x100 when running 23678ed8ab40SHari Bathini * a relocatable kernel. This ensures they can be reached from the short 23688ed8ab40SHari Bathini * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 23698ed8ab40SHari Bathini * directly, without using LOAD_HANDLER(). 23708ed8ab40SHari Bathini */ 23718ed8ab40SHari Bathini .align 7 23728ed8ab40SHari Bathini .globl __end_interrupts 23738ed8ab40SHari Bathini__end_interrupts: 237457f26649SNicholas PigginDEFINE_FIXED_SYMBOL(__end_interrupts) 237561383407SBenjamin Herrenschmidt 2376087aa036SChen Gang#ifdef CONFIG_PPC_970_NAP 23777c8cb4b5SNicholas PigginEXC_COMMON_BEGIN(power4_fixup_nap) 2378087aa036SChen Gang andc r9,r9,r10 2379087aa036SChen Gang std r9,TI_LOCAL_FLAGS(r11) 2380087aa036SChen Gang ld r10,_LINK(r1) /* make idle task do the */ 2381087aa036SChen Gang std r10,_NIP(r1) /* equivalent of a blr */ 2382087aa036SChen Gang blr 2383087aa036SChen Gang#endif 2384087aa036SChen Gang 238557f26649SNicholas PigginCLOSE_FIXED_SECTION(real_vectors); 238657f26649SNicholas PigginCLOSE_FIXED_SECTION(real_trampolines); 238757f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_vectors); 238857f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_trampolines); 238957f26649SNicholas Piggin 239057f26649SNicholas PigginUSE_TEXT_SECTION() 239157f26649SNicholas Piggin 2392087aa036SChen Gang/* 23930ebc4cdaSBenjamin Herrenschmidt * Hash table stuff 23940ebc4cdaSBenjamin Herrenschmidt */ 2395f4329f2eSNicholas Piggin .balign IFETCH_ALIGN_BYTES 23966a3bab90SAnton Blancharddo_hash_page: 23974e003747SMichael Ellerman#ifdef CONFIG_PPC_BOOK3S_64 2398e6c2a479SRam Pai lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h 2399398a719dSBenjamin Herrenschmidt ori r0,r0,DSISR_BAD_FAULT_64S@l 2400398a719dSBenjamin Herrenschmidt and. r0,r4,r0 /* weird error? */ 24010ebc4cdaSBenjamin Herrenschmidt bne- handle_page_fault /* if not, try to insert a HPTE */ 2402c911d2e1SChristophe Leroy ld r11, PACA_THREAD_INFO(r13) 24039c1e1052SPaul Mackerras lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 24049c1e1052SPaul Mackerras andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 24059c1e1052SPaul Mackerras bne 77f /* then don't call hash_page now */ 24060ebc4cdaSBenjamin Herrenschmidt 24070ebc4cdaSBenjamin Herrenschmidt /* 24080ebc4cdaSBenjamin Herrenschmidt * r3 contains the faulting address 2409106713a1SAneesh Kumar K.V * r4 msr 24100ebc4cdaSBenjamin Herrenschmidt * r5 contains the trap number 2411aefa5688SAneesh Kumar K.V * r6 contains dsisr 24120ebc4cdaSBenjamin Herrenschmidt * 24137230c564SBenjamin Herrenschmidt * at return r3 = 0 for success, 1 for page fault, negative for error 24140ebc4cdaSBenjamin Herrenschmidt */ 2415106713a1SAneesh Kumar K.V mr r4,r12 2416aefa5688SAneesh Kumar K.V ld r6,_DSISR(r1) 2417106713a1SAneesh Kumar K.V bl __hash_page /* build HPTE if possible */ 2418106713a1SAneesh Kumar K.V cmpdi r3,0 /* see if __hash_page succeeded */ 24190ebc4cdaSBenjamin Herrenschmidt 24207230c564SBenjamin Herrenschmidt /* Success */ 24210ebc4cdaSBenjamin Herrenschmidt beq fast_exc_return_irq /* Return from exception on success */ 24220ebc4cdaSBenjamin Herrenschmidt 24237230c564SBenjamin Herrenschmidt /* Error */ 24247230c564SBenjamin Herrenschmidt blt- 13f 2425d89ba535SNaveen N. Rao 2426d89ba535SNaveen N. Rao /* Reload DSISR into r4 for the DABR check below */ 2427d89ba535SNaveen N. Rao ld r4,_DSISR(r1) 24284e003747SMichael Ellerman#endif /* CONFIG_PPC_BOOK3S_64 */ 24290ebc4cdaSBenjamin Herrenschmidt 2430a546498fSBenjamin Herrenschmidt/* Here we have a page fault that hash_page can't handle. */ 2431a546498fSBenjamin Herrenschmidthandle_page_fault: 2432d89ba535SNaveen N. Rao11: andis. r0,r4,DSISR_DABRMATCH@h 2433d89ba535SNaveen N. Rao bne- handle_dabr_fault 2434d89ba535SNaveen N. Rao ld r4,_DAR(r1) 2435a546498fSBenjamin Herrenschmidt ld r5,_DSISR(r1) 2436a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 2437b1576fecSAnton Blanchard bl do_page_fault 2438a546498fSBenjamin Herrenschmidt cmpdi r3,0 2439f474c28fSRavi Bangoria beq+ ret_from_except_lite 2440b1576fecSAnton Blanchard bl save_nvgprs 2441a546498fSBenjamin Herrenschmidt mr r5,r3 2442a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 2443a546498fSBenjamin Herrenschmidt lwz r4,_DAR(r1) 2444b1576fecSAnton Blanchard bl bad_page_fault 2445b1576fecSAnton Blanchard b ret_from_except 24460ebc4cdaSBenjamin Herrenschmidt 24479c7cc234SK.Prasad/* We have a data breakpoint exception - handle it */ 24489c7cc234SK.Prasadhandle_dabr_fault: 2449b1576fecSAnton Blanchard bl save_nvgprs 24509c7cc234SK.Prasad ld r4,_DAR(r1) 24519c7cc234SK.Prasad ld r5,_DSISR(r1) 24529c7cc234SK.Prasad addi r3,r1,STACK_FRAME_OVERHEAD 2453b1576fecSAnton Blanchard bl do_break 2454f474c28fSRavi Bangoria /* 2455f474c28fSRavi Bangoria * do_break() may have changed the NV GPRS while handling a breakpoint. 2456f474c28fSRavi Bangoria * If so, we need to restore them with their updated values. Don't use 2457f474c28fSRavi Bangoria * ret_from_except_lite here. 2458f474c28fSRavi Bangoria */ 2459f474c28fSRavi Bangoria b ret_from_except 24609c7cc234SK.Prasad 24610ebc4cdaSBenjamin Herrenschmidt 24624e003747SMichael Ellerman#ifdef CONFIG_PPC_BOOK3S_64 24630ebc4cdaSBenjamin Herrenschmidt/* We have a page fault that hash_page could handle but HV refused 24640ebc4cdaSBenjamin Herrenschmidt * the PTE insertion 24650ebc4cdaSBenjamin Herrenschmidt */ 2466b1576fecSAnton Blanchard13: bl save_nvgprs 24670ebc4cdaSBenjamin Herrenschmidt mr r5,r3 24680ebc4cdaSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 24690ebc4cdaSBenjamin Herrenschmidt ld r4,_DAR(r1) 2470b1576fecSAnton Blanchard bl low_hash_fault 2471b1576fecSAnton Blanchard b ret_from_except 2472caca285eSAneesh Kumar K.V#endif 24730ebc4cdaSBenjamin Herrenschmidt 24749c1e1052SPaul Mackerras/* 24759c1e1052SPaul Mackerras * We come here as a result of a DSI at a point where we don't want 24769c1e1052SPaul Mackerras * to call hash_page, such as when we are accessing memory (possibly 24779c1e1052SPaul Mackerras * user memory) inside a PMU interrupt that occurred while interrupts 24789c1e1052SPaul Mackerras * were soft-disabled. We want to invoke the exception handler for 24799c1e1052SPaul Mackerras * the access, or panic if there isn't a handler. 24809c1e1052SPaul Mackerras */ 2481b1576fecSAnton Blanchard77: bl save_nvgprs 24829c1e1052SPaul Mackerras mr r4,r3 24839c1e1052SPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 24849c1e1052SPaul Mackerras li r5,SIGSEGV 2485b1576fecSAnton Blanchard bl bad_page_fault 2486b1576fecSAnton Blanchard b ret_from_except 24874e2bf01bSMichael Ellerman 24884e2bf01bSMichael Ellerman/* 24894e2bf01bSMichael Ellerman * Here we have detected that the kernel stack pointer is bad. 24904e2bf01bSMichael Ellerman * R9 contains the saved CR, r13 points to the paca, 24914e2bf01bSMichael Ellerman * r10 contains the (bad) kernel stack pointer, 24924e2bf01bSMichael Ellerman * r11 and r12 contain the saved SRR0 and SRR1. 24934e2bf01bSMichael Ellerman * We switch to using an emergency stack, save the registers there, 24944e2bf01bSMichael Ellerman * and call kernel_bad_stack(), which panics. 24954e2bf01bSMichael Ellerman */ 24964e2bf01bSMichael Ellermanbad_stack: 24974e2bf01bSMichael Ellerman ld r1,PACAEMERGSP(r13) 24984e2bf01bSMichael Ellerman subi r1,r1,64+INT_FRAME_SIZE 24994e2bf01bSMichael Ellerman std r9,_CCR(r1) 25004e2bf01bSMichael Ellerman std r10,GPR1(r1) 25014e2bf01bSMichael Ellerman std r11,_NIP(r1) 25024e2bf01bSMichael Ellerman std r12,_MSR(r1) 25034e2bf01bSMichael Ellerman mfspr r11,SPRN_DAR 25044e2bf01bSMichael Ellerman mfspr r12,SPRN_DSISR 25054e2bf01bSMichael Ellerman std r11,_DAR(r1) 25064e2bf01bSMichael Ellerman std r12,_DSISR(r1) 25074e2bf01bSMichael Ellerman mflr r10 25084e2bf01bSMichael Ellerman mfctr r11 25094e2bf01bSMichael Ellerman mfxer r12 25104e2bf01bSMichael Ellerman std r10,_LINK(r1) 25114e2bf01bSMichael Ellerman std r11,_CTR(r1) 25124e2bf01bSMichael Ellerman std r12,_XER(r1) 25134e2bf01bSMichael Ellerman SAVE_GPR(0,r1) 25144e2bf01bSMichael Ellerman SAVE_GPR(2,r1) 25154e2bf01bSMichael Ellerman ld r10,EX_R3(r3) 25164e2bf01bSMichael Ellerman std r10,GPR3(r1) 25174e2bf01bSMichael Ellerman SAVE_GPR(4,r1) 25184e2bf01bSMichael Ellerman SAVE_4GPRS(5,r1) 25194e2bf01bSMichael Ellerman ld r9,EX_R9(r3) 25204e2bf01bSMichael Ellerman ld r10,EX_R10(r3) 25214e2bf01bSMichael Ellerman SAVE_2GPRS(9,r1) 25224e2bf01bSMichael Ellerman ld r9,EX_R11(r3) 25234e2bf01bSMichael Ellerman ld r10,EX_R12(r3) 25244e2bf01bSMichael Ellerman ld r11,EX_R13(r3) 25254e2bf01bSMichael Ellerman std r9,GPR11(r1) 25264e2bf01bSMichael Ellerman std r10,GPR12(r1) 25274e2bf01bSMichael Ellerman std r11,GPR13(r1) 25284e2bf01bSMichael EllermanBEGIN_FTR_SECTION 25294e2bf01bSMichael Ellerman ld r10,EX_CFAR(r3) 25304e2bf01bSMichael Ellerman std r10,ORIG_GPR3(r1) 25314e2bf01bSMichael EllermanEND_FTR_SECTION_IFSET(CPU_FTR_CFAR) 25324e2bf01bSMichael Ellerman SAVE_8GPRS(14,r1) 25334e2bf01bSMichael Ellerman SAVE_10GPRS(22,r1) 25344e2bf01bSMichael Ellerman lhz r12,PACA_TRAP_SAVE(r13) 25354e2bf01bSMichael Ellerman std r12,_TRAP(r1) 25364e2bf01bSMichael Ellerman addi r11,r1,INT_FRAME_SIZE 25374e2bf01bSMichael Ellerman std r11,0(r1) 25384e2bf01bSMichael Ellerman li r12,0 25394e2bf01bSMichael Ellerman std r12,0(r11) 25404e2bf01bSMichael Ellerman ld r2,PACATOC(r13) 25414e2bf01bSMichael Ellerman ld r11,exception_marker@toc(r2) 25424e2bf01bSMichael Ellerman std r12,RESULT(r1) 25434e2bf01bSMichael Ellerman std r11,STACK_FRAME_OVERHEAD-16(r1) 25444e2bf01bSMichael Ellerman1: addi r3,r1,STACK_FRAME_OVERHEAD 25454e2bf01bSMichael Ellerman bl kernel_bad_stack 25464e2bf01bSMichael Ellerman b 1b 254715770a13SNaveen N. Rao_ASM_NOKPROBE_SYMBOL(bad_stack); 25480f0c6ca1SNicholas Piggin 25490f0c6ca1SNicholas Piggin/* 2550a9af97aaSNicholas Piggin * When doorbell is triggered from system reset wakeup, the message is 2551a9af97aaSNicholas Piggin * not cleared, so it would fire again when EE is enabled. 2552a9af97aaSNicholas Piggin * 2553a9af97aaSNicholas Piggin * When coming from local_irq_enable, there may be the same problem if 2554a9af97aaSNicholas Piggin * we were hard disabled. 2555a9af97aaSNicholas Piggin * 2556a9af97aaSNicholas Piggin * Execute msgclr to clear pending exceptions before handling it. 2557a9af97aaSNicholas Piggin */ 2558a9af97aaSNicholas Pigginh_doorbell_common_msgclr: 2559a9af97aaSNicholas Piggin LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 2560a9af97aaSNicholas Piggin PPC_MSGCLR(3) 2561a9af97aaSNicholas Piggin b h_doorbell_common 2562a9af97aaSNicholas Piggin 2563a9af97aaSNicholas Piggindoorbell_super_common_msgclr: 2564a9af97aaSNicholas Piggin LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 2565a9af97aaSNicholas Piggin PPC_MSGCLRP(3) 2566a9af97aaSNicholas Piggin b doorbell_super_common 2567a9af97aaSNicholas Piggin 2568a9af97aaSNicholas Piggin/* 25690f0c6ca1SNicholas Piggin * Called from arch_local_irq_enable when an interrupt needs 25700f0c6ca1SNicholas Piggin * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 25710f0c6ca1SNicholas Piggin * which kind of interrupt. MSR:EE is already off. We generate a 25720f0c6ca1SNicholas Piggin * stackframe like if a real interrupt had happened. 25730f0c6ca1SNicholas Piggin * 25740f0c6ca1SNicholas Piggin * Note: While MSR:EE is off, we need to make sure that _MSR 25750f0c6ca1SNicholas Piggin * in the generated frame has EE set to 1 or the exception 25760f0c6ca1SNicholas Piggin * handler will not properly re-enable them. 2577b48bbb82SNicholas Piggin * 2578b48bbb82SNicholas Piggin * Note that we don't specify LR as the NIP (return address) for 2579b48bbb82SNicholas Piggin * the interrupt because that would unbalance the return branch 2580b48bbb82SNicholas Piggin * predictor. 25810f0c6ca1SNicholas Piggin */ 25820f0c6ca1SNicholas Piggin_GLOBAL(__replay_interrupt) 25830f0c6ca1SNicholas Piggin /* We are going to jump to the exception common code which 25840f0c6ca1SNicholas Piggin * will retrieve various register values from the PACA which 25850f0c6ca1SNicholas Piggin * we don't give a damn about, so we don't bother storing them. 25860f0c6ca1SNicholas Piggin */ 25870f0c6ca1SNicholas Piggin mfmsr r12 25883e23a12bSMichael Ellerman LOAD_REG_ADDR(r11, replay_interrupt_return) 25890f0c6ca1SNicholas Piggin mfcr r9 25900f0c6ca1SNicholas Piggin ori r12,r12,MSR_EE 25910f0c6ca1SNicholas Piggin cmpwi r3,0x900 25920f0c6ca1SNicholas Piggin beq decrementer_common 25930f0c6ca1SNicholas Piggin cmpwi r3,0x500 2594e6c1203dSNicholas PigginBEGIN_FTR_SECTION 2595e6c1203dSNicholas Piggin beq h_virt_irq_common 2596e6c1203dSNicholas PigginFTR_SECTION_ELSE 25970f0c6ca1SNicholas Piggin beq hardware_interrupt_common 2598e6c1203dSNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) 2599f442d004SMadhavan Srinivasan cmpwi r3,0xf00 2600f442d004SMadhavan Srinivasan beq performance_monitor_common 26010f0c6ca1SNicholas PigginBEGIN_FTR_SECTION 2602d6f73fc6SNicholas Piggin cmpwi r3,0xa00 2603a9af97aaSNicholas Piggin beq h_doorbell_common_msgclr 26040f0c6ca1SNicholas Piggin cmpwi r3,0xe60 26050f0c6ca1SNicholas Piggin beq hmi_exception_common 26060f0c6ca1SNicholas PigginFTR_SECTION_ELSE 26070f0c6ca1SNicholas Piggin cmpwi r3,0xa00 2608a9af97aaSNicholas Piggin beq doorbell_super_common_msgclr 26090f0c6ca1SNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 26103e23a12bSMichael Ellermanreplay_interrupt_return: 26110f0c6ca1SNicholas Piggin blr 2612b48bbb82SNicholas Piggin 261315770a13SNaveen N. Rao_ASM_NOKPROBE_SYMBOL(__replay_interrupt) 2614