1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 20ebc4cdaSBenjamin Herrenschmidt/* 30ebc4cdaSBenjamin Herrenschmidt * This file contains the 64-bit "server" PowerPC variant 40ebc4cdaSBenjamin Herrenschmidt * of the low level exception handling including exception 50ebc4cdaSBenjamin Herrenschmidt * vectors, exception return, part of the slb and stab 60ebc4cdaSBenjamin Herrenschmidt * handling and other fixed offset specific things. 70ebc4cdaSBenjamin Herrenschmidt * 80ebc4cdaSBenjamin Herrenschmidt * This file is meant to be #included from head_64.S due to 925985edcSLucas De Marchi * position dependent assembly. 100ebc4cdaSBenjamin Herrenschmidt * 110ebc4cdaSBenjamin Herrenschmidt * Most of this originates from head_64.S and thus has the same 120ebc4cdaSBenjamin Herrenschmidt * copyright history. 130ebc4cdaSBenjamin Herrenschmidt * 140ebc4cdaSBenjamin Herrenschmidt */ 150ebc4cdaSBenjamin Herrenschmidt 167230c564SBenjamin Herrenschmidt#include <asm/hw_irq.h> 178aa34ab8SBenjamin Herrenschmidt#include <asm/exception-64s.h> 1846f52210SStephen Rothwell#include <asm/ptrace.h> 197cba160aSShreyas B. Prabhu#include <asm/cpuidle.h> 20da2bc464SMichael Ellerman#include <asm/head-64.h> 212c86cd18SChristophe Leroy#include <asm/feature-fixups.h> 22890274c2SMichael Ellerman#include <asm/kup.h> 238aa34ab8SBenjamin Herrenschmidt 2415820091SNicholas Piggin/* PACA save area offsets (exgen, exmc, etc) */ 2515820091SNicholas Piggin#define EX_R9 0 2615820091SNicholas Piggin#define EX_R10 8 2715820091SNicholas Piggin#define EX_R11 16 2815820091SNicholas Piggin#define EX_R12 24 2915820091SNicholas Piggin#define EX_R13 32 3015820091SNicholas Piggin#define EX_DAR 40 3115820091SNicholas Piggin#define EX_DSISR 48 3215820091SNicholas Piggin#define EX_CCR 52 3315820091SNicholas Piggin#define EX_CFAR 56 3415820091SNicholas Piggin#define EX_PPR 64 3515820091SNicholas Piggin#if defined(CONFIG_RELOCATABLE) 3615820091SNicholas Piggin#define EX_CTR 72 3715820091SNicholas Piggin.if EX_SIZE != 10 3815820091SNicholas Piggin .error "EX_SIZE is wrong" 3915820091SNicholas Piggin.endif 4015820091SNicholas Piggin#else 4115820091SNicholas Piggin.if EX_SIZE != 9 4215820091SNicholas Piggin .error "EX_SIZE is wrong" 4315820091SNicholas Piggin.endif 4415820091SNicholas Piggin#endif 4515820091SNicholas Piggin 460ebc4cdaSBenjamin Herrenschmidt/* 4712a04809SNicholas Piggin * We're short on space and time in the exception prolog, so we can't 4812a04809SNicholas Piggin * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 4912a04809SNicholas Piggin * Instead we get the base of the kernel from paca->kernelbase and or in the low 5012a04809SNicholas Piggin * part of label. This requires that the label be within 64KB of kernelbase, and 5112a04809SNicholas Piggin * that kernelbase be 64K aligned. 5212a04809SNicholas Piggin */ 5312a04809SNicholas Piggin#define LOAD_HANDLER(reg, label) \ 5412a04809SNicholas Piggin ld reg,PACAKBASE(r13); /* get high part of &label */ \ 5512a04809SNicholas Piggin ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) 5612a04809SNicholas Piggin 5712a04809SNicholas Piggin#define __LOAD_HANDLER(reg, label) \ 5812a04809SNicholas Piggin ld reg,PACAKBASE(r13); \ 5912a04809SNicholas Piggin ori reg,reg,(ABS_ADDR(label))@l 6012a04809SNicholas Piggin 6112a04809SNicholas Piggin/* 6212a04809SNicholas Piggin * Branches from unrelocated code (e.g., interrupts) to labels outside 6312a04809SNicholas Piggin * head-y require >64K offsets. 6412a04809SNicholas Piggin */ 6512a04809SNicholas Piggin#define __LOAD_FAR_HANDLER(reg, label) \ 6612a04809SNicholas Piggin ld reg,PACAKBASE(r13); \ 6712a04809SNicholas Piggin ori reg,reg,(ABS_ADDR(label))@l; \ 6812a04809SNicholas Piggin addis reg,reg,(ABS_ADDR(label))@h 6912a04809SNicholas Piggin 7012a04809SNicholas Piggin/* Exception register prefixes */ 7112a04809SNicholas Piggin#define EXC_HV 1 7212a04809SNicholas Piggin#define EXC_STD 0 7312a04809SNicholas Piggin 7412a04809SNicholas Piggin#if defined(CONFIG_RELOCATABLE) 7512a04809SNicholas Piggin/* 7612a04809SNicholas Piggin * If we support interrupts with relocation on AND we're a relocatable kernel, 7712a04809SNicholas Piggin * we need to use CTR to get to the 2nd level handler. So, save/restore it 7812a04809SNicholas Piggin * when required. 7912a04809SNicholas Piggin */ 8012a04809SNicholas Piggin#define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 8112a04809SNicholas Piggin#define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 8212a04809SNicholas Piggin#define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 8312a04809SNicholas Piggin#else 8412a04809SNicholas Piggin/* ...else CTR is unused and in register. */ 8512a04809SNicholas Piggin#define SAVE_CTR(reg, area) 8612a04809SNicholas Piggin#define GET_CTR(reg, area) mfctr reg 8712a04809SNicholas Piggin#define RESTORE_CTR(reg, area) 8812a04809SNicholas Piggin#endif 8912a04809SNicholas Piggin 9012a04809SNicholas Piggin/* 9112a04809SNicholas Piggin * PPR save/restore macros used in exceptions-64s.S 9212a04809SNicholas Piggin * Used for P7 or later processors 9312a04809SNicholas Piggin */ 9412a04809SNicholas Piggin#define SAVE_PPR(area, ra) \ 9512a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(940) \ 9612a04809SNicholas Piggin ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \ 9712a04809SNicholas Piggin std ra,_PPR(r1); \ 9812a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 9912a04809SNicholas Piggin 10012a04809SNicholas Piggin#define RESTORE_PPR_PACA(area, ra) \ 10112a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(941) \ 10212a04809SNicholas Piggin ld ra,area+EX_PPR(r13); \ 10312a04809SNicholas Piggin mtspr SPRN_PPR,ra; \ 10412a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 10512a04809SNicholas Piggin 10612a04809SNicholas Piggin/* 10712a04809SNicholas Piggin * Get an SPR into a register if the CPU has the given feature 10812a04809SNicholas Piggin */ 10912a04809SNicholas Piggin#define OPT_GET_SPR(ra, spr, ftr) \ 11012a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(943) \ 11112a04809SNicholas Piggin mfspr ra,spr; \ 11212a04809SNicholas PigginEND_FTR_SECTION_NESTED(ftr,ftr,943) 11312a04809SNicholas Piggin 11412a04809SNicholas Piggin/* 11512a04809SNicholas Piggin * Set an SPR from a register if the CPU has the given feature 11612a04809SNicholas Piggin */ 11712a04809SNicholas Piggin#define OPT_SET_SPR(ra, spr, ftr) \ 11812a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(943) \ 11912a04809SNicholas Piggin mtspr spr,ra; \ 12012a04809SNicholas PigginEND_FTR_SECTION_NESTED(ftr,ftr,943) 12112a04809SNicholas Piggin 12212a04809SNicholas Piggin/* 12312a04809SNicholas Piggin * Save a register to the PACA if the CPU has the given feature 12412a04809SNicholas Piggin */ 12512a04809SNicholas Piggin#define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 12612a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(943) \ 12712a04809SNicholas Piggin std ra,offset(r13); \ 12812a04809SNicholas PigginEND_FTR_SECTION_NESTED(ftr,ftr,943) 12912a04809SNicholas Piggin 13012a04809SNicholas Piggin.macro EXCEPTION_PROLOG_0 area 131d7fb34c7SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 13212a04809SNicholas Piggin GET_PACA(r13) 13312a04809SNicholas Piggin std r9,\area\()+EX_R9(r13) /* save r9 */ 13412a04809SNicholas Piggin OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR) 13512a04809SNicholas Piggin HMT_MEDIUM 13612a04809SNicholas Piggin std r10,\area\()+EX_R10(r13) /* save r10 - r12 */ 13712a04809SNicholas Piggin OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 13812a04809SNicholas Piggin.endm 13912a04809SNicholas Piggin 1405312c494SNicholas Piggin.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, dar, dsisr, bitmask 14112a04809SNicholas Piggin OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR) 14212a04809SNicholas Piggin OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR) 14312a04809SNicholas Piggin INTERRUPT_TO_KERNEL 14412a04809SNicholas Piggin SAVE_CTR(r10, \area\()) 14512a04809SNicholas Piggin mfcr r9 14612a04809SNicholas Piggin .if \kvm 14712a04809SNicholas Piggin KVMTEST \hsrr \vec 14812a04809SNicholas Piggin .endif 14912a04809SNicholas Piggin .if \bitmask 15012a04809SNicholas Piggin lbz r10,PACAIRQSOFTMASK(r13) 15112a04809SNicholas Piggin andi. r10,r10,\bitmask 15212a04809SNicholas Piggin /* Associate vector numbers with bits in paca->irq_happened */ 15312a04809SNicholas Piggin .if \vec == 0x500 || \vec == 0xea0 15412a04809SNicholas Piggin li r10,PACA_IRQ_EE 15512a04809SNicholas Piggin .elseif \vec == 0x900 15612a04809SNicholas Piggin li r10,PACA_IRQ_DEC 15712a04809SNicholas Piggin .elseif \vec == 0xa00 || \vec == 0xe80 15812a04809SNicholas Piggin li r10,PACA_IRQ_DBELL 15912a04809SNicholas Piggin .elseif \vec == 0xe60 16012a04809SNicholas Piggin li r10,PACA_IRQ_HMI 16112a04809SNicholas Piggin .elseif \vec == 0xf00 16212a04809SNicholas Piggin li r10,PACA_IRQ_PMI 16312a04809SNicholas Piggin .else 16412a04809SNicholas Piggin .abort "Bad maskable vector" 16512a04809SNicholas Piggin .endif 16612a04809SNicholas Piggin 16712a04809SNicholas Piggin .if \hsrr 16812a04809SNicholas Piggin bne masked_Hinterrupt 16912a04809SNicholas Piggin .else 17012a04809SNicholas Piggin bne masked_interrupt 17112a04809SNicholas Piggin .endif 17212a04809SNicholas Piggin .endif 17312a04809SNicholas Piggin 17412a04809SNicholas Piggin std r11,\area\()+EX_R11(r13) 17512a04809SNicholas Piggin std r12,\area\()+EX_R12(r13) 1765312c494SNicholas Piggin 1775312c494SNicholas Piggin /* 1785312c494SNicholas Piggin * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI], 1795312c494SNicholas Piggin * because a d-side MCE will clobber those registers so is 1805312c494SNicholas Piggin * not recoverable if they are live. 1815312c494SNicholas Piggin */ 18212a04809SNicholas Piggin GET_SCRATCH0(r10) 18312a04809SNicholas Piggin std r10,\area\()+EX_R13(r13) 1845312c494SNicholas Piggin .if \dar 1855312c494SNicholas Piggin mfspr r10,SPRN_DAR 1865312c494SNicholas Piggin std r10,\area\()+EX_DAR(r13) 1875312c494SNicholas Piggin .endif 1885312c494SNicholas Piggin .if \dsisr 1895312c494SNicholas Piggin mfspr r10,SPRN_DSISR 1905312c494SNicholas Piggin stw r10,\area\()+EX_DSISR(r13) 1915312c494SNicholas Piggin .endif 19212a04809SNicholas Piggin.endm 19312a04809SNicholas Piggin 19412a04809SNicholas Piggin.macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri 19512a04809SNicholas Piggin ld r10,PACAKMSR(r13) /* get MSR value for kernel */ 19612a04809SNicholas Piggin .if ! \set_ri 19712a04809SNicholas Piggin xori r10,r10,MSR_RI /* Clear MSR_RI */ 19812a04809SNicholas Piggin .endif 19912a04809SNicholas Piggin .if \hsrr 20012a04809SNicholas Piggin mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 20112a04809SNicholas Piggin mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 20212a04809SNicholas Piggin mtspr SPRN_HSRR1,r10 20312a04809SNicholas Piggin .else 20463d60d0cSNicholas Piggin mfspr r11,SPRN_SRR0 /* save SRR0 */ 20512a04809SNicholas Piggin mfspr r12,SPRN_SRR1 /* and SRR1 */ 20612a04809SNicholas Piggin mtspr SPRN_SRR1,r10 20763d60d0cSNicholas Piggin .endif 20863d60d0cSNicholas Piggin LOAD_HANDLER(r10, \label\()) 20963d60d0cSNicholas Piggin .if \hsrr 21063d60d0cSNicholas Piggin mtspr SPRN_HSRR0,r10 21163d60d0cSNicholas Piggin HRFI_TO_KERNEL 21263d60d0cSNicholas Piggin .else 21363d60d0cSNicholas Piggin mtspr SPRN_SRR0,r10 21412a04809SNicholas Piggin RFI_TO_KERNEL 21512a04809SNicholas Piggin .endif 21612a04809SNicholas Piggin b . /* prevent speculative execution */ 21712a04809SNicholas Piggin.endm 21812a04809SNicholas Piggin 21912a04809SNicholas Piggin.macro EXCEPTION_PROLOG_2_VIRT label, hsrr 22012a04809SNicholas Piggin#ifdef CONFIG_RELOCATABLE 22112a04809SNicholas Piggin .if \hsrr 22212a04809SNicholas Piggin mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 22312a04809SNicholas Piggin .else 22412a04809SNicholas Piggin mfspr r11,SPRN_SRR0 /* save SRR0 */ 22512a04809SNicholas Piggin .endif 22612a04809SNicholas Piggin LOAD_HANDLER(r12, \label\()) 22712a04809SNicholas Piggin mtctr r12 22812a04809SNicholas Piggin .if \hsrr 22912a04809SNicholas Piggin mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 23012a04809SNicholas Piggin .else 23112a04809SNicholas Piggin mfspr r12,SPRN_SRR1 /* and HSRR1 */ 23212a04809SNicholas Piggin .endif 23312a04809SNicholas Piggin li r10,MSR_RI 23412a04809SNicholas Piggin mtmsrd r10,1 /* Set RI (EE=0) */ 23512a04809SNicholas Piggin bctr 23612a04809SNicholas Piggin#else 23712a04809SNicholas Piggin .if \hsrr 23812a04809SNicholas Piggin mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 23912a04809SNicholas Piggin mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 24012a04809SNicholas Piggin .else 24112a04809SNicholas Piggin mfspr r11,SPRN_SRR0 /* save SRR0 */ 24212a04809SNicholas Piggin mfspr r12,SPRN_SRR1 /* and SRR1 */ 24312a04809SNicholas Piggin .endif 24412a04809SNicholas Piggin li r10,MSR_RI 24512a04809SNicholas Piggin mtmsrd r10,1 /* Set RI (EE=0) */ 24612a04809SNicholas Piggin b \label 24712a04809SNicholas Piggin#endif 24812a04809SNicholas Piggin.endm 24912a04809SNicholas Piggin 25012a04809SNicholas Piggin/* 25112a04809SNicholas Piggin * Branch to label using its 0xC000 address. This results in instruction 25212a04809SNicholas Piggin * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 25312a04809SNicholas Piggin * on using mtmsr rather than rfid. 25412a04809SNicholas Piggin * 25512a04809SNicholas Piggin * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 25612a04809SNicholas Piggin * load KBASE for a slight optimisation. 25712a04809SNicholas Piggin */ 25812a04809SNicholas Piggin#define BRANCH_TO_C000(reg, label) \ 2590e10be2bSNicholas Piggin __LOAD_FAR_HANDLER(reg, label); \ 26012a04809SNicholas Piggin mtctr reg; \ 26112a04809SNicholas Piggin bctr 26212a04809SNicholas Piggin 26312a04809SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 26412a04809SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 26512a04809SNicholas Piggin/* 26612a04809SNicholas Piggin * If hv is possible, interrupts come into to the hv version 26712a04809SNicholas Piggin * of the kvmppc_interrupt code, which then jumps to the PR handler, 26812a04809SNicholas Piggin * kvmppc_interrupt_pr, if the guest is a PR guest. 26912a04809SNicholas Piggin */ 27012a04809SNicholas Piggin#define kvmppc_interrupt kvmppc_interrupt_hv 27112a04809SNicholas Piggin#else 27212a04809SNicholas Piggin#define kvmppc_interrupt kvmppc_interrupt_pr 27312a04809SNicholas Piggin#endif 27412a04809SNicholas Piggin 27512a04809SNicholas Piggin.macro KVMTEST hsrr, n 27612a04809SNicholas Piggin lbz r10,HSTATE_IN_GUEST(r13) 27712a04809SNicholas Piggin cmpwi r10,0 27812a04809SNicholas Piggin .if \hsrr 27912a04809SNicholas Piggin bne do_kvm_H\n 28012a04809SNicholas Piggin .else 28112a04809SNicholas Piggin bne do_kvm_\n 28212a04809SNicholas Piggin .endif 28312a04809SNicholas Piggin.endm 28412a04809SNicholas Piggin 28512a04809SNicholas Piggin.macro KVM_HANDLER area, hsrr, n, skip 28612a04809SNicholas Piggin .if \skip 28712a04809SNicholas Piggin cmpwi r10,KVM_GUEST_MODE_SKIP 28812a04809SNicholas Piggin beq 89f 28912a04809SNicholas Piggin .else 29012a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(947) 29112a04809SNicholas Piggin ld r10,\area+EX_CFAR(r13) 29212a04809SNicholas Piggin std r10,HSTATE_CFAR(r13) 29312a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947) 29412a04809SNicholas Piggin .endif 29512a04809SNicholas Piggin 29612a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(948) 29712a04809SNicholas Piggin ld r10,\area+EX_PPR(r13) 29812a04809SNicholas Piggin std r10,HSTATE_PPR(r13) 29912a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948) 30012a04809SNicholas Piggin ld r10,\area+EX_R10(r13) 30112a04809SNicholas Piggin std r12,HSTATE_SCRATCH0(r13) 30212a04809SNicholas Piggin sldi r12,r9,32 30312a04809SNicholas Piggin /* HSRR variants have the 0x2 bit added to their trap number */ 30412a04809SNicholas Piggin .if \hsrr 30512a04809SNicholas Piggin ori r12,r12,(\n + 0x2) 30612a04809SNicholas Piggin .else 30712a04809SNicholas Piggin ori r12,r12,(\n) 30812a04809SNicholas Piggin .endif 30964e41351SNicholas Piggin 31064e41351SNicholas Piggin#ifdef CONFIG_RELOCATABLE 31164e41351SNicholas Piggin /* 31264e41351SNicholas Piggin * KVM requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives 31364e41351SNicholas Piggin * outside the head section. CONFIG_RELOCATABLE KVM expects CTR 31464e41351SNicholas Piggin * to be saved in HSTATE_SCRATCH1. 31564e41351SNicholas Piggin */ 31664e41351SNicholas Piggin mfctr r9 31764e41351SNicholas Piggin std r9,HSTATE_SCRATCH1(r13) 31864e41351SNicholas Piggin __LOAD_FAR_HANDLER(r9, kvmppc_interrupt) 31964e41351SNicholas Piggin mtctr r9 32064e41351SNicholas Piggin ld r9,\area+EX_R9(r13) 32164e41351SNicholas Piggin bctr 32264e41351SNicholas Piggin#else 32364e41351SNicholas Piggin ld r9,\area+EX_R9(r13) 32464e41351SNicholas Piggin b kvmppc_interrupt 32564e41351SNicholas Piggin#endif 32664e41351SNicholas Piggin 32712a04809SNicholas Piggin 32812a04809SNicholas Piggin .if \skip 32912a04809SNicholas Piggin89: mtocrf 0x80,r9 33012a04809SNicholas Piggin ld r9,\area+EX_R9(r13) 33112a04809SNicholas Piggin ld r10,\area+EX_R10(r13) 33212a04809SNicholas Piggin .if \hsrr 33312a04809SNicholas Piggin b kvmppc_skip_Hinterrupt 33412a04809SNicholas Piggin .else 33512a04809SNicholas Piggin b kvmppc_skip_interrupt 33612a04809SNicholas Piggin .endif 33712a04809SNicholas Piggin .endif 33812a04809SNicholas Piggin.endm 33912a04809SNicholas Piggin 34012a04809SNicholas Piggin#else 34112a04809SNicholas Piggin.macro KVMTEST hsrr, n 34212a04809SNicholas Piggin.endm 34312a04809SNicholas Piggin.macro KVM_HANDLER area, hsrr, n, skip 34412a04809SNicholas Piggin.endm 34512a04809SNicholas Piggin#endif 34612a04809SNicholas Piggin 34712a04809SNicholas Piggin#define EXCEPTION_PROLOG_COMMON_1() \ 34812a04809SNicholas Piggin std r9,_CCR(r1); /* save CR in stackframe */ \ 34912a04809SNicholas Piggin std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 35012a04809SNicholas Piggin std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 35112a04809SNicholas Piggin std r10,0(r1); /* make stack chain pointer */ \ 35212a04809SNicholas Piggin std r0,GPR0(r1); /* save r0 in stackframe */ \ 35312a04809SNicholas Piggin std r10,GPR1(r1); /* save r1 in stackframe */ \ 35412a04809SNicholas Piggin 35512a04809SNicholas Piggin/* Save original regs values from save area to stack frame. */ 35612a04809SNicholas Piggin#define EXCEPTION_PROLOG_COMMON_2(area) \ 35712a04809SNicholas Piggin ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 35812a04809SNicholas Piggin ld r10,area+EX_R10(r13); \ 35912a04809SNicholas Piggin std r9,GPR9(r1); \ 36012a04809SNicholas Piggin std r10,GPR10(r1); \ 36112a04809SNicholas Piggin ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 36212a04809SNicholas Piggin ld r10,area+EX_R12(r13); \ 36312a04809SNicholas Piggin ld r11,area+EX_R13(r13); \ 36412a04809SNicholas Piggin std r9,GPR11(r1); \ 36512a04809SNicholas Piggin std r10,GPR12(r1); \ 36612a04809SNicholas Piggin std r11,GPR13(r1); \ 36712a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(66); \ 36812a04809SNicholas Piggin ld r10,area+EX_CFAR(r13); \ 36912a04809SNicholas Piggin std r10,ORIG_GPR3(r1); \ 37012a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 37112a04809SNicholas Piggin GET_CTR(r10, area); \ 37212a04809SNicholas Piggin std r10,_CTR(r1); 37312a04809SNicholas Piggin 374d064151fSNicholas Piggin#define EXCEPTION_PROLOG_COMMON_3(trap) \ 37512a04809SNicholas Piggin std r2,GPR2(r1); /* save r2 in stackframe */ \ 37612a04809SNicholas Piggin SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 37712a04809SNicholas Piggin SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 37812a04809SNicholas Piggin mflr r9; /* Get LR, later save to stack */ \ 37912a04809SNicholas Piggin ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 38012a04809SNicholas Piggin std r9,_LINK(r1); \ 38112a04809SNicholas Piggin lbz r10,PACAIRQSOFTMASK(r13); \ 38212a04809SNicholas Piggin mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 38312a04809SNicholas Piggin std r10,SOFTE(r1); \ 38412a04809SNicholas Piggin std r11,_XER(r1); \ 385d064151fSNicholas Piggin li r9,(trap)+1; \ 38612a04809SNicholas Piggin std r9,_TRAP(r1); /* set trap number */ \ 38712a04809SNicholas Piggin li r10,0; \ 38812a04809SNicholas Piggin ld r11,exception_marker@toc(r2); \ 38912a04809SNicholas Piggin std r10,RESULT(r1); /* clear regs->result */ \ 39012a04809SNicholas Piggin std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 39112a04809SNicholas Piggin 392d064151fSNicholas Piggin/* 393d064151fSNicholas Piggin * On entry r13 points to the paca, r9-r13 are saved in the paca, 394d064151fSNicholas Piggin * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 395d064151fSNicholas Piggin * SRR1, and relocation is on. 396d064151fSNicholas Piggin */ 397d064151fSNicholas Piggin#define EXCEPTION_COMMON(area, trap) \ 398d064151fSNicholas Piggin andi. r10,r12,MSR_PR; /* See if coming from user */ \ 399d064151fSNicholas Piggin mr r10,r1; /* Save r1 */ \ 400d064151fSNicholas Piggin subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 401d064151fSNicholas Piggin beq- 1f; \ 402d064151fSNicholas Piggin ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 4030a882e28SNicholas Piggin1: tdgei r1,-INT_FRAME_SIZE; /* trap if r1 is in userspace */ \ 4040a882e28SNicholas Piggin EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0; \ 405d064151fSNicholas Piggin3: EXCEPTION_PROLOG_COMMON_1(); \ 406d064151fSNicholas Piggin kuap_save_amr_and_lock r9, r10, cr1, cr0; \ 407d064151fSNicholas Piggin beq 4f; /* if from kernel mode */ \ 408d064151fSNicholas Piggin ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 409d064151fSNicholas Piggin SAVE_PPR(area, r9); \ 410d064151fSNicholas Piggin4: EXCEPTION_PROLOG_COMMON_2(area); \ 411d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(trap); \ 412d064151fSNicholas Piggin ACCOUNT_STOLEN_TIME 413d064151fSNicholas Piggin 414d064151fSNicholas Piggin/* 415d064151fSNicholas Piggin * Exception where stack is already set in r1, r1 is saved in r10. 416d064151fSNicholas Piggin * PPR save and CPU accounting is not done (for some reason). 417d064151fSNicholas Piggin */ 418d064151fSNicholas Piggin#define EXCEPTION_COMMON_STACK(area, trap) \ 419d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_1(); \ 420d064151fSNicholas Piggin kuap_save_amr_and_lock r9, r10, cr1; \ 421d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_2(area); \ 422d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(trap) 423d064151fSNicholas Piggin 424391e941bSNicholas Piggin/* 425391e941bSNicholas Piggin * Restore all registers including H/SRR0/1 saved in a stack frame of a 426391e941bSNicholas Piggin * standard exception. 427391e941bSNicholas Piggin */ 428391e941bSNicholas Piggin.macro EXCEPTION_RESTORE_REGS hsrr 429391e941bSNicholas Piggin /* Move original SRR0 and SRR1 into the respective regs */ 430391e941bSNicholas Piggin ld r9,_MSR(r1) 431391e941bSNicholas Piggin .if \hsrr 432391e941bSNicholas Piggin mtspr SPRN_HSRR1,r9 433391e941bSNicholas Piggin .else 434391e941bSNicholas Piggin mtspr SPRN_SRR1,r9 435391e941bSNicholas Piggin .endif 436391e941bSNicholas Piggin ld r9,_NIP(r1) 437391e941bSNicholas Piggin .if \hsrr 438391e941bSNicholas Piggin mtspr SPRN_HSRR0,r9 439391e941bSNicholas Piggin .else 440391e941bSNicholas Piggin mtspr SPRN_SRR0,r9 441391e941bSNicholas Piggin .endif 442391e941bSNicholas Piggin ld r9,_CTR(r1) 443391e941bSNicholas Piggin mtctr r9 444391e941bSNicholas Piggin ld r9,_XER(r1) 445391e941bSNicholas Piggin mtxer r9 446391e941bSNicholas Piggin ld r9,_LINK(r1) 447391e941bSNicholas Piggin mtlr r9 448391e941bSNicholas Piggin ld r9,_CCR(r1) 449391e941bSNicholas Piggin mtcr r9 450391e941bSNicholas Piggin REST_8GPRS(2, r1) 451391e941bSNicholas Piggin REST_4GPRS(10, r1) 452391e941bSNicholas Piggin REST_GPR(0, r1) 453391e941bSNicholas Piggin /* restore original r1. */ 454391e941bSNicholas Piggin ld r1,GPR1(r1) 455391e941bSNicholas Piggin.endm 456d064151fSNicholas Piggin 45712a04809SNicholas Piggin#define RUNLATCH_ON \ 45812a04809SNicholas PigginBEGIN_FTR_SECTION \ 45912a04809SNicholas Piggin ld r3, PACA_THREAD_INFO(r13); \ 46012a04809SNicholas Piggin ld r4,TI_LOCAL_FLAGS(r3); \ 46112a04809SNicholas Piggin andi. r0,r4,_TLF_RUNLATCH; \ 46212a04809SNicholas Piggin beql ppc64_runlatch_on_trampoline; \ 46312a04809SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_CTRL) 46412a04809SNicholas Piggin 46512a04809SNicholas Piggin/* 46612a04809SNicholas Piggin * When the idle code in power4_idle puts the CPU into NAP mode, 46712a04809SNicholas Piggin * it has to do so in a loop, and relies on the external interrupt 46812a04809SNicholas Piggin * and decrementer interrupt entry code to get it out of the loop. 46912a04809SNicholas Piggin * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 47012a04809SNicholas Piggin * to signal that it is in the loop and needs help to get out. 47112a04809SNicholas Piggin */ 47212a04809SNicholas Piggin#ifdef CONFIG_PPC_970_NAP 47312a04809SNicholas Piggin#define FINISH_NAP \ 47412a04809SNicholas PigginBEGIN_FTR_SECTION \ 47512a04809SNicholas Piggin ld r11, PACA_THREAD_INFO(r13); \ 47612a04809SNicholas Piggin ld r9,TI_LOCAL_FLAGS(r11); \ 47712a04809SNicholas Piggin andi. r10,r9,_TLF_NAPPING; \ 47812a04809SNicholas Piggin bnel power4_fixup_nap; \ 47912a04809SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 48012a04809SNicholas Piggin#else 48112a04809SNicholas Piggin#define FINISH_NAP 48212a04809SNicholas Piggin#endif 48312a04809SNicholas Piggin 484a0502434SNicholas Piggin/* 485a0502434SNicholas Piggin * Following are the BOOK3S exception handler helper macros. 486a0502434SNicholas Piggin * Handlers come in a number of types, and each type has a number of varieties. 487a0502434SNicholas Piggin * 488a0502434SNicholas Piggin * EXC_REAL_* - real, unrelocated exception vectors 489a0502434SNicholas Piggin * EXC_VIRT_* - virt (AIL), unrelocated exception vectors 490a0502434SNicholas Piggin * TRAMP_REAL_* - real, unrelocated helpers (virt can call these) 491a0502434SNicholas Piggin * TRAMP_VIRT_* - virt, unreloc helpers (in practice, real can use) 492a0502434SNicholas Piggin * TRAMP_KVM - KVM handlers that get put into real, unrelocated 493a0502434SNicholas Piggin * EXC_COMMON - virt, relocated common handlers 494a0502434SNicholas Piggin * 495a0502434SNicholas Piggin * The EXC handlers are given a name, and branch to name_common, or the 496a0502434SNicholas Piggin * appropriate KVM or masking function. Vector handler verieties are as 497a0502434SNicholas Piggin * follows: 498a0502434SNicholas Piggin * 499a0502434SNicholas Piggin * EXC_{REAL|VIRT}_BEGIN/END - used to open-code the exception 500a0502434SNicholas Piggin * 501a0502434SNicholas Piggin * EXC_{REAL|VIRT} - standard exception 502a0502434SNicholas Piggin * 503a0502434SNicholas Piggin * EXC_{REAL|VIRT}_suffix 504a0502434SNicholas Piggin * where _suffix is: 505a0502434SNicholas Piggin * - _MASKABLE - maskable exception 506a0502434SNicholas Piggin * - _OOL - out of line with trampoline to common handler 507a0502434SNicholas Piggin * - _HV - HV exception 508a0502434SNicholas Piggin * 509a0502434SNicholas Piggin * There can be combinations, e.g., EXC_VIRT_OOL_MASKABLE_HV 510a0502434SNicholas Piggin * 511a0502434SNicholas Piggin * KVM handlers come in the following verieties: 512a0502434SNicholas Piggin * TRAMP_KVM 513a0502434SNicholas Piggin * TRAMP_KVM_SKIP 514a0502434SNicholas Piggin * TRAMP_KVM_HV 515a0502434SNicholas Piggin * TRAMP_KVM_HV_SKIP 516a0502434SNicholas Piggin * 517a0502434SNicholas Piggin * COMMON handlers come in the following verieties: 518a0502434SNicholas Piggin * EXC_COMMON_BEGIN/END - used to open-code the handler 519a0502434SNicholas Piggin * EXC_COMMON 520a0502434SNicholas Piggin * EXC_COMMON_ASYNC 521a0502434SNicholas Piggin * 522a0502434SNicholas Piggin * TRAMP_REAL and TRAMP_VIRT can be used with BEGIN/END. KVM 523a0502434SNicholas Piggin * and OOL handlers are implemented as types of TRAMP and TRAMP_VIRT handlers. 524a0502434SNicholas Piggin */ 525a0502434SNicholas Piggin 526a0502434SNicholas Piggin#define __EXC_REAL(name, start, size, area) \ 527a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 528a0502434SNicholas Piggin EXCEPTION_PROLOG_0 area ; \ 5295312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0, 0, 0 ; \ 530a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ 531a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 532a0502434SNicholas Piggin 533a0502434SNicholas Piggin#define EXC_REAL(name, start, size) \ 534a0502434SNicholas Piggin __EXC_REAL(name, start, size, PACA_EXGEN) 535a0502434SNicholas Piggin 536a0502434SNicholas Piggin#define __EXC_VIRT(name, start, size, realvec, area) \ 537a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 538a0502434SNicholas Piggin EXCEPTION_PROLOG_0 area ; \ 5395312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0, 0, 0; \ 540a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ 541a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 542a0502434SNicholas Piggin 543a0502434SNicholas Piggin#define EXC_VIRT(name, start, size, realvec) \ 544a0502434SNicholas Piggin __EXC_VIRT(name, start, size, realvec, PACA_EXGEN) 545a0502434SNicholas Piggin 546a0502434SNicholas Piggin#define EXC_REAL_MASKABLE(name, start, size, bitmask) \ 547a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 548a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 5495312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, 0, 0, bitmask ; \ 550a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ 551a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 552a0502434SNicholas Piggin 553a0502434SNicholas Piggin#define EXC_VIRT_MASKABLE(name, start, size, realvec, bitmask) \ 554a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 555a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 5565312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, 0, 0, bitmask ; \ 557a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ 558a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 559a0502434SNicholas Piggin 560a0502434SNicholas Piggin#define EXC_REAL_HV(name, start, size) \ 561a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 562a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN; \ 5635312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0, 0, 0 ; \ 564a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 ; \ 565a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 566a0502434SNicholas Piggin 567a0502434SNicholas Piggin#define EXC_VIRT_HV(name, start, size, realvec) \ 568a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 569a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN; \ 5705312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, 0 ; \ 571a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV ; \ 572a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 573a0502434SNicholas Piggin 574a0502434SNicholas Piggin#define __EXC_REAL_OOL(name, start, size) \ 575a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 576a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 577a0502434SNicholas Piggin b tramp_real_##name ; \ 578a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 579a0502434SNicholas Piggin 580a0502434SNicholas Piggin#define __TRAMP_REAL_OOL(name, vec) \ 581a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 5825312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0, 0, 0 ; \ 583a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 584a0502434SNicholas Piggin 585a0502434SNicholas Piggin#define EXC_REAL_OOL(name, start, size) \ 586a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size); \ 587a0502434SNicholas Piggin __TRAMP_REAL_OOL(name, start) 588a0502434SNicholas Piggin 589a0502434SNicholas Piggin#define __EXC_REAL_OOL_MASKABLE(name, start, size) \ 590a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size) 591a0502434SNicholas Piggin 592a0502434SNicholas Piggin#define __TRAMP_REAL_OOL_MASKABLE(name, vec, bitmask) \ 593a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 5945312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0, 0, bitmask ; \ 595a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 596a0502434SNicholas Piggin 597a0502434SNicholas Piggin#define EXC_REAL_OOL_MASKABLE(name, start, size, bitmask) \ 598a0502434SNicholas Piggin __EXC_REAL_OOL_MASKABLE(name, start, size); \ 599a0502434SNicholas Piggin __TRAMP_REAL_OOL_MASKABLE(name, start, bitmask) 600a0502434SNicholas Piggin 601a0502434SNicholas Piggin#define __EXC_REAL_OOL_HV(name, start, size) \ 602a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size) 603a0502434SNicholas Piggin 604a0502434SNicholas Piggin#define __TRAMP_REAL_OOL_HV(name, vec) \ 605a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 6065312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0, 0, 0 ; \ 607a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 608a0502434SNicholas Piggin 609a0502434SNicholas Piggin#define EXC_REAL_OOL_HV(name, start, size) \ 610a0502434SNicholas Piggin __EXC_REAL_OOL_HV(name, start, size); \ 611a0502434SNicholas Piggin __TRAMP_REAL_OOL_HV(name, start) 612a0502434SNicholas Piggin 613a0502434SNicholas Piggin#define __EXC_REAL_OOL_MASKABLE_HV(name, start, size) \ 614a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size) 615a0502434SNicholas Piggin 616a0502434SNicholas Piggin#define __TRAMP_REAL_OOL_MASKABLE_HV(name, vec, bitmask) \ 617a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 6185312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0, 0, bitmask ; \ 619a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 620a0502434SNicholas Piggin 621a0502434SNicholas Piggin#define EXC_REAL_OOL_MASKABLE_HV(name, start, size, bitmask) \ 622a0502434SNicholas Piggin __EXC_REAL_OOL_MASKABLE_HV(name, start, size); \ 623a0502434SNicholas Piggin __TRAMP_REAL_OOL_MASKABLE_HV(name, start, bitmask) 624a0502434SNicholas Piggin 625a0502434SNicholas Piggin#define __EXC_VIRT_OOL(name, start, size) \ 626a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 627a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 628a0502434SNicholas Piggin b tramp_virt_##name; \ 629a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 630a0502434SNicholas Piggin 631a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL(name, realvec) \ 632a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 6335312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0, 0, 0 ; \ 634a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD 635a0502434SNicholas Piggin 636a0502434SNicholas Piggin#define EXC_VIRT_OOL(name, start, size, realvec) \ 637a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size); \ 638a0502434SNicholas Piggin __TRAMP_VIRT_OOL(name, realvec) 639a0502434SNicholas Piggin 640a0502434SNicholas Piggin#define __EXC_VIRT_OOL_MASKABLE(name, start, size) \ 641a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size) 642a0502434SNicholas Piggin 643a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) \ 644a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 6455312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, 0, 0, bitmask ; \ 646a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 647a0502434SNicholas Piggin 648a0502434SNicholas Piggin#define EXC_VIRT_OOL_MASKABLE(name, start, size, realvec, bitmask) \ 649a0502434SNicholas Piggin __EXC_VIRT_OOL_MASKABLE(name, start, size); \ 650a0502434SNicholas Piggin __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) 651a0502434SNicholas Piggin 652a0502434SNicholas Piggin#define __EXC_VIRT_OOL_HV(name, start, size) \ 653a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size) 654a0502434SNicholas Piggin 655a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL_HV(name, realvec) \ 656a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 6575312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, 0 ; \ 658a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV 659a0502434SNicholas Piggin 660a0502434SNicholas Piggin#define EXC_VIRT_OOL_HV(name, start, size, realvec) \ 661a0502434SNicholas Piggin __EXC_VIRT_OOL_HV(name, start, size); \ 662a0502434SNicholas Piggin __TRAMP_VIRT_OOL_HV(name, realvec) 663a0502434SNicholas Piggin 664a0502434SNicholas Piggin#define __EXC_VIRT_OOL_MASKABLE_HV(name, start, size) \ 665a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size) 666a0502434SNicholas Piggin 667a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) \ 668a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 6695312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, bitmask ; \ 670a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV 671a0502434SNicholas Piggin 672a0502434SNicholas Piggin#define EXC_VIRT_OOL_MASKABLE_HV(name, start, size, realvec, bitmask) \ 673a0502434SNicholas Piggin __EXC_VIRT_OOL_MASKABLE_HV(name, start, size); \ 674a0502434SNicholas Piggin __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) 675a0502434SNicholas Piggin 676a0502434SNicholas Piggin#define TRAMP_KVM(area, n) \ 677a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_##n); \ 678a0502434SNicholas Piggin KVM_HANDLER area, EXC_STD, n, 0 679a0502434SNicholas Piggin 680a0502434SNicholas Piggin#define TRAMP_KVM_SKIP(area, n) \ 681a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_##n); \ 682a0502434SNicholas Piggin KVM_HANDLER area, EXC_STD, n, 1 683a0502434SNicholas Piggin 684a0502434SNicholas Piggin#define TRAMP_KVM_HV(area, n) \ 685a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_H##n); \ 686a0502434SNicholas Piggin KVM_HANDLER area, EXC_HV, n, 0 687a0502434SNicholas Piggin 688a0502434SNicholas Piggin#define TRAMP_KVM_HV_SKIP(area, n) \ 689a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_H##n); \ 690a0502434SNicholas Piggin KVM_HANDLER area, EXC_HV, n, 1 691a0502434SNicholas Piggin 692a0502434SNicholas Piggin#define EXC_COMMON(name, realvec, hdlr) \ 693a0502434SNicholas Piggin EXC_COMMON_BEGIN(name); \ 694a0502434SNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, realvec); \ 695a0502434SNicholas Piggin bl save_nvgprs; \ 696a0502434SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11); \ 697a0502434SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD; \ 698a0502434SNicholas Piggin bl hdlr; \ 699a0502434SNicholas Piggin b ret_from_except 700a0502434SNicholas Piggin 701a0502434SNicholas Piggin/* 702a0502434SNicholas Piggin * Like EXC_COMMON, but for exceptions that can occur in the idle task and 703a0502434SNicholas Piggin * therefore need the special idle handling (finish nap and runlatch) 704a0502434SNicholas Piggin */ 705a0502434SNicholas Piggin#define EXC_COMMON_ASYNC(name, realvec, hdlr) \ 706a0502434SNicholas Piggin EXC_COMMON_BEGIN(name); \ 707a0502434SNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, realvec); \ 708a0502434SNicholas Piggin FINISH_NAP; \ 709a0502434SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11); \ 710a0502434SNicholas Piggin RUNLATCH_ON; \ 711a0502434SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD; \ 712a0502434SNicholas Piggin bl hdlr; \ 713a0502434SNicholas Piggin b ret_from_except_lite 714a0502434SNicholas Piggin 71512a04809SNicholas Piggin 71612a04809SNicholas Piggin/* 71757f26649SNicholas Piggin * There are a few constraints to be concerned with. 71857f26649SNicholas Piggin * - Real mode exceptions code/data must be located at their physical location. 71957f26649SNicholas Piggin * - Virtual mode exceptions must be mapped at their 0xc000... location. 72057f26649SNicholas Piggin * - Fixed location code must not call directly beyond the __end_interrupts 72157f26649SNicholas Piggin * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 72257f26649SNicholas Piggin * must be used. 72357f26649SNicholas Piggin * - LOAD_HANDLER targets must be within first 64K of physical 0 / 72457f26649SNicholas Piggin * virtual 0xc00... 72557f26649SNicholas Piggin * - Conditional branch targets must be within +/-32K of caller. 72657f26649SNicholas Piggin * 72757f26649SNicholas Piggin * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 72857f26649SNicholas Piggin * therefore don't have to run in physically located code or rfid to 72957f26649SNicholas Piggin * virtual mode kernel code. However on relocatable kernels they do have 73057f26649SNicholas Piggin * to branch to KERNELBASE offset because the rest of the kernel (outside 73157f26649SNicholas Piggin * the exception vectors) may be located elsewhere. 73257f26649SNicholas Piggin * 73357f26649SNicholas Piggin * Virtual exceptions correspond with physical, except their entry points 73457f26649SNicholas Piggin * are offset by 0xc000000000000000 and also tend to get an added 0x4000 73557f26649SNicholas Piggin * offset applied. Virtual exceptions are enabled with the Alternate 73657f26649SNicholas Piggin * Interrupt Location (AIL) bit set in the LPCR. However this does not 73757f26649SNicholas Piggin * guarantee they will be delivered virtually. Some conditions (see the ISA) 73857f26649SNicholas Piggin * cause exceptions to be delivered in real mode. 73957f26649SNicholas Piggin * 74057f26649SNicholas Piggin * It's impossible to receive interrupts below 0x300 via AIL. 74157f26649SNicholas Piggin * 74257f26649SNicholas Piggin * KVM: None of the virtual exceptions are from the guest. Anything that 74357f26649SNicholas Piggin * escalated to HV=1 from HV=0 is delivered via real mode handlers. 74457f26649SNicholas Piggin * 74557f26649SNicholas Piggin * 7460ebc4cdaSBenjamin Herrenschmidt * We layout physical memory as follows: 7470ebc4cdaSBenjamin Herrenschmidt * 0x0000 - 0x00ff : Secondary processor spin code 74857f26649SNicholas Piggin * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 74957f26649SNicholas Piggin * 0x1900 - 0x3fff : Real mode trampolines 75057f26649SNicholas Piggin * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 75157f26649SNicholas Piggin * 0x5900 - 0x6fff : Relon mode trampolines 7520ebc4cdaSBenjamin Herrenschmidt * 0x7000 - 0x7fff : FWNMI data area 75357f26649SNicholas Piggin * 0x8000 - .... : Common interrupt handlers, remaining early 75457f26649SNicholas Piggin * setup code, rest of kernel. 755e0319829SNicholas Piggin * 756e0319829SNicholas Piggin * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 757e0319829SNicholas Piggin * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 758e0319829SNicholas Piggin * vectors there. 7590ebc4cdaSBenjamin Herrenschmidt */ 76057f26649SNicholas PigginOPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 76157f26649SNicholas PigginOPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 76257f26649SNicholas PigginOPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 76357f26649SNicholas PigginOPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 764ccd47702SNicholas Piggin 765ccd47702SNicholas Piggin#ifdef CONFIG_PPC_POWERNV 766bd3524feSNicholas Piggin .globl start_real_trampolines 767bd3524feSNicholas Piggin .globl end_real_trampolines 768bd3524feSNicholas Piggin .globl start_virt_trampolines 769bd3524feSNicholas Piggin .globl end_virt_trampolines 770ccd47702SNicholas Piggin#endif 771ccd47702SNicholas Piggin 77257f26649SNicholas Piggin#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 77357f26649SNicholas Piggin/* 77457f26649SNicholas Piggin * Data area reserved for FWNMI option. 77557f26649SNicholas Piggin * This address (0x7000) is fixed by the RPA. 77657f26649SNicholas Piggin * pseries and powernv need to keep the whole page from 77757f26649SNicholas Piggin * 0x7000 to 0x8000 free for use by the firmware 77857f26649SNicholas Piggin */ 77957f26649SNicholas PigginZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 78057f26649SNicholas PigginOPEN_TEXT_SECTION(0x8000) 78157f26649SNicholas Piggin#else 78257f26649SNicholas PigginOPEN_TEXT_SECTION(0x7000) 78357f26649SNicholas Piggin#endif 78457f26649SNicholas Piggin 78557f26649SNicholas PigginUSE_FIXED_SECTION(real_vectors) 78657f26649SNicholas Piggin 7870ebc4cdaSBenjamin Herrenschmidt/* 7880ebc4cdaSBenjamin Herrenschmidt * This is the start of the interrupt handlers for pSeries 7890ebc4cdaSBenjamin Herrenschmidt * This code runs with relocation off. 7900ebc4cdaSBenjamin Herrenschmidt * Code from here to __end_interrupts gets copied down to real 7910ebc4cdaSBenjamin Herrenschmidt * address 0x100 when we are running a relocatable kernel. 7920ebc4cdaSBenjamin Herrenschmidt * Therefore any relative branches in this section must only 7930ebc4cdaSBenjamin Herrenschmidt * branch to labels in this section. 7940ebc4cdaSBenjamin Herrenschmidt */ 7950ebc4cdaSBenjamin Herrenschmidt .globl __start_interrupts 7960ebc4cdaSBenjamin Herrenschmidt__start_interrupts: 7970ebc4cdaSBenjamin Herrenschmidt 798e0319829SNicholas Piggin/* No virt vectors corresponding with 0x0..0x100 */ 7991a6822d1SNicholas PigginEXC_VIRT_NONE(0x4000, 0x100) 800e0319829SNicholas Piggin 801fb479e44SNicholas Piggin 802a7c1ca19SNicholas PigginEXC_REAL_BEGIN(system_reset, 0x100, 0x100) 803fb479e44SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 804fb479e44SNicholas Piggin /* 805fb479e44SNicholas Piggin * If running native on arch 2.06 or later, check if we are waking up 806ba6d334aSBenjamin Herrenschmidt * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 807ba6d334aSBenjamin Herrenschmidt * bits 46:47. A non-0 value indicates that we are coming from a power 808ba6d334aSBenjamin Herrenschmidt * saving state. The idle wakeup handler initially runs in real mode, 809ba6d334aSBenjamin Herrenschmidt * but we branch to the 0xc000... address so we can turn on relocation 8100e10be2bSNicholas Piggin * with mtmsrd later, after SPRs are restored. 8110e10be2bSNicholas Piggin * 8120e10be2bSNicholas Piggin * Careful to minimise cost for the fast path (idle wakeup) while 8130e10be2bSNicholas Piggin * also avoiding clobbering CFAR for the debug path (non-idle). 8140e10be2bSNicholas Piggin * 8150e10be2bSNicholas Piggin * For the idle wake case volatile registers can be clobbered, which 8160e10be2bSNicholas Piggin * is why we use those initially. If it turns out to not be an idle 8170e10be2bSNicholas Piggin * wake, carefully put everything back the way it was, so we can use 8180e10be2bSNicholas Piggin * common exception macros to handle it. 819fb479e44SNicholas Piggin */ 820a7c1ca19SNicholas PigginBEGIN_FTR_SECTION 8210e10be2bSNicholas Piggin SET_SCRATCH0(r13) 8220e10be2bSNicholas Piggin GET_PACA(r13) 8230e10be2bSNicholas Piggin std r3,PACA_EXNMI+0*8(r13) 8240e10be2bSNicholas Piggin std r4,PACA_EXNMI+1*8(r13) 8250e10be2bSNicholas Piggin std r5,PACA_EXNMI+2*8(r13) 826a7c1ca19SNicholas Piggin mfspr r3,SPRN_SRR1 8270e10be2bSNicholas Piggin mfocrf r4,0x80 8280e10be2bSNicholas Piggin rlwinm. r5,r3,47-31,30,31 8290e10be2bSNicholas Piggin bne+ system_reset_idle_wake 8300e10be2bSNicholas Piggin /* Not powersave wakeup. Restore regs for regular interrupt handler. */ 8310e10be2bSNicholas Piggin mtocrf 0x80,r4 8320e10be2bSNicholas Piggin ld r3,PACA_EXNMI+0*8(r13) 8330e10be2bSNicholas Piggin ld r4,PACA_EXNMI+1*8(r13) 8340e10be2bSNicholas Piggin ld r5,PACA_EXNMI+2*8(r13) 8350e10be2bSNicholas Piggin GET_SCRATCH0(r13) 836a7c1ca19SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 837fb479e44SNicholas Piggin#endif 838fb479e44SNicholas Piggin 8390e10be2bSNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXNMI 8400e10be2bSNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 1, 0x100, 0, 0, 0 841a7c1ca19SNicholas Piggin EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 842c4f3b52cSNicholas Piggin /* 843c4f3b52cSNicholas Piggin * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 844c4f3b52cSNicholas Piggin * being used, so a nested NMI exception would corrupt it. 8450e10be2bSNicholas Piggin * 8460e10be2bSNicholas Piggin * In theory, we should not enable relocation here if it was disabled 8470e10be2bSNicholas Piggin * in SRR1, because the MMU may not be configured to support it (e.g., 8480e10be2bSNicholas Piggin * SLB may have been cleared). In practice, there should only be a few 8490e10be2bSNicholas Piggin * small windows where that's the case, and sreset is considered to 8500e10be2bSNicholas Piggin * be dangerous anyway. 851c4f3b52cSNicholas Piggin */ 8521a6822d1SNicholas PigginEXC_REAL_END(system_reset, 0x100, 0x100) 8530e10be2bSNicholas Piggin 8541a6822d1SNicholas PigginEXC_VIRT_NONE(0x4100, 0x100) 8556de6638bSNicholas PigginTRAMP_KVM(PACA_EXNMI, 0x100) 856fb479e44SNicholas Piggin 857fb479e44SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 8580e10be2bSNicholas PigginTRAMP_REAL_BEGIN(system_reset_idle_wake) 8590e10be2bSNicholas Piggin /* We are waking up from idle, so may clobber any volatile register */ 8600e10be2bSNicholas Piggin cmpwi cr1,r5,2 8610e10be2bSNicholas Piggin bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */ 8620e10be2bSNicholas Piggin BRANCH_TO_C000(r12, DOTSYM(idle_return_gpr_loss)) 863371fefd6SPaul Mackerras#endif 864371fefd6SPaul Mackerras 865acc8da44SNicholas Piggin#ifdef CONFIG_PPC_PSERIES 866acc8da44SNicholas Piggin/* 867acc8da44SNicholas Piggin * Vectors for the FWNMI option. Share common code. 868acc8da44SNicholas Piggin */ 869acc8da44SNicholas PigginTRAMP_REAL_BEGIN(system_reset_fwnmi) 870acc8da44SNicholas Piggin /* See comment at system_reset exception, don't turn on RI */ 871acc8da44SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXNMI 872acc8da44SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0, 0, 0 873acc8da44SNicholas Piggin EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 874acc8da44SNicholas Piggin 875acc8da44SNicholas Piggin#endif /* CONFIG_PPC_PSERIES */ 876acc8da44SNicholas Piggin 877a3d96f70SNicholas PigginEXC_COMMON_BEGIN(system_reset_common) 878c4f3b52cSNicholas Piggin /* 879c4f3b52cSNicholas Piggin * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 880c4f3b52cSNicholas Piggin * to recover, but nested NMI will notice in_nmi and not recover 881c4f3b52cSNicholas Piggin * because of the use of the NMI stack. in_nmi reentrancy is tested in 882c4f3b52cSNicholas Piggin * system_reset_exception. 883c4f3b52cSNicholas Piggin */ 884c4f3b52cSNicholas Piggin lhz r10,PACA_IN_NMI(r13) 885c4f3b52cSNicholas Piggin addi r10,r10,1 886c4f3b52cSNicholas Piggin sth r10,PACA_IN_NMI(r13) 887c4f3b52cSNicholas Piggin li r10,MSR_RI 888c4f3b52cSNicholas Piggin mtmsrd r10,1 889aca79d2bSVaidyanathan Srinivasan 890b1ee8a3dSNicholas Piggin mr r10,r1 891b1ee8a3dSNicholas Piggin ld r1,PACA_NMI_EMERG_SP(r13) 892b1ee8a3dSNicholas Piggin subi r1,r1,INT_FRAME_SIZE 89347169fbaSNicholas Piggin EXCEPTION_COMMON_STACK(PACA_EXNMI, 0x100) 89447169fbaSNicholas Piggin bl save_nvgprs 89547169fbaSNicholas Piggin /* 89647169fbaSNicholas Piggin * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does 89747169fbaSNicholas Piggin * the right thing. We do not want to reconcile because that goes 89847169fbaSNicholas Piggin * through irq tracing which we don't want in NMI. 89947169fbaSNicholas Piggin * 90047169fbaSNicholas Piggin * Save PACAIRQHAPPENED because some code will do a hard disable 90147169fbaSNicholas Piggin * (e.g., xmon). So we want to restore this back to where it was 90247169fbaSNicholas Piggin * when we return. DAR is unused in the stack, so save it there. 90347169fbaSNicholas Piggin */ 90447169fbaSNicholas Piggin li r10,IRQS_ALL_DISABLED 90547169fbaSNicholas Piggin stb r10,PACAIRQSOFTMASK(r13) 90647169fbaSNicholas Piggin lbz r10,PACAIRQHAPPENED(r13) 90747169fbaSNicholas Piggin std r10,_DAR(r1) 90847169fbaSNicholas Piggin 909c06075f3SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 910c06075f3SNicholas Piggin bl system_reset_exception 91115b4dd79SNicholas Piggin 91215b4dd79SNicholas Piggin /* Clear MSR_RI before setting SRR0 and SRR1. */ 913fbc50063SNicholas Piggin li r9,0 91415b4dd79SNicholas Piggin mtmsrd r9,1 915c4f3b52cSNicholas Piggin 916c4f3b52cSNicholas Piggin /* 91715b4dd79SNicholas Piggin * MSR_RI is clear, now we can decrement paca->in_nmi. 918c4f3b52cSNicholas Piggin */ 919c4f3b52cSNicholas Piggin lhz r10,PACA_IN_NMI(r13) 920c4f3b52cSNicholas Piggin subi r10,r10,1 921c4f3b52cSNicholas Piggin sth r10,PACA_IN_NMI(r13) 922c4f3b52cSNicholas Piggin 92315b4dd79SNicholas Piggin /* 92415b4dd79SNicholas Piggin * Restore soft mask settings. 92515b4dd79SNicholas Piggin */ 92615b4dd79SNicholas Piggin ld r10,_DAR(r1) 92715b4dd79SNicholas Piggin stb r10,PACAIRQHAPPENED(r13) 92815b4dd79SNicholas Piggin ld r10,SOFTE(r1) 92915b4dd79SNicholas Piggin stb r10,PACAIRQSOFTMASK(r13) 93015b4dd79SNicholas Piggin 931391e941bSNicholas Piggin EXCEPTION_RESTORE_REGS EXC_STD 93215b4dd79SNicholas Piggin RFI_TO_USER_OR_KERNEL 933582baf44SNicholas Piggin 9340ebc4cdaSBenjamin Herrenschmidt 9351a6822d1SNicholas PigginEXC_REAL_BEGIN(machine_check, 0x200, 0x100) 936b01c8b54SPaul Mackerras /* This is moved out of line as it can be patched by FW, but 937b01c8b54SPaul Mackerras * some code path might still want to branch into the original 938b01c8b54SPaul Mackerras * vector 939b01c8b54SPaul Mackerras */ 9405dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXMC 9411e9b4507SMahesh SalgaonkarBEGIN_FTR_SECTION 942db7d31acSMahesh Salgaonkar b machine_check_common_early 9431e9b4507SMahesh SalgaonkarFTR_SECTION_ELSE 9441707dd16SPaul Mackerras b machine_check_pSeries_0 9451e9b4507SMahesh SalgaonkarALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 9461a6822d1SNicholas PigginEXC_REAL_END(machine_check, 0x200, 0x100) 9471a6822d1SNicholas PigginEXC_VIRT_NONE(0x4200, 0x100) 948db7d31acSMahesh SalgaonkarTRAMP_REAL_BEGIN(machine_check_common_early) 9495312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0, 0, 0 950afcf0095SNicholas Piggin /* 951afcf0095SNicholas Piggin * Register contents: 952afcf0095SNicholas Piggin * R13 = PACA 953afcf0095SNicholas Piggin * R9 = CR 954afcf0095SNicholas Piggin * Original R9 to R13 is saved on PACA_EXMC 955afcf0095SNicholas Piggin * 956afcf0095SNicholas Piggin * Switch to mc_emergency stack and handle re-entrancy (we limit 957afcf0095SNicholas Piggin * the nested MCE upto level 4 to avoid stack overflow). 958afcf0095SNicholas Piggin * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 959afcf0095SNicholas Piggin * 960afcf0095SNicholas Piggin * We use paca->in_mce to check whether this is the first entry or 961afcf0095SNicholas Piggin * nested machine check. We increment paca->in_mce to track nested 962afcf0095SNicholas Piggin * machine checks. 963afcf0095SNicholas Piggin * 964afcf0095SNicholas Piggin * If this is the first entry then set stack pointer to 965afcf0095SNicholas Piggin * paca->mc_emergency_sp, otherwise r1 is already pointing to 966afcf0095SNicholas Piggin * stack frame on mc_emergency stack. 967afcf0095SNicholas Piggin * 968afcf0095SNicholas Piggin * NOTE: We are here with MSR_ME=0 (off), which means we risk a 969afcf0095SNicholas Piggin * checkstop if we get another machine check exception before we do 970afcf0095SNicholas Piggin * rfid with MSR_ME=1. 9711945bc45SNicholas Piggin * 9721945bc45SNicholas Piggin * This interrupt can wake directly from idle. If that is the case, 9731945bc45SNicholas Piggin * the machine check is handled then the idle wakeup code is called 9742bf1071aSNicholas Piggin * to restore state. 975afcf0095SNicholas Piggin */ 976afcf0095SNicholas Piggin mr r11,r1 /* Save r1 */ 977afcf0095SNicholas Piggin lhz r10,PACA_IN_MCE(r13) 978afcf0095SNicholas Piggin cmpwi r10,0 /* Are we in nested machine check */ 979afcf0095SNicholas Piggin bne 0f /* Yes, we are. */ 980afcf0095SNicholas Piggin /* First machine check entry */ 981afcf0095SNicholas Piggin ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 982afcf0095SNicholas Piggin0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 983afcf0095SNicholas Piggin addi r10,r10,1 /* increment paca->in_mce */ 984afcf0095SNicholas Piggin sth r10,PACA_IN_MCE(r13) 985afcf0095SNicholas Piggin /* Limit nested MCE to level 4 to avoid stack overflow */ 986ba41e1e1SBalbir Singh cmpwi r10,MAX_MCE_DEPTH 987afcf0095SNicholas Piggin bgt 2f /* Check if we hit limit of 4 */ 988afcf0095SNicholas Piggin std r11,GPR1(r1) /* Save r1 on the stack. */ 989afcf0095SNicholas Piggin std r11,0(r1) /* make stack chain pointer */ 990afcf0095SNicholas Piggin mfspr r11,SPRN_SRR0 /* Save SRR0 */ 991afcf0095SNicholas Piggin std r11,_NIP(r1) 992afcf0095SNicholas Piggin mfspr r11,SPRN_SRR1 /* Save SRR1 */ 993afcf0095SNicholas Piggin std r11,_MSR(r1) 994afcf0095SNicholas Piggin mfspr r11,SPRN_DAR /* Save DAR */ 995afcf0095SNicholas Piggin std r11,_DAR(r1) 996afcf0095SNicholas Piggin mfspr r11,SPRN_DSISR /* Save DSISR */ 997afcf0095SNicholas Piggin std r11,_DSISR(r1) 998afcf0095SNicholas Piggin std r9,_CCR(r1) /* Save CR in stackframe */ 999e13e7cd4SNicholas Piggin /* We don't touch AMR here, we never go to virtual mode */ 1000afcf0095SNicholas Piggin /* Save r9 through r13 from EXMC save area to stack frame. */ 1001afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 1002afcf0095SNicholas Piggin mfmsr r11 /* get MSR value */ 1003db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1004afcf0095SNicholas Piggin ori r11,r11,MSR_ME /* turn on ME bit */ 1005db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1006afcf0095SNicholas Piggin ori r11,r11,MSR_RI /* turn on RI bit */ 1007afcf0095SNicholas Piggin LOAD_HANDLER(r12, machine_check_handle_early) 1008afcf0095SNicholas Piggin1: mtspr SPRN_SRR0,r12 1009afcf0095SNicholas Piggin mtspr SPRN_SRR1,r11 1010222f20f1SNicholas Piggin RFI_TO_KERNEL 1011afcf0095SNicholas Piggin b . /* prevent speculative execution */ 1012afcf0095SNicholas Piggin2: 1013afcf0095SNicholas Piggin /* Stack overflow. Stay on emergency stack and panic. 1014afcf0095SNicholas Piggin * Keep the ME bit off while panic-ing, so that if we hit 1015afcf0095SNicholas Piggin * another machine check we checkstop. 1016afcf0095SNicholas Piggin */ 1017afcf0095SNicholas Piggin addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 1018afcf0095SNicholas Piggin ld r11,PACAKMSR(r13) 1019afcf0095SNicholas Piggin LOAD_HANDLER(r12, unrecover_mce) 1020afcf0095SNicholas Piggin li r10,MSR_ME 1021afcf0095SNicholas Piggin andc r11,r11,r10 /* Turn off MSR_ME */ 1022afcf0095SNicholas Piggin b 1b 1023afcf0095SNicholas Piggin b . /* prevent speculative execution */ 1024afcf0095SNicholas Piggin 1025afcf0095SNicholas PigginTRAMP_REAL_BEGIN(machine_check_pSeries) 1026afcf0095SNicholas Piggin .globl machine_check_fwnmi 1027afcf0095SNicholas Pigginmachine_check_fwnmi: 10285dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXMC 1029a43c1590SMahesh SalgaonkarBEGIN_FTR_SECTION 1030db7d31acSMahesh Salgaonkar b machine_check_common_early 1031a43c1590SMahesh SalgaonkarEND_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 1032afcf0095SNicholas Pigginmachine_check_pSeries_0: 103302a12581SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 1, 1, 0 1034afcf0095SNicholas Piggin /* 103583a980f7SNicholas Piggin * MSR_RI is not enabled, because PACA_EXMC is being used, so a 103683a980f7SNicholas Piggin * nested machine check corrupts it. machine_check_common enables 103783a980f7SNicholas Piggin * MSR_RI. 1038afcf0095SNicholas Piggin */ 10392d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0 1040afcf0095SNicholas Piggin 1041afcf0095SNicholas PigginTRAMP_KVM_SKIP(PACA_EXMC, 0x200) 1042afcf0095SNicholas Piggin 1043afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_common) 1044afcf0095SNicholas Piggin /* 1045afcf0095SNicholas Piggin * Machine check is different because we use a different 1046afcf0095SNicholas Piggin * save area: PACA_EXMC instead of PACA_EXGEN. 1047afcf0095SNicholas Piggin */ 1048d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXMC, 0x200) 1049afcf0095SNicholas Piggin FINISH_NAP 1050afcf0095SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1051afcf0095SNicholas Piggin ld r3,PACA_EXMC+EX_DAR(r13) 1052afcf0095SNicholas Piggin lwz r4,PACA_EXMC+EX_DSISR(r13) 1053afcf0095SNicholas Piggin /* Enable MSR_RI when finished with PACA_EXMC */ 1054afcf0095SNicholas Piggin li r10,MSR_RI 1055afcf0095SNicholas Piggin mtmsrd r10,1 1056afcf0095SNicholas Piggin std r3,_DAR(r1) 1057afcf0095SNicholas Piggin std r4,_DSISR(r1) 1058afcf0095SNicholas Piggin bl save_nvgprs 1059afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1060afcf0095SNicholas Piggin bl machine_check_exception 1061afcf0095SNicholas Piggin b ret_from_except 1062afcf0095SNicholas Piggin 1063afcf0095SNicholas Piggin#define MACHINE_CHECK_HANDLER_WINDUP \ 1064afcf0095SNicholas Piggin /* Clear MSR_RI before setting SRR0 and SRR1. */\ 1065fbc50063SNicholas Piggin li r9,0; \ 1066afcf0095SNicholas Piggin mtmsrd r9,1; /* Clear MSR_RI */ \ 1067ad73d8d4SNicholas Piggin /* Decrement paca->in_mce now RI is clear. */ \ 1068ad73d8d4SNicholas Piggin lhz r12,PACA_IN_MCE(r13); \ 1069ad73d8d4SNicholas Piggin subi r12,r12,1; \ 1070ad73d8d4SNicholas Piggin sth r12,PACA_IN_MCE(r13); \ 1071391e941bSNicholas Piggin EXCEPTION_RESTORE_REGS EXC_STD 1072afcf0095SNicholas Piggin 10731945bc45SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 10741945bc45SNicholas Piggin/* 10751945bc45SNicholas Piggin * This is an idle wakeup. Low level machine check has already been 10761945bc45SNicholas Piggin * done. Queue the event then call the idle code to do the wake up. 10771945bc45SNicholas Piggin */ 10781945bc45SNicholas PigginEXC_COMMON_BEGIN(machine_check_idle_common) 10791945bc45SNicholas Piggin bl machine_check_queue_event 10801945bc45SNicholas Piggin 10811945bc45SNicholas Piggin /* 10821945bc45SNicholas Piggin * We have not used any non-volatile GPRs here, and as a rule 10831945bc45SNicholas Piggin * most exception code including machine check does not. 10841945bc45SNicholas Piggin * Therefore PACA_NAPSTATELOST does not need to be set. Idle 10851945bc45SNicholas Piggin * wakeup will restore volatile registers. 10861945bc45SNicholas Piggin * 10871945bc45SNicholas Piggin * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. 10881945bc45SNicholas Piggin * 10891945bc45SNicholas Piggin * Then decrement MCE nesting after finishing with the stack. 10901945bc45SNicholas Piggin */ 10911945bc45SNicholas Piggin ld r3,_MSR(r1) 109210d91611SNicholas Piggin ld r4,_LINK(r1) 10931945bc45SNicholas Piggin 10941945bc45SNicholas Piggin lhz r11,PACA_IN_MCE(r13) 10951945bc45SNicholas Piggin subi r11,r11,1 10961945bc45SNicholas Piggin sth r11,PACA_IN_MCE(r13) 10971945bc45SNicholas Piggin 109810d91611SNicholas Piggin mtlr r4 109910d91611SNicholas Piggin rlwinm r10,r3,47-31,30,31 110010d91611SNicholas Piggin cmpwi cr1,r10,2 110110d91611SNicholas Piggin bltlr cr1 /* no state loss, return to idle caller */ 110210d91611SNicholas Piggin b idle_return_gpr_loss 11031945bc45SNicholas Piggin#endif 1104afcf0095SNicholas Piggin /* 1105afcf0095SNicholas Piggin * Handle machine check early in real mode. We come here with 1106afcf0095SNicholas Piggin * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 1107afcf0095SNicholas Piggin */ 1108afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_handle_early) 1109afcf0095SNicholas Piggin std r0,GPR0(r1) /* Save r0 */ 1110afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_3(0x200) 1111afcf0095SNicholas Piggin bl save_nvgprs 1112afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1113afcf0095SNicholas Piggin bl machine_check_early 1114afcf0095SNicholas Piggin std r3,RESULT(r1) /* Save result */ 1115afcf0095SNicholas Piggin ld r12,_MSR(r1) 1116db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1117db7d31acSMahesh Salgaonkar b 4f 1118db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 11191945bc45SNicholas Piggin 1120afcf0095SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 1121afcf0095SNicholas Piggin /* 1122afcf0095SNicholas Piggin * Check if thread was in power saving mode. We come here when any 1123afcf0095SNicholas Piggin * of the following is true: 1124afcf0095SNicholas Piggin * a. thread wasn't in power saving mode 1125afcf0095SNicholas Piggin * b. thread was in power saving mode with no state loss, 1126afcf0095SNicholas Piggin * supervisor state loss or hypervisor state loss. 1127afcf0095SNicholas Piggin * 1128afcf0095SNicholas Piggin * Go back to nap/sleep/winkle mode again if (b) is true. 1129afcf0095SNicholas Piggin */ 11301945bc45SNicholas PigginBEGIN_FTR_SECTION 11311945bc45SNicholas Piggin rlwinm. r11,r12,47-31,30,31 11326102c005SNicholas Piggin bne machine_check_idle_common 11331945bc45SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 1134afcf0095SNicholas Piggin#endif 11351945bc45SNicholas Piggin 1136afcf0095SNicholas Piggin /* 1137afcf0095SNicholas Piggin * Check if we are coming from hypervisor userspace. If yes then we 1138afcf0095SNicholas Piggin * continue in host kernel in V mode to deliver the MC event. 1139afcf0095SNicholas Piggin */ 1140afcf0095SNicholas Piggin rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 1141afcf0095SNicholas Piggin beq 5f 1142db7d31acSMahesh Salgaonkar4: andi. r11,r12,MSR_PR /* See if coming from user. */ 1143afcf0095SNicholas Piggin bne 9f /* continue in V mode if we are. */ 1144afcf0095SNicholas Piggin 1145afcf0095SNicholas Piggin5: 1146afcf0095SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1147db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1148afcf0095SNicholas Piggin /* 1149afcf0095SNicholas Piggin * We are coming from kernel context. Check if we are coming from 1150afcf0095SNicholas Piggin * guest. if yes, then we can continue. We will fall through 1151afcf0095SNicholas Piggin * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 1152afcf0095SNicholas Piggin */ 1153afcf0095SNicholas Piggin lbz r11,HSTATE_IN_GUEST(r13) 1154afcf0095SNicholas Piggin cmpwi r11,0 /* Check if coming from guest */ 1155afcf0095SNicholas Piggin bne 9f /* continue if we are. */ 1156db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1157afcf0095SNicholas Piggin#endif 1158afcf0095SNicholas Piggin /* 1159afcf0095SNicholas Piggin * At this point we are not sure about what context we come from. 1160afcf0095SNicholas Piggin * Queue up the MCE event and return from the interrupt. 1161afcf0095SNicholas Piggin * But before that, check if this is an un-recoverable exception. 1162afcf0095SNicholas Piggin * If yes, then stay on emergency stack and panic. 1163afcf0095SNicholas Piggin */ 1164afcf0095SNicholas Piggin andi. r11,r12,MSR_RI 1165afcf0095SNicholas Piggin bne 2f 1166afcf0095SNicholas Piggin1: mfspr r11,SPRN_SRR0 1167afcf0095SNicholas Piggin LOAD_HANDLER(r10,unrecover_mce) 1168afcf0095SNicholas Piggin mtspr SPRN_SRR0,r10 1169afcf0095SNicholas Piggin ld r10,PACAKMSR(r13) 1170afcf0095SNicholas Piggin /* 1171afcf0095SNicholas Piggin * We are going down. But there are chances that we might get hit by 1172afcf0095SNicholas Piggin * another MCE during panic path and we may run into unstable state 1173afcf0095SNicholas Piggin * with no way out. Hence, turn ME bit off while going down, so that 1174afcf0095SNicholas Piggin * when another MCE is hit during panic path, system will checkstop 1175afcf0095SNicholas Piggin * and hypervisor will get restarted cleanly by SP. 1176afcf0095SNicholas Piggin */ 1177afcf0095SNicholas Piggin li r3,MSR_ME 1178afcf0095SNicholas Piggin andc r10,r10,r3 /* Turn off MSR_ME */ 1179afcf0095SNicholas Piggin mtspr SPRN_SRR1,r10 1180222f20f1SNicholas Piggin RFI_TO_KERNEL 1181afcf0095SNicholas Piggin b . 1182afcf0095SNicholas Piggin2: 1183afcf0095SNicholas Piggin /* 1184afcf0095SNicholas Piggin * Check if we have successfully handled/recovered from error, if not 1185afcf0095SNicholas Piggin * then stay on emergency stack and panic. 1186afcf0095SNicholas Piggin */ 1187afcf0095SNicholas Piggin ld r3,RESULT(r1) /* Load result */ 1188afcf0095SNicholas Piggin cmpdi r3,0 /* see if we handled MCE successfully */ 1189afcf0095SNicholas Piggin 1190afcf0095SNicholas Piggin beq 1b /* if !handled then panic */ 1191db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1192afcf0095SNicholas Piggin /* 1193afcf0095SNicholas Piggin * Return from MC interrupt. 1194afcf0095SNicholas Piggin * Queue up the MCE event so that we can log it later, while 1195afcf0095SNicholas Piggin * returning from kernel or opal call. 1196afcf0095SNicholas Piggin */ 1197afcf0095SNicholas Piggin bl machine_check_queue_event 1198afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 1199222f20f1SNicholas Piggin RFI_TO_USER_OR_KERNEL 1200db7d31acSMahesh SalgaonkarFTR_SECTION_ELSE 1201db7d31acSMahesh Salgaonkar /* 1202db7d31acSMahesh Salgaonkar * pSeries: Return from MC interrupt. Before that stay on emergency 1203db7d31acSMahesh Salgaonkar * stack and call machine_check_exception to log the MCE event. 1204db7d31acSMahesh Salgaonkar */ 1205db7d31acSMahesh Salgaonkar LOAD_HANDLER(r10,mce_return) 1206db7d31acSMahesh Salgaonkar mtspr SPRN_SRR0,r10 1207db7d31acSMahesh Salgaonkar ld r10,PACAKMSR(r13) 1208db7d31acSMahesh Salgaonkar mtspr SPRN_SRR1,r10 1209db7d31acSMahesh Salgaonkar RFI_TO_KERNEL 1210db7d31acSMahesh Salgaonkar b . 1211db7d31acSMahesh SalgaonkarALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 1212afcf0095SNicholas Piggin9: 1213afcf0095SNicholas Piggin /* Deliver the machine check to host kernel in V mode. */ 1214afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 12155dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXMC 1216db7d31acSMahesh Salgaonkar b machine_check_pSeries_0 1217afcf0095SNicholas Piggin 1218afcf0095SNicholas PigginEXC_COMMON_BEGIN(unrecover_mce) 1219afcf0095SNicholas Piggin /* Invoke machine_check_exception to print MCE event and panic. */ 1220afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1221afcf0095SNicholas Piggin bl machine_check_exception 1222afcf0095SNicholas Piggin /* 1223afcf0095SNicholas Piggin * We will not reach here. Even if we did, there is no way out. Call 1224afcf0095SNicholas Piggin * unrecoverable_exception and die. 1225afcf0095SNicholas Piggin */ 1226afcf0095SNicholas Piggin1: addi r3,r1,STACK_FRAME_OVERHEAD 1227afcf0095SNicholas Piggin bl unrecoverable_exception 1228afcf0095SNicholas Piggin b 1b 1229afcf0095SNicholas Piggin 1230a43c1590SMahesh SalgaonkarEXC_COMMON_BEGIN(mce_return) 1231a43c1590SMahesh Salgaonkar /* Invoke machine_check_exception to print MCE event and return. */ 1232a43c1590SMahesh Salgaonkar addi r3,r1,STACK_FRAME_OVERHEAD 1233a43c1590SMahesh Salgaonkar bl machine_check_exception 1234db7d31acSMahesh Salgaonkar MACHINE_CHECK_HANDLER_WINDUP 1235a43c1590SMahesh Salgaonkar RFI_TO_KERNEL 1236a43c1590SMahesh Salgaonkar b . 12370ebc4cdaSBenjamin Herrenschmidt 1238e779fc93SNicholas PigginEXC_REAL_BEGIN(data_access, 0x300, 0x80) 12395dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1240e779fc93SNicholas Piggin b tramp_real_data_access 1241e779fc93SNicholas PigginEXC_REAL_END(data_access, 0x300, 0x80) 1242e779fc93SNicholas Piggin 1243e779fc93SNicholas PigginTRAMP_REAL_BEGIN(tramp_real_data_access) 12445312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 1, 1, 0 12452d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1 1246e779fc93SNicholas Piggin 1247e779fc93SNicholas PigginEXC_VIRT_BEGIN(data_access, 0x4300, 0x80) 12485dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 12495312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 1, 1, 0 12502d046308SNicholas PigginEXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD 1251e779fc93SNicholas PigginEXC_VIRT_END(data_access, 0x4300, 0x80) 1252e779fc93SNicholas Piggin 125380795e6cSNicholas PigginTRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 125480795e6cSNicholas Piggin 125580795e6cSNicholas PigginEXC_COMMON_BEGIN(data_access_common) 125680795e6cSNicholas Piggin /* 125780795e6cSNicholas Piggin * Here r13 points to the paca, r9 contains the saved CR, 125880795e6cSNicholas Piggin * SRR0 and SRR1 are saved in r11 and r12, 125980795e6cSNicholas Piggin * r9 - r13 are saved in paca->exgen. 126038555434SNicholas Piggin * EX_DAR and EX_DSISR have saved DAR/DSISR 126180795e6cSNicholas Piggin */ 1262d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x300) 126380795e6cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 126480795e6cSNicholas Piggin ld r12,_MSR(r1) 126580795e6cSNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 126680795e6cSNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 126780795e6cSNicholas Piggin li r5,0x300 126880795e6cSNicholas Piggin std r3,_DAR(r1) 126980795e6cSNicholas Piggin std r4,_DSISR(r1) 127080795e6cSNicholas PigginBEGIN_MMU_FTR_SECTION 127180795e6cSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 127280795e6cSNicholas PigginMMU_FTR_SECTION_ELSE 127380795e6cSNicholas Piggin b handle_page_fault 127480795e6cSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 127580795e6cSNicholas Piggin 12760ebc4cdaSBenjamin Herrenschmidt 12771a6822d1SNicholas PigginEXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 12785dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXSLB 1279e779fc93SNicholas Piggin b tramp_real_data_access_slb 12801a6822d1SNicholas PigginEXC_REAL_END(data_access_slb, 0x380, 0x80) 12810ebc4cdaSBenjamin Herrenschmidt 1282e779fc93SNicholas PigginTRAMP_REAL_BEGIN(tramp_real_data_access_slb) 12835312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 1, 0, 0 12842d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1 1285e779fc93SNicholas Piggin 12861a6822d1SNicholas PigginEXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 12875dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXSLB 12885312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 1, 0, 0 12892d046308SNicholas Piggin EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD 12901a6822d1SNicholas PigginEXC_VIRT_END(data_access_slb, 0x4380, 0x80) 129148e7b769SNicholas Piggin 12922b9af6e4SNicholas PigginTRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 12932b9af6e4SNicholas Piggin 129448e7b769SNicholas PigginEXC_COMMON_BEGIN(data_access_slb_common) 1295d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXSLB, 0x380) 129648e7b769SNicholas Piggin ld r4,PACA_EXSLB+EX_DAR(r13) 129748e7b769SNicholas Piggin std r4,_DAR(r1) 129848e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 12997100e870SNicholas PigginBEGIN_MMU_FTR_SECTION 13007100e870SNicholas Piggin /* HPT case, do SLB fault */ 130148e7b769SNicholas Piggin bl do_slb_fault 130248e7b769SNicholas Piggin cmpdi r3,0 130348e7b769SNicholas Piggin bne- 1f 130448e7b769SNicholas Piggin b fast_exception_return 130548e7b769SNicholas Piggin1: /* Error case */ 13067100e870SNicholas PigginMMU_FTR_SECTION_ELSE 13077100e870SNicholas Piggin /* Radix case, access is outside page table range */ 13087100e870SNicholas Piggin li r3,-EFAULT 13097100e870SNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 131048e7b769SNicholas Piggin std r3,RESULT(r1) 131148e7b769SNicholas Piggin bl save_nvgprs 131248e7b769SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 131348e7b769SNicholas Piggin ld r4,_DAR(r1) 131448e7b769SNicholas Piggin ld r5,RESULT(r1) 131548e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 131648e7b769SNicholas Piggin bl do_bad_slb_fault 131748e7b769SNicholas Piggin b ret_from_except 131848e7b769SNicholas Piggin 13192b9af6e4SNicholas Piggin 13201a6822d1SNicholas PigginEXC_REAL(instruction_access, 0x400, 0x80) 13211a6822d1SNicholas PigginEXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) 132227ce77dfSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x400) 132327ce77dfSNicholas Piggin 132427ce77dfSNicholas PigginEXC_COMMON_BEGIN(instruction_access_common) 1325d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x400) 132627ce77dfSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 132727ce77dfSNicholas Piggin ld r12,_MSR(r1) 132827ce77dfSNicholas Piggin ld r3,_NIP(r1) 1329475b581fSMichael Ellerman andis. r4,r12,DSISR_SRR1_MATCH_64S@h 133027ce77dfSNicholas Piggin li r5,0x400 133127ce77dfSNicholas Piggin std r3,_DAR(r1) 133227ce77dfSNicholas Piggin std r4,_DSISR(r1) 133327ce77dfSNicholas PigginBEGIN_MMU_FTR_SECTION 133427ce77dfSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 133527ce77dfSNicholas PigginMMU_FTR_SECTION_ELSE 133627ce77dfSNicholas Piggin b handle_page_fault 133727ce77dfSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 133827ce77dfSNicholas Piggin 13390ebc4cdaSBenjamin Herrenschmidt 1340fc557537SNicholas Piggin__EXC_REAL(instruction_access_slb, 0x480, 0x80, PACA_EXSLB) 1341fc557537SNicholas Piggin__EXC_VIRT(instruction_access_slb, 0x4480, 0x80, 0x480, PACA_EXSLB) 13428d04631aSNicholas PigginTRAMP_KVM(PACA_EXSLB, 0x480) 13438d04631aSNicholas Piggin 134448e7b769SNicholas PigginEXC_COMMON_BEGIN(instruction_access_slb_common) 1345d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXSLB, 0x480) 134648e7b769SNicholas Piggin ld r4,_NIP(r1) 134754be0b9cSMichael Ellerman addi r3,r1,STACK_FRAME_OVERHEAD 13487100e870SNicholas PigginBEGIN_MMU_FTR_SECTION 13497100e870SNicholas Piggin /* HPT case, do SLB fault */ 135048e7b769SNicholas Piggin bl do_slb_fault 135148e7b769SNicholas Piggin cmpdi r3,0 135248e7b769SNicholas Piggin bne- 1f 135348e7b769SNicholas Piggin b fast_exception_return 135448e7b769SNicholas Piggin1: /* Error case */ 13557100e870SNicholas PigginMMU_FTR_SECTION_ELSE 13567100e870SNicholas Piggin /* Radix case, access is outside page table range */ 13577100e870SNicholas Piggin li r3,-EFAULT 13587100e870SNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 135948e7b769SNicholas Piggin std r3,RESULT(r1) 136048e7b769SNicholas Piggin bl save_nvgprs 136148e7b769SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 136248e7b769SNicholas Piggin ld r4,_NIP(r1) 136348e7b769SNicholas Piggin ld r5,RESULT(r1) 136448e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 136548e7b769SNicholas Piggin bl do_bad_slb_fault 136654be0b9cSMichael Ellerman b ret_from_except 13675e46e29eSNicholas Piggin 136848e7b769SNicholas Piggin 13691a6822d1SNicholas PigginEXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 1370fc557537SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 137180bd9177SNicholas PigginBEGIN_FTR_SECTION 13725312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED 1373fc557537SNicholas Piggin EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1 1374de56a948SPaul MackerrasFTR_SECTION_ELSE 13755312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED 1376fc557537SNicholas Piggin EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1 1377969391c5SPaul MackerrasALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 13781a6822d1SNicholas PigginEXC_REAL_END(hardware_interrupt, 0x500, 0x100) 1379a5d4f3adSBenjamin Herrenschmidt 13801a6822d1SNicholas PigginEXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 1381fc557537SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 138280bd9177SNicholas PigginBEGIN_FTR_SECTION 13835312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED 1384fc557537SNicholas Piggin EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV 1385c138e588SNicholas PigginFTR_SECTION_ELSE 13865312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED 1387fc557537SNicholas Piggin EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD 1388c138e588SNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 13891a6822d1SNicholas PigginEXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 1390c138e588SNicholas Piggin 13917ede5317SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x500) 13927ede5317SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0x500) 1393c138e588SNicholas PigginEXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 1394c138e588SNicholas Piggin 1395c138e588SNicholas Piggin 1396e779fc93SNicholas PigginEXC_REAL_BEGIN(alignment, 0x600, 0x100) 13975dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 13985312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 1, 1, 0 13992d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1 1400e779fc93SNicholas PigginEXC_REAL_END(alignment, 0x600, 0x100) 1401e779fc93SNicholas Piggin 1402e779fc93SNicholas PigginEXC_VIRT_BEGIN(alignment, 0x4600, 0x100) 14035dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 14045312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 1, 1, 0 14052d046308SNicholas Piggin EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD 1406e779fc93SNicholas PigginEXC_VIRT_END(alignment, 0x4600, 0x100) 1407e779fc93SNicholas Piggin 1408da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x600) 1409f9aa6714SNicholas PigginEXC_COMMON_BEGIN(alignment_common) 1410d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x600) 1411f9aa6714SNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 1412f9aa6714SNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 1413f9aa6714SNicholas Piggin std r3,_DAR(r1) 1414f9aa6714SNicholas Piggin std r4,_DSISR(r1) 1415f9aa6714SNicholas Piggin bl save_nvgprs 1416f9aa6714SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1417f9aa6714SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1418f9aa6714SNicholas Piggin bl alignment_exception 1419f9aa6714SNicholas Piggin b ret_from_except 1420f9aa6714SNicholas Piggin 1421b01c8b54SPaul Mackerras 14221a6822d1SNicholas PigginEXC_REAL(program_check, 0x700, 0x100) 14231a6822d1SNicholas PigginEXC_VIRT(program_check, 0x4700, 0x100, 0x700) 1424da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x700) 142511e87346SNicholas PigginEXC_COMMON_BEGIN(program_check_common) 1426265e60a1SCyril Bur /* 1427265e60a1SCyril Bur * It's possible to receive a TM Bad Thing type program check with 1428265e60a1SCyril Bur * userspace register values (in particular r1), but with SRR1 reporting 1429265e60a1SCyril Bur * that we came from the kernel. Normally that would confuse the bad 1430265e60a1SCyril Bur * stack logic, and we would report a bad kernel stack pointer. Instead 1431265e60a1SCyril Bur * we switch to the emergency stack if we're taking a TM Bad Thing from 1432265e60a1SCyril Bur * the kernel. 1433265e60a1SCyril Bur */ 1434265e60a1SCyril Bur 14350a882e28SNicholas Piggin andi. r10,r12,MSR_PR 14360a882e28SNicholas Piggin bne 2f /* If userspace, go normal path */ 14370a882e28SNicholas Piggin 14380a882e28SNicholas Piggin andis. r10,r12,(SRR1_PROGTM)@h 14390a882e28SNicholas Piggin bne 1f /* If TM, emergency */ 14400a882e28SNicholas Piggin 14410a882e28SNicholas Piggin cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */ 14420a882e28SNicholas Piggin blt 2f /* normal path if not */ 14430a882e28SNicholas Piggin 14440a882e28SNicholas Piggin /* Use the emergency stack */ 14450a882e28SNicholas Piggin1: andi. r10,r12,MSR_PR /* Set CR0 correctly for label */ 1446265e60a1SCyril Bur /* 3 in EXCEPTION_PROLOG_COMMON */ 1447265e60a1SCyril Bur mr r10,r1 /* Save r1 */ 1448265e60a1SCyril Bur ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 1449265e60a1SCyril Bur subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1450265e60a1SCyril Bur b 3f /* Jump into the macro !! */ 14510a882e28SNicholas Piggin2: 14520a882e28SNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x700) 145311e87346SNicholas Piggin bl save_nvgprs 145411e87346SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 145511e87346SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 145611e87346SNicholas Piggin bl program_check_exception 145711e87346SNicholas Piggin b ret_from_except 145811e87346SNicholas Piggin 1459a485c709SPaul Mackerras 14601a6822d1SNicholas PigginEXC_REAL(fp_unavailable, 0x800, 0x100) 14611a6822d1SNicholas PigginEXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) 1462da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x800) 1463c78d9b97SNicholas PigginEXC_COMMON_BEGIN(fp_unavailable_common) 1464d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x800) 1465c78d9b97SNicholas Piggin bne 1f /* if from user, just load it up */ 1466c78d9b97SNicholas Piggin bl save_nvgprs 1467c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1468c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1469c78d9b97SNicholas Piggin bl kernel_fp_unavailable_exception 1470*63ce271bSChristophe Leroy0: trap 1471*63ce271bSChristophe Leroy EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 1472c78d9b97SNicholas Piggin1: 1473c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1474c78d9b97SNicholas PigginBEGIN_FTR_SECTION 1475c78d9b97SNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1476c78d9b97SNicholas Piggin * transaction), go do TM stuff 1477c78d9b97SNicholas Piggin */ 1478c78d9b97SNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1479c78d9b97SNicholas Piggin bne- 2f 1480c78d9b97SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_TM) 1481c78d9b97SNicholas Piggin#endif 1482c78d9b97SNicholas Piggin bl load_up_fpu 1483c78d9b97SNicholas Piggin b fast_exception_return 1484c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1485c78d9b97SNicholas Piggin2: /* User process was in a transaction */ 1486c78d9b97SNicholas Piggin bl save_nvgprs 1487c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1488c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1489c78d9b97SNicholas Piggin bl fp_unavailable_tm 1490c78d9b97SNicholas Piggin b ret_from_except 1491c78d9b97SNicholas Piggin#endif 1492c78d9b97SNicholas Piggin 1493b01c8b54SPaul Mackerras 1494a048a07dSNicholas PigginEXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) 1495f14e953bSMadhavan SrinivasanEXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) 149639c0da57SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x900) 149739c0da57SNicholas PigginEXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 149839c0da57SNicholas Piggin 14990ebc4cdaSBenjamin Herrenschmidt 15001a6822d1SNicholas PigginEXC_REAL_HV(hdecrementer, 0x980, 0x80) 15011a6822d1SNicholas PigginEXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) 1502facc6d74SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0x980) 1503facc6d74SNicholas PigginEXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 1504facc6d74SNicholas Piggin 1505da2bc464SMichael Ellerman 1506f14e953bSMadhavan SrinivasanEXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) 1507f14e953bSMadhavan SrinivasanEXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) 1508da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xa00) 1509ca243163SNicholas Piggin#ifdef CONFIG_PPC_DOORBELL 1510ca243163SNicholas PigginEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 1511ca243163SNicholas Piggin#else 1512ca243163SNicholas PigginEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 1513ca243163SNicholas Piggin#endif 1514ca243163SNicholas Piggin 1515da2bc464SMichael Ellerman 15161a6822d1SNicholas PigginEXC_REAL(trap_0b, 0xb00, 0x100) 15171a6822d1SNicholas PigginEXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) 1518da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xb00) 1519341215dcSNicholas PigginEXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 1520341215dcSNicholas Piggin 1521acd7d8ceSNicholas Piggin/* 1522acd7d8ceSNicholas Piggin * system call / hypercall (0xc00, 0x4c00) 1523acd7d8ceSNicholas Piggin * 1524acd7d8ceSNicholas Piggin * The system call exception is invoked with "sc 0" and does not alter HV bit. 1525acd7d8ceSNicholas Piggin * There is support for kernel code to invoke system calls but there are no 1526acd7d8ceSNicholas Piggin * in-tree users. 1527acd7d8ceSNicholas Piggin * 1528acd7d8ceSNicholas Piggin * The hypercall is invoked with "sc 1" and sets HV=1. 1529acd7d8ceSNicholas Piggin * 1530acd7d8ceSNicholas Piggin * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 1531acd7d8ceSNicholas Piggin * 0x4c00 virtual mode. 1532acd7d8ceSNicholas Piggin * 1533acd7d8ceSNicholas Piggin * Call convention: 1534acd7d8ceSNicholas Piggin * 15354d2e26a3SMauro Carvalho Chehab * syscall register convention is in Documentation/powerpc/syscall64-abi.rst 1536acd7d8ceSNicholas Piggin * 1537acd7d8ceSNicholas Piggin * For hypercalls, the register convention is as follows: 1538acd7d8ceSNicholas Piggin * r0 volatile 1539acd7d8ceSNicholas Piggin * r1-2 nonvolatile 1540acd7d8ceSNicholas Piggin * r3 volatile parameter and return value for status 1541acd7d8ceSNicholas Piggin * r4-r10 volatile input and output value 1542acd7d8ceSNicholas Piggin * r11 volatile hypercall number and output value 154376fc0cfcSNicholas Piggin * r12 volatile input and output value 1544acd7d8ceSNicholas Piggin * r13-r31 nonvolatile 1545acd7d8ceSNicholas Piggin * LR nonvolatile 1546acd7d8ceSNicholas Piggin * CTR volatile 1547acd7d8ceSNicholas Piggin * XER volatile 1548acd7d8ceSNicholas Piggin * CR0-1 CR5-7 volatile 1549acd7d8ceSNicholas Piggin * CR2-4 nonvolatile 1550acd7d8ceSNicholas Piggin * Other registers nonvolatile 1551acd7d8ceSNicholas Piggin * 1552acd7d8ceSNicholas Piggin * The intersection of volatile registers that don't contain possible 155376fc0cfcSNicholas Piggin * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 155476fc0cfcSNicholas Piggin * without saving, though xer is not a good idea to use, as hardware may 155576fc0cfcSNicholas Piggin * interpret some bits so it may be costly to change them. 1556acd7d8ceSNicholas Piggin */ 15571b4d4a79SNicholas Piggin.macro SYSTEM_CALL virt 1558bc355125SPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1559bc355125SPaul Mackerras /* 1560acd7d8ceSNicholas Piggin * There is a little bit of juggling to get syscall and hcall 156176fc0cfcSNicholas Piggin * working well. Save r13 in ctr to avoid using SPRG scratch 156276fc0cfcSNicholas Piggin * register. 1563acd7d8ceSNicholas Piggin * 1564acd7d8ceSNicholas Piggin * Userspace syscalls have already saved the PPR, hcalls must save 1565acd7d8ceSNicholas Piggin * it before setting HMT_MEDIUM. 1566bc355125SPaul Mackerras */ 15671b4d4a79SNicholas Piggin mtctr r13 15681b4d4a79SNicholas Piggin GET_PACA(r13) 15691b4d4a79SNicholas Piggin std r10,PACA_EXGEN+EX_R10(r13) 15701b4d4a79SNicholas Piggin INTERRUPT_TO_KERNEL 15711b4d4a79SNicholas Piggin KVMTEST EXC_STD 0xc00 /* uses r10, branch to do_kvm_0xc00_system_call */ 15721b4d4a79SNicholas Piggin mfctr r9 1573bc355125SPaul Mackerras#else 15741b4d4a79SNicholas Piggin mr r9,r13 15751b4d4a79SNicholas Piggin GET_PACA(r13) 15761b4d4a79SNicholas Piggin INTERRUPT_TO_KERNEL 1577bc355125SPaul Mackerras#endif 1578bc355125SPaul Mackerras 1579727f1361SMichael Ellerman#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 15801b4d4a79SNicholas PigginBEGIN_FTR_SECTION 15811b4d4a79SNicholas Piggin cmpdi r0,0x1ebe 15821b4d4a79SNicholas Piggin beq- 1f 15831b4d4a79SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) 15841b4d4a79SNicholas Piggin#endif 15855c2511bfSMichael Ellerman 1586b0b2a93dSNicholas Piggin /* We reach here with PACA in r13, r13 in r9. */ 15871b4d4a79SNicholas Piggin mfspr r11,SPRN_SRR0 15881b4d4a79SNicholas Piggin mfspr r12,SPRN_SRR1 1589b0b2a93dSNicholas Piggin 1590b0b2a93dSNicholas Piggin HMT_MEDIUM 1591b0b2a93dSNicholas Piggin 1592b0b2a93dSNicholas Piggin .if ! \virt 15931b4d4a79SNicholas Piggin __LOAD_HANDLER(r10, system_call_common) 15941b4d4a79SNicholas Piggin mtspr SPRN_SRR0,r10 15951b4d4a79SNicholas Piggin ld r10,PACAKMSR(r13) 15961b4d4a79SNicholas Piggin mtspr SPRN_SRR1,r10 15971b4d4a79SNicholas Piggin RFI_TO_KERNEL 15981b4d4a79SNicholas Piggin b . /* prevent speculative execution */ 15991b4d4a79SNicholas Piggin .else 16001b4d4a79SNicholas Piggin li r10,MSR_RI 16011b4d4a79SNicholas Piggin mtmsrd r10,1 /* Set RI (EE=0) */ 1602b0b2a93dSNicholas Piggin#ifdef CONFIG_RELOCATABLE 1603b0b2a93dSNicholas Piggin __LOAD_HANDLER(r10, system_call_common) 1604b0b2a93dSNicholas Piggin mtctr r10 1605b0b2a93dSNicholas Piggin bctr 1606b0b2a93dSNicholas Piggin#else 16071b4d4a79SNicholas Piggin b system_call_common 1608d807ad37SNicholas Piggin#endif 16091b4d4a79SNicholas Piggin .endif 16101b4d4a79SNicholas Piggin 16111b4d4a79SNicholas Piggin#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 16121b4d4a79SNicholas Piggin /* Fast LE/BE switch system call */ 16131b4d4a79SNicholas Piggin1: mfspr r12,SPRN_SRR1 16141b4d4a79SNicholas Piggin xori r12,r12,MSR_LE 16151b4d4a79SNicholas Piggin mtspr SPRN_SRR1,r12 16161b4d4a79SNicholas Piggin mr r13,r9 16171b4d4a79SNicholas Piggin RFI_TO_USER /* return to userspace */ 16181b4d4a79SNicholas Piggin b . /* prevent speculative execution */ 16191b4d4a79SNicholas Piggin#endif 16201b4d4a79SNicholas Piggin.endm 1621d807ad37SNicholas Piggin 16221a6822d1SNicholas PigginEXC_REAL_BEGIN(system_call, 0xc00, 0x100) 16231b4d4a79SNicholas Piggin SYSTEM_CALL 0 16241a6822d1SNicholas PigginEXC_REAL_END(system_call, 0xc00, 0x100) 1625b01c8b54SPaul Mackerras 16261a6822d1SNicholas PigginEXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 16271b4d4a79SNicholas Piggin SYSTEM_CALL 1 16281a6822d1SNicholas PigginEXC_VIRT_END(system_call, 0x4c00, 0x100) 1629d807ad37SNicholas Piggin 1630acd7d8ceSNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1631acd7d8ceSNicholas Piggin /* 1632acd7d8ceSNicholas Piggin * This is a hcall, so register convention is as above, with these 1633acd7d8ceSNicholas Piggin * differences: 1634acd7d8ceSNicholas Piggin * r13 = PACA 163576fc0cfcSNicholas Piggin * ctr = orig r13 163676fc0cfcSNicholas Piggin * orig r10 saved in PACA 1637acd7d8ceSNicholas Piggin */ 1638acd7d8ceSNicholas PigginTRAMP_KVM_BEGIN(do_kvm_0xc00) 1639acd7d8ceSNicholas Piggin /* 1640acd7d8ceSNicholas Piggin * Save the PPR (on systems that support it) before changing to 1641acd7d8ceSNicholas Piggin * HMT_MEDIUM. That allows the KVM code to save that value into the 1642acd7d8ceSNicholas Piggin * guest state (it is the guest's PPR value). 1643acd7d8ceSNicholas Piggin */ 164476fc0cfcSNicholas Piggin OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) 1645acd7d8ceSNicholas Piggin HMT_MEDIUM 164676fc0cfcSNicholas Piggin OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) 1647acd7d8ceSNicholas Piggin mfctr r10 164876fc0cfcSNicholas Piggin SET_SCRATCH0(r10) 1649acd7d8ceSNicholas Piggin std r9,PACA_EXGEN+EX_R9(r13) 1650acd7d8ceSNicholas Piggin mfcr r9 165117bdc064SNicholas Piggin KVM_HANDLER PACA_EXGEN, EXC_STD, 0xc00, 0 1652acd7d8ceSNicholas Piggin#endif 1653da2bc464SMichael Ellerman 1654d807ad37SNicholas Piggin 16551a6822d1SNicholas PigginEXC_REAL(single_step, 0xd00, 0x100) 16561a6822d1SNicholas PigginEXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) 1657da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xd00) 1658bc6675c6SNicholas PigginEXC_COMMON(single_step_common, 0xd00, single_step_exception) 1659da2bc464SMichael Ellerman 16601a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) 1661da0e7e62SMichael EllermanEXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) 1662f5c32c1dSNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 1663f5c32c1dSNicholas PigginEXC_COMMON_BEGIN(h_data_storage_common) 1664f5c32c1dSNicholas Piggin mfspr r10,SPRN_HDAR 1665f5c32c1dSNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 1666f5c32c1dSNicholas Piggin mfspr r10,SPRN_HDSISR 1667f5c32c1dSNicholas Piggin stw r10,PACA_EXGEN+EX_DSISR(r13) 1668d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xe00) 1669f5c32c1dSNicholas Piggin bl save_nvgprs 1670f5c32c1dSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1671f5c32c1dSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1672d7b45615SSuraj Jitindar SinghBEGIN_MMU_FTR_SECTION 1673d7b45615SSuraj Jitindar Singh ld r4,PACA_EXGEN+EX_DAR(r13) 1674d7b45615SSuraj Jitindar Singh lwz r5,PACA_EXGEN+EX_DSISR(r13) 1675d7b45615SSuraj Jitindar Singh std r4,_DAR(r1) 1676d7b45615SSuraj Jitindar Singh std r5,_DSISR(r1) 1677d7b45615SSuraj Jitindar Singh li r5,SIGSEGV 1678d7b45615SSuraj Jitindar Singh bl bad_page_fault 1679d7b45615SSuraj Jitindar SinghMMU_FTR_SECTION_ELSE 1680f5c32c1dSNicholas Piggin bl unknown_exception 1681d7b45615SSuraj Jitindar SinghALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) 1682f5c32c1dSNicholas Piggin b ret_from_except 1683f5c32c1dSNicholas Piggin 16841707dd16SPaul Mackerras 16851a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) 1686da0e7e62SMichael EllermanEXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) 168782517cabSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe20) 168882517cabSNicholas PigginEXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 168982517cabSNicholas Piggin 16901707dd16SPaul Mackerras 16911a6822d1SNicholas PigginEXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) 16921a6822d1SNicholas PigginEXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) 1693031b4026SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe40) 1694031b4026SNicholas PigginEXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 1695031b4026SNicholas Piggin 16961707dd16SPaul Mackerras 1697e0319829SNicholas Piggin/* 1698e0319829SNicholas Piggin * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 1699e0319829SNicholas Piggin * first, and then eventaully from there to the trampoline to get into virtual 1700e0319829SNicholas Piggin * mode. 1701e0319829SNicholas Piggin */ 1702f34c9675SNicholas PigginEXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20) 1703f34c9675SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1704f34c9675SNicholas Piggin b hmi_exception_early 1705f34c9675SNicholas PigginEXC_REAL_END(hmi_exception, 0xe60, 0x20) 17061a6822d1SNicholas PigginEXC_VIRT_NONE(0x4e60, 0x20) 170762f9b03bSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe60) 170862f9b03bSNicholas PigginTRAMP_REAL_BEGIN(hmi_exception_early) 17095312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0, 0, 0 1710293c2e27SNicholas Piggin mfctr r10 /* save ctr, even for !RELOCATABLE */ 1711293c2e27SNicholas Piggin BRANCH_TO_C000(r11, hmi_exception_early_common) 1712293c2e27SNicholas Piggin 1713293c2e27SNicholas PigginEXC_COMMON_BEGIN(hmi_exception_early_common) 1714293c2e27SNicholas Piggin mtctr r10 /* Restore ctr */ 1715293c2e27SNicholas Piggin mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 1716293c2e27SNicholas Piggin mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ 171762f9b03bSNicholas Piggin mr r10,r1 /* Save r1 */ 1718a4087a4dSNicholas Piggin ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 171962f9b03bSNicholas Piggin subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1720a4087a4dSNicholas Piggin EXCEPTION_PROLOG_COMMON_1() 1721890274c2SMichael Ellerman /* We don't touch AMR here, we never go to virtual mode */ 172262f9b03bSNicholas Piggin EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 172362f9b03bSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(0xe60) 172462f9b03bSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1725293c2e27SNicholas Piggin bl hmi_exception_realmode 17265080332cSMichael Neuling cmpdi cr0,r3,0 172767d4160aSNicholas Piggin bne 1f 17285080332cSMichael Neuling 1729391e941bSNicholas Piggin EXCEPTION_RESTORE_REGS EXC_HV 1730222f20f1SNicholas Piggin HRFI_TO_USER_OR_KERNEL 17315080332cSMichael Neuling 173267d4160aSNicholas Piggin1: 173362f9b03bSNicholas Piggin /* 173462f9b03bSNicholas Piggin * Go to virtual mode and pull the HMI event information from 173562f9b03bSNicholas Piggin * firmware. 173662f9b03bSNicholas Piggin */ 1737391e941bSNicholas Piggin EXCEPTION_RESTORE_REGS EXC_HV 17385dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1739293c2e27SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0, 0, IRQS_DISABLED 1740293c2e27SNicholas Piggin EXCEPTION_PROLOG_2_REAL hmi_exception_common, EXC_HV, 1 174162f9b03bSNicholas Piggin 17425080332cSMichael NeulingEXC_COMMON_BEGIN(hmi_exception_common) 174347169fbaSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xe60) 174447169fbaSNicholas Piggin FINISH_NAP 174547169fbaSNicholas Piggin bl save_nvgprs 174647169fbaSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 174747169fbaSNicholas Piggin RUNLATCH_ON 1748c06075f3SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1749c06075f3SNicholas Piggin bl handle_hmi_exception 1750c06075f3SNicholas Piggin b ret_from_except 17511707dd16SPaul Mackerras 1752f14e953bSMadhavan SrinivasanEXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) 1753f14e953bSMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) 17549bcb81bfSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe80) 17559bcb81bfSNicholas Piggin#ifdef CONFIG_PPC_DOORBELL 17569bcb81bfSNicholas PigginEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 17579bcb81bfSNicholas Piggin#else 17589bcb81bfSNicholas PigginEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 17599bcb81bfSNicholas Piggin#endif 17609bcb81bfSNicholas Piggin 17610ebc4cdaSBenjamin Herrenschmidt 1762f14e953bSMadhavan SrinivasanEXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) 1763f14e953bSMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) 176474408776SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xea0) 176574408776SNicholas PigginEXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 176674408776SNicholas Piggin 17679baaef0aSBenjamin Herrenschmidt 17681a6822d1SNicholas PigginEXC_REAL_NONE(0xec0, 0x20) 17691a6822d1SNicholas PigginEXC_VIRT_NONE(0x4ec0, 0x20) 17701a6822d1SNicholas PigginEXC_REAL_NONE(0xee0, 0x20) 17711a6822d1SNicholas PigginEXC_VIRT_NONE(0x4ee0, 0x20) 1772bda7fea2SNicholas Piggin 17730ebc4cdaSBenjamin Herrenschmidt 1774f442d004SMadhavan SrinivasanEXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) 1775f442d004SMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) 1776b1c7f150SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf00) 1777b1c7f150SNicholas PigginEXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1778b1c7f150SNicholas Piggin 17790ebc4cdaSBenjamin Herrenschmidt 17801a6822d1SNicholas PigginEXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) 17811a6822d1SNicholas PigginEXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) 1782d1a0ca9cSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf20) 1783d1a0ca9cSNicholas PigginEXC_COMMON_BEGIN(altivec_unavailable_common) 1784d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xf20) 1785d1a0ca9cSNicholas Piggin#ifdef CONFIG_ALTIVEC 1786d1a0ca9cSNicholas PigginBEGIN_FTR_SECTION 1787d1a0ca9cSNicholas Piggin beq 1f 1788d1a0ca9cSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1789d1a0ca9cSNicholas Piggin BEGIN_FTR_SECTION_NESTED(69) 1790d1a0ca9cSNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1791d1a0ca9cSNicholas Piggin * transaction), go do TM stuff 1792d1a0ca9cSNicholas Piggin */ 1793d1a0ca9cSNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1794d1a0ca9cSNicholas Piggin bne- 2f 1795d1a0ca9cSNicholas Piggin END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1796d1a0ca9cSNicholas Piggin#endif 1797d1a0ca9cSNicholas Piggin bl load_up_altivec 1798d1a0ca9cSNicholas Piggin b fast_exception_return 1799d1a0ca9cSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1800d1a0ca9cSNicholas Piggin2: /* User process was in a transaction */ 1801d1a0ca9cSNicholas Piggin bl save_nvgprs 1802d1a0ca9cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1803d1a0ca9cSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1804d1a0ca9cSNicholas Piggin bl altivec_unavailable_tm 1805d1a0ca9cSNicholas Piggin b ret_from_except 1806d1a0ca9cSNicholas Piggin#endif 1807d1a0ca9cSNicholas Piggin1: 1808d1a0ca9cSNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1809d1a0ca9cSNicholas Piggin#endif 1810d1a0ca9cSNicholas Piggin bl save_nvgprs 1811d1a0ca9cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1812d1a0ca9cSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1813d1a0ca9cSNicholas Piggin bl altivec_unavailable_exception 1814d1a0ca9cSNicholas Piggin b ret_from_except 1815d1a0ca9cSNicholas Piggin 18160ebc4cdaSBenjamin Herrenschmidt 18171a6822d1SNicholas PigginEXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) 18181a6822d1SNicholas PigginEXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) 1819792cbdddSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf40) 1820792cbdddSNicholas PigginEXC_COMMON_BEGIN(vsx_unavailable_common) 1821d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xf40) 1822792cbdddSNicholas Piggin#ifdef CONFIG_VSX 1823792cbdddSNicholas PigginBEGIN_FTR_SECTION 1824792cbdddSNicholas Piggin beq 1f 1825792cbdddSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1826792cbdddSNicholas Piggin BEGIN_FTR_SECTION_NESTED(69) 1827792cbdddSNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1828792cbdddSNicholas Piggin * transaction), go do TM stuff 1829792cbdddSNicholas Piggin */ 1830792cbdddSNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1831792cbdddSNicholas Piggin bne- 2f 1832792cbdddSNicholas Piggin END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1833792cbdddSNicholas Piggin#endif 1834792cbdddSNicholas Piggin b load_up_vsx 1835792cbdddSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1836792cbdddSNicholas Piggin2: /* User process was in a transaction */ 1837792cbdddSNicholas Piggin bl save_nvgprs 1838792cbdddSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1839792cbdddSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1840792cbdddSNicholas Piggin bl vsx_unavailable_tm 1841792cbdddSNicholas Piggin b ret_from_except 1842792cbdddSNicholas Piggin#endif 1843792cbdddSNicholas Piggin1: 1844792cbdddSNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 1845792cbdddSNicholas Piggin#endif 1846792cbdddSNicholas Piggin bl save_nvgprs 1847792cbdddSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1848792cbdddSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1849792cbdddSNicholas Piggin bl vsx_unavailable_exception 1850792cbdddSNicholas Piggin b ret_from_except 1851792cbdddSNicholas Piggin 1852d0c0c9a1SMichael Neuling 18531a6822d1SNicholas PigginEXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) 18541a6822d1SNicholas PigginEXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) 18551134713cSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf60) 18561134713cSNicholas PigginEXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 18571134713cSNicholas Piggin 1858da2bc464SMichael Ellerman 18591a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) 18601a6822d1SNicholas PigginEXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) 186114b0072cSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xf80) 186214b0072cSNicholas PigginEXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 186314b0072cSNicholas Piggin 1864da2bc464SMichael Ellerman 18651a6822d1SNicholas PigginEXC_REAL_NONE(0xfa0, 0x20) 18661a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fa0, 0x20) 18671a6822d1SNicholas PigginEXC_REAL_NONE(0xfc0, 0x20) 18681a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fc0, 0x20) 18691a6822d1SNicholas PigginEXC_REAL_NONE(0xfe0, 0x20) 18701a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fe0, 0x20) 18711a6822d1SNicholas Piggin 18721a6822d1SNicholas PigginEXC_REAL_NONE(0x1000, 0x100) 18731a6822d1SNicholas PigginEXC_VIRT_NONE(0x5000, 0x100) 18741a6822d1SNicholas PigginEXC_REAL_NONE(0x1100, 0x100) 18751a6822d1SNicholas PigginEXC_VIRT_NONE(0x5100, 0x100) 1876da2bc464SMichael Ellerman 18770ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 18781a6822d1SNicholas PigginEXC_REAL_HV(cbe_system_error, 0x1200, 0x100) 18791a6822d1SNicholas PigginEXC_VIRT_NONE(0x5200, 0x100) 1880da2bc464SMichael EllermanTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1881ff1b3206SNicholas PigginEXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1882da2bc464SMichael Ellerman#else /* CONFIG_CBE_RAS */ 18831a6822d1SNicholas PigginEXC_REAL_NONE(0x1200, 0x100) 18841a6822d1SNicholas PigginEXC_VIRT_NONE(0x5200, 0x100) 1885da2bc464SMichael Ellerman#endif 1886da2bc464SMichael Ellerman 1887ff1b3206SNicholas Piggin 18881a6822d1SNicholas PigginEXC_REAL(instruction_breakpoint, 0x1300, 0x100) 18891a6822d1SNicholas PigginEXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) 1890da2bc464SMichael EllermanTRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 18914e96dbbfSNicholas PigginEXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 18924e96dbbfSNicholas Piggin 18931a6822d1SNicholas PigginEXC_REAL_NONE(0x1400, 0x100) 18941a6822d1SNicholas PigginEXC_VIRT_NONE(0x5400, 0x100) 1895da2bc464SMichael Ellerman 18961a6822d1SNicholas PigginEXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) 18975dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 18985312c494SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0, 0, 0 1899b92a66a6SMichael Neuling 1900b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 1901b92a66a6SMichael Neuling mfspr r10,SPRN_HSRR1 1902b92a66a6SMichael Neuling andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1903b92a66a6SMichael Neuling bne+ denorm_assist 1904b92a66a6SMichael Neuling#endif 1905b92a66a6SMichael Neuling 1906a7c1ca19SNicholas Piggin KVMTEST EXC_HV 0x1500 19072d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1 19081a6822d1SNicholas PigginEXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) 1909da2bc464SMichael Ellerman 1910d7e89849SNicholas Piggin#ifdef CONFIG_PPC_DENORMALISATION 19111a6822d1SNicholas PigginEXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 1912d7e89849SNicholas Piggin b exc_real_0x1500_denorm_exception_hv 19131a6822d1SNicholas PigginEXC_VIRT_END(denorm_exception, 0x5500, 0x100) 1914d7e89849SNicholas Piggin#else 19151a6822d1SNicholas PigginEXC_VIRT_NONE(0x5500, 0x100) 1916d7e89849SNicholas Piggin#endif 1917d7e89849SNicholas Piggin 19184bb3c7a0SPaul MackerrasTRAMP_KVM_HV(PACA_EXGEN, 0x1500) 1919b92a66a6SMichael Neuling 1920b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 1921da2bc464SMichael EllermanTRAMP_REAL_BEGIN(denorm_assist) 1922b92a66a6SMichael NeulingBEGIN_FTR_SECTION 1923b92a66a6SMichael Neuling/* 1924b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 1925b92a66a6SMichael Neuling * For POWER6 do that here for all FP regs. 1926b92a66a6SMichael Neuling */ 1927b92a66a6SMichael Neuling mfmsr r10 1928b92a66a6SMichael Neuling ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 1929b92a66a6SMichael Neuling xori r10,r10,(MSR_FE0|MSR_FE1) 1930b92a66a6SMichael Neuling mtmsrd r10 1931b92a66a6SMichael Neuling sync 1932d7c67fb1SMichael Neuling 1933f3c8b6c6SNicholas Piggin .Lreg=0 1934f3c8b6c6SNicholas Piggin .rept 32 1935f3c8b6c6SNicholas Piggin fmr .Lreg,.Lreg 1936f3c8b6c6SNicholas Piggin .Lreg=.Lreg+1 1937f3c8b6c6SNicholas Piggin .endr 1938d7c67fb1SMichael Neuling 1939b92a66a6SMichael NeulingFTR_SECTION_ELSE 1940b92a66a6SMichael Neuling/* 1941b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 1942b92a66a6SMichael Neuling * For POWER7 do that here for the first 32 VSX registers only. 1943b92a66a6SMichael Neuling */ 1944b92a66a6SMichael Neuling mfmsr r10 1945b92a66a6SMichael Neuling oris r10,r10,MSR_VSX@h 1946b92a66a6SMichael Neuling mtmsrd r10 1947b92a66a6SMichael Neuling sync 1948d7c67fb1SMichael Neuling 1949f3c8b6c6SNicholas Piggin .Lreg=0 1950f3c8b6c6SNicholas Piggin .rept 32 1951f3c8b6c6SNicholas Piggin XVCPSGNDP(.Lreg,.Lreg,.Lreg) 1952f3c8b6c6SNicholas Piggin .Lreg=.Lreg+1 1953f3c8b6c6SNicholas Piggin .endr 1954d7c67fb1SMichael Neuling 1955b92a66a6SMichael NeulingALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 1956fb0fce3eSMichael Neuling 1957fb0fce3eSMichael NeulingBEGIN_FTR_SECTION 1958fb0fce3eSMichael Neuling b denorm_done 1959fb0fce3eSMichael NeulingEND_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 1960fb0fce3eSMichael Neuling/* 1961fb0fce3eSMichael Neuling * To denormalise we need to move a copy of the register to itself. 1962fb0fce3eSMichael Neuling * For POWER8 we need to do that for all 64 VSX registers 1963fb0fce3eSMichael Neuling */ 1964f3c8b6c6SNicholas Piggin .Lreg=32 1965f3c8b6c6SNicholas Piggin .rept 32 1966f3c8b6c6SNicholas Piggin XVCPSGNDP(.Lreg,.Lreg,.Lreg) 1967f3c8b6c6SNicholas Piggin .Lreg=.Lreg+1 1968f3c8b6c6SNicholas Piggin .endr 1969f3c8b6c6SNicholas Piggin 1970fb0fce3eSMichael Neulingdenorm_done: 1971f14040bcSMichael Neuling mfspr r11,SPRN_HSRR0 1972f14040bcSMichael Neuling subi r11,r11,4 1973b92a66a6SMichael Neuling mtspr SPRN_HSRR0,r11 1974b92a66a6SMichael Neuling mtcrf 0x80,r9 1975b92a66a6SMichael Neuling ld r9,PACA_EXGEN+EX_R9(r13) 197644e9309fSHaren Myneni RESTORE_PPR_PACA(PACA_EXGEN, r10) 1977630573c1SPaul MackerrasBEGIN_FTR_SECTION 1978630573c1SPaul Mackerras ld r10,PACA_EXGEN+EX_CFAR(r13) 1979630573c1SPaul Mackerras mtspr SPRN_CFAR,r10 1980630573c1SPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1981b92a66a6SMichael Neuling ld r10,PACA_EXGEN+EX_R10(r13) 1982b92a66a6SMichael Neuling ld r11,PACA_EXGEN+EX_R11(r13) 1983b92a66a6SMichael Neuling ld r12,PACA_EXGEN+EX_R12(r13) 1984b92a66a6SMichael Neuling ld r13,PACA_EXGEN+EX_R13(r13) 1985222f20f1SNicholas Piggin HRFI_TO_UNKNOWN 1986b92a66a6SMichael Neuling b . 1987b92a66a6SMichael Neuling#endif 1988b92a66a6SMichael Neuling 1989872e2ae4SBenjamin HerrenschmidtEXC_COMMON(denorm_common, 0x1500, unknown_exception) 1990d7e89849SNicholas Piggin 1991d7e89849SNicholas Piggin 1992d7e89849SNicholas Piggin#ifdef CONFIG_CBE_RAS 19931a6822d1SNicholas PigginEXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) 19941a6822d1SNicholas PigginEXC_VIRT_NONE(0x5600, 0x100) 1995d7e89849SNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 199669a79344SNicholas PigginEXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 1997d7e89849SNicholas Piggin#else /* CONFIG_CBE_RAS */ 19981a6822d1SNicholas PigginEXC_REAL_NONE(0x1600, 0x100) 19991a6822d1SNicholas PigginEXC_VIRT_NONE(0x5600, 0x100) 2000d7e89849SNicholas Piggin#endif 2001d7e89849SNicholas Piggin 200269a79344SNicholas Piggin 20031a6822d1SNicholas PigginEXC_REAL(altivec_assist, 0x1700, 0x100) 20041a6822d1SNicholas PigginEXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) 2005d7e89849SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x1700) 2006b51c079eSNicholas Piggin#ifdef CONFIG_ALTIVEC 2007b51c079eSNicholas PigginEXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 2008b51c079eSNicholas Piggin#else 2009b51c079eSNicholas PigginEXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 2010b51c079eSNicholas Piggin#endif 2011b51c079eSNicholas Piggin 2012d7e89849SNicholas Piggin 2013d7e89849SNicholas Piggin#ifdef CONFIG_CBE_RAS 20141a6822d1SNicholas PigginEXC_REAL_HV(cbe_thermal, 0x1800, 0x100) 20151a6822d1SNicholas PigginEXC_VIRT_NONE(0x5800, 0x100) 2016d7e89849SNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 20173965f8abSNicholas PigginEXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 2018d7e89849SNicholas Piggin#else /* CONFIG_CBE_RAS */ 20191a6822d1SNicholas PigginEXC_REAL_NONE(0x1800, 0x100) 20201a6822d1SNicholas PigginEXC_VIRT_NONE(0x5800, 0x100) 2021d7e89849SNicholas Piggin#endif 2022d7e89849SNicholas Piggin 202375eb767eSNicholas Piggin#ifdef CONFIG_PPC_WATCHDOG 20242104180aSNicholas Piggin 20252104180aSNicholas Piggin#define MASKED_DEC_HANDLER_LABEL 3f 20262104180aSNicholas Piggin 20272104180aSNicholas Piggin#define MASKED_DEC_HANDLER(_H) \ 20282104180aSNicholas Piggin3: /* soft-nmi */ \ 20292104180aSNicholas Piggin std r12,PACA_EXGEN+EX_R12(r13); \ 20302104180aSNicholas Piggin GET_SCRATCH0(r10); \ 20312104180aSNicholas Piggin std r10,PACA_EXGEN+EX_R13(r13); \ 20322d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1 20332104180aSNicholas Piggin 2034cc491f1dSNicholas Piggin/* 2035cc491f1dSNicholas Piggin * Branch to soft_nmi_interrupt using the emergency stack. The emergency 2036cc491f1dSNicholas Piggin * stack is one that is usable by maskable interrupts so long as MSR_EE 2037cc491f1dSNicholas Piggin * remains off. It is used for recovery when something has corrupted the 2038cc491f1dSNicholas Piggin * normal kernel stack, for example. The "soft NMI" must not use the process 2039cc491f1dSNicholas Piggin * stack because we want irq disabled sections to avoid touching the stack 2040cc491f1dSNicholas Piggin * at all (other than PMU interrupts), so use the emergency stack for this, 2041cc491f1dSNicholas Piggin * and run it entirely with interrupts hard disabled. 2042cc491f1dSNicholas Piggin */ 20432104180aSNicholas PigginEXC_COMMON_BEGIN(soft_nmi_common) 20442104180aSNicholas Piggin mr r10,r1 20452104180aSNicholas Piggin ld r1,PACAEMERGSP(r13) 20462104180aSNicholas Piggin subi r1,r1,INT_FRAME_SIZE 204747169fbaSNicholas Piggin EXCEPTION_COMMON_STACK(PACA_EXGEN, 0x900) 204847169fbaSNicholas Piggin bl save_nvgprs 204947169fbaSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 2050c06075f3SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 2051c06075f3SNicholas Piggin bl soft_nmi_interrupt 20522104180aSNicholas Piggin b ret_from_except 20532104180aSNicholas Piggin 205475eb767eSNicholas Piggin#else /* CONFIG_PPC_WATCHDOG */ 20552104180aSNicholas Piggin#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ 20562104180aSNicholas Piggin#define MASKED_DEC_HANDLER(_H) 205775eb767eSNicholas Piggin#endif /* CONFIG_PPC_WATCHDOG */ 2058d7e89849SNicholas Piggin 20590ebc4cdaSBenjamin Herrenschmidt/* 2060fe9e1d54SIan Munsie * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 2061fe9e1d54SIan Munsie * - If it was a decrementer interrupt, we bump the dec to max and and return. 2062fe9e1d54SIan Munsie * - If it was a doorbell we return immediately since doorbells are edge 2063fe9e1d54SIan Munsie * triggered and won't automatically refire. 20640869b6fdSMahesh Salgaonkar * - If it was a HMI we return immediately since we handled it in realmode 20650869b6fdSMahesh Salgaonkar * and it won't refire. 20666cc3f91bSNicholas Piggin * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. 2067fe9e1d54SIan Munsie * This is called with r10 containing the value to OR to the paca field. 20680ebc4cdaSBenjamin Herrenschmidt */ 20694508a74aSNicholas Piggin.macro MASKED_INTERRUPT hsrr 20704508a74aSNicholas Piggin .if \hsrr 20714508a74aSNicholas Pigginmasked_Hinterrupt: 20724508a74aSNicholas Piggin .else 20734508a74aSNicholas Pigginmasked_interrupt: 20744508a74aSNicholas Piggin .endif 20754508a74aSNicholas Piggin std r11,PACA_EXGEN+EX_R11(r13) 20764508a74aSNicholas Piggin lbz r11,PACAIRQHAPPENED(r13) 20774508a74aSNicholas Piggin or r11,r11,r10 20784508a74aSNicholas Piggin stb r11,PACAIRQHAPPENED(r13) 20794508a74aSNicholas Piggin cmpwi r10,PACA_IRQ_DEC 20804508a74aSNicholas Piggin bne 1f 20814508a74aSNicholas Piggin lis r10,0x7fff 20824508a74aSNicholas Piggin ori r10,r10,0xffff 20834508a74aSNicholas Piggin mtspr SPRN_DEC,r10 20844508a74aSNicholas Piggin b MASKED_DEC_HANDLER_LABEL 20854508a74aSNicholas Piggin1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK 20864508a74aSNicholas Piggin beq 2f 20874508a74aSNicholas Piggin .if \hsrr 20884508a74aSNicholas Piggin mfspr r10,SPRN_HSRR1 20894508a74aSNicholas Piggin xori r10,r10,MSR_EE /* clear MSR_EE */ 20904508a74aSNicholas Piggin mtspr SPRN_HSRR1,r10 20914508a74aSNicholas Piggin .else 20924508a74aSNicholas Piggin mfspr r10,SPRN_SRR1 20934508a74aSNicholas Piggin xori r10,r10,MSR_EE /* clear MSR_EE */ 20944508a74aSNicholas Piggin mtspr SPRN_SRR1,r10 20954508a74aSNicholas Piggin .endif 20964508a74aSNicholas Piggin ori r11,r11,PACA_IRQ_HARD_DIS 20974508a74aSNicholas Piggin stb r11,PACAIRQHAPPENED(r13) 20984508a74aSNicholas Piggin2: /* done */ 20994508a74aSNicholas Piggin mtcrf 0x80,r9 21004508a74aSNicholas Piggin std r1,PACAR1(r13) 21014508a74aSNicholas Piggin ld r9,PACA_EXGEN+EX_R9(r13) 21024508a74aSNicholas Piggin ld r10,PACA_EXGEN+EX_R10(r13) 21034508a74aSNicholas Piggin ld r11,PACA_EXGEN+EX_R11(r13) 21044508a74aSNicholas Piggin /* returns to kernel where r13 must be set up, so don't restore it */ 21054508a74aSNicholas Piggin .if \hsrr 21064508a74aSNicholas Piggin HRFI_TO_KERNEL 21074508a74aSNicholas Piggin .else 21084508a74aSNicholas Piggin RFI_TO_KERNEL 21094508a74aSNicholas Piggin .endif 21104508a74aSNicholas Piggin b . 21114508a74aSNicholas Piggin MASKED_DEC_HANDLER(\hsrr\()) 21124508a74aSNicholas Piggin.endm 21130ebc4cdaSBenjamin Herrenschmidt 2114a048a07dSNicholas PigginTRAMP_REAL_BEGIN(stf_barrier_fallback) 2115a048a07dSNicholas Piggin std r9,PACA_EXRFI+EX_R9(r13) 2116a048a07dSNicholas Piggin std r10,PACA_EXRFI+EX_R10(r13) 2117a048a07dSNicholas Piggin sync 2118a048a07dSNicholas Piggin ld r9,PACA_EXRFI+EX_R9(r13) 2119a048a07dSNicholas Piggin ld r10,PACA_EXRFI+EX_R10(r13) 2120a048a07dSNicholas Piggin ori 31,31,0 2121a048a07dSNicholas Piggin .rept 14 2122a048a07dSNicholas Piggin b 1f 2123a048a07dSNicholas Piggin1: 2124a048a07dSNicholas Piggin .endr 2125a048a07dSNicholas Piggin blr 2126a048a07dSNicholas Piggin 2127aa8a5e00SMichael EllermanTRAMP_REAL_BEGIN(rfi_flush_fallback) 2128aa8a5e00SMichael Ellerman SET_SCRATCH0(r13); 2129aa8a5e00SMichael Ellerman GET_PACA(r13); 213078ee9946SMichael Ellerman std r1,PACA_EXRFI+EX_R12(r13) 213178ee9946SMichael Ellerman ld r1,PACAKSAVE(r13) 2132aa8a5e00SMichael Ellerman std r9,PACA_EXRFI+EX_R9(r13) 2133aa8a5e00SMichael Ellerman std r10,PACA_EXRFI+EX_R10(r13) 2134aa8a5e00SMichael Ellerman std r11,PACA_EXRFI+EX_R11(r13) 2135aa8a5e00SMichael Ellerman mfctr r9 2136aa8a5e00SMichael Ellerman ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2137bdcb1aefSNicholas Piggin ld r11,PACA_L1D_FLUSH_SIZE(r13) 2138bdcb1aefSNicholas Piggin srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2139aa8a5e00SMichael Ellerman mtctr r11 214015a3204dSNicholas Piggin DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2141aa8a5e00SMichael Ellerman 2142aa8a5e00SMichael Ellerman /* order ld/st prior to dcbt stop all streams with flushing */ 2143aa8a5e00SMichael Ellerman sync 2144bdcb1aefSNicholas Piggin 2145bdcb1aefSNicholas Piggin /* 2146bdcb1aefSNicholas Piggin * The load adresses are at staggered offsets within cachelines, 2147bdcb1aefSNicholas Piggin * which suits some pipelines better (on others it should not 2148bdcb1aefSNicholas Piggin * hurt). 2149bdcb1aefSNicholas Piggin */ 2150bdcb1aefSNicholas Piggin1: 2151bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*0(r10) 2152bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*1(r10) 2153bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*2(r10) 2154bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*3(r10) 2155bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*4(r10) 2156bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*5(r10) 2157bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*6(r10) 2158bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*7(r10) 2159bdcb1aefSNicholas Piggin addi r10,r10,0x80*8 2160aa8a5e00SMichael Ellerman bdnz 1b 2161aa8a5e00SMichael Ellerman 2162aa8a5e00SMichael Ellerman mtctr r9 2163aa8a5e00SMichael Ellerman ld r9,PACA_EXRFI+EX_R9(r13) 2164aa8a5e00SMichael Ellerman ld r10,PACA_EXRFI+EX_R10(r13) 2165aa8a5e00SMichael Ellerman ld r11,PACA_EXRFI+EX_R11(r13) 216678ee9946SMichael Ellerman ld r1,PACA_EXRFI+EX_R12(r13) 2167aa8a5e00SMichael Ellerman GET_SCRATCH0(r13); 2168aa8a5e00SMichael Ellerman rfid 2169aa8a5e00SMichael Ellerman 2170aa8a5e00SMichael EllermanTRAMP_REAL_BEGIN(hrfi_flush_fallback) 2171aa8a5e00SMichael Ellerman SET_SCRATCH0(r13); 2172aa8a5e00SMichael Ellerman GET_PACA(r13); 217378ee9946SMichael Ellerman std r1,PACA_EXRFI+EX_R12(r13) 217478ee9946SMichael Ellerman ld r1,PACAKSAVE(r13) 2175aa8a5e00SMichael Ellerman std r9,PACA_EXRFI+EX_R9(r13) 2176aa8a5e00SMichael Ellerman std r10,PACA_EXRFI+EX_R10(r13) 2177aa8a5e00SMichael Ellerman std r11,PACA_EXRFI+EX_R11(r13) 2178aa8a5e00SMichael Ellerman mfctr r9 2179aa8a5e00SMichael Ellerman ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2180bdcb1aefSNicholas Piggin ld r11,PACA_L1D_FLUSH_SIZE(r13) 2181bdcb1aefSNicholas Piggin srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2182aa8a5e00SMichael Ellerman mtctr r11 218315a3204dSNicholas Piggin DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2184aa8a5e00SMichael Ellerman 2185aa8a5e00SMichael Ellerman /* order ld/st prior to dcbt stop all streams with flushing */ 2186aa8a5e00SMichael Ellerman sync 2187bdcb1aefSNicholas Piggin 2188bdcb1aefSNicholas Piggin /* 2189bdcb1aefSNicholas Piggin * The load adresses are at staggered offsets within cachelines, 2190bdcb1aefSNicholas Piggin * which suits some pipelines better (on others it should not 2191bdcb1aefSNicholas Piggin * hurt). 2192bdcb1aefSNicholas Piggin */ 2193bdcb1aefSNicholas Piggin1: 2194bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*0(r10) 2195bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*1(r10) 2196bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*2(r10) 2197bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*3(r10) 2198bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*4(r10) 2199bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*5(r10) 2200bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*6(r10) 2201bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*7(r10) 2202bdcb1aefSNicholas Piggin addi r10,r10,0x80*8 2203aa8a5e00SMichael Ellerman bdnz 1b 2204aa8a5e00SMichael Ellerman 2205aa8a5e00SMichael Ellerman mtctr r9 2206aa8a5e00SMichael Ellerman ld r9,PACA_EXRFI+EX_R9(r13) 2207aa8a5e00SMichael Ellerman ld r10,PACA_EXRFI+EX_R10(r13) 2208aa8a5e00SMichael Ellerman ld r11,PACA_EXRFI+EX_R11(r13) 220978ee9946SMichael Ellerman ld r1,PACA_EXRFI+EX_R12(r13) 2210aa8a5e00SMichael Ellerman GET_SCRATCH0(r13); 2211aa8a5e00SMichael Ellerman hrfid 2212aa8a5e00SMichael Ellerman 221357f26649SNicholas Piggin/* 221457f26649SNicholas Piggin * Real mode exceptions actually use this too, but alternate 221557f26649SNicholas Piggin * instruction code patches (which end up in the common .text area) 221657f26649SNicholas Piggin * cannot reach these if they are put there. 221757f26649SNicholas Piggin */ 221857f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 22194508a74aSNicholas Piggin MASKED_INTERRUPT EXC_STD 22204508a74aSNicholas Piggin MASKED_INTERRUPT EXC_HV 22217230c564SBenjamin Herrenschmidt 22224f6c11dbSPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 2223da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 22244f6c11dbSPaul Mackerras /* 22254f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 22264f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 22274f6c11dbSPaul Mackerras */ 22284f6c11dbSPaul Mackerras mfspr r13, SPRN_SRR0 22294f6c11dbSPaul Mackerras addi r13, r13, 4 22304f6c11dbSPaul Mackerras mtspr SPRN_SRR0, r13 22314f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 2232222f20f1SNicholas Piggin RFI_TO_KERNEL 22334f6c11dbSPaul Mackerras b . 22344f6c11dbSPaul Mackerras 2235da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 22364f6c11dbSPaul Mackerras /* 22374f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 22384f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 22394f6c11dbSPaul Mackerras */ 22404f6c11dbSPaul Mackerras mfspr r13, SPRN_HSRR0 22414f6c11dbSPaul Mackerras addi r13, r13, 4 22424f6c11dbSPaul Mackerras mtspr SPRN_HSRR0, r13 22434f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 2244222f20f1SNicholas Piggin HRFI_TO_KERNEL 22454f6c11dbSPaul Mackerras b . 22464f6c11dbSPaul Mackerras#endif 22474f6c11dbSPaul Mackerras 22480ebc4cdaSBenjamin Herrenschmidt/* 2249057b6d7eSHari Bathini * Ensure that any handlers that get invoked from the exception prologs 2250057b6d7eSHari Bathini * above are below the first 64KB (0x10000) of the kernel image because 2251057b6d7eSHari Bathini * the prologs assemble the addresses of these handlers using the 2252057b6d7eSHari Bathini * LOAD_HANDLER macro, which uses an ori instruction. 22530ebc4cdaSBenjamin Herrenschmidt */ 22540ebc4cdaSBenjamin Herrenschmidt 22550ebc4cdaSBenjamin Herrenschmidt/*** Common interrupt handlers ***/ 22560ebc4cdaSBenjamin Herrenschmidt 22570ebc4cdaSBenjamin Herrenschmidt 2258c1fb6816SMichael Neuling /* 2259c1fb6816SMichael Neuling * Relocation-on interrupts: A subset of the interrupts can be delivered 2260c1fb6816SMichael Neuling * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 2261c1fb6816SMichael Neuling * it. Addresses are the same as the original interrupt addresses, but 2262c1fb6816SMichael Neuling * offset by 0xc000000000004000. 2263c1fb6816SMichael Neuling * It's impossible to receive interrupts below 0x300 via this mechanism. 2264c1fb6816SMichael Neuling * KVM: None of these traps are from the guest ; anything that escalated 2265c1fb6816SMichael Neuling * to HV=1 from HV=0 is delivered via real mode handlers. 2266c1fb6816SMichael Neuling */ 2267c1fb6816SMichael Neuling 2268c1fb6816SMichael Neuling /* 2269c1fb6816SMichael Neuling * This uses the standard macro, since the original 0x300 vector 2270c1fb6816SMichael Neuling * only has extra guff for STAB-based processors -- which never 2271c1fb6816SMichael Neuling * come here. 2272c1fb6816SMichael Neuling */ 2273da2bc464SMichael Ellerman 227457f26649SNicholas PigginEXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 2275b1576fecSAnton Blanchard b __ppc64_runlatch_on 2276fe1952fcSBenjamin Herrenschmidt 227757f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 22788ed8ab40SHari Bathini /* 22798ed8ab40SHari Bathini * The __end_interrupts marker must be past the out-of-line (OOL) 22808ed8ab40SHari Bathini * handlers, so that they are copied to real address 0x100 when running 22818ed8ab40SHari Bathini * a relocatable kernel. This ensures they can be reached from the short 22828ed8ab40SHari Bathini * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 22838ed8ab40SHari Bathini * directly, without using LOAD_HANDLER(). 22848ed8ab40SHari Bathini */ 22858ed8ab40SHari Bathini .align 7 22868ed8ab40SHari Bathini .globl __end_interrupts 22878ed8ab40SHari Bathini__end_interrupts: 228857f26649SNicholas PigginDEFINE_FIXED_SYMBOL(__end_interrupts) 228961383407SBenjamin Herrenschmidt 2290087aa036SChen Gang#ifdef CONFIG_PPC_970_NAP 22917c8cb4b5SNicholas PigginEXC_COMMON_BEGIN(power4_fixup_nap) 2292087aa036SChen Gang andc r9,r9,r10 2293087aa036SChen Gang std r9,TI_LOCAL_FLAGS(r11) 2294087aa036SChen Gang ld r10,_LINK(r1) /* make idle task do the */ 2295087aa036SChen Gang std r10,_NIP(r1) /* equivalent of a blr */ 2296087aa036SChen Gang blr 2297087aa036SChen Gang#endif 2298087aa036SChen Gang 229957f26649SNicholas PigginCLOSE_FIXED_SECTION(real_vectors); 230057f26649SNicholas PigginCLOSE_FIXED_SECTION(real_trampolines); 230157f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_vectors); 230257f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_trampolines); 230357f26649SNicholas Piggin 230457f26649SNicholas PigginUSE_TEXT_SECTION() 230557f26649SNicholas Piggin 2306087aa036SChen Gang/* 23070ebc4cdaSBenjamin Herrenschmidt * Hash table stuff 23080ebc4cdaSBenjamin Herrenschmidt */ 2309f4329f2eSNicholas Piggin .balign IFETCH_ALIGN_BYTES 23106a3bab90SAnton Blancharddo_hash_page: 23114e003747SMichael Ellerman#ifdef CONFIG_PPC_BOOK3S_64 2312e6c2a479SRam Pai lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h 2313398a719dSBenjamin Herrenschmidt ori r0,r0,DSISR_BAD_FAULT_64S@l 2314398a719dSBenjamin Herrenschmidt and. r0,r4,r0 /* weird error? */ 23150ebc4cdaSBenjamin Herrenschmidt bne- handle_page_fault /* if not, try to insert a HPTE */ 2316c911d2e1SChristophe Leroy ld r11, PACA_THREAD_INFO(r13) 23179c1e1052SPaul Mackerras lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 23189c1e1052SPaul Mackerras andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 23199c1e1052SPaul Mackerras bne 77f /* then don't call hash_page now */ 23200ebc4cdaSBenjamin Herrenschmidt 23210ebc4cdaSBenjamin Herrenschmidt /* 23220ebc4cdaSBenjamin Herrenschmidt * r3 contains the faulting address 2323106713a1SAneesh Kumar K.V * r4 msr 23240ebc4cdaSBenjamin Herrenschmidt * r5 contains the trap number 2325aefa5688SAneesh Kumar K.V * r6 contains dsisr 23260ebc4cdaSBenjamin Herrenschmidt * 23277230c564SBenjamin Herrenschmidt * at return r3 = 0 for success, 1 for page fault, negative for error 23280ebc4cdaSBenjamin Herrenschmidt */ 2329106713a1SAneesh Kumar K.V mr r4,r12 2330aefa5688SAneesh Kumar K.V ld r6,_DSISR(r1) 2331106713a1SAneesh Kumar K.V bl __hash_page /* build HPTE if possible */ 2332106713a1SAneesh Kumar K.V cmpdi r3,0 /* see if __hash_page succeeded */ 23330ebc4cdaSBenjamin Herrenschmidt 23347230c564SBenjamin Herrenschmidt /* Success */ 23350ebc4cdaSBenjamin Herrenschmidt beq fast_exc_return_irq /* Return from exception on success */ 23360ebc4cdaSBenjamin Herrenschmidt 23377230c564SBenjamin Herrenschmidt /* Error */ 23387230c564SBenjamin Herrenschmidt blt- 13f 2339d89ba535SNaveen N. Rao 2340d89ba535SNaveen N. Rao /* Reload DSISR into r4 for the DABR check below */ 2341d89ba535SNaveen N. Rao ld r4,_DSISR(r1) 23424e003747SMichael Ellerman#endif /* CONFIG_PPC_BOOK3S_64 */ 23430ebc4cdaSBenjamin Herrenschmidt 2344a546498fSBenjamin Herrenschmidt/* Here we have a page fault that hash_page can't handle. */ 2345a546498fSBenjamin Herrenschmidthandle_page_fault: 2346d89ba535SNaveen N. Rao11: andis. r0,r4,DSISR_DABRMATCH@h 2347d89ba535SNaveen N. Rao bne- handle_dabr_fault 2348d89ba535SNaveen N. Rao ld r4,_DAR(r1) 2349a546498fSBenjamin Herrenschmidt ld r5,_DSISR(r1) 2350a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 2351b1576fecSAnton Blanchard bl do_page_fault 2352a546498fSBenjamin Herrenschmidt cmpdi r3,0 2353f474c28fSRavi Bangoria beq+ ret_from_except_lite 2354b1576fecSAnton Blanchard bl save_nvgprs 2355a546498fSBenjamin Herrenschmidt mr r5,r3 2356a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 2357a546498fSBenjamin Herrenschmidt lwz r4,_DAR(r1) 2358b1576fecSAnton Blanchard bl bad_page_fault 2359b1576fecSAnton Blanchard b ret_from_except 23600ebc4cdaSBenjamin Herrenschmidt 23619c7cc234SK.Prasad/* We have a data breakpoint exception - handle it */ 23629c7cc234SK.Prasadhandle_dabr_fault: 2363b1576fecSAnton Blanchard bl save_nvgprs 23649c7cc234SK.Prasad ld r4,_DAR(r1) 23659c7cc234SK.Prasad ld r5,_DSISR(r1) 23669c7cc234SK.Prasad addi r3,r1,STACK_FRAME_OVERHEAD 2367b1576fecSAnton Blanchard bl do_break 2368f474c28fSRavi Bangoria /* 2369f474c28fSRavi Bangoria * do_break() may have changed the NV GPRS while handling a breakpoint. 2370f474c28fSRavi Bangoria * If so, we need to restore them with their updated values. Don't use 2371f474c28fSRavi Bangoria * ret_from_except_lite here. 2372f474c28fSRavi Bangoria */ 2373f474c28fSRavi Bangoria b ret_from_except 23749c7cc234SK.Prasad 23750ebc4cdaSBenjamin Herrenschmidt 23764e003747SMichael Ellerman#ifdef CONFIG_PPC_BOOK3S_64 23770ebc4cdaSBenjamin Herrenschmidt/* We have a page fault that hash_page could handle but HV refused 23780ebc4cdaSBenjamin Herrenschmidt * the PTE insertion 23790ebc4cdaSBenjamin Herrenschmidt */ 2380b1576fecSAnton Blanchard13: bl save_nvgprs 23810ebc4cdaSBenjamin Herrenschmidt mr r5,r3 23820ebc4cdaSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 23830ebc4cdaSBenjamin Herrenschmidt ld r4,_DAR(r1) 2384b1576fecSAnton Blanchard bl low_hash_fault 2385b1576fecSAnton Blanchard b ret_from_except 2386caca285eSAneesh Kumar K.V#endif 23870ebc4cdaSBenjamin Herrenschmidt 23889c1e1052SPaul Mackerras/* 23899c1e1052SPaul Mackerras * We come here as a result of a DSI at a point where we don't want 23909c1e1052SPaul Mackerras * to call hash_page, such as when we are accessing memory (possibly 23919c1e1052SPaul Mackerras * user memory) inside a PMU interrupt that occurred while interrupts 23929c1e1052SPaul Mackerras * were soft-disabled. We want to invoke the exception handler for 23939c1e1052SPaul Mackerras * the access, or panic if there isn't a handler. 23949c1e1052SPaul Mackerras */ 2395b1576fecSAnton Blanchard77: bl save_nvgprs 23969c1e1052SPaul Mackerras mr r4,r3 23979c1e1052SPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 23989c1e1052SPaul Mackerras li r5,SIGSEGV 2399b1576fecSAnton Blanchard bl bad_page_fault 2400b1576fecSAnton Blanchard b ret_from_except 24014e2bf01bSMichael Ellerman 24024e2bf01bSMichael Ellerman/* 2403a9af97aaSNicholas Piggin * When doorbell is triggered from system reset wakeup, the message is 2404a9af97aaSNicholas Piggin * not cleared, so it would fire again when EE is enabled. 2405a9af97aaSNicholas Piggin * 2406a9af97aaSNicholas Piggin * When coming from local_irq_enable, there may be the same problem if 2407a9af97aaSNicholas Piggin * we were hard disabled. 2408a9af97aaSNicholas Piggin * 2409a9af97aaSNicholas Piggin * Execute msgclr to clear pending exceptions before handling it. 2410a9af97aaSNicholas Piggin */ 2411a9af97aaSNicholas Pigginh_doorbell_common_msgclr: 2412a9af97aaSNicholas Piggin LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 2413a9af97aaSNicholas Piggin PPC_MSGCLR(3) 2414a9af97aaSNicholas Piggin b h_doorbell_common 2415a9af97aaSNicholas Piggin 2416a9af97aaSNicholas Piggindoorbell_super_common_msgclr: 2417a9af97aaSNicholas Piggin LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 2418a9af97aaSNicholas Piggin PPC_MSGCLRP(3) 2419a9af97aaSNicholas Piggin b doorbell_super_common 2420a9af97aaSNicholas Piggin 2421a9af97aaSNicholas Piggin/* 24220f0c6ca1SNicholas Piggin * Called from arch_local_irq_enable when an interrupt needs 24230f0c6ca1SNicholas Piggin * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 24240f0c6ca1SNicholas Piggin * which kind of interrupt. MSR:EE is already off. We generate a 24250f0c6ca1SNicholas Piggin * stackframe like if a real interrupt had happened. 24260f0c6ca1SNicholas Piggin * 24270f0c6ca1SNicholas Piggin * Note: While MSR:EE is off, we need to make sure that _MSR 24280f0c6ca1SNicholas Piggin * in the generated frame has EE set to 1 or the exception 24290f0c6ca1SNicholas Piggin * handler will not properly re-enable them. 2430b48bbb82SNicholas Piggin * 2431b48bbb82SNicholas Piggin * Note that we don't specify LR as the NIP (return address) for 2432b48bbb82SNicholas Piggin * the interrupt because that would unbalance the return branch 2433b48bbb82SNicholas Piggin * predictor. 24340f0c6ca1SNicholas Piggin */ 24350f0c6ca1SNicholas Piggin_GLOBAL(__replay_interrupt) 24360f0c6ca1SNicholas Piggin /* We are going to jump to the exception common code which 24370f0c6ca1SNicholas Piggin * will retrieve various register values from the PACA which 24380f0c6ca1SNicholas Piggin * we don't give a damn about, so we don't bother storing them. 24390f0c6ca1SNicholas Piggin */ 24400f0c6ca1SNicholas Piggin mfmsr r12 24413e23a12bSMichael Ellerman LOAD_REG_ADDR(r11, replay_interrupt_return) 24420f0c6ca1SNicholas Piggin mfcr r9 24430f0c6ca1SNicholas Piggin ori r12,r12,MSR_EE 24440f0c6ca1SNicholas Piggin cmpwi r3,0x900 24450f0c6ca1SNicholas Piggin beq decrementer_common 24460f0c6ca1SNicholas Piggin cmpwi r3,0x500 2447e6c1203dSNicholas PigginBEGIN_FTR_SECTION 2448e6c1203dSNicholas Piggin beq h_virt_irq_common 2449e6c1203dSNicholas PigginFTR_SECTION_ELSE 24500f0c6ca1SNicholas Piggin beq hardware_interrupt_common 2451e6c1203dSNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) 2452f442d004SMadhavan Srinivasan cmpwi r3,0xf00 2453f442d004SMadhavan Srinivasan beq performance_monitor_common 24540f0c6ca1SNicholas PigginBEGIN_FTR_SECTION 2455d6f73fc6SNicholas Piggin cmpwi r3,0xa00 2456a9af97aaSNicholas Piggin beq h_doorbell_common_msgclr 24570f0c6ca1SNicholas Piggin cmpwi r3,0xe60 24580f0c6ca1SNicholas Piggin beq hmi_exception_common 24590f0c6ca1SNicholas PigginFTR_SECTION_ELSE 24600f0c6ca1SNicholas Piggin cmpwi r3,0xa00 2461a9af97aaSNicholas Piggin beq doorbell_super_common_msgclr 24620f0c6ca1SNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 24633e23a12bSMichael Ellermanreplay_interrupt_return: 24640f0c6ca1SNicholas Piggin blr 2465b48bbb82SNicholas Piggin 246615770a13SNaveen N. Rao_ASM_NOKPROBE_SYMBOL(__replay_interrupt) 2467